1 //===- InstrEmitter.h - Emit MachineInstrs for the SelectionDAG -*- C++ -*--==// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This declares the Emit routines for the SelectionDAG class, which creates 10 // MachineInstrs based on the decisions of the SelectionDAG instruction 11 // selection. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_LIB_CODEGEN_SELECTIONDAG_INSTREMITTER_H 16 #define LLVM_LIB_CODEGEN_SELECTIONDAG_INSTREMITTER_H 17 18 #include "llvm/ADT/DenseMap.h" 19 #include "llvm/CodeGen/MachineBasicBlock.h" 20 #include "llvm/CodeGen/SelectionDAGNodes.h" 21 22 namespace llvm { 23 24 class MachineInstrBuilder; 25 class MCInstrDesc; 26 class SDDbgLabel; 27 class SDDbgValue; 28 class TargetLowering; 29 class TargetMachine; 30 31 class LLVM_LIBRARY_VISIBILITY InstrEmitter { 32 MachineFunction *MF; 33 MachineRegisterInfo *MRI; 34 const TargetInstrInfo *TII; 35 const TargetRegisterInfo *TRI; 36 const TargetLowering *TLI; 37 38 MachineBasicBlock *MBB; 39 MachineBasicBlock::iterator InsertPos; 40 41 /// Should we try to produce DBG_INSTR_REF instructions? 42 bool EmitDebugInstrRefs; 43 44 /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an 45 /// implicit physical register output. 46 void EmitCopyFromReg(SDNode *Node, unsigned ResNo, 47 bool IsClone, bool IsCloned, 48 Register SrcReg, 49 DenseMap<SDValue, Register> &VRBaseMap); 50 51 void CreateVirtualRegisters(SDNode *Node, 52 MachineInstrBuilder &MIB, 53 const MCInstrDesc &II, 54 bool IsClone, bool IsCloned, 55 DenseMap<SDValue, Register> &VRBaseMap); 56 57 /// getVR - Return the virtual register corresponding to the specified result 58 /// of the specified node. 59 Register getVR(SDValue Op, 60 DenseMap<SDValue, Register> &VRBaseMap); 61 62 /// AddRegisterOperand - Add the specified register as an operand to the 63 /// specified machine instr. Insert register copies if the register is 64 /// not in the required register class. 65 void AddRegisterOperand(MachineInstrBuilder &MIB, 66 SDValue Op, 67 unsigned IIOpNum, 68 const MCInstrDesc *II, 69 DenseMap<SDValue, Register> &VRBaseMap, 70 bool IsDebug, bool IsClone, bool IsCloned); 71 72 /// AddOperand - Add the specified operand to the specified machine instr. II 73 /// specifies the instruction information for the node, and IIOpNum is the 74 /// operand number (in the II) that we are adding. IIOpNum and II are used for 75 /// assertions only. 76 void AddOperand(MachineInstrBuilder &MIB, 77 SDValue Op, 78 unsigned IIOpNum, 79 const MCInstrDesc *II, 80 DenseMap<SDValue, Register> &VRBaseMap, 81 bool IsDebug, bool IsClone, bool IsCloned); 82 83 /// ConstrainForSubReg - Try to constrain VReg to a register class that 84 /// supports SubIdx sub-registers. Emit a copy if that isn't possible. 85 /// Return the virtual register to use. 86 Register ConstrainForSubReg(Register VReg, unsigned SubIdx, MVT VT, 87 bool isDivergent, const DebugLoc &DL); 88 89 /// EmitSubregNode - Generate machine code for subreg nodes. 90 /// 91 void EmitSubregNode(SDNode *Node, DenseMap<SDValue, Register> &VRBaseMap, 92 bool IsClone, bool IsCloned); 93 94 /// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes. 95 /// COPY_TO_REGCLASS is just a normal copy, except that the destination 96 /// register is constrained to be in a particular register class. 97 /// 98 void EmitCopyToRegClassNode(SDNode *Node, 99 DenseMap<SDValue, Register> &VRBaseMap); 100 101 /// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes. 102 /// 103 void EmitRegSequence(SDNode *Node, DenseMap<SDValue, Register> &VRBaseMap, 104 bool IsClone, bool IsCloned); 105 public: 106 /// CountResults - The results of target nodes have register or immediate 107 /// operands first, then an optional chain, and optional flag operands 108 /// (which do not go into the machine instrs.) 109 static unsigned CountResults(SDNode *Node); 110 111 /// EmitDbgValue - Generate machine instruction for a dbg_value node. 112 /// 113 MachineInstr *EmitDbgValue(SDDbgValue *SD, 114 DenseMap<SDValue, Register> &VRBaseMap); 115 116 /// Attempt to emit a dbg_value as a DBG_INSTR_REF. May fail and return 117 /// nullptr, in which case we fall back to plain EmitDbgValue. 118 MachineInstr *EmitDbgInstrRef(SDDbgValue *SD, 119 DenseMap<SDValue, Register> &VRBaseMap); 120 121 /// Generate machine instruction for a dbg_label node. 122 MachineInstr *EmitDbgLabel(SDDbgLabel *SD); 123 124 /// EmitNode - Generate machine code for a node and needed dependencies. 125 /// 126 void EmitNode(SDNode *Node, bool IsClone, bool IsCloned, 127 DenseMap<SDValue, Register> &VRBaseMap) { 128 if (Node->isMachineOpcode()) 129 EmitMachineNode(Node, IsClone, IsCloned, VRBaseMap); 130 else 131 EmitSpecialNode(Node, IsClone, IsCloned, VRBaseMap); 132 } 133 134 /// getBlock - Return the current basic block. 135 MachineBasicBlock *getBlock() { return MBB; } 136 137 /// getInsertPos - Return the current insertion position. 138 MachineBasicBlock::iterator getInsertPos() { return InsertPos; } 139 140 /// InstrEmitter - Construct an InstrEmitter and set it to start inserting 141 /// at the given position in the given block. 142 InstrEmitter(const TargetMachine &TM, MachineBasicBlock *mbb, 143 MachineBasicBlock::iterator insertpos); 144 145 private: 146 void EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned, 147 DenseMap<SDValue, Register> &VRBaseMap); 148 void EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned, 149 DenseMap<SDValue, Register> &VRBaseMap); 150 }; 151 152 } 153 154 #endif 155