1 //===- SelectionDAGBuilder.cpp - Selection-DAG building -------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This implements routines for translating from LLVM IR into SelectionDAG IR. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "SelectionDAGBuilder.h" 14 #include "SDNodeDbgValue.h" 15 #include "llvm/ADT/APFloat.h" 16 #include "llvm/ADT/APInt.h" 17 #include "llvm/ADT/BitVector.h" 18 #include "llvm/ADT/None.h" 19 #include "llvm/ADT/Optional.h" 20 #include "llvm/ADT/STLExtras.h" 21 #include "llvm/ADT/SmallPtrSet.h" 22 #include "llvm/ADT/SmallSet.h" 23 #include "llvm/ADT/StringRef.h" 24 #include "llvm/ADT/Triple.h" 25 #include "llvm/ADT/Twine.h" 26 #include "llvm/Analysis/AliasAnalysis.h" 27 #include "llvm/Analysis/BranchProbabilityInfo.h" 28 #include "llvm/Analysis/ConstantFolding.h" 29 #include "llvm/Analysis/EHPersonalities.h" 30 #include "llvm/Analysis/MemoryLocation.h" 31 #include "llvm/Analysis/TargetLibraryInfo.h" 32 #include "llvm/Analysis/ValueTracking.h" 33 #include "llvm/CodeGen/Analysis.h" 34 #include "llvm/CodeGen/CodeGenCommonISel.h" 35 #include "llvm/CodeGen/FunctionLoweringInfo.h" 36 #include "llvm/CodeGen/GCMetadata.h" 37 #include "llvm/CodeGen/MachineBasicBlock.h" 38 #include "llvm/CodeGen/MachineFrameInfo.h" 39 #include "llvm/CodeGen/MachineFunction.h" 40 #include "llvm/CodeGen/MachineInstrBuilder.h" 41 #include "llvm/CodeGen/MachineInstrBundleIterator.h" 42 #include "llvm/CodeGen/MachineMemOperand.h" 43 #include "llvm/CodeGen/MachineModuleInfo.h" 44 #include "llvm/CodeGen/MachineOperand.h" 45 #include "llvm/CodeGen/MachineRegisterInfo.h" 46 #include "llvm/CodeGen/RuntimeLibcalls.h" 47 #include "llvm/CodeGen/SelectionDAG.h" 48 #include "llvm/CodeGen/SelectionDAGTargetInfo.h" 49 #include "llvm/CodeGen/StackMaps.h" 50 #include "llvm/CodeGen/SwiftErrorValueTracking.h" 51 #include "llvm/CodeGen/TargetFrameLowering.h" 52 #include "llvm/CodeGen/TargetInstrInfo.h" 53 #include "llvm/CodeGen/TargetOpcodes.h" 54 #include "llvm/CodeGen/TargetRegisterInfo.h" 55 #include "llvm/CodeGen/TargetSubtargetInfo.h" 56 #include "llvm/CodeGen/WinEHFuncInfo.h" 57 #include "llvm/IR/Argument.h" 58 #include "llvm/IR/Attributes.h" 59 #include "llvm/IR/BasicBlock.h" 60 #include "llvm/IR/CFG.h" 61 #include "llvm/IR/CallingConv.h" 62 #include "llvm/IR/Constant.h" 63 #include "llvm/IR/ConstantRange.h" 64 #include "llvm/IR/Constants.h" 65 #include "llvm/IR/DataLayout.h" 66 #include "llvm/IR/DebugInfoMetadata.h" 67 #include "llvm/IR/DerivedTypes.h" 68 #include "llvm/IR/DiagnosticInfo.h" 69 #include "llvm/IR/Function.h" 70 #include "llvm/IR/GetElementPtrTypeIterator.h" 71 #include "llvm/IR/InlineAsm.h" 72 #include "llvm/IR/InstrTypes.h" 73 #include "llvm/IR/Instructions.h" 74 #include "llvm/IR/IntrinsicInst.h" 75 #include "llvm/IR/Intrinsics.h" 76 #include "llvm/IR/IntrinsicsAArch64.h" 77 #include "llvm/IR/IntrinsicsWebAssembly.h" 78 #include "llvm/IR/LLVMContext.h" 79 #include "llvm/IR/Metadata.h" 80 #include "llvm/IR/Module.h" 81 #include "llvm/IR/Operator.h" 82 #include "llvm/IR/PatternMatch.h" 83 #include "llvm/IR/Statepoint.h" 84 #include "llvm/IR/Type.h" 85 #include "llvm/IR/User.h" 86 #include "llvm/IR/Value.h" 87 #include "llvm/MC/MCContext.h" 88 #include "llvm/Support/AtomicOrdering.h" 89 #include "llvm/Support/Casting.h" 90 #include "llvm/Support/CommandLine.h" 91 #include "llvm/Support/Compiler.h" 92 #include "llvm/Support/Debug.h" 93 #include "llvm/Support/MathExtras.h" 94 #include "llvm/Support/raw_ostream.h" 95 #include "llvm/Target/TargetIntrinsicInfo.h" 96 #include "llvm/Target/TargetMachine.h" 97 #include "llvm/Target/TargetOptions.h" 98 #include "llvm/Transforms/Utils/Local.h" 99 #include <cstddef> 100 #include <iterator> 101 #include <limits> 102 #include <tuple> 103 104 using namespace llvm; 105 using namespace PatternMatch; 106 using namespace SwitchCG; 107 108 #define DEBUG_TYPE "isel" 109 110 /// LimitFloatPrecision - Generate low-precision inline sequences for 111 /// some float libcalls (6, 8 or 12 bits). 112 static unsigned LimitFloatPrecision; 113 114 static cl::opt<bool> 115 InsertAssertAlign("insert-assert-align", cl::init(true), 116 cl::desc("Insert the experimental `assertalign` node."), 117 cl::ReallyHidden); 118 119 static cl::opt<unsigned, true> 120 LimitFPPrecision("limit-float-precision", 121 cl::desc("Generate low-precision inline sequences " 122 "for some float libcalls"), 123 cl::location(LimitFloatPrecision), cl::Hidden, 124 cl::init(0)); 125 126 static cl::opt<unsigned> SwitchPeelThreshold( 127 "switch-peel-threshold", cl::Hidden, cl::init(66), 128 cl::desc("Set the case probability threshold for peeling the case from a " 129 "switch statement. A value greater than 100 will void this " 130 "optimization")); 131 132 // Limit the width of DAG chains. This is important in general to prevent 133 // DAG-based analysis from blowing up. For example, alias analysis and 134 // load clustering may not complete in reasonable time. It is difficult to 135 // recognize and avoid this situation within each individual analysis, and 136 // future analyses are likely to have the same behavior. Limiting DAG width is 137 // the safe approach and will be especially important with global DAGs. 138 // 139 // MaxParallelChains default is arbitrarily high to avoid affecting 140 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st 141 // sequence over this should have been converted to llvm.memcpy by the 142 // frontend. It is easy to induce this behavior with .ll code such as: 143 // %buffer = alloca [4096 x i8] 144 // %data = load [4096 x i8]* %argPtr 145 // store [4096 x i8] %data, [4096 x i8]* %buffer 146 static const unsigned MaxParallelChains = 64; 147 148 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, const SDLoc &DL, 149 const SDValue *Parts, unsigned NumParts, 150 MVT PartVT, EVT ValueVT, const Value *V, 151 Optional<CallingConv::ID> CC); 152 153 /// getCopyFromParts - Create a value that contains the specified legal parts 154 /// combined into the value they represent. If the parts combine to a type 155 /// larger than ValueVT then AssertOp can be used to specify whether the extra 156 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 157 /// (ISD::AssertSext). 158 static SDValue getCopyFromParts(SelectionDAG &DAG, const SDLoc &DL, 159 const SDValue *Parts, unsigned NumParts, 160 MVT PartVT, EVT ValueVT, const Value *V, 161 Optional<CallingConv::ID> CC = None, 162 Optional<ISD::NodeType> AssertOp = None) { 163 // Let the target assemble the parts if it wants to 164 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 165 if (SDValue Val = TLI.joinRegisterPartsIntoValue(DAG, DL, Parts, NumParts, 166 PartVT, ValueVT, CC)) 167 return Val; 168 169 if (ValueVT.isVector()) 170 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT, V, 171 CC); 172 173 assert(NumParts > 0 && "No parts to assemble!"); 174 SDValue Val = Parts[0]; 175 176 if (NumParts > 1) { 177 // Assemble the value from multiple parts. 178 if (ValueVT.isInteger()) { 179 unsigned PartBits = PartVT.getSizeInBits(); 180 unsigned ValueBits = ValueVT.getSizeInBits(); 181 182 // Assemble the power of 2 part. 183 unsigned RoundParts = 184 (NumParts & (NumParts - 1)) ? 1 << Log2_32(NumParts) : NumParts; 185 unsigned RoundBits = PartBits * RoundParts; 186 EVT RoundVT = RoundBits == ValueBits ? 187 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits); 188 SDValue Lo, Hi; 189 190 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2); 191 192 if (RoundParts > 2) { 193 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2, 194 PartVT, HalfVT, V); 195 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2, 196 RoundParts / 2, PartVT, HalfVT, V); 197 } else { 198 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]); 199 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]); 200 } 201 202 if (DAG.getDataLayout().isBigEndian()) 203 std::swap(Lo, Hi); 204 205 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi); 206 207 if (RoundParts < NumParts) { 208 // Assemble the trailing non-power-of-2 part. 209 unsigned OddParts = NumParts - RoundParts; 210 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits); 211 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts, OddParts, PartVT, 212 OddVT, V, CC); 213 214 // Combine the round and odd parts. 215 Lo = Val; 216 if (DAG.getDataLayout().isBigEndian()) 217 std::swap(Lo, Hi); 218 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 219 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi); 220 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi, 221 DAG.getConstant(Lo.getValueSizeInBits(), DL, 222 TLI.getShiftAmountTy( 223 TotalVT, DAG.getDataLayout()))); 224 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo); 225 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi); 226 } 227 } else if (PartVT.isFloatingPoint()) { 228 // FP split into multiple FP parts (for ppcf128) 229 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 && 230 "Unexpected split"); 231 SDValue Lo, Hi; 232 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]); 233 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]); 234 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout())) 235 std::swap(Lo, Hi); 236 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi); 237 } else { 238 // FP split into integer parts (soft fp) 239 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() && 240 !PartVT.isVector() && "Unexpected split"); 241 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); 242 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V, CC); 243 } 244 } 245 246 // There is now one part, held in Val. Correct it to match ValueVT. 247 // PartEVT is the type of the register class that holds the value. 248 // ValueVT is the type of the inline asm operation. 249 EVT PartEVT = Val.getValueType(); 250 251 if (PartEVT == ValueVT) 252 return Val; 253 254 if (PartEVT.isInteger() && ValueVT.isFloatingPoint() && 255 ValueVT.bitsLT(PartEVT)) { 256 // For an FP value in an integer part, we need to truncate to the right 257 // width first. 258 PartEVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); 259 Val = DAG.getNode(ISD::TRUNCATE, DL, PartEVT, Val); 260 } 261 262 // Handle types that have the same size. 263 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits()) 264 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 265 266 // Handle types with different sizes. 267 if (PartEVT.isInteger() && ValueVT.isInteger()) { 268 if (ValueVT.bitsLT(PartEVT)) { 269 // For a truncate, see if we have any information to 270 // indicate whether the truncated bits will always be 271 // zero or sign-extension. 272 if (AssertOp) 273 Val = DAG.getNode(*AssertOp, DL, PartEVT, Val, 274 DAG.getValueType(ValueVT)); 275 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 276 } 277 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val); 278 } 279 280 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 281 // FP_ROUND's are always exact here. 282 if (ValueVT.bitsLT(Val.getValueType())) 283 return DAG.getNode( 284 ISD::FP_ROUND, DL, ValueVT, Val, 285 DAG.getTargetConstant(1, DL, TLI.getPointerTy(DAG.getDataLayout()))); 286 287 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val); 288 } 289 290 // Handle MMX to a narrower integer type by bitcasting MMX to integer and 291 // then truncating. 292 if (PartEVT == MVT::x86mmx && ValueVT.isInteger() && 293 ValueVT.bitsLT(PartEVT)) { 294 Val = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Val); 295 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 296 } 297 298 report_fatal_error("Unknown mismatch in getCopyFromParts!"); 299 } 300 301 static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V, 302 const Twine &ErrMsg) { 303 const Instruction *I = dyn_cast_or_null<Instruction>(V); 304 if (!V) 305 return Ctx.emitError(ErrMsg); 306 307 const char *AsmError = ", possible invalid constraint for vector type"; 308 if (const CallInst *CI = dyn_cast<CallInst>(I)) 309 if (CI->isInlineAsm()) 310 return Ctx.emitError(I, ErrMsg + AsmError); 311 312 return Ctx.emitError(I, ErrMsg); 313 } 314 315 /// getCopyFromPartsVector - Create a value that contains the specified legal 316 /// parts combined into the value they represent. If the parts combine to a 317 /// type larger than ValueVT then AssertOp can be used to specify whether the 318 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from 319 /// ValueVT (ISD::AssertSext). 320 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, const SDLoc &DL, 321 const SDValue *Parts, unsigned NumParts, 322 MVT PartVT, EVT ValueVT, const Value *V, 323 Optional<CallingConv::ID> CallConv) { 324 assert(ValueVT.isVector() && "Not a vector value"); 325 assert(NumParts > 0 && "No parts to assemble!"); 326 const bool IsABIRegCopy = CallConv.has_value(); 327 328 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 329 SDValue Val = Parts[0]; 330 331 // Handle a multi-element vector. 332 if (NumParts > 1) { 333 EVT IntermediateVT; 334 MVT RegisterVT; 335 unsigned NumIntermediates; 336 unsigned NumRegs; 337 338 if (IsABIRegCopy) { 339 NumRegs = TLI.getVectorTypeBreakdownForCallingConv( 340 *DAG.getContext(), *CallConv, ValueVT, IntermediateVT, 341 NumIntermediates, RegisterVT); 342 } else { 343 NumRegs = 344 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT, 345 NumIntermediates, RegisterVT); 346 } 347 348 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 349 NumParts = NumRegs; // Silence a compiler warning. 350 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 351 assert(RegisterVT.getSizeInBits() == 352 Parts[0].getSimpleValueType().getSizeInBits() && 353 "Part type sizes don't match!"); 354 355 // Assemble the parts into intermediate operands. 356 SmallVector<SDValue, 8> Ops(NumIntermediates); 357 if (NumIntermediates == NumParts) { 358 // If the register was not expanded, truncate or copy the value, 359 // as appropriate. 360 for (unsigned i = 0; i != NumParts; ++i) 361 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1, 362 PartVT, IntermediateVT, V, CallConv); 363 } else if (NumParts > 0) { 364 // If the intermediate type was expanded, build the intermediate 365 // operands from the parts. 366 assert(NumParts % NumIntermediates == 0 && 367 "Must expand into a divisible number of parts!"); 368 unsigned Factor = NumParts / NumIntermediates; 369 for (unsigned i = 0; i != NumIntermediates; ++i) 370 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor, 371 PartVT, IntermediateVT, V, CallConv); 372 } 373 374 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the 375 // intermediate operands. 376 EVT BuiltVectorTy = 377 IntermediateVT.isVector() 378 ? EVT::getVectorVT( 379 *DAG.getContext(), IntermediateVT.getScalarType(), 380 IntermediateVT.getVectorElementCount() * NumParts) 381 : EVT::getVectorVT(*DAG.getContext(), 382 IntermediateVT.getScalarType(), 383 NumIntermediates); 384 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS 385 : ISD::BUILD_VECTOR, 386 DL, BuiltVectorTy, Ops); 387 } 388 389 // There is now one part, held in Val. Correct it to match ValueVT. 390 EVT PartEVT = Val.getValueType(); 391 392 if (PartEVT == ValueVT) 393 return Val; 394 395 if (PartEVT.isVector()) { 396 // Vector/Vector bitcast. 397 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits()) 398 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 399 400 // If the element type of the source/dest vectors are the same, but the 401 // parts vector has more elements than the value vector, then we have a 402 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the 403 // elements we want. 404 if (PartEVT.getVectorElementCount() != ValueVT.getVectorElementCount()) { 405 assert((PartEVT.getVectorElementCount().getKnownMinValue() > 406 ValueVT.getVectorElementCount().getKnownMinValue()) && 407 (PartEVT.getVectorElementCount().isScalable() == 408 ValueVT.getVectorElementCount().isScalable()) && 409 "Cannot narrow, it would be a lossy transformation"); 410 PartEVT = 411 EVT::getVectorVT(*DAG.getContext(), PartEVT.getVectorElementType(), 412 ValueVT.getVectorElementCount()); 413 Val = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, PartEVT, Val, 414 DAG.getVectorIdxConstant(0, DL)); 415 if (PartEVT == ValueVT) 416 return Val; 417 } 418 419 // Promoted vector extract 420 return DAG.getAnyExtOrTrunc(Val, DL, ValueVT); 421 } 422 423 // Trivial bitcast if the types are the same size and the destination 424 // vector type is legal. 425 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() && 426 TLI.isTypeLegal(ValueVT)) 427 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 428 429 if (ValueVT.getVectorNumElements() != 1) { 430 // Certain ABIs require that vectors are passed as integers. For vectors 431 // are the same size, this is an obvious bitcast. 432 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits()) { 433 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 434 } else if (ValueVT.bitsLT(PartEVT)) { 435 const uint64_t ValueSize = ValueVT.getFixedSizeInBits(); 436 EVT IntermediateType = EVT::getIntegerVT(*DAG.getContext(), ValueSize); 437 // Drop the extra bits. 438 Val = DAG.getNode(ISD::TRUNCATE, DL, IntermediateType, Val); 439 return DAG.getBitcast(ValueVT, Val); 440 } 441 442 diagnosePossiblyInvalidConstraint( 443 *DAG.getContext(), V, "non-trivial scalar-to-vector conversion"); 444 return DAG.getUNDEF(ValueVT); 445 } 446 447 // Handle cases such as i8 -> <1 x i1> 448 EVT ValueSVT = ValueVT.getVectorElementType(); 449 if (ValueVT.getVectorNumElements() == 1 && ValueSVT != PartEVT) { 450 if (ValueSVT.getSizeInBits() == PartEVT.getSizeInBits()) 451 Val = DAG.getNode(ISD::BITCAST, DL, ValueSVT, Val); 452 else 453 Val = ValueVT.isFloatingPoint() 454 ? DAG.getFPExtendOrRound(Val, DL, ValueSVT) 455 : DAG.getAnyExtOrTrunc(Val, DL, ValueSVT); 456 } 457 458 return DAG.getBuildVector(ValueVT, DL, Val); 459 } 460 461 static void getCopyToPartsVector(SelectionDAG &DAG, const SDLoc &dl, 462 SDValue Val, SDValue *Parts, unsigned NumParts, 463 MVT PartVT, const Value *V, 464 Optional<CallingConv::ID> CallConv); 465 466 /// getCopyToParts - Create a series of nodes that contain the specified value 467 /// split into legal parts. If the parts contain more bits than Val, then, for 468 /// integers, ExtendKind can be used to specify how to generate the extra bits. 469 static void getCopyToParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val, 470 SDValue *Parts, unsigned NumParts, MVT PartVT, 471 const Value *V, 472 Optional<CallingConv::ID> CallConv = None, 473 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) { 474 // Let the target split the parts if it wants to 475 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 476 if (TLI.splitValueIntoRegisterParts(DAG, DL, Val, Parts, NumParts, PartVT, 477 CallConv)) 478 return; 479 EVT ValueVT = Val.getValueType(); 480 481 // Handle the vector case separately. 482 if (ValueVT.isVector()) 483 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V, 484 CallConv); 485 486 unsigned PartBits = PartVT.getSizeInBits(); 487 unsigned OrigNumParts = NumParts; 488 assert(DAG.getTargetLoweringInfo().isTypeLegal(PartVT) && 489 "Copying to an illegal type!"); 490 491 if (NumParts == 0) 492 return; 493 494 assert(!ValueVT.isVector() && "Vector case handled elsewhere"); 495 EVT PartEVT = PartVT; 496 if (PartEVT == ValueVT) { 497 assert(NumParts == 1 && "No-op copy with multiple parts!"); 498 Parts[0] = Val; 499 return; 500 } 501 502 if (NumParts * PartBits > ValueVT.getSizeInBits()) { 503 // If the parts cover more bits than the value has, promote the value. 504 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 505 assert(NumParts == 1 && "Do not know what to promote to!"); 506 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val); 507 } else { 508 if (ValueVT.isFloatingPoint()) { 509 // FP values need to be bitcast, then extended if they are being put 510 // into a larger container. 511 ValueVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); 512 Val = DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 513 } 514 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) && 515 ValueVT.isInteger() && 516 "Unknown mismatch!"); 517 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 518 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val); 519 if (PartVT == MVT::x86mmx) 520 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 521 } 522 } else if (PartBits == ValueVT.getSizeInBits()) { 523 // Different types of the same size. 524 assert(NumParts == 1 && PartEVT != ValueVT); 525 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 526 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) { 527 // If the parts cover less bits than value has, truncate the value. 528 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) && 529 ValueVT.isInteger() && 530 "Unknown mismatch!"); 531 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 532 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 533 if (PartVT == MVT::x86mmx) 534 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 535 } 536 537 // The value may have changed - recompute ValueVT. 538 ValueVT = Val.getValueType(); 539 assert(NumParts * PartBits == ValueVT.getSizeInBits() && 540 "Failed to tile the value with PartVT!"); 541 542 if (NumParts == 1) { 543 if (PartEVT != ValueVT) { 544 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V, 545 "scalar-to-vector conversion failed"); 546 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 547 } 548 549 Parts[0] = Val; 550 return; 551 } 552 553 // Expand the value into multiple parts. 554 if (NumParts & (NumParts - 1)) { 555 // The number of parts is not a power of 2. Split off and copy the tail. 556 assert(PartVT.isInteger() && ValueVT.isInteger() && 557 "Do not know what to expand to!"); 558 unsigned RoundParts = 1 << Log2_32(NumParts); 559 unsigned RoundBits = RoundParts * PartBits; 560 unsigned OddParts = NumParts - RoundParts; 561 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val, 562 DAG.getShiftAmountConstant(RoundBits, ValueVT, DL)); 563 564 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V, 565 CallConv); 566 567 if (DAG.getDataLayout().isBigEndian()) 568 // The odd parts were reversed by getCopyToParts - unreverse them. 569 std::reverse(Parts + RoundParts, Parts + NumParts); 570 571 NumParts = RoundParts; 572 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 573 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 574 } 575 576 // The number of parts is a power of 2. Repeatedly bisect the value using 577 // EXTRACT_ELEMENT. 578 Parts[0] = DAG.getNode(ISD::BITCAST, DL, 579 EVT::getIntegerVT(*DAG.getContext(), 580 ValueVT.getSizeInBits()), 581 Val); 582 583 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) { 584 for (unsigned i = 0; i < NumParts; i += StepSize) { 585 unsigned ThisBits = StepSize * PartBits / 2; 586 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits); 587 SDValue &Part0 = Parts[i]; 588 SDValue &Part1 = Parts[i+StepSize/2]; 589 590 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 591 ThisVT, Part0, DAG.getIntPtrConstant(1, DL)); 592 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 593 ThisVT, Part0, DAG.getIntPtrConstant(0, DL)); 594 595 if (ThisBits == PartBits && ThisVT != PartVT) { 596 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0); 597 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1); 598 } 599 } 600 } 601 602 if (DAG.getDataLayout().isBigEndian()) 603 std::reverse(Parts, Parts + OrigNumParts); 604 } 605 606 static SDValue widenVectorToPartType(SelectionDAG &DAG, SDValue Val, 607 const SDLoc &DL, EVT PartVT) { 608 if (!PartVT.isVector()) 609 return SDValue(); 610 611 EVT ValueVT = Val.getValueType(); 612 ElementCount PartNumElts = PartVT.getVectorElementCount(); 613 ElementCount ValueNumElts = ValueVT.getVectorElementCount(); 614 615 // We only support widening vectors with equivalent element types and 616 // fixed/scalable properties. If a target needs to widen a fixed-length type 617 // to a scalable one, it should be possible to use INSERT_SUBVECTOR below. 618 if (ElementCount::isKnownLE(PartNumElts, ValueNumElts) || 619 PartNumElts.isScalable() != ValueNumElts.isScalable() || 620 PartVT.getVectorElementType() != ValueVT.getVectorElementType()) 621 return SDValue(); 622 623 // Widening a scalable vector to another scalable vector is done by inserting 624 // the vector into a larger undef one. 625 if (PartNumElts.isScalable()) 626 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, PartVT, DAG.getUNDEF(PartVT), 627 Val, DAG.getVectorIdxConstant(0, DL)); 628 629 EVT ElementVT = PartVT.getVectorElementType(); 630 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in 631 // undef elements. 632 SmallVector<SDValue, 16> Ops; 633 DAG.ExtractVectorElements(Val, Ops); 634 SDValue EltUndef = DAG.getUNDEF(ElementVT); 635 Ops.append((PartNumElts - ValueNumElts).getFixedValue(), EltUndef); 636 637 // FIXME: Use CONCAT for 2x -> 4x. 638 return DAG.getBuildVector(PartVT, DL, Ops); 639 } 640 641 /// getCopyToPartsVector - Create a series of nodes that contain the specified 642 /// value split into legal parts. 643 static void getCopyToPartsVector(SelectionDAG &DAG, const SDLoc &DL, 644 SDValue Val, SDValue *Parts, unsigned NumParts, 645 MVT PartVT, const Value *V, 646 Optional<CallingConv::ID> CallConv) { 647 EVT ValueVT = Val.getValueType(); 648 assert(ValueVT.isVector() && "Not a vector"); 649 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 650 const bool IsABIRegCopy = CallConv.has_value(); 651 652 if (NumParts == 1) { 653 EVT PartEVT = PartVT; 654 if (PartEVT == ValueVT) { 655 // Nothing to do. 656 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) { 657 // Bitconvert vector->vector case. 658 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 659 } else if (SDValue Widened = widenVectorToPartType(DAG, Val, DL, PartVT)) { 660 Val = Widened; 661 } else if (PartVT.isVector() && 662 PartEVT.getVectorElementType().bitsGE( 663 ValueVT.getVectorElementType()) && 664 PartEVT.getVectorElementCount() == 665 ValueVT.getVectorElementCount()) { 666 667 // Promoted vector extract 668 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT); 669 } else if (PartEVT.isVector() && 670 PartEVT.getVectorElementType() != 671 ValueVT.getVectorElementType() && 672 TLI.getTypeAction(*DAG.getContext(), ValueVT) == 673 TargetLowering::TypeWidenVector) { 674 // Combination of widening and promotion. 675 EVT WidenVT = 676 EVT::getVectorVT(*DAG.getContext(), ValueVT.getVectorElementType(), 677 PartVT.getVectorElementCount()); 678 SDValue Widened = widenVectorToPartType(DAG, Val, DL, WidenVT); 679 Val = DAG.getAnyExtOrTrunc(Widened, DL, PartVT); 680 } else { 681 if (ValueVT.getVectorElementCount().isScalar()) { 682 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, PartVT, Val, 683 DAG.getVectorIdxConstant(0, DL)); 684 } else { 685 uint64_t ValueSize = ValueVT.getFixedSizeInBits(); 686 assert(PartVT.getFixedSizeInBits() > ValueSize && 687 "lossy conversion of vector to scalar type"); 688 EVT IntermediateType = EVT::getIntegerVT(*DAG.getContext(), ValueSize); 689 Val = DAG.getBitcast(IntermediateType, Val); 690 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT); 691 } 692 } 693 694 assert(Val.getValueType() == PartVT && "Unexpected vector part value type"); 695 Parts[0] = Val; 696 return; 697 } 698 699 // Handle a multi-element vector. 700 EVT IntermediateVT; 701 MVT RegisterVT; 702 unsigned NumIntermediates; 703 unsigned NumRegs; 704 if (IsABIRegCopy) { 705 NumRegs = TLI.getVectorTypeBreakdownForCallingConv( 706 *DAG.getContext(), CallConv.value(), ValueVT, IntermediateVT, 707 NumIntermediates, RegisterVT); 708 } else { 709 NumRegs = 710 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT, 711 NumIntermediates, RegisterVT); 712 } 713 714 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 715 NumParts = NumRegs; // Silence a compiler warning. 716 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 717 718 assert(IntermediateVT.isScalableVector() == ValueVT.isScalableVector() && 719 "Mixing scalable and fixed vectors when copying in parts"); 720 721 Optional<ElementCount> DestEltCnt; 722 723 if (IntermediateVT.isVector()) 724 DestEltCnt = IntermediateVT.getVectorElementCount() * NumIntermediates; 725 else 726 DestEltCnt = ElementCount::getFixed(NumIntermediates); 727 728 EVT BuiltVectorTy = EVT::getVectorVT( 729 *DAG.getContext(), IntermediateVT.getScalarType(), *DestEltCnt); 730 731 if (ValueVT == BuiltVectorTy) { 732 // Nothing to do. 733 } else if (ValueVT.getSizeInBits() == BuiltVectorTy.getSizeInBits()) { 734 // Bitconvert vector->vector case. 735 Val = DAG.getNode(ISD::BITCAST, DL, BuiltVectorTy, Val); 736 } else { 737 if (BuiltVectorTy.getVectorElementType().bitsGT( 738 ValueVT.getVectorElementType())) { 739 // Integer promotion. 740 ValueVT = EVT::getVectorVT(*DAG.getContext(), 741 BuiltVectorTy.getVectorElementType(), 742 ValueVT.getVectorElementCount()); 743 Val = DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val); 744 } 745 746 if (SDValue Widened = widenVectorToPartType(DAG, Val, DL, BuiltVectorTy)) { 747 Val = Widened; 748 } 749 } 750 751 assert(Val.getValueType() == BuiltVectorTy && "Unexpected vector value type"); 752 753 // Split the vector into intermediate operands. 754 SmallVector<SDValue, 8> Ops(NumIntermediates); 755 for (unsigned i = 0; i != NumIntermediates; ++i) { 756 if (IntermediateVT.isVector()) { 757 // This does something sensible for scalable vectors - see the 758 // definition of EXTRACT_SUBVECTOR for further details. 759 unsigned IntermediateNumElts = IntermediateVT.getVectorMinNumElements(); 760 Ops[i] = 761 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, IntermediateVT, Val, 762 DAG.getVectorIdxConstant(i * IntermediateNumElts, DL)); 763 } else { 764 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, IntermediateVT, Val, 765 DAG.getVectorIdxConstant(i, DL)); 766 } 767 } 768 769 // Split the intermediate operands into legal parts. 770 if (NumParts == NumIntermediates) { 771 // If the register was not expanded, promote or copy the value, 772 // as appropriate. 773 for (unsigned i = 0; i != NumParts; ++i) 774 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V, CallConv); 775 } else if (NumParts > 0) { 776 // If the intermediate type was expanded, split each the value into 777 // legal parts. 778 assert(NumIntermediates != 0 && "division by zero"); 779 assert(NumParts % NumIntermediates == 0 && 780 "Must expand into a divisible number of parts!"); 781 unsigned Factor = NumParts / NumIntermediates; 782 for (unsigned i = 0; i != NumIntermediates; ++i) 783 getCopyToParts(DAG, DL, Ops[i], &Parts[i * Factor], Factor, PartVT, V, 784 CallConv); 785 } 786 } 787 788 RegsForValue::RegsForValue(const SmallVector<unsigned, 4> ®s, MVT regvt, 789 EVT valuevt, Optional<CallingConv::ID> CC) 790 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs), 791 RegCount(1, regs.size()), CallConv(CC) {} 792 793 RegsForValue::RegsForValue(LLVMContext &Context, const TargetLowering &TLI, 794 const DataLayout &DL, unsigned Reg, Type *Ty, 795 Optional<CallingConv::ID> CC) { 796 ComputeValueVTs(TLI, DL, Ty, ValueVTs); 797 798 CallConv = CC; 799 800 for (EVT ValueVT : ValueVTs) { 801 unsigned NumRegs = 802 isABIMangled() 803 ? TLI.getNumRegistersForCallingConv(Context, CC.value(), ValueVT) 804 : TLI.getNumRegisters(Context, ValueVT); 805 MVT RegisterVT = 806 isABIMangled() 807 ? TLI.getRegisterTypeForCallingConv(Context, CC.value(), ValueVT) 808 : TLI.getRegisterType(Context, ValueVT); 809 for (unsigned i = 0; i != NumRegs; ++i) 810 Regs.push_back(Reg + i); 811 RegVTs.push_back(RegisterVT); 812 RegCount.push_back(NumRegs); 813 Reg += NumRegs; 814 } 815 } 816 817 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, 818 FunctionLoweringInfo &FuncInfo, 819 const SDLoc &dl, SDValue &Chain, 820 SDValue *Flag, const Value *V) const { 821 // A Value with type {} or [0 x %t] needs no registers. 822 if (ValueVTs.empty()) 823 return SDValue(); 824 825 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 826 827 // Assemble the legal parts into the final values. 828 SmallVector<SDValue, 4> Values(ValueVTs.size()); 829 SmallVector<SDValue, 8> Parts; 830 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 831 // Copy the legal parts from the registers. 832 EVT ValueVT = ValueVTs[Value]; 833 unsigned NumRegs = RegCount[Value]; 834 MVT RegisterVT = 835 isABIMangled() ? TLI.getRegisterTypeForCallingConv( 836 *DAG.getContext(), CallConv.value(), RegVTs[Value]) 837 : RegVTs[Value]; 838 839 Parts.resize(NumRegs); 840 for (unsigned i = 0; i != NumRegs; ++i) { 841 SDValue P; 842 if (!Flag) { 843 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT); 844 } else { 845 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag); 846 *Flag = P.getValue(2); 847 } 848 849 Chain = P.getValue(1); 850 Parts[i] = P; 851 852 // If the source register was virtual and if we know something about it, 853 // add an assert node. 854 if (!Register::isVirtualRegister(Regs[Part + i]) || 855 !RegisterVT.isInteger()) 856 continue; 857 858 const FunctionLoweringInfo::LiveOutInfo *LOI = 859 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]); 860 if (!LOI) 861 continue; 862 863 unsigned RegSize = RegisterVT.getScalarSizeInBits(); 864 unsigned NumSignBits = LOI->NumSignBits; 865 unsigned NumZeroBits = LOI->Known.countMinLeadingZeros(); 866 867 if (NumZeroBits == RegSize) { 868 // The current value is a zero. 869 // Explicitly express that as it would be easier for 870 // optimizations to kick in. 871 Parts[i] = DAG.getConstant(0, dl, RegisterVT); 872 continue; 873 } 874 875 // FIXME: We capture more information than the dag can represent. For 876 // now, just use the tightest assertzext/assertsext possible. 877 bool isSExt; 878 EVT FromVT(MVT::Other); 879 if (NumZeroBits) { 880 FromVT = EVT::getIntegerVT(*DAG.getContext(), RegSize - NumZeroBits); 881 isSExt = false; 882 } else if (NumSignBits > 1) { 883 FromVT = 884 EVT::getIntegerVT(*DAG.getContext(), RegSize - NumSignBits + 1); 885 isSExt = true; 886 } else { 887 continue; 888 } 889 // Add an assertion node. 890 assert(FromVT != MVT::Other); 891 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, 892 RegisterVT, P, DAG.getValueType(FromVT)); 893 } 894 895 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(), NumRegs, 896 RegisterVT, ValueVT, V, CallConv); 897 Part += NumRegs; 898 Parts.clear(); 899 } 900 901 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values); 902 } 903 904 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, 905 const SDLoc &dl, SDValue &Chain, SDValue *Flag, 906 const Value *V, 907 ISD::NodeType PreferredExtendType) const { 908 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 909 ISD::NodeType ExtendKind = PreferredExtendType; 910 911 // Get the list of the values's legal parts. 912 unsigned NumRegs = Regs.size(); 913 SmallVector<SDValue, 8> Parts(NumRegs); 914 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 915 unsigned NumParts = RegCount[Value]; 916 917 MVT RegisterVT = 918 isABIMangled() ? TLI.getRegisterTypeForCallingConv( 919 *DAG.getContext(), CallConv.value(), RegVTs[Value]) 920 : RegVTs[Value]; 921 922 if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT)) 923 ExtendKind = ISD::ZERO_EXTEND; 924 925 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value), &Parts[Part], 926 NumParts, RegisterVT, V, CallConv, ExtendKind); 927 Part += NumParts; 928 } 929 930 // Copy the parts into the registers. 931 SmallVector<SDValue, 8> Chains(NumRegs); 932 for (unsigned i = 0; i != NumRegs; ++i) { 933 SDValue Part; 934 if (!Flag) { 935 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]); 936 } else { 937 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag); 938 *Flag = Part.getValue(1); 939 } 940 941 Chains[i] = Part.getValue(0); 942 } 943 944 if (NumRegs == 1 || Flag) 945 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is 946 // flagged to it. That is the CopyToReg nodes and the user are considered 947 // a single scheduling unit. If we create a TokenFactor and return it as 948 // chain, then the TokenFactor is both a predecessor (operand) of the 949 // user as well as a successor (the TF operands are flagged to the user). 950 // c1, f1 = CopyToReg 951 // c2, f2 = CopyToReg 952 // c3 = TokenFactor c1, c2 953 // ... 954 // = op c3, ..., f2 955 Chain = Chains[NumRegs-1]; 956 else 957 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains); 958 } 959 960 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching, 961 unsigned MatchingIdx, const SDLoc &dl, 962 SelectionDAG &DAG, 963 std::vector<SDValue> &Ops) const { 964 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 965 966 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size()); 967 if (HasMatching) 968 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx); 969 else if (!Regs.empty() && Register::isVirtualRegister(Regs.front())) { 970 // Put the register class of the virtual registers in the flag word. That 971 // way, later passes can recompute register class constraints for inline 972 // assembly as well as normal instructions. 973 // Don't do this for tied operands that can use the regclass information 974 // from the def. 975 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); 976 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front()); 977 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID()); 978 } 979 980 SDValue Res = DAG.getTargetConstant(Flag, dl, MVT::i32); 981 Ops.push_back(Res); 982 983 if (Code == InlineAsm::Kind_Clobber) { 984 // Clobbers should always have a 1:1 mapping with registers, and may 985 // reference registers that have illegal (e.g. vector) types. Hence, we 986 // shouldn't try to apply any sort of splitting logic to them. 987 assert(Regs.size() == RegVTs.size() && Regs.size() == ValueVTs.size() && 988 "No 1:1 mapping from clobbers to regs?"); 989 Register SP = TLI.getStackPointerRegisterToSaveRestore(); 990 (void)SP; 991 for (unsigned I = 0, E = ValueVTs.size(); I != E; ++I) { 992 Ops.push_back(DAG.getRegister(Regs[I], RegVTs[I])); 993 assert( 994 (Regs[I] != SP || 995 DAG.getMachineFunction().getFrameInfo().hasOpaqueSPAdjustment()) && 996 "If we clobbered the stack pointer, MFI should know about it."); 997 } 998 return; 999 } 1000 1001 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) { 1002 MVT RegisterVT = RegVTs[Value]; 1003 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value], 1004 RegisterVT); 1005 for (unsigned i = 0; i != NumRegs; ++i) { 1006 assert(Reg < Regs.size() && "Mismatch in # registers expected"); 1007 unsigned TheReg = Regs[Reg++]; 1008 Ops.push_back(DAG.getRegister(TheReg, RegisterVT)); 1009 } 1010 } 1011 } 1012 1013 SmallVector<std::pair<unsigned, TypeSize>, 4> 1014 RegsForValue::getRegsAndSizes() const { 1015 SmallVector<std::pair<unsigned, TypeSize>, 4> OutVec; 1016 unsigned I = 0; 1017 for (auto CountAndVT : zip_first(RegCount, RegVTs)) { 1018 unsigned RegCount = std::get<0>(CountAndVT); 1019 MVT RegisterVT = std::get<1>(CountAndVT); 1020 TypeSize RegisterSize = RegisterVT.getSizeInBits(); 1021 for (unsigned E = I + RegCount; I != E; ++I) 1022 OutVec.push_back(std::make_pair(Regs[I], RegisterSize)); 1023 } 1024 return OutVec; 1025 } 1026 1027 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis *aa, 1028 const TargetLibraryInfo *li) { 1029 AA = aa; 1030 GFI = gfi; 1031 LibInfo = li; 1032 Context = DAG.getContext(); 1033 LPadToCallSiteMap.clear(); 1034 SL->init(DAG.getTargetLoweringInfo(), TM, DAG.getDataLayout()); 1035 } 1036 1037 void SelectionDAGBuilder::clear() { 1038 NodeMap.clear(); 1039 UnusedArgNodeMap.clear(); 1040 PendingLoads.clear(); 1041 PendingExports.clear(); 1042 PendingConstrainedFP.clear(); 1043 PendingConstrainedFPStrict.clear(); 1044 CurInst = nullptr; 1045 HasTailCall = false; 1046 SDNodeOrder = LowestSDNodeOrder; 1047 StatepointLowering.clear(); 1048 } 1049 1050 void SelectionDAGBuilder::clearDanglingDebugInfo() { 1051 DanglingDebugInfoMap.clear(); 1052 } 1053 1054 // Update DAG root to include dependencies on Pending chains. 1055 SDValue SelectionDAGBuilder::updateRoot(SmallVectorImpl<SDValue> &Pending) { 1056 SDValue Root = DAG.getRoot(); 1057 1058 if (Pending.empty()) 1059 return Root; 1060 1061 // Add current root to PendingChains, unless we already indirectly 1062 // depend on it. 1063 if (Root.getOpcode() != ISD::EntryToken) { 1064 unsigned i = 0, e = Pending.size(); 1065 for (; i != e; ++i) { 1066 assert(Pending[i].getNode()->getNumOperands() > 1); 1067 if (Pending[i].getNode()->getOperand(0) == Root) 1068 break; // Don't add the root if we already indirectly depend on it. 1069 } 1070 1071 if (i == e) 1072 Pending.push_back(Root); 1073 } 1074 1075 if (Pending.size() == 1) 1076 Root = Pending[0]; 1077 else 1078 Root = DAG.getTokenFactor(getCurSDLoc(), Pending); 1079 1080 DAG.setRoot(Root); 1081 Pending.clear(); 1082 return Root; 1083 } 1084 1085 SDValue SelectionDAGBuilder::getMemoryRoot() { 1086 return updateRoot(PendingLoads); 1087 } 1088 1089 SDValue SelectionDAGBuilder::getRoot() { 1090 // Chain up all pending constrained intrinsics together with all 1091 // pending loads, by simply appending them to PendingLoads and 1092 // then calling getMemoryRoot(). 1093 PendingLoads.reserve(PendingLoads.size() + 1094 PendingConstrainedFP.size() + 1095 PendingConstrainedFPStrict.size()); 1096 PendingLoads.append(PendingConstrainedFP.begin(), 1097 PendingConstrainedFP.end()); 1098 PendingLoads.append(PendingConstrainedFPStrict.begin(), 1099 PendingConstrainedFPStrict.end()); 1100 PendingConstrainedFP.clear(); 1101 PendingConstrainedFPStrict.clear(); 1102 return getMemoryRoot(); 1103 } 1104 1105 SDValue SelectionDAGBuilder::getControlRoot() { 1106 // We need to emit pending fpexcept.strict constrained intrinsics, 1107 // so append them to the PendingExports list. 1108 PendingExports.append(PendingConstrainedFPStrict.begin(), 1109 PendingConstrainedFPStrict.end()); 1110 PendingConstrainedFPStrict.clear(); 1111 return updateRoot(PendingExports); 1112 } 1113 1114 void SelectionDAGBuilder::visit(const Instruction &I) { 1115 // Set up outgoing PHI node register values before emitting the terminator. 1116 if (I.isTerminator()) { 1117 HandlePHINodesInSuccessorBlocks(I.getParent()); 1118 } 1119 1120 // Increase the SDNodeOrder if dealing with a non-debug instruction. 1121 if (!isa<DbgInfoIntrinsic>(I)) 1122 ++SDNodeOrder; 1123 1124 CurInst = &I; 1125 1126 visit(I.getOpcode(), I); 1127 1128 if (!I.isTerminator() && !HasTailCall && 1129 !isa<GCStatepointInst>(I)) // statepoints handle their exports internally 1130 CopyToExportRegsIfNeeded(&I); 1131 1132 CurInst = nullptr; 1133 } 1134 1135 void SelectionDAGBuilder::visitPHI(const PHINode &) { 1136 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!"); 1137 } 1138 1139 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) { 1140 // Note: this doesn't use InstVisitor, because it has to work with 1141 // ConstantExpr's in addition to instructions. 1142 switch (Opcode) { 1143 default: llvm_unreachable("Unknown instruction type encountered!"); 1144 // Build the switch statement using the Instruction.def file. 1145 #define HANDLE_INST(NUM, OPCODE, CLASS) \ 1146 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break; 1147 #include "llvm/IR/Instruction.def" 1148 } 1149 } 1150 1151 void SelectionDAGBuilder::addDanglingDebugInfo(const DbgValueInst *DI, 1152 DebugLoc DL, unsigned Order) { 1153 // We treat variadic dbg_values differently at this stage. 1154 if (DI->hasArgList()) { 1155 // For variadic dbg_values we will now insert an undef. 1156 // FIXME: We can potentially recover these! 1157 SmallVector<SDDbgOperand, 2> Locs; 1158 for (const Value *V : DI->getValues()) { 1159 auto Undef = UndefValue::get(V->getType()); 1160 Locs.push_back(SDDbgOperand::fromConst(Undef)); 1161 } 1162 SDDbgValue *SDV = DAG.getDbgValueList( 1163 DI->getVariable(), DI->getExpression(), Locs, {}, 1164 /*IsIndirect=*/false, DL, Order, /*IsVariadic=*/true); 1165 DAG.AddDbgValue(SDV, /*isParameter=*/false); 1166 } else { 1167 // TODO: Dangling debug info will eventually either be resolved or produce 1168 // an Undef DBG_VALUE. However in the resolution case, a gap may appear 1169 // between the original dbg.value location and its resolved DBG_VALUE, 1170 // which we should ideally fill with an extra Undef DBG_VALUE. 1171 assert(DI->getNumVariableLocationOps() == 1 && 1172 "DbgValueInst without an ArgList should have a single location " 1173 "operand."); 1174 DanglingDebugInfoMap[DI->getValue(0)].emplace_back(DI, DL, Order); 1175 } 1176 } 1177 1178 void SelectionDAGBuilder::dropDanglingDebugInfo(const DILocalVariable *Variable, 1179 const DIExpression *Expr) { 1180 auto isMatchingDbgValue = [&](DanglingDebugInfo &DDI) { 1181 const DbgValueInst *DI = DDI.getDI(); 1182 DIVariable *DanglingVariable = DI->getVariable(); 1183 DIExpression *DanglingExpr = DI->getExpression(); 1184 if (DanglingVariable == Variable && Expr->fragmentsOverlap(DanglingExpr)) { 1185 LLVM_DEBUG(dbgs() << "Dropping dangling debug info for " << *DI << "\n"); 1186 return true; 1187 } 1188 return false; 1189 }; 1190 1191 for (auto &DDIMI : DanglingDebugInfoMap) { 1192 DanglingDebugInfoVector &DDIV = DDIMI.second; 1193 1194 // If debug info is to be dropped, run it through final checks to see 1195 // whether it can be salvaged. 1196 for (auto &DDI : DDIV) 1197 if (isMatchingDbgValue(DDI)) 1198 salvageUnresolvedDbgValue(DDI); 1199 1200 erase_if(DDIV, isMatchingDbgValue); 1201 } 1202 } 1203 1204 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V, 1205 // generate the debug data structures now that we've seen its definition. 1206 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V, 1207 SDValue Val) { 1208 auto DanglingDbgInfoIt = DanglingDebugInfoMap.find(V); 1209 if (DanglingDbgInfoIt == DanglingDebugInfoMap.end()) 1210 return; 1211 1212 DanglingDebugInfoVector &DDIV = DanglingDbgInfoIt->second; 1213 for (auto &DDI : DDIV) { 1214 const DbgValueInst *DI = DDI.getDI(); 1215 assert(!DI->hasArgList() && "Not implemented for variadic dbg_values"); 1216 assert(DI && "Ill-formed DanglingDebugInfo"); 1217 DebugLoc dl = DDI.getdl(); 1218 unsigned ValSDNodeOrder = Val.getNode()->getIROrder(); 1219 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder(); 1220 DILocalVariable *Variable = DI->getVariable(); 1221 DIExpression *Expr = DI->getExpression(); 1222 assert(Variable->isValidLocationForIntrinsic(dl) && 1223 "Expected inlined-at fields to agree"); 1224 SDDbgValue *SDV; 1225 if (Val.getNode()) { 1226 // FIXME: I doubt that it is correct to resolve a dangling DbgValue as a 1227 // FuncArgumentDbgValue (it would be hoisted to the function entry, and if 1228 // we couldn't resolve it directly when examining the DbgValue intrinsic 1229 // in the first place we should not be more successful here). Unless we 1230 // have some test case that prove this to be correct we should avoid 1231 // calling EmitFuncArgumentDbgValue here. 1232 if (!EmitFuncArgumentDbgValue(V, Variable, Expr, dl, 1233 FuncArgumentDbgValueKind::Value, Val)) { 1234 LLVM_DEBUG(dbgs() << "Resolve dangling debug info [order=" 1235 << DbgSDNodeOrder << "] for:\n " << *DI << "\n"); 1236 LLVM_DEBUG(dbgs() << " By mapping to:\n "; Val.dump()); 1237 // Increase the SDNodeOrder for the DbgValue here to make sure it is 1238 // inserted after the definition of Val when emitting the instructions 1239 // after ISel. An alternative could be to teach 1240 // ScheduleDAGSDNodes::EmitSchedule to delay the insertion properly. 1241 LLVM_DEBUG(if (ValSDNodeOrder > DbgSDNodeOrder) dbgs() 1242 << "changing SDNodeOrder from " << DbgSDNodeOrder << " to " 1243 << ValSDNodeOrder << "\n"); 1244 SDV = getDbgValue(Val, Variable, Expr, dl, 1245 std::max(DbgSDNodeOrder, ValSDNodeOrder)); 1246 DAG.AddDbgValue(SDV, false); 1247 } else 1248 LLVM_DEBUG(dbgs() << "Resolved dangling debug info for " << *DI 1249 << "in EmitFuncArgumentDbgValue\n"); 1250 } else { 1251 LLVM_DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n"); 1252 auto Undef = UndefValue::get(DDI.getDI()->getValue(0)->getType()); 1253 auto SDV = 1254 DAG.getConstantDbgValue(Variable, Expr, Undef, dl, DbgSDNodeOrder); 1255 DAG.AddDbgValue(SDV, false); 1256 } 1257 } 1258 DDIV.clear(); 1259 } 1260 1261 void SelectionDAGBuilder::salvageUnresolvedDbgValue(DanglingDebugInfo &DDI) { 1262 // TODO: For the variadic implementation, instead of only checking the fail 1263 // state of `handleDebugValue`, we need know specifically which values were 1264 // invalid, so that we attempt to salvage only those values when processing 1265 // a DIArgList. 1266 assert(!DDI.getDI()->hasArgList() && 1267 "Not implemented for variadic dbg_values"); 1268 Value *V = DDI.getDI()->getValue(0); 1269 DILocalVariable *Var = DDI.getDI()->getVariable(); 1270 DIExpression *Expr = DDI.getDI()->getExpression(); 1271 DebugLoc DL = DDI.getdl(); 1272 DebugLoc InstDL = DDI.getDI()->getDebugLoc(); 1273 unsigned SDOrder = DDI.getSDNodeOrder(); 1274 // Currently we consider only dbg.value intrinsics -- we tell the salvager 1275 // that DW_OP_stack_value is desired. 1276 assert(isa<DbgValueInst>(DDI.getDI())); 1277 bool StackValue = true; 1278 1279 // Can this Value can be encoded without any further work? 1280 if (handleDebugValue(V, Var, Expr, DL, InstDL, SDOrder, /*IsVariadic=*/false)) 1281 return; 1282 1283 // Attempt to salvage back through as many instructions as possible. Bail if 1284 // a non-instruction is seen, such as a constant expression or global 1285 // variable. FIXME: Further work could recover those too. 1286 while (isa<Instruction>(V)) { 1287 Instruction &VAsInst = *cast<Instruction>(V); 1288 // Temporary "0", awaiting real implementation. 1289 SmallVector<uint64_t, 16> Ops; 1290 SmallVector<Value *, 4> AdditionalValues; 1291 V = salvageDebugInfoImpl(VAsInst, Expr->getNumLocationOperands(), Ops, 1292 AdditionalValues); 1293 // If we cannot salvage any further, and haven't yet found a suitable debug 1294 // expression, bail out. 1295 if (!V) 1296 break; 1297 1298 // TODO: If AdditionalValues isn't empty, then the salvage can only be 1299 // represented with a DBG_VALUE_LIST, so we give up. When we have support 1300 // here for variadic dbg_values, remove that condition. 1301 if (!AdditionalValues.empty()) 1302 break; 1303 1304 // New value and expr now represent this debuginfo. 1305 Expr = DIExpression::appendOpsToArg(Expr, Ops, 0, StackValue); 1306 1307 // Some kind of simplification occurred: check whether the operand of the 1308 // salvaged debug expression can be encoded in this DAG. 1309 if (handleDebugValue(V, Var, Expr, DL, InstDL, SDOrder, 1310 /*IsVariadic=*/false)) { 1311 LLVM_DEBUG(dbgs() << "Salvaged debug location info for:\n " 1312 << *DDI.getDI() << "\nBy stripping back to:\n " << *V); 1313 return; 1314 } 1315 } 1316 1317 // This was the final opportunity to salvage this debug information, and it 1318 // couldn't be done. Place an undef DBG_VALUE at this location to terminate 1319 // any earlier variable location. 1320 auto Undef = UndefValue::get(DDI.getDI()->getValue(0)->getType()); 1321 auto SDV = DAG.getConstantDbgValue(Var, Expr, Undef, DL, SDNodeOrder); 1322 DAG.AddDbgValue(SDV, false); 1323 1324 LLVM_DEBUG(dbgs() << "Dropping debug value info for:\n " << *DDI.getDI() 1325 << "\n"); 1326 LLVM_DEBUG(dbgs() << " Last seen at:\n " << *DDI.getDI()->getOperand(0) 1327 << "\n"); 1328 } 1329 1330 bool SelectionDAGBuilder::handleDebugValue(ArrayRef<const Value *> Values, 1331 DILocalVariable *Var, 1332 DIExpression *Expr, DebugLoc dl, 1333 DebugLoc InstDL, unsigned Order, 1334 bool IsVariadic) { 1335 if (Values.empty()) 1336 return true; 1337 SmallVector<SDDbgOperand> LocationOps; 1338 SmallVector<SDNode *> Dependencies; 1339 for (const Value *V : Values) { 1340 // Constant value. 1341 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V) || 1342 isa<ConstantPointerNull>(V)) { 1343 LocationOps.emplace_back(SDDbgOperand::fromConst(V)); 1344 continue; 1345 } 1346 1347 // If the Value is a frame index, we can create a FrameIndex debug value 1348 // without relying on the DAG at all. 1349 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 1350 auto SI = FuncInfo.StaticAllocaMap.find(AI); 1351 if (SI != FuncInfo.StaticAllocaMap.end()) { 1352 LocationOps.emplace_back(SDDbgOperand::fromFrameIdx(SI->second)); 1353 continue; 1354 } 1355 } 1356 1357 // Do not use getValue() in here; we don't want to generate code at 1358 // this point if it hasn't been done yet. 1359 SDValue N = NodeMap[V]; 1360 if (!N.getNode() && isa<Argument>(V)) // Check unused arguments map. 1361 N = UnusedArgNodeMap[V]; 1362 if (N.getNode()) { 1363 // Only emit func arg dbg value for non-variadic dbg.values for now. 1364 if (!IsVariadic && 1365 EmitFuncArgumentDbgValue(V, Var, Expr, dl, 1366 FuncArgumentDbgValueKind::Value, N)) 1367 return true; 1368 if (auto *FISDN = dyn_cast<FrameIndexSDNode>(N.getNode())) { 1369 // Construct a FrameIndexDbgValue for FrameIndexSDNodes so we can 1370 // describe stack slot locations. 1371 // 1372 // Consider "int x = 0; int *px = &x;". There are two kinds of 1373 // interesting debug values here after optimization: 1374 // 1375 // dbg.value(i32* %px, !"int *px", !DIExpression()), and 1376 // dbg.value(i32* %px, !"int x", !DIExpression(DW_OP_deref)) 1377 // 1378 // Both describe the direct values of their associated variables. 1379 Dependencies.push_back(N.getNode()); 1380 LocationOps.emplace_back(SDDbgOperand::fromFrameIdx(FISDN->getIndex())); 1381 continue; 1382 } 1383 LocationOps.emplace_back( 1384 SDDbgOperand::fromNode(N.getNode(), N.getResNo())); 1385 continue; 1386 } 1387 1388 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 1389 // Special rules apply for the first dbg.values of parameter variables in a 1390 // function. Identify them by the fact they reference Argument Values, that 1391 // they're parameters, and they are parameters of the current function. We 1392 // need to let them dangle until they get an SDNode. 1393 bool IsParamOfFunc = 1394 isa<Argument>(V) && Var->isParameter() && !InstDL.getInlinedAt(); 1395 if (IsParamOfFunc) 1396 return false; 1397 1398 // The value is not used in this block yet (or it would have an SDNode). 1399 // We still want the value to appear for the user if possible -- if it has 1400 // an associated VReg, we can refer to that instead. 1401 auto VMI = FuncInfo.ValueMap.find(V); 1402 if (VMI != FuncInfo.ValueMap.end()) { 1403 unsigned Reg = VMI->second; 1404 // If this is a PHI node, it may be split up into several MI PHI nodes 1405 // (in FunctionLoweringInfo::set). 1406 RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), Reg, 1407 V->getType(), None); 1408 if (RFV.occupiesMultipleRegs()) { 1409 // FIXME: We could potentially support variadic dbg_values here. 1410 if (IsVariadic) 1411 return false; 1412 unsigned Offset = 0; 1413 unsigned BitsToDescribe = 0; 1414 if (auto VarSize = Var->getSizeInBits()) 1415 BitsToDescribe = *VarSize; 1416 if (auto Fragment = Expr->getFragmentInfo()) 1417 BitsToDescribe = Fragment->SizeInBits; 1418 for (const auto &RegAndSize : RFV.getRegsAndSizes()) { 1419 // Bail out if all bits are described already. 1420 if (Offset >= BitsToDescribe) 1421 break; 1422 // TODO: handle scalable vectors. 1423 unsigned RegisterSize = RegAndSize.second; 1424 unsigned FragmentSize = (Offset + RegisterSize > BitsToDescribe) 1425 ? BitsToDescribe - Offset 1426 : RegisterSize; 1427 auto FragmentExpr = DIExpression::createFragmentExpression( 1428 Expr, Offset, FragmentSize); 1429 if (!FragmentExpr) 1430 continue; 1431 SDDbgValue *SDV = DAG.getVRegDbgValue( 1432 Var, *FragmentExpr, RegAndSize.first, false, dl, SDNodeOrder); 1433 DAG.AddDbgValue(SDV, false); 1434 Offset += RegisterSize; 1435 } 1436 return true; 1437 } 1438 // We can use simple vreg locations for variadic dbg_values as well. 1439 LocationOps.emplace_back(SDDbgOperand::fromVReg(Reg)); 1440 continue; 1441 } 1442 // We failed to create a SDDbgOperand for V. 1443 return false; 1444 } 1445 1446 // We have created a SDDbgOperand for each Value in Values. 1447 // Should use Order instead of SDNodeOrder? 1448 assert(!LocationOps.empty()); 1449 SDDbgValue *SDV = 1450 DAG.getDbgValueList(Var, Expr, LocationOps, Dependencies, 1451 /*IsIndirect=*/false, dl, SDNodeOrder, IsVariadic); 1452 DAG.AddDbgValue(SDV, /*isParameter=*/false); 1453 return true; 1454 } 1455 1456 void SelectionDAGBuilder::resolveOrClearDbgInfo() { 1457 // Try to fixup any remaining dangling debug info -- and drop it if we can't. 1458 for (auto &Pair : DanglingDebugInfoMap) 1459 for (auto &DDI : Pair.second) 1460 salvageUnresolvedDbgValue(DDI); 1461 clearDanglingDebugInfo(); 1462 } 1463 1464 /// getCopyFromRegs - If there was virtual register allocated for the value V 1465 /// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise. 1466 SDValue SelectionDAGBuilder::getCopyFromRegs(const Value *V, Type *Ty) { 1467 DenseMap<const Value *, Register>::iterator It = FuncInfo.ValueMap.find(V); 1468 SDValue Result; 1469 1470 if (It != FuncInfo.ValueMap.end()) { 1471 Register InReg = It->second; 1472 1473 RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(), 1474 DAG.getDataLayout(), InReg, Ty, 1475 None); // This is not an ABI copy. 1476 SDValue Chain = DAG.getEntryNode(); 1477 Result = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, 1478 V); 1479 resolveDanglingDebugInfo(V, Result); 1480 } 1481 1482 return Result; 1483 } 1484 1485 /// getValue - Return an SDValue for the given Value. 1486 SDValue SelectionDAGBuilder::getValue(const Value *V) { 1487 // If we already have an SDValue for this value, use it. It's important 1488 // to do this first, so that we don't create a CopyFromReg if we already 1489 // have a regular SDValue. 1490 SDValue &N = NodeMap[V]; 1491 if (N.getNode()) return N; 1492 1493 // If there's a virtual register allocated and initialized for this 1494 // value, use it. 1495 if (SDValue copyFromReg = getCopyFromRegs(V, V->getType())) 1496 return copyFromReg; 1497 1498 // Otherwise create a new SDValue and remember it. 1499 SDValue Val = getValueImpl(V); 1500 NodeMap[V] = Val; 1501 resolveDanglingDebugInfo(V, Val); 1502 return Val; 1503 } 1504 1505 /// getNonRegisterValue - Return an SDValue for the given Value, but 1506 /// don't look in FuncInfo.ValueMap for a virtual register. 1507 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) { 1508 // If we already have an SDValue for this value, use it. 1509 SDValue &N = NodeMap[V]; 1510 if (N.getNode()) { 1511 if (isa<ConstantSDNode>(N) || isa<ConstantFPSDNode>(N)) { 1512 // Remove the debug location from the node as the node is about to be used 1513 // in a location which may differ from the original debug location. This 1514 // is relevant to Constant and ConstantFP nodes because they can appear 1515 // as constant expressions inside PHI nodes. 1516 N->setDebugLoc(DebugLoc()); 1517 } 1518 return N; 1519 } 1520 1521 // Otherwise create a new SDValue and remember it. 1522 SDValue Val = getValueImpl(V); 1523 NodeMap[V] = Val; 1524 resolveDanglingDebugInfo(V, Val); 1525 return Val; 1526 } 1527 1528 /// getValueImpl - Helper function for getValue and getNonRegisterValue. 1529 /// Create an SDValue for the given value. 1530 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) { 1531 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 1532 1533 if (const Constant *C = dyn_cast<Constant>(V)) { 1534 EVT VT = TLI.getValueType(DAG.getDataLayout(), V->getType(), true); 1535 1536 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C)) 1537 return DAG.getConstant(*CI, getCurSDLoc(), VT); 1538 1539 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C)) 1540 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT); 1541 1542 if (isa<ConstantPointerNull>(C)) { 1543 unsigned AS = V->getType()->getPointerAddressSpace(); 1544 return DAG.getConstant(0, getCurSDLoc(), 1545 TLI.getPointerTy(DAG.getDataLayout(), AS)); 1546 } 1547 1548 if (match(C, m_VScale(DAG.getDataLayout()))) 1549 return DAG.getVScale(getCurSDLoc(), VT, APInt(VT.getSizeInBits(), 1)); 1550 1551 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C)) 1552 return DAG.getConstantFP(*CFP, getCurSDLoc(), VT); 1553 1554 if (isa<UndefValue>(C) && !V->getType()->isAggregateType()) 1555 return DAG.getUNDEF(VT); 1556 1557 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 1558 visit(CE->getOpcode(), *CE); 1559 SDValue N1 = NodeMap[V]; 1560 assert(N1.getNode() && "visit didn't populate the NodeMap!"); 1561 return N1; 1562 } 1563 1564 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) { 1565 SmallVector<SDValue, 4> Constants; 1566 for (const Use &U : C->operands()) { 1567 SDNode *Val = getValue(U).getNode(); 1568 // If the operand is an empty aggregate, there are no values. 1569 if (!Val) continue; 1570 // Add each leaf value from the operand to the Constants list 1571 // to form a flattened list of all the values. 1572 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) 1573 Constants.push_back(SDValue(Val, i)); 1574 } 1575 1576 return DAG.getMergeValues(Constants, getCurSDLoc()); 1577 } 1578 1579 if (const ConstantDataSequential *CDS = 1580 dyn_cast<ConstantDataSequential>(C)) { 1581 SmallVector<SDValue, 4> Ops; 1582 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) { 1583 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode(); 1584 // Add each leaf value from the operand to the Constants list 1585 // to form a flattened list of all the values. 1586 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) 1587 Ops.push_back(SDValue(Val, i)); 1588 } 1589 1590 if (isa<ArrayType>(CDS->getType())) 1591 return DAG.getMergeValues(Ops, getCurSDLoc()); 1592 return NodeMap[V] = DAG.getBuildVector(VT, getCurSDLoc(), Ops); 1593 } 1594 1595 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) { 1596 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && 1597 "Unknown struct or array constant!"); 1598 1599 SmallVector<EVT, 4> ValueVTs; 1600 ComputeValueVTs(TLI, DAG.getDataLayout(), C->getType(), ValueVTs); 1601 unsigned NumElts = ValueVTs.size(); 1602 if (NumElts == 0) 1603 return SDValue(); // empty struct 1604 SmallVector<SDValue, 4> Constants(NumElts); 1605 for (unsigned i = 0; i != NumElts; ++i) { 1606 EVT EltVT = ValueVTs[i]; 1607 if (isa<UndefValue>(C)) 1608 Constants[i] = DAG.getUNDEF(EltVT); 1609 else if (EltVT.isFloatingPoint()) 1610 Constants[i] = DAG.getConstantFP(0, getCurSDLoc(), EltVT); 1611 else 1612 Constants[i] = DAG.getConstant(0, getCurSDLoc(), EltVT); 1613 } 1614 1615 return DAG.getMergeValues(Constants, getCurSDLoc()); 1616 } 1617 1618 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C)) 1619 return DAG.getBlockAddress(BA, VT); 1620 1621 if (const auto *Equiv = dyn_cast<DSOLocalEquivalent>(C)) 1622 return getValue(Equiv->getGlobalValue()); 1623 1624 if (const auto *NC = dyn_cast<NoCFIValue>(C)) 1625 return getValue(NC->getGlobalValue()); 1626 1627 VectorType *VecTy = cast<VectorType>(V->getType()); 1628 1629 // Now that we know the number and type of the elements, get that number of 1630 // elements into the Ops array based on what kind of constant it is. 1631 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) { 1632 SmallVector<SDValue, 16> Ops; 1633 unsigned NumElements = cast<FixedVectorType>(VecTy)->getNumElements(); 1634 for (unsigned i = 0; i != NumElements; ++i) 1635 Ops.push_back(getValue(CV->getOperand(i))); 1636 1637 return NodeMap[V] = DAG.getBuildVector(VT, getCurSDLoc(), Ops); 1638 } 1639 1640 if (isa<ConstantAggregateZero>(C)) { 1641 EVT EltVT = 1642 TLI.getValueType(DAG.getDataLayout(), VecTy->getElementType()); 1643 1644 SDValue Op; 1645 if (EltVT.isFloatingPoint()) 1646 Op = DAG.getConstantFP(0, getCurSDLoc(), EltVT); 1647 else 1648 Op = DAG.getConstant(0, getCurSDLoc(), EltVT); 1649 1650 if (isa<ScalableVectorType>(VecTy)) 1651 return NodeMap[V] = DAG.getSplatVector(VT, getCurSDLoc(), Op); 1652 1653 SmallVector<SDValue, 16> Ops; 1654 Ops.assign(cast<FixedVectorType>(VecTy)->getNumElements(), Op); 1655 return NodeMap[V] = DAG.getBuildVector(VT, getCurSDLoc(), Ops); 1656 } 1657 1658 llvm_unreachable("Unknown vector constant"); 1659 } 1660 1661 // If this is a static alloca, generate it as the frameindex instead of 1662 // computation. 1663 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 1664 DenseMap<const AllocaInst*, int>::iterator SI = 1665 FuncInfo.StaticAllocaMap.find(AI); 1666 if (SI != FuncInfo.StaticAllocaMap.end()) 1667 return DAG.getFrameIndex(SI->second, 1668 TLI.getFrameIndexTy(DAG.getDataLayout())); 1669 } 1670 1671 // If this is an instruction which fast-isel has deferred, select it now. 1672 if (const Instruction *Inst = dyn_cast<Instruction>(V)) { 1673 unsigned InReg = FuncInfo.InitializeRegForValue(Inst); 1674 1675 RegsForValue RFV(*DAG.getContext(), TLI, DAG.getDataLayout(), InReg, 1676 Inst->getType(), None); 1677 SDValue Chain = DAG.getEntryNode(); 1678 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V); 1679 } 1680 1681 if (const MetadataAsValue *MD = dyn_cast<MetadataAsValue>(V)) 1682 return DAG.getMDNode(cast<MDNode>(MD->getMetadata())); 1683 1684 if (const auto *BB = dyn_cast<BasicBlock>(V)) 1685 return DAG.getBasicBlock(FuncInfo.MBBMap[BB]); 1686 1687 llvm_unreachable("Can't get register for value!"); 1688 } 1689 1690 void SelectionDAGBuilder::visitCatchPad(const CatchPadInst &I) { 1691 auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn()); 1692 bool IsMSVCCXX = Pers == EHPersonality::MSVC_CXX; 1693 bool IsCoreCLR = Pers == EHPersonality::CoreCLR; 1694 bool IsSEH = isAsynchronousEHPersonality(Pers); 1695 MachineBasicBlock *CatchPadMBB = FuncInfo.MBB; 1696 if (!IsSEH) 1697 CatchPadMBB->setIsEHScopeEntry(); 1698 // In MSVC C++ and CoreCLR, catchblocks are funclets and need prologues. 1699 if (IsMSVCCXX || IsCoreCLR) 1700 CatchPadMBB->setIsEHFuncletEntry(); 1701 } 1702 1703 void SelectionDAGBuilder::visitCatchRet(const CatchReturnInst &I) { 1704 // Update machine-CFG edge. 1705 MachineBasicBlock *TargetMBB = FuncInfo.MBBMap[I.getSuccessor()]; 1706 FuncInfo.MBB->addSuccessor(TargetMBB); 1707 TargetMBB->setIsEHCatchretTarget(true); 1708 DAG.getMachineFunction().setHasEHCatchret(true); 1709 1710 auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn()); 1711 bool IsSEH = isAsynchronousEHPersonality(Pers); 1712 if (IsSEH) { 1713 // If this is not a fall-through branch or optimizations are switched off, 1714 // emit the branch. 1715 if (TargetMBB != NextBlock(FuncInfo.MBB) || 1716 TM.getOptLevel() == CodeGenOpt::None) 1717 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, 1718 getControlRoot(), DAG.getBasicBlock(TargetMBB))); 1719 return; 1720 } 1721 1722 // Figure out the funclet membership for the catchret's successor. 1723 // This will be used by the FuncletLayout pass to determine how to order the 1724 // BB's. 1725 // A 'catchret' returns to the outer scope's color. 1726 Value *ParentPad = I.getCatchSwitchParentPad(); 1727 const BasicBlock *SuccessorColor; 1728 if (isa<ConstantTokenNone>(ParentPad)) 1729 SuccessorColor = &FuncInfo.Fn->getEntryBlock(); 1730 else 1731 SuccessorColor = cast<Instruction>(ParentPad)->getParent(); 1732 assert(SuccessorColor && "No parent funclet for catchret!"); 1733 MachineBasicBlock *SuccessorColorMBB = FuncInfo.MBBMap[SuccessorColor]; 1734 assert(SuccessorColorMBB && "No MBB for SuccessorColor!"); 1735 1736 // Create the terminator node. 1737 SDValue Ret = DAG.getNode(ISD::CATCHRET, getCurSDLoc(), MVT::Other, 1738 getControlRoot(), DAG.getBasicBlock(TargetMBB), 1739 DAG.getBasicBlock(SuccessorColorMBB)); 1740 DAG.setRoot(Ret); 1741 } 1742 1743 void SelectionDAGBuilder::visitCleanupPad(const CleanupPadInst &CPI) { 1744 // Don't emit any special code for the cleanuppad instruction. It just marks 1745 // the start of an EH scope/funclet. 1746 FuncInfo.MBB->setIsEHScopeEntry(); 1747 auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn()); 1748 if (Pers != EHPersonality::Wasm_CXX) { 1749 FuncInfo.MBB->setIsEHFuncletEntry(); 1750 FuncInfo.MBB->setIsCleanupFuncletEntry(); 1751 } 1752 } 1753 1754 // In wasm EH, even though a catchpad may not catch an exception if a tag does 1755 // not match, it is OK to add only the first unwind destination catchpad to the 1756 // successors, because there will be at least one invoke instruction within the 1757 // catch scope that points to the next unwind destination, if one exists, so 1758 // CFGSort cannot mess up with BB sorting order. 1759 // (All catchpads with 'catch (type)' clauses have a 'llvm.rethrow' intrinsic 1760 // call within them, and catchpads only consisting of 'catch (...)' have a 1761 // '__cxa_end_catch' call within them, both of which generate invokes in case 1762 // the next unwind destination exists, i.e., the next unwind destination is not 1763 // the caller.) 1764 // 1765 // Having at most one EH pad successor is also simpler and helps later 1766 // transformations. 1767 // 1768 // For example, 1769 // current: 1770 // invoke void @foo to ... unwind label %catch.dispatch 1771 // catch.dispatch: 1772 // %0 = catchswitch within ... [label %catch.start] unwind label %next 1773 // catch.start: 1774 // ... 1775 // ... in this BB or some other child BB dominated by this BB there will be an 1776 // invoke that points to 'next' BB as an unwind destination 1777 // 1778 // next: ; We don't need to add this to 'current' BB's successor 1779 // ... 1780 static void findWasmUnwindDestinations( 1781 FunctionLoweringInfo &FuncInfo, const BasicBlock *EHPadBB, 1782 BranchProbability Prob, 1783 SmallVectorImpl<std::pair<MachineBasicBlock *, BranchProbability>> 1784 &UnwindDests) { 1785 while (EHPadBB) { 1786 const Instruction *Pad = EHPadBB->getFirstNonPHI(); 1787 if (isa<CleanupPadInst>(Pad)) { 1788 // Stop on cleanup pads. 1789 UnwindDests.emplace_back(FuncInfo.MBBMap[EHPadBB], Prob); 1790 UnwindDests.back().first->setIsEHScopeEntry(); 1791 break; 1792 } else if (auto *CatchSwitch = dyn_cast<CatchSwitchInst>(Pad)) { 1793 // Add the catchpad handlers to the possible destinations. We don't 1794 // continue to the unwind destination of the catchswitch for wasm. 1795 for (const BasicBlock *CatchPadBB : CatchSwitch->handlers()) { 1796 UnwindDests.emplace_back(FuncInfo.MBBMap[CatchPadBB], Prob); 1797 UnwindDests.back().first->setIsEHScopeEntry(); 1798 } 1799 break; 1800 } else { 1801 continue; 1802 } 1803 } 1804 } 1805 1806 /// When an invoke or a cleanupret unwinds to the next EH pad, there are 1807 /// many places it could ultimately go. In the IR, we have a single unwind 1808 /// destination, but in the machine CFG, we enumerate all the possible blocks. 1809 /// This function skips over imaginary basic blocks that hold catchswitch 1810 /// instructions, and finds all the "real" machine 1811 /// basic block destinations. As those destinations may not be successors of 1812 /// EHPadBB, here we also calculate the edge probability to those destinations. 1813 /// The passed-in Prob is the edge probability to EHPadBB. 1814 static void findUnwindDestinations( 1815 FunctionLoweringInfo &FuncInfo, const BasicBlock *EHPadBB, 1816 BranchProbability Prob, 1817 SmallVectorImpl<std::pair<MachineBasicBlock *, BranchProbability>> 1818 &UnwindDests) { 1819 EHPersonality Personality = 1820 classifyEHPersonality(FuncInfo.Fn->getPersonalityFn()); 1821 bool IsMSVCCXX = Personality == EHPersonality::MSVC_CXX; 1822 bool IsCoreCLR = Personality == EHPersonality::CoreCLR; 1823 bool IsWasmCXX = Personality == EHPersonality::Wasm_CXX; 1824 bool IsSEH = isAsynchronousEHPersonality(Personality); 1825 1826 if (IsWasmCXX) { 1827 findWasmUnwindDestinations(FuncInfo, EHPadBB, Prob, UnwindDests); 1828 assert(UnwindDests.size() <= 1 && 1829 "There should be at most one unwind destination for wasm"); 1830 return; 1831 } 1832 1833 while (EHPadBB) { 1834 const Instruction *Pad = EHPadBB->getFirstNonPHI(); 1835 BasicBlock *NewEHPadBB = nullptr; 1836 if (isa<LandingPadInst>(Pad)) { 1837 // Stop on landingpads. They are not funclets. 1838 UnwindDests.emplace_back(FuncInfo.MBBMap[EHPadBB], Prob); 1839 break; 1840 } else if (isa<CleanupPadInst>(Pad)) { 1841 // Stop on cleanup pads. Cleanups are always funclet entries for all known 1842 // personalities. 1843 UnwindDests.emplace_back(FuncInfo.MBBMap[EHPadBB], Prob); 1844 UnwindDests.back().first->setIsEHScopeEntry(); 1845 UnwindDests.back().first->setIsEHFuncletEntry(); 1846 break; 1847 } else if (auto *CatchSwitch = dyn_cast<CatchSwitchInst>(Pad)) { 1848 // Add the catchpad handlers to the possible destinations. 1849 for (const BasicBlock *CatchPadBB : CatchSwitch->handlers()) { 1850 UnwindDests.emplace_back(FuncInfo.MBBMap[CatchPadBB], Prob); 1851 // For MSVC++ and the CLR, catchblocks are funclets and need prologues. 1852 if (IsMSVCCXX || IsCoreCLR) 1853 UnwindDests.back().first->setIsEHFuncletEntry(); 1854 if (!IsSEH) 1855 UnwindDests.back().first->setIsEHScopeEntry(); 1856 } 1857 NewEHPadBB = CatchSwitch->getUnwindDest(); 1858 } else { 1859 continue; 1860 } 1861 1862 BranchProbabilityInfo *BPI = FuncInfo.BPI; 1863 if (BPI && NewEHPadBB) 1864 Prob *= BPI->getEdgeProbability(EHPadBB, NewEHPadBB); 1865 EHPadBB = NewEHPadBB; 1866 } 1867 } 1868 1869 void SelectionDAGBuilder::visitCleanupRet(const CleanupReturnInst &I) { 1870 // Update successor info. 1871 SmallVector<std::pair<MachineBasicBlock *, BranchProbability>, 1> UnwindDests; 1872 auto UnwindDest = I.getUnwindDest(); 1873 BranchProbabilityInfo *BPI = FuncInfo.BPI; 1874 BranchProbability UnwindDestProb = 1875 (BPI && UnwindDest) 1876 ? BPI->getEdgeProbability(FuncInfo.MBB->getBasicBlock(), UnwindDest) 1877 : BranchProbability::getZero(); 1878 findUnwindDestinations(FuncInfo, UnwindDest, UnwindDestProb, UnwindDests); 1879 for (auto &UnwindDest : UnwindDests) { 1880 UnwindDest.first->setIsEHPad(); 1881 addSuccessorWithProb(FuncInfo.MBB, UnwindDest.first, UnwindDest.second); 1882 } 1883 FuncInfo.MBB->normalizeSuccProbs(); 1884 1885 // Create the terminator node. 1886 SDValue Ret = 1887 DAG.getNode(ISD::CLEANUPRET, getCurSDLoc(), MVT::Other, getControlRoot()); 1888 DAG.setRoot(Ret); 1889 } 1890 1891 void SelectionDAGBuilder::visitCatchSwitch(const CatchSwitchInst &CSI) { 1892 report_fatal_error("visitCatchSwitch not yet implemented!"); 1893 } 1894 1895 void SelectionDAGBuilder::visitRet(const ReturnInst &I) { 1896 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 1897 auto &DL = DAG.getDataLayout(); 1898 SDValue Chain = getControlRoot(); 1899 SmallVector<ISD::OutputArg, 8> Outs; 1900 SmallVector<SDValue, 8> OutVals; 1901 1902 // Calls to @llvm.experimental.deoptimize don't generate a return value, so 1903 // lower 1904 // 1905 // %val = call <ty> @llvm.experimental.deoptimize() 1906 // ret <ty> %val 1907 // 1908 // differently. 1909 if (I.getParent()->getTerminatingDeoptimizeCall()) { 1910 LowerDeoptimizingReturn(); 1911 return; 1912 } 1913 1914 if (!FuncInfo.CanLowerReturn) { 1915 unsigned DemoteReg = FuncInfo.DemoteRegister; 1916 const Function *F = I.getParent()->getParent(); 1917 1918 // Emit a store of the return value through the virtual register. 1919 // Leave Outs empty so that LowerReturn won't try to load return 1920 // registers the usual way. 1921 SmallVector<EVT, 1> PtrValueVTs; 1922 ComputeValueVTs(TLI, DL, 1923 F->getReturnType()->getPointerTo( 1924 DAG.getDataLayout().getAllocaAddrSpace()), 1925 PtrValueVTs); 1926 1927 SDValue RetPtr = 1928 DAG.getCopyFromReg(Chain, getCurSDLoc(), DemoteReg, PtrValueVTs[0]); 1929 SDValue RetOp = getValue(I.getOperand(0)); 1930 1931 SmallVector<EVT, 4> ValueVTs, MemVTs; 1932 SmallVector<uint64_t, 4> Offsets; 1933 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs, &MemVTs, 1934 &Offsets); 1935 unsigned NumValues = ValueVTs.size(); 1936 1937 SmallVector<SDValue, 4> Chains(NumValues); 1938 Align BaseAlign = DL.getPrefTypeAlign(I.getOperand(0)->getType()); 1939 for (unsigned i = 0; i != NumValues; ++i) { 1940 // An aggregate return value cannot wrap around the address space, so 1941 // offsets to its parts don't wrap either. 1942 SDValue Ptr = DAG.getObjectPtrOffset(getCurSDLoc(), RetPtr, 1943 TypeSize::Fixed(Offsets[i])); 1944 1945 SDValue Val = RetOp.getValue(RetOp.getResNo() + i); 1946 if (MemVTs[i] != ValueVTs[i]) 1947 Val = DAG.getPtrExtOrTrunc(Val, getCurSDLoc(), MemVTs[i]); 1948 Chains[i] = DAG.getStore( 1949 Chain, getCurSDLoc(), Val, 1950 // FIXME: better loc info would be nice. 1951 Ptr, MachinePointerInfo::getUnknownStack(DAG.getMachineFunction()), 1952 commonAlignment(BaseAlign, Offsets[i])); 1953 } 1954 1955 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), 1956 MVT::Other, Chains); 1957 } else if (I.getNumOperands() != 0) { 1958 SmallVector<EVT, 4> ValueVTs; 1959 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs); 1960 unsigned NumValues = ValueVTs.size(); 1961 if (NumValues) { 1962 SDValue RetOp = getValue(I.getOperand(0)); 1963 1964 const Function *F = I.getParent()->getParent(); 1965 1966 bool NeedsRegBlock = TLI.functionArgumentNeedsConsecutiveRegisters( 1967 I.getOperand(0)->getType(), F->getCallingConv(), 1968 /*IsVarArg*/ false, DL); 1969 1970 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1971 if (F->getAttributes().hasRetAttr(Attribute::SExt)) 1972 ExtendKind = ISD::SIGN_EXTEND; 1973 else if (F->getAttributes().hasRetAttr(Attribute::ZExt)) 1974 ExtendKind = ISD::ZERO_EXTEND; 1975 1976 LLVMContext &Context = F->getContext(); 1977 bool RetInReg = F->getAttributes().hasRetAttr(Attribute::InReg); 1978 1979 for (unsigned j = 0; j != NumValues; ++j) { 1980 EVT VT = ValueVTs[j]; 1981 1982 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) 1983 VT = TLI.getTypeForExtReturn(Context, VT, ExtendKind); 1984 1985 CallingConv::ID CC = F->getCallingConv(); 1986 1987 unsigned NumParts = TLI.getNumRegistersForCallingConv(Context, CC, VT); 1988 MVT PartVT = TLI.getRegisterTypeForCallingConv(Context, CC, VT); 1989 SmallVector<SDValue, 4> Parts(NumParts); 1990 getCopyToParts(DAG, getCurSDLoc(), 1991 SDValue(RetOp.getNode(), RetOp.getResNo() + j), 1992 &Parts[0], NumParts, PartVT, &I, CC, ExtendKind); 1993 1994 // 'inreg' on function refers to return value 1995 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1996 if (RetInReg) 1997 Flags.setInReg(); 1998 1999 if (I.getOperand(0)->getType()->isPointerTy()) { 2000 Flags.setPointer(); 2001 Flags.setPointerAddrSpace( 2002 cast<PointerType>(I.getOperand(0)->getType())->getAddressSpace()); 2003 } 2004 2005 if (NeedsRegBlock) { 2006 Flags.setInConsecutiveRegs(); 2007 if (j == NumValues - 1) 2008 Flags.setInConsecutiveRegsLast(); 2009 } 2010 2011 // Propagate extension type if any 2012 if (ExtendKind == ISD::SIGN_EXTEND) 2013 Flags.setSExt(); 2014 else if (ExtendKind == ISD::ZERO_EXTEND) 2015 Flags.setZExt(); 2016 2017 for (unsigned i = 0; i < NumParts; ++i) { 2018 Outs.push_back(ISD::OutputArg(Flags, 2019 Parts[i].getValueType().getSimpleVT(), 2020 VT, /*isfixed=*/true, 0, 0)); 2021 OutVals.push_back(Parts[i]); 2022 } 2023 } 2024 } 2025 } 2026 2027 // Push in swifterror virtual register as the last element of Outs. This makes 2028 // sure swifterror virtual register will be returned in the swifterror 2029 // physical register. 2030 const Function *F = I.getParent()->getParent(); 2031 if (TLI.supportSwiftError() && 2032 F->getAttributes().hasAttrSomewhere(Attribute::SwiftError)) { 2033 assert(SwiftError.getFunctionArg() && "Need a swift error argument"); 2034 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 2035 Flags.setSwiftError(); 2036 Outs.push_back(ISD::OutputArg( 2037 Flags, /*vt=*/TLI.getPointerTy(DL), /*argvt=*/EVT(TLI.getPointerTy(DL)), 2038 /*isfixed=*/true, /*origidx=*/1, /*partOffs=*/0)); 2039 // Create SDNode for the swifterror virtual register. 2040 OutVals.push_back( 2041 DAG.getRegister(SwiftError.getOrCreateVRegUseAt( 2042 &I, FuncInfo.MBB, SwiftError.getFunctionArg()), 2043 EVT(TLI.getPointerTy(DL)))); 2044 } 2045 2046 bool isVarArg = DAG.getMachineFunction().getFunction().isVarArg(); 2047 CallingConv::ID CallConv = 2048 DAG.getMachineFunction().getFunction().getCallingConv(); 2049 Chain = DAG.getTargetLoweringInfo().LowerReturn( 2050 Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG); 2051 2052 // Verify that the target's LowerReturn behaved as expected. 2053 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 2054 "LowerReturn didn't return a valid chain!"); 2055 2056 // Update the DAG with the new chain value resulting from return lowering. 2057 DAG.setRoot(Chain); 2058 } 2059 2060 /// CopyToExportRegsIfNeeded - If the given value has virtual registers 2061 /// created for it, emit nodes to copy the value into the virtual 2062 /// registers. 2063 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) { 2064 // Skip empty types 2065 if (V->getType()->isEmptyTy()) 2066 return; 2067 2068 DenseMap<const Value *, Register>::iterator VMI = FuncInfo.ValueMap.find(V); 2069 if (VMI != FuncInfo.ValueMap.end()) { 2070 assert(!V->use_empty() && "Unused value assigned virtual registers!"); 2071 CopyValueToVirtualRegister(V, VMI->second); 2072 } 2073 } 2074 2075 /// ExportFromCurrentBlock - If this condition isn't known to be exported from 2076 /// the current basic block, add it to ValueMap now so that we'll get a 2077 /// CopyTo/FromReg. 2078 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) { 2079 // No need to export constants. 2080 if (!isa<Instruction>(V) && !isa<Argument>(V)) return; 2081 2082 // Already exported? 2083 if (FuncInfo.isExportedInst(V)) return; 2084 2085 unsigned Reg = FuncInfo.InitializeRegForValue(V); 2086 CopyValueToVirtualRegister(V, Reg); 2087 } 2088 2089 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V, 2090 const BasicBlock *FromBB) { 2091 // The operands of the setcc have to be in this block. We don't know 2092 // how to export them from some other block. 2093 if (const Instruction *VI = dyn_cast<Instruction>(V)) { 2094 // Can export from current BB. 2095 if (VI->getParent() == FromBB) 2096 return true; 2097 2098 // Is already exported, noop. 2099 return FuncInfo.isExportedInst(V); 2100 } 2101 2102 // If this is an argument, we can export it if the BB is the entry block or 2103 // if it is already exported. 2104 if (isa<Argument>(V)) { 2105 if (FromBB->isEntryBlock()) 2106 return true; 2107 2108 // Otherwise, can only export this if it is already exported. 2109 return FuncInfo.isExportedInst(V); 2110 } 2111 2112 // Otherwise, constants can always be exported. 2113 return true; 2114 } 2115 2116 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks. 2117 BranchProbability 2118 SelectionDAGBuilder::getEdgeProbability(const MachineBasicBlock *Src, 2119 const MachineBasicBlock *Dst) const { 2120 BranchProbabilityInfo *BPI = FuncInfo.BPI; 2121 const BasicBlock *SrcBB = Src->getBasicBlock(); 2122 const BasicBlock *DstBB = Dst->getBasicBlock(); 2123 if (!BPI) { 2124 // If BPI is not available, set the default probability as 1 / N, where N is 2125 // the number of successors. 2126 auto SuccSize = std::max<uint32_t>(succ_size(SrcBB), 1); 2127 return BranchProbability(1, SuccSize); 2128 } 2129 return BPI->getEdgeProbability(SrcBB, DstBB); 2130 } 2131 2132 void SelectionDAGBuilder::addSuccessorWithProb(MachineBasicBlock *Src, 2133 MachineBasicBlock *Dst, 2134 BranchProbability Prob) { 2135 if (!FuncInfo.BPI) 2136 Src->addSuccessorWithoutProb(Dst); 2137 else { 2138 if (Prob.isUnknown()) 2139 Prob = getEdgeProbability(Src, Dst); 2140 Src->addSuccessor(Dst, Prob); 2141 } 2142 } 2143 2144 static bool InBlock(const Value *V, const BasicBlock *BB) { 2145 if (const Instruction *I = dyn_cast<Instruction>(V)) 2146 return I->getParent() == BB; 2147 return true; 2148 } 2149 2150 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions. 2151 /// This function emits a branch and is used at the leaves of an OR or an 2152 /// AND operator tree. 2153 void 2154 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond, 2155 MachineBasicBlock *TBB, 2156 MachineBasicBlock *FBB, 2157 MachineBasicBlock *CurBB, 2158 MachineBasicBlock *SwitchBB, 2159 BranchProbability TProb, 2160 BranchProbability FProb, 2161 bool InvertCond) { 2162 const BasicBlock *BB = CurBB->getBasicBlock(); 2163 2164 // If the leaf of the tree is a comparison, merge the condition into 2165 // the caseblock. 2166 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) { 2167 // The operands of the cmp have to be in this block. We don't know 2168 // how to export them from some other block. If this is the first block 2169 // of the sequence, no exporting is needed. 2170 if (CurBB == SwitchBB || 2171 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) && 2172 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) { 2173 ISD::CondCode Condition; 2174 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) { 2175 ICmpInst::Predicate Pred = 2176 InvertCond ? IC->getInversePredicate() : IC->getPredicate(); 2177 Condition = getICmpCondCode(Pred); 2178 } else { 2179 const FCmpInst *FC = cast<FCmpInst>(Cond); 2180 FCmpInst::Predicate Pred = 2181 InvertCond ? FC->getInversePredicate() : FC->getPredicate(); 2182 Condition = getFCmpCondCode(Pred); 2183 if (TM.Options.NoNaNsFPMath) 2184 Condition = getFCmpCodeWithoutNaN(Condition); 2185 } 2186 2187 CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr, 2188 TBB, FBB, CurBB, getCurSDLoc(), TProb, FProb); 2189 SL->SwitchCases.push_back(CB); 2190 return; 2191 } 2192 } 2193 2194 // Create a CaseBlock record representing this branch. 2195 ISD::CondCode Opc = InvertCond ? ISD::SETNE : ISD::SETEQ; 2196 CaseBlock CB(Opc, Cond, ConstantInt::getTrue(*DAG.getContext()), 2197 nullptr, TBB, FBB, CurBB, getCurSDLoc(), TProb, FProb); 2198 SL->SwitchCases.push_back(CB); 2199 } 2200 2201 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond, 2202 MachineBasicBlock *TBB, 2203 MachineBasicBlock *FBB, 2204 MachineBasicBlock *CurBB, 2205 MachineBasicBlock *SwitchBB, 2206 Instruction::BinaryOps Opc, 2207 BranchProbability TProb, 2208 BranchProbability FProb, 2209 bool InvertCond) { 2210 // Skip over not part of the tree and remember to invert op and operands at 2211 // next level. 2212 Value *NotCond; 2213 if (match(Cond, m_OneUse(m_Not(m_Value(NotCond)))) && 2214 InBlock(NotCond, CurBB->getBasicBlock())) { 2215 FindMergedConditions(NotCond, TBB, FBB, CurBB, SwitchBB, Opc, TProb, FProb, 2216 !InvertCond); 2217 return; 2218 } 2219 2220 const Instruction *BOp = dyn_cast<Instruction>(Cond); 2221 const Value *BOpOp0, *BOpOp1; 2222 // Compute the effective opcode for Cond, taking into account whether it needs 2223 // to be inverted, e.g. 2224 // and (not (or A, B)), C 2225 // gets lowered as 2226 // and (and (not A, not B), C) 2227 Instruction::BinaryOps BOpc = (Instruction::BinaryOps)0; 2228 if (BOp) { 2229 BOpc = match(BOp, m_LogicalAnd(m_Value(BOpOp0), m_Value(BOpOp1))) 2230 ? Instruction::And 2231 : (match(BOp, m_LogicalOr(m_Value(BOpOp0), m_Value(BOpOp1))) 2232 ? Instruction::Or 2233 : (Instruction::BinaryOps)0); 2234 if (InvertCond) { 2235 if (BOpc == Instruction::And) 2236 BOpc = Instruction::Or; 2237 else if (BOpc == Instruction::Or) 2238 BOpc = Instruction::And; 2239 } 2240 } 2241 2242 // If this node is not part of the or/and tree, emit it as a branch. 2243 // Note that all nodes in the tree should have same opcode. 2244 bool BOpIsInOrAndTree = BOpc && BOpc == Opc && BOp->hasOneUse(); 2245 if (!BOpIsInOrAndTree || BOp->getParent() != CurBB->getBasicBlock() || 2246 !InBlock(BOpOp0, CurBB->getBasicBlock()) || 2247 !InBlock(BOpOp1, CurBB->getBasicBlock())) { 2248 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB, 2249 TProb, FProb, InvertCond); 2250 return; 2251 } 2252 2253 // Create TmpBB after CurBB. 2254 MachineFunction::iterator BBI(CurBB); 2255 MachineFunction &MF = DAG.getMachineFunction(); 2256 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock()); 2257 CurBB->getParent()->insert(++BBI, TmpBB); 2258 2259 if (Opc == Instruction::Or) { 2260 // Codegen X | Y as: 2261 // BB1: 2262 // jmp_if_X TBB 2263 // jmp TmpBB 2264 // TmpBB: 2265 // jmp_if_Y TBB 2266 // jmp FBB 2267 // 2268 2269 // We have flexibility in setting Prob for BB1 and Prob for TmpBB. 2270 // The requirement is that 2271 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB) 2272 // = TrueProb for original BB. 2273 // Assuming the original probabilities are A and B, one choice is to set 2274 // BB1's probabilities to A/2 and A/2+B, and set TmpBB's probabilities to 2275 // A/(1+B) and 2B/(1+B). This choice assumes that 2276 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB. 2277 // Another choice is to assume TrueProb for BB1 equals to TrueProb for 2278 // TmpBB, but the math is more complicated. 2279 2280 auto NewTrueProb = TProb / 2; 2281 auto NewFalseProb = TProb / 2 + FProb; 2282 // Emit the LHS condition. 2283 FindMergedConditions(BOpOp0, TBB, TmpBB, CurBB, SwitchBB, Opc, NewTrueProb, 2284 NewFalseProb, InvertCond); 2285 2286 // Normalize A/2 and B to get A/(1+B) and 2B/(1+B). 2287 SmallVector<BranchProbability, 2> Probs{TProb / 2, FProb}; 2288 BranchProbability::normalizeProbabilities(Probs.begin(), Probs.end()); 2289 // Emit the RHS condition into TmpBB. 2290 FindMergedConditions(BOpOp1, TBB, FBB, TmpBB, SwitchBB, Opc, Probs[0], 2291 Probs[1], InvertCond); 2292 } else { 2293 assert(Opc == Instruction::And && "Unknown merge op!"); 2294 // Codegen X & Y as: 2295 // BB1: 2296 // jmp_if_X TmpBB 2297 // jmp FBB 2298 // TmpBB: 2299 // jmp_if_Y TBB 2300 // jmp FBB 2301 // 2302 // This requires creation of TmpBB after CurBB. 2303 2304 // We have flexibility in setting Prob for BB1 and Prob for TmpBB. 2305 // The requirement is that 2306 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB) 2307 // = FalseProb for original BB. 2308 // Assuming the original probabilities are A and B, one choice is to set 2309 // BB1's probabilities to A+B/2 and B/2, and set TmpBB's probabilities to 2310 // 2A/(1+A) and B/(1+A). This choice assumes that FalseProb for BB1 == 2311 // TrueProb for BB1 * FalseProb for TmpBB. 2312 2313 auto NewTrueProb = TProb + FProb / 2; 2314 auto NewFalseProb = FProb / 2; 2315 // Emit the LHS condition. 2316 FindMergedConditions(BOpOp0, TmpBB, FBB, CurBB, SwitchBB, Opc, NewTrueProb, 2317 NewFalseProb, InvertCond); 2318 2319 // Normalize A and B/2 to get 2A/(1+A) and B/(1+A). 2320 SmallVector<BranchProbability, 2> Probs{TProb, FProb / 2}; 2321 BranchProbability::normalizeProbabilities(Probs.begin(), Probs.end()); 2322 // Emit the RHS condition into TmpBB. 2323 FindMergedConditions(BOpOp1, TBB, FBB, TmpBB, SwitchBB, Opc, Probs[0], 2324 Probs[1], InvertCond); 2325 } 2326 } 2327 2328 /// If the set of cases should be emitted as a series of branches, return true. 2329 /// If we should emit this as a bunch of and/or'd together conditions, return 2330 /// false. 2331 bool 2332 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) { 2333 if (Cases.size() != 2) return true; 2334 2335 // If this is two comparisons of the same values or'd or and'd together, they 2336 // will get folded into a single comparison, so don't emit two blocks. 2337 if ((Cases[0].CmpLHS == Cases[1].CmpLHS && 2338 Cases[0].CmpRHS == Cases[1].CmpRHS) || 2339 (Cases[0].CmpRHS == Cases[1].CmpLHS && 2340 Cases[0].CmpLHS == Cases[1].CmpRHS)) { 2341 return false; 2342 } 2343 2344 // Handle: (X != null) | (Y != null) --> (X|Y) != 0 2345 // Handle: (X == null) & (Y == null) --> (X|Y) == 0 2346 if (Cases[0].CmpRHS == Cases[1].CmpRHS && 2347 Cases[0].CC == Cases[1].CC && 2348 isa<Constant>(Cases[0].CmpRHS) && 2349 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) { 2350 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB) 2351 return false; 2352 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB) 2353 return false; 2354 } 2355 2356 return true; 2357 } 2358 2359 void SelectionDAGBuilder::visitBr(const BranchInst &I) { 2360 MachineBasicBlock *BrMBB = FuncInfo.MBB; 2361 2362 // Update machine-CFG edges. 2363 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 2364 2365 if (I.isUnconditional()) { 2366 // Update machine-CFG edges. 2367 BrMBB->addSuccessor(Succ0MBB); 2368 2369 // If this is not a fall-through branch or optimizations are switched off, 2370 // emit the branch. 2371 if (Succ0MBB != NextBlock(BrMBB) || TM.getOptLevel() == CodeGenOpt::None) 2372 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), 2373 MVT::Other, getControlRoot(), 2374 DAG.getBasicBlock(Succ0MBB))); 2375 2376 return; 2377 } 2378 2379 // If this condition is one of the special cases we handle, do special stuff 2380 // now. 2381 const Value *CondVal = I.getCondition(); 2382 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 2383 2384 // If this is a series of conditions that are or'd or and'd together, emit 2385 // this as a sequence of branches instead of setcc's with and/or operations. 2386 // As long as jumps are not expensive (exceptions for multi-use logic ops, 2387 // unpredictable branches, and vector extracts because those jumps are likely 2388 // expensive for any target), this should improve performance. 2389 // For example, instead of something like: 2390 // cmp A, B 2391 // C = seteq 2392 // cmp D, E 2393 // F = setle 2394 // or C, F 2395 // jnz foo 2396 // Emit: 2397 // cmp A, B 2398 // je foo 2399 // cmp D, E 2400 // jle foo 2401 const Instruction *BOp = dyn_cast<Instruction>(CondVal); 2402 if (!DAG.getTargetLoweringInfo().isJumpExpensive() && BOp && 2403 BOp->hasOneUse() && !I.hasMetadata(LLVMContext::MD_unpredictable)) { 2404 Value *Vec; 2405 const Value *BOp0, *BOp1; 2406 Instruction::BinaryOps Opcode = (Instruction::BinaryOps)0; 2407 if (match(BOp, m_LogicalAnd(m_Value(BOp0), m_Value(BOp1)))) 2408 Opcode = Instruction::And; 2409 else if (match(BOp, m_LogicalOr(m_Value(BOp0), m_Value(BOp1)))) 2410 Opcode = Instruction::Or; 2411 2412 if (Opcode && !(match(BOp0, m_ExtractElt(m_Value(Vec), m_Value())) && 2413 match(BOp1, m_ExtractElt(m_Specific(Vec), m_Value())))) { 2414 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB, Opcode, 2415 getEdgeProbability(BrMBB, Succ0MBB), 2416 getEdgeProbability(BrMBB, Succ1MBB), 2417 /*InvertCond=*/false); 2418 // If the compares in later blocks need to use values not currently 2419 // exported from this block, export them now. This block should always 2420 // be the first entry. 2421 assert(SL->SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!"); 2422 2423 // Allow some cases to be rejected. 2424 if (ShouldEmitAsBranches(SL->SwitchCases)) { 2425 for (unsigned i = 1, e = SL->SwitchCases.size(); i != e; ++i) { 2426 ExportFromCurrentBlock(SL->SwitchCases[i].CmpLHS); 2427 ExportFromCurrentBlock(SL->SwitchCases[i].CmpRHS); 2428 } 2429 2430 // Emit the branch for this block. 2431 visitSwitchCase(SL->SwitchCases[0], BrMBB); 2432 SL->SwitchCases.erase(SL->SwitchCases.begin()); 2433 return; 2434 } 2435 2436 // Okay, we decided not to do this, remove any inserted MBB's and clear 2437 // SwitchCases. 2438 for (unsigned i = 1, e = SL->SwitchCases.size(); i != e; ++i) 2439 FuncInfo.MF->erase(SL->SwitchCases[i].ThisBB); 2440 2441 SL->SwitchCases.clear(); 2442 } 2443 } 2444 2445 // Create a CaseBlock record representing this branch. 2446 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()), 2447 nullptr, Succ0MBB, Succ1MBB, BrMBB, getCurSDLoc()); 2448 2449 // Use visitSwitchCase to actually insert the fast branch sequence for this 2450 // cond branch. 2451 visitSwitchCase(CB, BrMBB); 2452 } 2453 2454 /// visitSwitchCase - Emits the necessary code to represent a single node in 2455 /// the binary search tree resulting from lowering a switch instruction. 2456 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB, 2457 MachineBasicBlock *SwitchBB) { 2458 SDValue Cond; 2459 SDValue CondLHS = getValue(CB.CmpLHS); 2460 SDLoc dl = CB.DL; 2461 2462 if (CB.CC == ISD::SETTRUE) { 2463 // Branch or fall through to TrueBB. 2464 addSuccessorWithProb(SwitchBB, CB.TrueBB, CB.TrueProb); 2465 SwitchBB->normalizeSuccProbs(); 2466 if (CB.TrueBB != NextBlock(SwitchBB)) { 2467 DAG.setRoot(DAG.getNode(ISD::BR, dl, MVT::Other, getControlRoot(), 2468 DAG.getBasicBlock(CB.TrueBB))); 2469 } 2470 return; 2471 } 2472 2473 auto &TLI = DAG.getTargetLoweringInfo(); 2474 EVT MemVT = TLI.getMemValueType(DAG.getDataLayout(), CB.CmpLHS->getType()); 2475 2476 // Build the setcc now. 2477 if (!CB.CmpMHS) { 2478 // Fold "(X == true)" to X and "(X == false)" to !X to 2479 // handle common cases produced by branch lowering. 2480 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) && 2481 CB.CC == ISD::SETEQ) 2482 Cond = CondLHS; 2483 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) && 2484 CB.CC == ISD::SETEQ) { 2485 SDValue True = DAG.getConstant(1, dl, CondLHS.getValueType()); 2486 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True); 2487 } else { 2488 SDValue CondRHS = getValue(CB.CmpRHS); 2489 2490 // If a pointer's DAG type is larger than its memory type then the DAG 2491 // values are zero-extended. This breaks signed comparisons so truncate 2492 // back to the underlying type before doing the compare. 2493 if (CondLHS.getValueType() != MemVT) { 2494 CondLHS = DAG.getPtrExtOrTrunc(CondLHS, getCurSDLoc(), MemVT); 2495 CondRHS = DAG.getPtrExtOrTrunc(CondRHS, getCurSDLoc(), MemVT); 2496 } 2497 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, CondRHS, CB.CC); 2498 } 2499 } else { 2500 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now"); 2501 2502 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue(); 2503 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue(); 2504 2505 SDValue CmpOp = getValue(CB.CmpMHS); 2506 EVT VT = CmpOp.getValueType(); 2507 2508 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) { 2509 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, dl, VT), 2510 ISD::SETLE); 2511 } else { 2512 SDValue SUB = DAG.getNode(ISD::SUB, dl, 2513 VT, CmpOp, DAG.getConstant(Low, dl, VT)); 2514 Cond = DAG.getSetCC(dl, MVT::i1, SUB, 2515 DAG.getConstant(High-Low, dl, VT), ISD::SETULE); 2516 } 2517 } 2518 2519 // Update successor info 2520 addSuccessorWithProb(SwitchBB, CB.TrueBB, CB.TrueProb); 2521 // TrueBB and FalseBB are always different unless the incoming IR is 2522 // degenerate. This only happens when running llc on weird IR. 2523 if (CB.TrueBB != CB.FalseBB) 2524 addSuccessorWithProb(SwitchBB, CB.FalseBB, CB.FalseProb); 2525 SwitchBB->normalizeSuccProbs(); 2526 2527 // If the lhs block is the next block, invert the condition so that we can 2528 // fall through to the lhs instead of the rhs block. 2529 if (CB.TrueBB == NextBlock(SwitchBB)) { 2530 std::swap(CB.TrueBB, CB.FalseBB); 2531 SDValue True = DAG.getConstant(1, dl, Cond.getValueType()); 2532 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True); 2533 } 2534 2535 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, 2536 MVT::Other, getControlRoot(), Cond, 2537 DAG.getBasicBlock(CB.TrueBB)); 2538 2539 // Insert the false branch. Do this even if it's a fall through branch, 2540 // this makes it easier to do DAG optimizations which require inverting 2541 // the branch condition. 2542 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond, 2543 DAG.getBasicBlock(CB.FalseBB)); 2544 2545 DAG.setRoot(BrCond); 2546 } 2547 2548 /// visitJumpTable - Emit JumpTable node in the current MBB 2549 void SelectionDAGBuilder::visitJumpTable(SwitchCG::JumpTable &JT) { 2550 // Emit the code for the jump table 2551 assert(JT.Reg != -1U && "Should lower JT Header first!"); 2552 EVT PTy = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout()); 2553 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(), 2554 JT.Reg, PTy); 2555 SDValue Table = DAG.getJumpTable(JT.JTI, PTy); 2556 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(), 2557 MVT::Other, Index.getValue(1), 2558 Table, Index); 2559 DAG.setRoot(BrJumpTable); 2560 } 2561 2562 /// visitJumpTableHeader - This function emits necessary code to produce index 2563 /// in the JumpTable from switch case. 2564 void SelectionDAGBuilder::visitJumpTableHeader(SwitchCG::JumpTable &JT, 2565 JumpTableHeader &JTH, 2566 MachineBasicBlock *SwitchBB) { 2567 SDLoc dl = getCurSDLoc(); 2568 2569 // Subtract the lowest switch case value from the value being switched on. 2570 SDValue SwitchOp = getValue(JTH.SValue); 2571 EVT VT = SwitchOp.getValueType(); 2572 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp, 2573 DAG.getConstant(JTH.First, dl, VT)); 2574 2575 // The SDNode we just created, which holds the value being switched on minus 2576 // the smallest case value, needs to be copied to a virtual register so it 2577 // can be used as an index into the jump table in a subsequent basic block. 2578 // This value may be smaller or larger than the target's pointer type, and 2579 // therefore require extension or truncating. 2580 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 2581 SwitchOp = DAG.getZExtOrTrunc(Sub, dl, TLI.getPointerTy(DAG.getDataLayout())); 2582 2583 unsigned JumpTableReg = 2584 FuncInfo.CreateReg(TLI.getPointerTy(DAG.getDataLayout())); 2585 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl, 2586 JumpTableReg, SwitchOp); 2587 JT.Reg = JumpTableReg; 2588 2589 if (!JTH.FallthroughUnreachable) { 2590 // Emit the range check for the jump table, and branch to the default block 2591 // for the switch statement if the value being switched on exceeds the 2592 // largest case in the switch. 2593 SDValue CMP = DAG.getSetCC( 2594 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), 2595 Sub.getValueType()), 2596 Sub, DAG.getConstant(JTH.Last - JTH.First, dl, VT), ISD::SETUGT); 2597 2598 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, 2599 MVT::Other, CopyTo, CMP, 2600 DAG.getBasicBlock(JT.Default)); 2601 2602 // Avoid emitting unnecessary branches to the next block. 2603 if (JT.MBB != NextBlock(SwitchBB)) 2604 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond, 2605 DAG.getBasicBlock(JT.MBB)); 2606 2607 DAG.setRoot(BrCond); 2608 } else { 2609 // Avoid emitting unnecessary branches to the next block. 2610 if (JT.MBB != NextBlock(SwitchBB)) 2611 DAG.setRoot(DAG.getNode(ISD::BR, dl, MVT::Other, CopyTo, 2612 DAG.getBasicBlock(JT.MBB))); 2613 else 2614 DAG.setRoot(CopyTo); 2615 } 2616 } 2617 2618 /// Create a LOAD_STACK_GUARD node, and let it carry the target specific global 2619 /// variable if there exists one. 2620 static SDValue getLoadStackGuard(SelectionDAG &DAG, const SDLoc &DL, 2621 SDValue &Chain) { 2622 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 2623 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout()); 2624 EVT PtrMemTy = TLI.getPointerMemTy(DAG.getDataLayout()); 2625 MachineFunction &MF = DAG.getMachineFunction(); 2626 Value *Global = TLI.getSDagStackGuard(*MF.getFunction().getParent()); 2627 MachineSDNode *Node = 2628 DAG.getMachineNode(TargetOpcode::LOAD_STACK_GUARD, DL, PtrTy, Chain); 2629 if (Global) { 2630 MachinePointerInfo MPInfo(Global); 2631 auto Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant | 2632 MachineMemOperand::MODereferenceable; 2633 MachineMemOperand *MemRef = MF.getMachineMemOperand( 2634 MPInfo, Flags, PtrTy.getSizeInBits() / 8, DAG.getEVTAlign(PtrTy)); 2635 DAG.setNodeMemRefs(Node, {MemRef}); 2636 } 2637 if (PtrTy != PtrMemTy) 2638 return DAG.getPtrExtOrTrunc(SDValue(Node, 0), DL, PtrMemTy); 2639 return SDValue(Node, 0); 2640 } 2641 2642 /// Codegen a new tail for a stack protector check ParentMBB which has had its 2643 /// tail spliced into a stack protector check success bb. 2644 /// 2645 /// For a high level explanation of how this fits into the stack protector 2646 /// generation see the comment on the declaration of class 2647 /// StackProtectorDescriptor. 2648 void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD, 2649 MachineBasicBlock *ParentBB) { 2650 2651 // First create the loads to the guard/stack slot for the comparison. 2652 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 2653 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout()); 2654 EVT PtrMemTy = TLI.getPointerMemTy(DAG.getDataLayout()); 2655 2656 MachineFrameInfo &MFI = ParentBB->getParent()->getFrameInfo(); 2657 int FI = MFI.getStackProtectorIndex(); 2658 2659 SDValue Guard; 2660 SDLoc dl = getCurSDLoc(); 2661 SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy); 2662 const Module &M = *ParentBB->getParent()->getFunction().getParent(); 2663 Align Align = 2664 DAG.getDataLayout().getPrefTypeAlign(Type::getInt8PtrTy(M.getContext())); 2665 2666 // Generate code to load the content of the guard slot. 2667 SDValue GuardVal = DAG.getLoad( 2668 PtrMemTy, dl, DAG.getEntryNode(), StackSlotPtr, 2669 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), Align, 2670 MachineMemOperand::MOVolatile); 2671 2672 if (TLI.useStackGuardXorFP()) 2673 GuardVal = TLI.emitStackGuardXorFP(DAG, GuardVal, dl); 2674 2675 // Retrieve guard check function, nullptr if instrumentation is inlined. 2676 if (const Function *GuardCheckFn = TLI.getSSPStackGuardCheck(M)) { 2677 // The target provides a guard check function to validate the guard value. 2678 // Generate a call to that function with the content of the guard slot as 2679 // argument. 2680 FunctionType *FnTy = GuardCheckFn->getFunctionType(); 2681 assert(FnTy->getNumParams() == 1 && "Invalid function signature"); 2682 2683 TargetLowering::ArgListTy Args; 2684 TargetLowering::ArgListEntry Entry; 2685 Entry.Node = GuardVal; 2686 Entry.Ty = FnTy->getParamType(0); 2687 if (GuardCheckFn->hasParamAttribute(0, Attribute::AttrKind::InReg)) 2688 Entry.IsInReg = true; 2689 Args.push_back(Entry); 2690 2691 TargetLowering::CallLoweringInfo CLI(DAG); 2692 CLI.setDebugLoc(getCurSDLoc()) 2693 .setChain(DAG.getEntryNode()) 2694 .setCallee(GuardCheckFn->getCallingConv(), FnTy->getReturnType(), 2695 getValue(GuardCheckFn), std::move(Args)); 2696 2697 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI); 2698 DAG.setRoot(Result.second); 2699 return; 2700 } 2701 2702 // If useLoadStackGuardNode returns true, generate LOAD_STACK_GUARD. 2703 // Otherwise, emit a volatile load to retrieve the stack guard value. 2704 SDValue Chain = DAG.getEntryNode(); 2705 if (TLI.useLoadStackGuardNode()) { 2706 Guard = getLoadStackGuard(DAG, dl, Chain); 2707 } else { 2708 const Value *IRGuard = TLI.getSDagStackGuard(M); 2709 SDValue GuardPtr = getValue(IRGuard); 2710 2711 Guard = DAG.getLoad(PtrMemTy, dl, Chain, GuardPtr, 2712 MachinePointerInfo(IRGuard, 0), Align, 2713 MachineMemOperand::MOVolatile); 2714 } 2715 2716 // Perform the comparison via a getsetcc. 2717 SDValue Cmp = DAG.getSetCC(dl, TLI.getSetCCResultType(DAG.getDataLayout(), 2718 *DAG.getContext(), 2719 Guard.getValueType()), 2720 Guard, GuardVal, ISD::SETNE); 2721 2722 // If the guard/stackslot do not equal, branch to failure MBB. 2723 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, 2724 MVT::Other, GuardVal.getOperand(0), 2725 Cmp, DAG.getBasicBlock(SPD.getFailureMBB())); 2726 // Otherwise branch to success MBB. 2727 SDValue Br = DAG.getNode(ISD::BR, dl, 2728 MVT::Other, BrCond, 2729 DAG.getBasicBlock(SPD.getSuccessMBB())); 2730 2731 DAG.setRoot(Br); 2732 } 2733 2734 /// Codegen the failure basic block for a stack protector check. 2735 /// 2736 /// A failure stack protector machine basic block consists simply of a call to 2737 /// __stack_chk_fail(). 2738 /// 2739 /// For a high level explanation of how this fits into the stack protector 2740 /// generation see the comment on the declaration of class 2741 /// StackProtectorDescriptor. 2742 void 2743 SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) { 2744 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 2745 TargetLowering::MakeLibCallOptions CallOptions; 2746 CallOptions.setDiscardResult(true); 2747 SDValue Chain = 2748 TLI.makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL, MVT::isVoid, 2749 None, CallOptions, getCurSDLoc()).second; 2750 // On PS4/PS5, the "return address" must still be within the calling 2751 // function, even if it's at the very end, so emit an explicit TRAP here. 2752 // Passing 'true' for doesNotReturn above won't generate the trap for us. 2753 if (TM.getTargetTriple().isPS()) 2754 Chain = DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, Chain); 2755 // WebAssembly needs an unreachable instruction after a non-returning call, 2756 // because the function return type can be different from __stack_chk_fail's 2757 // return type (void). 2758 if (TM.getTargetTriple().isWasm()) 2759 Chain = DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, Chain); 2760 2761 DAG.setRoot(Chain); 2762 } 2763 2764 /// visitBitTestHeader - This function emits necessary code to produce value 2765 /// suitable for "bit tests" 2766 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B, 2767 MachineBasicBlock *SwitchBB) { 2768 SDLoc dl = getCurSDLoc(); 2769 2770 // Subtract the minimum value. 2771 SDValue SwitchOp = getValue(B.SValue); 2772 EVT VT = SwitchOp.getValueType(); 2773 SDValue RangeSub = 2774 DAG.getNode(ISD::SUB, dl, VT, SwitchOp, DAG.getConstant(B.First, dl, VT)); 2775 2776 // Determine the type of the test operands. 2777 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 2778 bool UsePtrType = false; 2779 if (!TLI.isTypeLegal(VT)) { 2780 UsePtrType = true; 2781 } else { 2782 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i) 2783 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) { 2784 // Switch table case range are encoded into series of masks. 2785 // Just use pointer type, it's guaranteed to fit. 2786 UsePtrType = true; 2787 break; 2788 } 2789 } 2790 SDValue Sub = RangeSub; 2791 if (UsePtrType) { 2792 VT = TLI.getPointerTy(DAG.getDataLayout()); 2793 Sub = DAG.getZExtOrTrunc(Sub, dl, VT); 2794 } 2795 2796 B.RegVT = VT.getSimpleVT(); 2797 B.Reg = FuncInfo.CreateReg(B.RegVT); 2798 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl, B.Reg, Sub); 2799 2800 MachineBasicBlock* MBB = B.Cases[0].ThisBB; 2801 2802 if (!B.FallthroughUnreachable) 2803 addSuccessorWithProb(SwitchBB, B.Default, B.DefaultProb); 2804 addSuccessorWithProb(SwitchBB, MBB, B.Prob); 2805 SwitchBB->normalizeSuccProbs(); 2806 2807 SDValue Root = CopyTo; 2808 if (!B.FallthroughUnreachable) { 2809 // Conditional branch to the default block. 2810 SDValue RangeCmp = DAG.getSetCC(dl, 2811 TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), 2812 RangeSub.getValueType()), 2813 RangeSub, DAG.getConstant(B.Range, dl, RangeSub.getValueType()), 2814 ISD::SETUGT); 2815 2816 Root = DAG.getNode(ISD::BRCOND, dl, MVT::Other, Root, RangeCmp, 2817 DAG.getBasicBlock(B.Default)); 2818 } 2819 2820 // Avoid emitting unnecessary branches to the next block. 2821 if (MBB != NextBlock(SwitchBB)) 2822 Root = DAG.getNode(ISD::BR, dl, MVT::Other, Root, DAG.getBasicBlock(MBB)); 2823 2824 DAG.setRoot(Root); 2825 } 2826 2827 /// visitBitTestCase - this function produces one "bit test" 2828 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB, 2829 MachineBasicBlock* NextMBB, 2830 BranchProbability BranchProbToNext, 2831 unsigned Reg, 2832 BitTestCase &B, 2833 MachineBasicBlock *SwitchBB) { 2834 SDLoc dl = getCurSDLoc(); 2835 MVT VT = BB.RegVT; 2836 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), dl, Reg, VT); 2837 SDValue Cmp; 2838 unsigned PopCount = countPopulation(B.Mask); 2839 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 2840 if (PopCount == 1) { 2841 // Testing for a single bit; just compare the shift count with what it 2842 // would need to be to shift a 1 bit in that position. 2843 Cmp = DAG.getSetCC( 2844 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT), 2845 ShiftOp, DAG.getConstant(countTrailingZeros(B.Mask), dl, VT), 2846 ISD::SETEQ); 2847 } else if (PopCount == BB.Range) { 2848 // There is only one zero bit in the range, test for it directly. 2849 Cmp = DAG.getSetCC( 2850 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT), 2851 ShiftOp, DAG.getConstant(countTrailingOnes(B.Mask), dl, VT), 2852 ISD::SETNE); 2853 } else { 2854 // Make desired shift 2855 SDValue SwitchVal = DAG.getNode(ISD::SHL, dl, VT, 2856 DAG.getConstant(1, dl, VT), ShiftOp); 2857 2858 // Emit bit tests and jumps 2859 SDValue AndOp = DAG.getNode(ISD::AND, dl, 2860 VT, SwitchVal, DAG.getConstant(B.Mask, dl, VT)); 2861 Cmp = DAG.getSetCC( 2862 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT), 2863 AndOp, DAG.getConstant(0, dl, VT), ISD::SETNE); 2864 } 2865 2866 // The branch probability from SwitchBB to B.TargetBB is B.ExtraProb. 2867 addSuccessorWithProb(SwitchBB, B.TargetBB, B.ExtraProb); 2868 // The branch probability from SwitchBB to NextMBB is BranchProbToNext. 2869 addSuccessorWithProb(SwitchBB, NextMBB, BranchProbToNext); 2870 // It is not guaranteed that the sum of B.ExtraProb and BranchProbToNext is 2871 // one as they are relative probabilities (and thus work more like weights), 2872 // and hence we need to normalize them to let the sum of them become one. 2873 SwitchBB->normalizeSuccProbs(); 2874 2875 SDValue BrAnd = DAG.getNode(ISD::BRCOND, dl, 2876 MVT::Other, getControlRoot(), 2877 Cmp, DAG.getBasicBlock(B.TargetBB)); 2878 2879 // Avoid emitting unnecessary branches to the next block. 2880 if (NextMBB != NextBlock(SwitchBB)) 2881 BrAnd = DAG.getNode(ISD::BR, dl, MVT::Other, BrAnd, 2882 DAG.getBasicBlock(NextMBB)); 2883 2884 DAG.setRoot(BrAnd); 2885 } 2886 2887 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) { 2888 MachineBasicBlock *InvokeMBB = FuncInfo.MBB; 2889 2890 // Retrieve successors. Look through artificial IR level blocks like 2891 // catchswitch for successors. 2892 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; 2893 const BasicBlock *EHPadBB = I.getSuccessor(1); 2894 2895 // Deopt bundles are lowered in LowerCallSiteWithDeoptBundle, and we don't 2896 // have to do anything here to lower funclet bundles. 2897 assert(!I.hasOperandBundlesOtherThan( 2898 {LLVMContext::OB_deopt, LLVMContext::OB_gc_transition, 2899 LLVMContext::OB_gc_live, LLVMContext::OB_funclet, 2900 LLVMContext::OB_cfguardtarget, 2901 LLVMContext::OB_clang_arc_attachedcall}) && 2902 "Cannot lower invokes with arbitrary operand bundles yet!"); 2903 2904 const Value *Callee(I.getCalledOperand()); 2905 const Function *Fn = dyn_cast<Function>(Callee); 2906 if (isa<InlineAsm>(Callee)) 2907 visitInlineAsm(I, EHPadBB); 2908 else if (Fn && Fn->isIntrinsic()) { 2909 switch (Fn->getIntrinsicID()) { 2910 default: 2911 llvm_unreachable("Cannot invoke this intrinsic"); 2912 case Intrinsic::donothing: 2913 // Ignore invokes to @llvm.donothing: jump directly to the next BB. 2914 case Intrinsic::seh_try_begin: 2915 case Intrinsic::seh_scope_begin: 2916 case Intrinsic::seh_try_end: 2917 case Intrinsic::seh_scope_end: 2918 break; 2919 case Intrinsic::experimental_patchpoint_void: 2920 case Intrinsic::experimental_patchpoint_i64: 2921 visitPatchpoint(I, EHPadBB); 2922 break; 2923 case Intrinsic::experimental_gc_statepoint: 2924 LowerStatepoint(cast<GCStatepointInst>(I), EHPadBB); 2925 break; 2926 case Intrinsic::wasm_rethrow: { 2927 // This is usually done in visitTargetIntrinsic, but this intrinsic is 2928 // special because it can be invoked, so we manually lower it to a DAG 2929 // node here. 2930 SmallVector<SDValue, 8> Ops; 2931 Ops.push_back(getRoot()); // inchain 2932 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 2933 Ops.push_back( 2934 DAG.getTargetConstant(Intrinsic::wasm_rethrow, getCurSDLoc(), 2935 TLI.getPointerTy(DAG.getDataLayout()))); 2936 SDVTList VTs = DAG.getVTList(ArrayRef<EVT>({MVT::Other})); // outchain 2937 DAG.setRoot(DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops)); 2938 break; 2939 } 2940 } 2941 } else if (I.countOperandBundlesOfType(LLVMContext::OB_deopt)) { 2942 // Currently we do not lower any intrinsic calls with deopt operand bundles. 2943 // Eventually we will support lowering the @llvm.experimental.deoptimize 2944 // intrinsic, and right now there are no plans to support other intrinsics 2945 // with deopt state. 2946 LowerCallSiteWithDeoptBundle(&I, getValue(Callee), EHPadBB); 2947 } else { 2948 LowerCallTo(I, getValue(Callee), false, false, EHPadBB); 2949 } 2950 2951 // If the value of the invoke is used outside of its defining block, make it 2952 // available as a virtual register. 2953 // We already took care of the exported value for the statepoint instruction 2954 // during call to the LowerStatepoint. 2955 if (!isa<GCStatepointInst>(I)) { 2956 CopyToExportRegsIfNeeded(&I); 2957 } 2958 2959 SmallVector<std::pair<MachineBasicBlock *, BranchProbability>, 1> UnwindDests; 2960 BranchProbabilityInfo *BPI = FuncInfo.BPI; 2961 BranchProbability EHPadBBProb = 2962 BPI ? BPI->getEdgeProbability(InvokeMBB->getBasicBlock(), EHPadBB) 2963 : BranchProbability::getZero(); 2964 findUnwindDestinations(FuncInfo, EHPadBB, EHPadBBProb, UnwindDests); 2965 2966 // Update successor info. 2967 addSuccessorWithProb(InvokeMBB, Return); 2968 for (auto &UnwindDest : UnwindDests) { 2969 UnwindDest.first->setIsEHPad(); 2970 addSuccessorWithProb(InvokeMBB, UnwindDest.first, UnwindDest.second); 2971 } 2972 InvokeMBB->normalizeSuccProbs(); 2973 2974 // Drop into normal successor. 2975 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, getControlRoot(), 2976 DAG.getBasicBlock(Return))); 2977 } 2978 2979 void SelectionDAGBuilder::visitCallBr(const CallBrInst &I) { 2980 MachineBasicBlock *CallBrMBB = FuncInfo.MBB; 2981 2982 // Deopt bundles are lowered in LowerCallSiteWithDeoptBundle, and we don't 2983 // have to do anything here to lower funclet bundles. 2984 assert(!I.hasOperandBundlesOtherThan( 2985 {LLVMContext::OB_deopt, LLVMContext::OB_funclet}) && 2986 "Cannot lower callbrs with arbitrary operand bundles yet!"); 2987 2988 assert(I.isInlineAsm() && "Only know how to handle inlineasm callbr"); 2989 visitInlineAsm(I); 2990 CopyToExportRegsIfNeeded(&I); 2991 2992 // Retrieve successors. 2993 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getDefaultDest()]; 2994 2995 // Update successor info. 2996 addSuccessorWithProb(CallBrMBB, Return, BranchProbability::getOne()); 2997 for (unsigned i = 0, e = I.getNumIndirectDests(); i < e; ++i) { 2998 MachineBasicBlock *Target = FuncInfo.MBBMap[I.getIndirectDest(i)]; 2999 addSuccessorWithProb(CallBrMBB, Target, BranchProbability::getZero()); 3000 Target->setIsInlineAsmBrIndirectTarget(); 3001 } 3002 CallBrMBB->normalizeSuccProbs(); 3003 3004 // Drop into default successor. 3005 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), 3006 MVT::Other, getControlRoot(), 3007 DAG.getBasicBlock(Return))); 3008 } 3009 3010 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) { 3011 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!"); 3012 } 3013 3014 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) { 3015 assert(FuncInfo.MBB->isEHPad() && 3016 "Call to landingpad not in landing pad!"); 3017 3018 // If there aren't registers to copy the values into (e.g., during SjLj 3019 // exceptions), then don't bother to create these DAG nodes. 3020 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3021 const Constant *PersonalityFn = FuncInfo.Fn->getPersonalityFn(); 3022 if (TLI.getExceptionPointerRegister(PersonalityFn) == 0 && 3023 TLI.getExceptionSelectorRegister(PersonalityFn) == 0) 3024 return; 3025 3026 // If landingpad's return type is token type, we don't create DAG nodes 3027 // for its exception pointer and selector value. The extraction of exception 3028 // pointer or selector value from token type landingpads is not currently 3029 // supported. 3030 if (LP.getType()->isTokenTy()) 3031 return; 3032 3033 SmallVector<EVT, 2> ValueVTs; 3034 SDLoc dl = getCurSDLoc(); 3035 ComputeValueVTs(TLI, DAG.getDataLayout(), LP.getType(), ValueVTs); 3036 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported"); 3037 3038 // Get the two live-in registers as SDValues. The physregs have already been 3039 // copied into virtual registers. 3040 SDValue Ops[2]; 3041 if (FuncInfo.ExceptionPointerVirtReg) { 3042 Ops[0] = DAG.getZExtOrTrunc( 3043 DAG.getCopyFromReg(DAG.getEntryNode(), dl, 3044 FuncInfo.ExceptionPointerVirtReg, 3045 TLI.getPointerTy(DAG.getDataLayout())), 3046 dl, ValueVTs[0]); 3047 } else { 3048 Ops[0] = DAG.getConstant(0, dl, TLI.getPointerTy(DAG.getDataLayout())); 3049 } 3050 Ops[1] = DAG.getZExtOrTrunc( 3051 DAG.getCopyFromReg(DAG.getEntryNode(), dl, 3052 FuncInfo.ExceptionSelectorVirtReg, 3053 TLI.getPointerTy(DAG.getDataLayout())), 3054 dl, ValueVTs[1]); 3055 3056 // Merge into one. 3057 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl, 3058 DAG.getVTList(ValueVTs), Ops); 3059 setValue(&LP, Res); 3060 } 3061 3062 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First, 3063 MachineBasicBlock *Last) { 3064 // Update JTCases. 3065 for (JumpTableBlock &JTB : SL->JTCases) 3066 if (JTB.first.HeaderBB == First) 3067 JTB.first.HeaderBB = Last; 3068 3069 // Update BitTestCases. 3070 for (BitTestBlock &BTB : SL->BitTestCases) 3071 if (BTB.Parent == First) 3072 BTB.Parent = Last; 3073 } 3074 3075 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) { 3076 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB; 3077 3078 // Update machine-CFG edges with unique successors. 3079 SmallSet<BasicBlock*, 32> Done; 3080 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) { 3081 BasicBlock *BB = I.getSuccessor(i); 3082 bool Inserted = Done.insert(BB).second; 3083 if (!Inserted) 3084 continue; 3085 3086 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB]; 3087 addSuccessorWithProb(IndirectBrMBB, Succ); 3088 } 3089 IndirectBrMBB->normalizeSuccProbs(); 3090 3091 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(), 3092 MVT::Other, getControlRoot(), 3093 getValue(I.getAddress()))); 3094 } 3095 3096 void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) { 3097 if (!DAG.getTarget().Options.TrapUnreachable) 3098 return; 3099 3100 // We may be able to ignore unreachable behind a noreturn call. 3101 if (DAG.getTarget().Options.NoTrapAfterNoreturn) { 3102 const BasicBlock &BB = *I.getParent(); 3103 if (&I != &BB.front()) { 3104 BasicBlock::const_iterator PredI = 3105 std::prev(BasicBlock::const_iterator(&I)); 3106 if (const CallInst *Call = dyn_cast<CallInst>(&*PredI)) { 3107 if (Call->doesNotReturn()) 3108 return; 3109 } 3110 } 3111 } 3112 3113 DAG.setRoot(DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot())); 3114 } 3115 3116 void SelectionDAGBuilder::visitUnary(const User &I, unsigned Opcode) { 3117 SDNodeFlags Flags; 3118 if (auto *FPOp = dyn_cast<FPMathOperator>(&I)) 3119 Flags.copyFMF(*FPOp); 3120 3121 SDValue Op = getValue(I.getOperand(0)); 3122 SDValue UnNodeValue = DAG.getNode(Opcode, getCurSDLoc(), Op.getValueType(), 3123 Op, Flags); 3124 setValue(&I, UnNodeValue); 3125 } 3126 3127 void SelectionDAGBuilder::visitBinary(const User &I, unsigned Opcode) { 3128 SDNodeFlags Flags; 3129 if (auto *OFBinOp = dyn_cast<OverflowingBinaryOperator>(&I)) { 3130 Flags.setNoSignedWrap(OFBinOp->hasNoSignedWrap()); 3131 Flags.setNoUnsignedWrap(OFBinOp->hasNoUnsignedWrap()); 3132 } 3133 if (auto *ExactOp = dyn_cast<PossiblyExactOperator>(&I)) 3134 Flags.setExact(ExactOp->isExact()); 3135 if (auto *FPOp = dyn_cast<FPMathOperator>(&I)) 3136 Flags.copyFMF(*FPOp); 3137 3138 SDValue Op1 = getValue(I.getOperand(0)); 3139 SDValue Op2 = getValue(I.getOperand(1)); 3140 SDValue BinNodeValue = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), 3141 Op1, Op2, Flags); 3142 setValue(&I, BinNodeValue); 3143 } 3144 3145 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) { 3146 SDValue Op1 = getValue(I.getOperand(0)); 3147 SDValue Op2 = getValue(I.getOperand(1)); 3148 3149 EVT ShiftTy = DAG.getTargetLoweringInfo().getShiftAmountTy( 3150 Op1.getValueType(), DAG.getDataLayout()); 3151 3152 // Coerce the shift amount to the right type if we can. This exposes the 3153 // truncate or zext to optimization early. 3154 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) { 3155 assert(ShiftTy.getSizeInBits() >= Log2_32_Ceil(Op1.getValueSizeInBits()) && 3156 "Unexpected shift type"); 3157 Op2 = DAG.getZExtOrTrunc(Op2, getCurSDLoc(), ShiftTy); 3158 } 3159 3160 bool nuw = false; 3161 bool nsw = false; 3162 bool exact = false; 3163 3164 if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) { 3165 3166 if (const OverflowingBinaryOperator *OFBinOp = 3167 dyn_cast<const OverflowingBinaryOperator>(&I)) { 3168 nuw = OFBinOp->hasNoUnsignedWrap(); 3169 nsw = OFBinOp->hasNoSignedWrap(); 3170 } 3171 if (const PossiblyExactOperator *ExactOp = 3172 dyn_cast<const PossiblyExactOperator>(&I)) 3173 exact = ExactOp->isExact(); 3174 } 3175 SDNodeFlags Flags; 3176 Flags.setExact(exact); 3177 Flags.setNoSignedWrap(nsw); 3178 Flags.setNoUnsignedWrap(nuw); 3179 SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2, 3180 Flags); 3181 setValue(&I, Res); 3182 } 3183 3184 void SelectionDAGBuilder::visitSDiv(const User &I) { 3185 SDValue Op1 = getValue(I.getOperand(0)); 3186 SDValue Op2 = getValue(I.getOperand(1)); 3187 3188 SDNodeFlags Flags; 3189 Flags.setExact(isa<PossiblyExactOperator>(&I) && 3190 cast<PossiblyExactOperator>(&I)->isExact()); 3191 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(), Op1, 3192 Op2, Flags)); 3193 } 3194 3195 void SelectionDAGBuilder::visitICmp(const User &I) { 3196 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 3197 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I)) 3198 predicate = IC->getPredicate(); 3199 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 3200 predicate = ICmpInst::Predicate(IC->getPredicate()); 3201 SDValue Op1 = getValue(I.getOperand(0)); 3202 SDValue Op2 = getValue(I.getOperand(1)); 3203 ISD::CondCode Opcode = getICmpCondCode(predicate); 3204 3205 auto &TLI = DAG.getTargetLoweringInfo(); 3206 EVT MemVT = 3207 TLI.getMemValueType(DAG.getDataLayout(), I.getOperand(0)->getType()); 3208 3209 // If a pointer's DAG type is larger than its memory type then the DAG values 3210 // are zero-extended. This breaks signed comparisons so truncate back to the 3211 // underlying type before doing the compare. 3212 if (Op1.getValueType() != MemVT) { 3213 Op1 = DAG.getPtrExtOrTrunc(Op1, getCurSDLoc(), MemVT); 3214 Op2 = DAG.getPtrExtOrTrunc(Op2, getCurSDLoc(), MemVT); 3215 } 3216 3217 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), 3218 I.getType()); 3219 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode)); 3220 } 3221 3222 void SelectionDAGBuilder::visitFCmp(const User &I) { 3223 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 3224 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I)) 3225 predicate = FC->getPredicate(); 3226 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 3227 predicate = FCmpInst::Predicate(FC->getPredicate()); 3228 SDValue Op1 = getValue(I.getOperand(0)); 3229 SDValue Op2 = getValue(I.getOperand(1)); 3230 3231 ISD::CondCode Condition = getFCmpCondCode(predicate); 3232 auto *FPMO = cast<FPMathOperator>(&I); 3233 if (FPMO->hasNoNaNs() || TM.Options.NoNaNsFPMath) 3234 Condition = getFCmpCodeWithoutNaN(Condition); 3235 3236 SDNodeFlags Flags; 3237 Flags.copyFMF(*FPMO); 3238 SelectionDAG::FlagInserter FlagsInserter(DAG, Flags); 3239 3240 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), 3241 I.getType()); 3242 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition)); 3243 } 3244 3245 // Check if the condition of the select has one use or two users that are both 3246 // selects with the same condition. 3247 static bool hasOnlySelectUsers(const Value *Cond) { 3248 return llvm::all_of(Cond->users(), [](const Value *V) { 3249 return isa<SelectInst>(V); 3250 }); 3251 } 3252 3253 void SelectionDAGBuilder::visitSelect(const User &I) { 3254 SmallVector<EVT, 4> ValueVTs; 3255 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), I.getType(), 3256 ValueVTs); 3257 unsigned NumValues = ValueVTs.size(); 3258 if (NumValues == 0) return; 3259 3260 SmallVector<SDValue, 4> Values(NumValues); 3261 SDValue Cond = getValue(I.getOperand(0)); 3262 SDValue LHSVal = getValue(I.getOperand(1)); 3263 SDValue RHSVal = getValue(I.getOperand(2)); 3264 SmallVector<SDValue, 1> BaseOps(1, Cond); 3265 ISD::NodeType OpCode = 3266 Cond.getValueType().isVector() ? ISD::VSELECT : ISD::SELECT; 3267 3268 bool IsUnaryAbs = false; 3269 bool Negate = false; 3270 3271 SDNodeFlags Flags; 3272 if (auto *FPOp = dyn_cast<FPMathOperator>(&I)) 3273 Flags.copyFMF(*FPOp); 3274 3275 // Min/max matching is only viable if all output VTs are the same. 3276 if (is_splat(ValueVTs)) { 3277 EVT VT = ValueVTs[0]; 3278 LLVMContext &Ctx = *DAG.getContext(); 3279 auto &TLI = DAG.getTargetLoweringInfo(); 3280 3281 // We care about the legality of the operation after it has been type 3282 // legalized. 3283 while (TLI.getTypeAction(Ctx, VT) != TargetLoweringBase::TypeLegal) 3284 VT = TLI.getTypeToTransformTo(Ctx, VT); 3285 3286 // If the vselect is legal, assume we want to leave this as a vector setcc + 3287 // vselect. Otherwise, if this is going to be scalarized, we want to see if 3288 // min/max is legal on the scalar type. 3289 bool UseScalarMinMax = VT.isVector() && 3290 !TLI.isOperationLegalOrCustom(ISD::VSELECT, VT); 3291 3292 Value *LHS, *RHS; 3293 auto SPR = matchSelectPattern(const_cast<User*>(&I), LHS, RHS); 3294 ISD::NodeType Opc = ISD::DELETED_NODE; 3295 switch (SPR.Flavor) { 3296 case SPF_UMAX: Opc = ISD::UMAX; break; 3297 case SPF_UMIN: Opc = ISD::UMIN; break; 3298 case SPF_SMAX: Opc = ISD::SMAX; break; 3299 case SPF_SMIN: Opc = ISD::SMIN; break; 3300 case SPF_FMINNUM: 3301 switch (SPR.NaNBehavior) { 3302 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?"); 3303 case SPNB_RETURNS_NAN: Opc = ISD::FMINIMUM; break; 3304 case SPNB_RETURNS_OTHER: Opc = ISD::FMINNUM; break; 3305 case SPNB_RETURNS_ANY: { 3306 if (TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT)) 3307 Opc = ISD::FMINNUM; 3308 else if (TLI.isOperationLegalOrCustom(ISD::FMINIMUM, VT)) 3309 Opc = ISD::FMINIMUM; 3310 else if (UseScalarMinMax) 3311 Opc = TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT.getScalarType()) ? 3312 ISD::FMINNUM : ISD::FMINIMUM; 3313 break; 3314 } 3315 } 3316 break; 3317 case SPF_FMAXNUM: 3318 switch (SPR.NaNBehavior) { 3319 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?"); 3320 case SPNB_RETURNS_NAN: Opc = ISD::FMAXIMUM; break; 3321 case SPNB_RETURNS_OTHER: Opc = ISD::FMAXNUM; break; 3322 case SPNB_RETURNS_ANY: 3323 3324 if (TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT)) 3325 Opc = ISD::FMAXNUM; 3326 else if (TLI.isOperationLegalOrCustom(ISD::FMAXIMUM, VT)) 3327 Opc = ISD::FMAXIMUM; 3328 else if (UseScalarMinMax) 3329 Opc = TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT.getScalarType()) ? 3330 ISD::FMAXNUM : ISD::FMAXIMUM; 3331 break; 3332 } 3333 break; 3334 case SPF_NABS: 3335 Negate = true; 3336 LLVM_FALLTHROUGH; 3337 case SPF_ABS: 3338 IsUnaryAbs = true; 3339 Opc = ISD::ABS; 3340 break; 3341 default: break; 3342 } 3343 3344 if (!IsUnaryAbs && Opc != ISD::DELETED_NODE && 3345 (TLI.isOperationLegalOrCustom(Opc, VT) || 3346 (UseScalarMinMax && 3347 TLI.isOperationLegalOrCustom(Opc, VT.getScalarType()))) && 3348 // If the underlying comparison instruction is used by any other 3349 // instruction, the consumed instructions won't be destroyed, so it is 3350 // not profitable to convert to a min/max. 3351 hasOnlySelectUsers(cast<SelectInst>(I).getCondition())) { 3352 OpCode = Opc; 3353 LHSVal = getValue(LHS); 3354 RHSVal = getValue(RHS); 3355 BaseOps.clear(); 3356 } 3357 3358 if (IsUnaryAbs) { 3359 OpCode = Opc; 3360 LHSVal = getValue(LHS); 3361 BaseOps.clear(); 3362 } 3363 } 3364 3365 if (IsUnaryAbs) { 3366 for (unsigned i = 0; i != NumValues; ++i) { 3367 SDLoc dl = getCurSDLoc(); 3368 EVT VT = LHSVal.getNode()->getValueType(LHSVal.getResNo() + i); 3369 Values[i] = 3370 DAG.getNode(OpCode, dl, VT, LHSVal.getValue(LHSVal.getResNo() + i)); 3371 if (Negate) 3372 Values[i] = DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(0, dl, VT), 3373 Values[i]); 3374 } 3375 } else { 3376 for (unsigned i = 0; i != NumValues; ++i) { 3377 SmallVector<SDValue, 3> Ops(BaseOps.begin(), BaseOps.end()); 3378 Ops.push_back(SDValue(LHSVal.getNode(), LHSVal.getResNo() + i)); 3379 Ops.push_back(SDValue(RHSVal.getNode(), RHSVal.getResNo() + i)); 3380 Values[i] = DAG.getNode( 3381 OpCode, getCurSDLoc(), 3382 LHSVal.getNode()->getValueType(LHSVal.getResNo() + i), Ops, Flags); 3383 } 3384 } 3385 3386 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), 3387 DAG.getVTList(ValueVTs), Values)); 3388 } 3389 3390 void SelectionDAGBuilder::visitTrunc(const User &I) { 3391 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). 3392 SDValue N = getValue(I.getOperand(0)); 3393 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), 3394 I.getType()); 3395 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N)); 3396 } 3397 3398 void SelectionDAGBuilder::visitZExt(const User &I) { 3399 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 3400 // ZExt also can't be a cast to bool for same reason. So, nothing much to do 3401 SDValue N = getValue(I.getOperand(0)); 3402 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), 3403 I.getType()); 3404 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N)); 3405 } 3406 3407 void SelectionDAGBuilder::visitSExt(const User &I) { 3408 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 3409 // SExt also can't be a cast to bool for same reason. So, nothing much to do 3410 SDValue N = getValue(I.getOperand(0)); 3411 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), 3412 I.getType()); 3413 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N)); 3414 } 3415 3416 void SelectionDAGBuilder::visitFPTrunc(const User &I) { 3417 // FPTrunc is never a no-op cast, no need to check 3418 SDValue N = getValue(I.getOperand(0)); 3419 SDLoc dl = getCurSDLoc(); 3420 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3421 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType()); 3422 setValue(&I, DAG.getNode(ISD::FP_ROUND, dl, DestVT, N, 3423 DAG.getTargetConstant( 3424 0, dl, TLI.getPointerTy(DAG.getDataLayout())))); 3425 } 3426 3427 void SelectionDAGBuilder::visitFPExt(const User &I) { 3428 // FPExt is never a no-op cast, no need to check 3429 SDValue N = getValue(I.getOperand(0)); 3430 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), 3431 I.getType()); 3432 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N)); 3433 } 3434 3435 void SelectionDAGBuilder::visitFPToUI(const User &I) { 3436 // FPToUI is never a no-op cast, no need to check 3437 SDValue N = getValue(I.getOperand(0)); 3438 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), 3439 I.getType()); 3440 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N)); 3441 } 3442 3443 void SelectionDAGBuilder::visitFPToSI(const User &I) { 3444 // FPToSI is never a no-op cast, no need to check 3445 SDValue N = getValue(I.getOperand(0)); 3446 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), 3447 I.getType()); 3448 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N)); 3449 } 3450 3451 void SelectionDAGBuilder::visitUIToFP(const User &I) { 3452 // UIToFP is never a no-op cast, no need to check 3453 SDValue N = getValue(I.getOperand(0)); 3454 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), 3455 I.getType()); 3456 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N)); 3457 } 3458 3459 void SelectionDAGBuilder::visitSIToFP(const User &I) { 3460 // SIToFP is never a no-op cast, no need to check 3461 SDValue N = getValue(I.getOperand(0)); 3462 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), 3463 I.getType()); 3464 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N)); 3465 } 3466 3467 void SelectionDAGBuilder::visitPtrToInt(const User &I) { 3468 // What to do depends on the size of the integer and the size of the pointer. 3469 // We can either truncate, zero extend, or no-op, accordingly. 3470 SDValue N = getValue(I.getOperand(0)); 3471 auto &TLI = DAG.getTargetLoweringInfo(); 3472 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), 3473 I.getType()); 3474 EVT PtrMemVT = 3475 TLI.getMemValueType(DAG.getDataLayout(), I.getOperand(0)->getType()); 3476 N = DAG.getPtrExtOrTrunc(N, getCurSDLoc(), PtrMemVT); 3477 N = DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT); 3478 setValue(&I, N); 3479 } 3480 3481 void SelectionDAGBuilder::visitIntToPtr(const User &I) { 3482 // What to do depends on the size of the integer and the size of the pointer. 3483 // We can either truncate, zero extend, or no-op, accordingly. 3484 SDValue N = getValue(I.getOperand(0)); 3485 auto &TLI = DAG.getTargetLoweringInfo(); 3486 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType()); 3487 EVT PtrMemVT = TLI.getMemValueType(DAG.getDataLayout(), I.getType()); 3488 N = DAG.getZExtOrTrunc(N, getCurSDLoc(), PtrMemVT); 3489 N = DAG.getPtrExtOrTrunc(N, getCurSDLoc(), DestVT); 3490 setValue(&I, N); 3491 } 3492 3493 void SelectionDAGBuilder::visitBitCast(const User &I) { 3494 SDValue N = getValue(I.getOperand(0)); 3495 SDLoc dl = getCurSDLoc(); 3496 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), 3497 I.getType()); 3498 3499 // BitCast assures us that source and destination are the same size so this is 3500 // either a BITCAST or a no-op. 3501 if (DestVT != N.getValueType()) 3502 setValue(&I, DAG.getNode(ISD::BITCAST, dl, 3503 DestVT, N)); // convert types. 3504 // Check if the original LLVM IR Operand was a ConstantInt, because getValue() 3505 // might fold any kind of constant expression to an integer constant and that 3506 // is not what we are looking for. Only recognize a bitcast of a genuine 3507 // constant integer as an opaque constant. 3508 else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0))) 3509 setValue(&I, DAG.getConstant(C->getValue(), dl, DestVT, /*isTarget=*/false, 3510 /*isOpaque*/true)); 3511 else 3512 setValue(&I, N); // noop cast. 3513 } 3514 3515 void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) { 3516 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3517 const Value *SV = I.getOperand(0); 3518 SDValue N = getValue(SV); 3519 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType()); 3520 3521 unsigned SrcAS = SV->getType()->getPointerAddressSpace(); 3522 unsigned DestAS = I.getType()->getPointerAddressSpace(); 3523 3524 if (!TM.isNoopAddrSpaceCast(SrcAS, DestAS)) 3525 N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS); 3526 3527 setValue(&I, N); 3528 } 3529 3530 void SelectionDAGBuilder::visitInsertElement(const User &I) { 3531 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3532 SDValue InVec = getValue(I.getOperand(0)); 3533 SDValue InVal = getValue(I.getOperand(1)); 3534 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)), getCurSDLoc(), 3535 TLI.getVectorIdxTy(DAG.getDataLayout())); 3536 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(), 3537 TLI.getValueType(DAG.getDataLayout(), I.getType()), 3538 InVec, InVal, InIdx)); 3539 } 3540 3541 void SelectionDAGBuilder::visitExtractElement(const User &I) { 3542 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3543 SDValue InVec = getValue(I.getOperand(0)); 3544 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)), getCurSDLoc(), 3545 TLI.getVectorIdxTy(DAG.getDataLayout())); 3546 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(), 3547 TLI.getValueType(DAG.getDataLayout(), I.getType()), 3548 InVec, InIdx)); 3549 } 3550 3551 void SelectionDAGBuilder::visitShuffleVector(const User &I) { 3552 SDValue Src1 = getValue(I.getOperand(0)); 3553 SDValue Src2 = getValue(I.getOperand(1)); 3554 ArrayRef<int> Mask; 3555 if (auto *SVI = dyn_cast<ShuffleVectorInst>(&I)) 3556 Mask = SVI->getShuffleMask(); 3557 else 3558 Mask = cast<ConstantExpr>(I).getShuffleMask(); 3559 SDLoc DL = getCurSDLoc(); 3560 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3561 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType()); 3562 EVT SrcVT = Src1.getValueType(); 3563 3564 if (all_of(Mask, [](int Elem) { return Elem == 0; }) && 3565 VT.isScalableVector()) { 3566 // Canonical splat form of first element of first input vector. 3567 SDValue FirstElt = 3568 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, SrcVT.getScalarType(), Src1, 3569 DAG.getVectorIdxConstant(0, DL)); 3570 setValue(&I, DAG.getNode(ISD::SPLAT_VECTOR, DL, VT, FirstElt)); 3571 return; 3572 } 3573 3574 // For now, we only handle splats for scalable vectors. 3575 // The DAGCombiner will perform a BUILD_VECTOR -> SPLAT_VECTOR transformation 3576 // for targets that support a SPLAT_VECTOR for non-scalable vector types. 3577 assert(!VT.isScalableVector() && "Unsupported scalable vector shuffle"); 3578 3579 unsigned SrcNumElts = SrcVT.getVectorNumElements(); 3580 unsigned MaskNumElts = Mask.size(); 3581 3582 if (SrcNumElts == MaskNumElts) { 3583 setValue(&I, DAG.getVectorShuffle(VT, DL, Src1, Src2, Mask)); 3584 return; 3585 } 3586 3587 // Normalize the shuffle vector since mask and vector length don't match. 3588 if (SrcNumElts < MaskNumElts) { 3589 // Mask is longer than the source vectors. We can use concatenate vector to 3590 // make the mask and vectors lengths match. 3591 3592 if (MaskNumElts % SrcNumElts == 0) { 3593 // Mask length is a multiple of the source vector length. 3594 // Check if the shuffle is some kind of concatenation of the input 3595 // vectors. 3596 unsigned NumConcat = MaskNumElts / SrcNumElts; 3597 bool IsConcat = true; 3598 SmallVector<int, 8> ConcatSrcs(NumConcat, -1); 3599 for (unsigned i = 0; i != MaskNumElts; ++i) { 3600 int Idx = Mask[i]; 3601 if (Idx < 0) 3602 continue; 3603 // Ensure the indices in each SrcVT sized piece are sequential and that 3604 // the same source is used for the whole piece. 3605 if ((Idx % SrcNumElts != (i % SrcNumElts)) || 3606 (ConcatSrcs[i / SrcNumElts] >= 0 && 3607 ConcatSrcs[i / SrcNumElts] != (int)(Idx / SrcNumElts))) { 3608 IsConcat = false; 3609 break; 3610 } 3611 // Remember which source this index came from. 3612 ConcatSrcs[i / SrcNumElts] = Idx / SrcNumElts; 3613 } 3614 3615 // The shuffle is concatenating multiple vectors together. Just emit 3616 // a CONCAT_VECTORS operation. 3617 if (IsConcat) { 3618 SmallVector<SDValue, 8> ConcatOps; 3619 for (auto Src : ConcatSrcs) { 3620 if (Src < 0) 3621 ConcatOps.push_back(DAG.getUNDEF(SrcVT)); 3622 else if (Src == 0) 3623 ConcatOps.push_back(Src1); 3624 else 3625 ConcatOps.push_back(Src2); 3626 } 3627 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, ConcatOps)); 3628 return; 3629 } 3630 } 3631 3632 unsigned PaddedMaskNumElts = alignTo(MaskNumElts, SrcNumElts); 3633 unsigned NumConcat = PaddedMaskNumElts / SrcNumElts; 3634 EVT PaddedVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(), 3635 PaddedMaskNumElts); 3636 3637 // Pad both vectors with undefs to make them the same length as the mask. 3638 SDValue UndefVal = DAG.getUNDEF(SrcVT); 3639 3640 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal); 3641 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal); 3642 MOps1[0] = Src1; 3643 MOps2[0] = Src2; 3644 3645 Src1 = DAG.getNode(ISD::CONCAT_VECTORS, DL, PaddedVT, MOps1); 3646 Src2 = DAG.getNode(ISD::CONCAT_VECTORS, DL, PaddedVT, MOps2); 3647 3648 // Readjust mask for new input vector length. 3649 SmallVector<int, 8> MappedOps(PaddedMaskNumElts, -1); 3650 for (unsigned i = 0; i != MaskNumElts; ++i) { 3651 int Idx = Mask[i]; 3652 if (Idx >= (int)SrcNumElts) 3653 Idx -= SrcNumElts - PaddedMaskNumElts; 3654 MappedOps[i] = Idx; 3655 } 3656 3657 SDValue Result = DAG.getVectorShuffle(PaddedVT, DL, Src1, Src2, MappedOps); 3658 3659 // If the concatenated vector was padded, extract a subvector with the 3660 // correct number of elements. 3661 if (MaskNumElts != PaddedMaskNumElts) 3662 Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Result, 3663 DAG.getVectorIdxConstant(0, DL)); 3664 3665 setValue(&I, Result); 3666 return; 3667 } 3668 3669 if (SrcNumElts > MaskNumElts) { 3670 // Analyze the access pattern of the vector to see if we can extract 3671 // two subvectors and do the shuffle. 3672 int StartIdx[2] = { -1, -1 }; // StartIdx to extract from 3673 bool CanExtract = true; 3674 for (int Idx : Mask) { 3675 unsigned Input = 0; 3676 if (Idx < 0) 3677 continue; 3678 3679 if (Idx >= (int)SrcNumElts) { 3680 Input = 1; 3681 Idx -= SrcNumElts; 3682 } 3683 3684 // If all the indices come from the same MaskNumElts sized portion of 3685 // the sources we can use extract. Also make sure the extract wouldn't 3686 // extract past the end of the source. 3687 int NewStartIdx = alignDown(Idx, MaskNumElts); 3688 if (NewStartIdx + MaskNumElts > SrcNumElts || 3689 (StartIdx[Input] >= 0 && StartIdx[Input] != NewStartIdx)) 3690 CanExtract = false; 3691 // Make sure we always update StartIdx as we use it to track if all 3692 // elements are undef. 3693 StartIdx[Input] = NewStartIdx; 3694 } 3695 3696 if (StartIdx[0] < 0 && StartIdx[1] < 0) { 3697 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used. 3698 return; 3699 } 3700 if (CanExtract) { 3701 // Extract appropriate subvector and generate a vector shuffle 3702 for (unsigned Input = 0; Input < 2; ++Input) { 3703 SDValue &Src = Input == 0 ? Src1 : Src2; 3704 if (StartIdx[Input] < 0) 3705 Src = DAG.getUNDEF(VT); 3706 else { 3707 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Src, 3708 DAG.getVectorIdxConstant(StartIdx[Input], DL)); 3709 } 3710 } 3711 3712 // Calculate new mask. 3713 SmallVector<int, 8> MappedOps(Mask.begin(), Mask.end()); 3714 for (int &Idx : MappedOps) { 3715 if (Idx >= (int)SrcNumElts) 3716 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts; 3717 else if (Idx >= 0) 3718 Idx -= StartIdx[0]; 3719 } 3720 3721 setValue(&I, DAG.getVectorShuffle(VT, DL, Src1, Src2, MappedOps)); 3722 return; 3723 } 3724 } 3725 3726 // We can't use either concat vectors or extract subvectors so fall back to 3727 // replacing the shuffle with extract and build vector. 3728 // to insert and build vector. 3729 EVT EltVT = VT.getVectorElementType(); 3730 SmallVector<SDValue,8> Ops; 3731 for (int Idx : Mask) { 3732 SDValue Res; 3733 3734 if (Idx < 0) { 3735 Res = DAG.getUNDEF(EltVT); 3736 } else { 3737 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2; 3738 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts; 3739 3740 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Src, 3741 DAG.getVectorIdxConstant(Idx, DL)); 3742 } 3743 3744 Ops.push_back(Res); 3745 } 3746 3747 setValue(&I, DAG.getBuildVector(VT, DL, Ops)); 3748 } 3749 3750 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) { 3751 ArrayRef<unsigned> Indices = I.getIndices(); 3752 const Value *Op0 = I.getOperand(0); 3753 const Value *Op1 = I.getOperand(1); 3754 Type *AggTy = I.getType(); 3755 Type *ValTy = Op1->getType(); 3756 bool IntoUndef = isa<UndefValue>(Op0); 3757 bool FromUndef = isa<UndefValue>(Op1); 3758 3759 unsigned LinearIndex = ComputeLinearIndex(AggTy, Indices); 3760 3761 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3762 SmallVector<EVT, 4> AggValueVTs; 3763 ComputeValueVTs(TLI, DAG.getDataLayout(), AggTy, AggValueVTs); 3764 SmallVector<EVT, 4> ValValueVTs; 3765 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs); 3766 3767 unsigned NumAggValues = AggValueVTs.size(); 3768 unsigned NumValValues = ValValueVTs.size(); 3769 SmallVector<SDValue, 4> Values(NumAggValues); 3770 3771 // Ignore an insertvalue that produces an empty object 3772 if (!NumAggValues) { 3773 setValue(&I, DAG.getUNDEF(MVT(MVT::Other))); 3774 return; 3775 } 3776 3777 SDValue Agg = getValue(Op0); 3778 unsigned i = 0; 3779 // Copy the beginning value(s) from the original aggregate. 3780 for (; i != LinearIndex; ++i) 3781 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 3782 SDValue(Agg.getNode(), Agg.getResNo() + i); 3783 // Copy values from the inserted value(s). 3784 if (NumValValues) { 3785 SDValue Val = getValue(Op1); 3786 for (; i != LinearIndex + NumValValues; ++i) 3787 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) : 3788 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex); 3789 } 3790 // Copy remaining value(s) from the original aggregate. 3791 for (; i != NumAggValues; ++i) 3792 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 3793 SDValue(Agg.getNode(), Agg.getResNo() + i); 3794 3795 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), 3796 DAG.getVTList(AggValueVTs), Values)); 3797 } 3798 3799 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) { 3800 ArrayRef<unsigned> Indices = I.getIndices(); 3801 const Value *Op0 = I.getOperand(0); 3802 Type *AggTy = Op0->getType(); 3803 Type *ValTy = I.getType(); 3804 bool OutOfUndef = isa<UndefValue>(Op0); 3805 3806 unsigned LinearIndex = ComputeLinearIndex(AggTy, Indices); 3807 3808 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3809 SmallVector<EVT, 4> ValValueVTs; 3810 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs); 3811 3812 unsigned NumValValues = ValValueVTs.size(); 3813 3814 // Ignore a extractvalue that produces an empty object 3815 if (!NumValValues) { 3816 setValue(&I, DAG.getUNDEF(MVT(MVT::Other))); 3817 return; 3818 } 3819 3820 SmallVector<SDValue, 4> Values(NumValValues); 3821 3822 SDValue Agg = getValue(Op0); 3823 // Copy out the selected value(s). 3824 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i) 3825 Values[i - LinearIndex] = 3826 OutOfUndef ? 3827 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) : 3828 SDValue(Agg.getNode(), Agg.getResNo() + i); 3829 3830 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), 3831 DAG.getVTList(ValValueVTs), Values)); 3832 } 3833 3834 void SelectionDAGBuilder::visitGetElementPtr(const User &I) { 3835 Value *Op0 = I.getOperand(0); 3836 // Note that the pointer operand may be a vector of pointers. Take the scalar 3837 // element which holds a pointer. 3838 unsigned AS = Op0->getType()->getScalarType()->getPointerAddressSpace(); 3839 SDValue N = getValue(Op0); 3840 SDLoc dl = getCurSDLoc(); 3841 auto &TLI = DAG.getTargetLoweringInfo(); 3842 3843 // Normalize Vector GEP - all scalar operands should be converted to the 3844 // splat vector. 3845 bool IsVectorGEP = I.getType()->isVectorTy(); 3846 ElementCount VectorElementCount = 3847 IsVectorGEP ? cast<VectorType>(I.getType())->getElementCount() 3848 : ElementCount::getFixed(0); 3849 3850 if (IsVectorGEP && !N.getValueType().isVector()) { 3851 LLVMContext &Context = *DAG.getContext(); 3852 EVT VT = EVT::getVectorVT(Context, N.getValueType(), VectorElementCount); 3853 if (VectorElementCount.isScalable()) 3854 N = DAG.getSplatVector(VT, dl, N); 3855 else 3856 N = DAG.getSplatBuildVector(VT, dl, N); 3857 } 3858 3859 for (gep_type_iterator GTI = gep_type_begin(&I), E = gep_type_end(&I); 3860 GTI != E; ++GTI) { 3861 const Value *Idx = GTI.getOperand(); 3862 if (StructType *StTy = GTI.getStructTypeOrNull()) { 3863 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue(); 3864 if (Field) { 3865 // N = N + Offset 3866 uint64_t Offset = 3867 DAG.getDataLayout().getStructLayout(StTy)->getElementOffset(Field); 3868 3869 // In an inbounds GEP with an offset that is nonnegative even when 3870 // interpreted as signed, assume there is no unsigned overflow. 3871 SDNodeFlags Flags; 3872 if (int64_t(Offset) >= 0 && cast<GEPOperator>(I).isInBounds()) 3873 Flags.setNoUnsignedWrap(true); 3874 3875 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N, 3876 DAG.getConstant(Offset, dl, N.getValueType()), Flags); 3877 } 3878 } else { 3879 // IdxSize is the width of the arithmetic according to IR semantics. 3880 // In SelectionDAG, we may prefer to do arithmetic in a wider bitwidth 3881 // (and fix up the result later). 3882 unsigned IdxSize = DAG.getDataLayout().getIndexSizeInBits(AS); 3883 MVT IdxTy = MVT::getIntegerVT(IdxSize); 3884 TypeSize ElementSize = 3885 DAG.getDataLayout().getTypeAllocSize(GTI.getIndexedType()); 3886 // We intentionally mask away the high bits here; ElementSize may not 3887 // fit in IdxTy. 3888 APInt ElementMul(IdxSize, ElementSize.getKnownMinSize()); 3889 bool ElementScalable = ElementSize.isScalable(); 3890 3891 // If this is a scalar constant or a splat vector of constants, 3892 // handle it quickly. 3893 const auto *C = dyn_cast<Constant>(Idx); 3894 if (C && isa<VectorType>(C->getType())) 3895 C = C->getSplatValue(); 3896 3897 const auto *CI = dyn_cast_or_null<ConstantInt>(C); 3898 if (CI && CI->isZero()) 3899 continue; 3900 if (CI && !ElementScalable) { 3901 APInt Offs = ElementMul * CI->getValue().sextOrTrunc(IdxSize); 3902 LLVMContext &Context = *DAG.getContext(); 3903 SDValue OffsVal; 3904 if (IsVectorGEP) 3905 OffsVal = DAG.getConstant( 3906 Offs, dl, EVT::getVectorVT(Context, IdxTy, VectorElementCount)); 3907 else 3908 OffsVal = DAG.getConstant(Offs, dl, IdxTy); 3909 3910 // In an inbounds GEP with an offset that is nonnegative even when 3911 // interpreted as signed, assume there is no unsigned overflow. 3912 SDNodeFlags Flags; 3913 if (Offs.isNonNegative() && cast<GEPOperator>(I).isInBounds()) 3914 Flags.setNoUnsignedWrap(true); 3915 3916 OffsVal = DAG.getSExtOrTrunc(OffsVal, dl, N.getValueType()); 3917 3918 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N, OffsVal, Flags); 3919 continue; 3920 } 3921 3922 // N = N + Idx * ElementMul; 3923 SDValue IdxN = getValue(Idx); 3924 3925 if (!IdxN.getValueType().isVector() && IsVectorGEP) { 3926 EVT VT = EVT::getVectorVT(*Context, IdxN.getValueType(), 3927 VectorElementCount); 3928 if (VectorElementCount.isScalable()) 3929 IdxN = DAG.getSplatVector(VT, dl, IdxN); 3930 else 3931 IdxN = DAG.getSplatBuildVector(VT, dl, IdxN); 3932 } 3933 3934 // If the index is smaller or larger than intptr_t, truncate or extend 3935 // it. 3936 IdxN = DAG.getSExtOrTrunc(IdxN, dl, N.getValueType()); 3937 3938 if (ElementScalable) { 3939 EVT VScaleTy = N.getValueType().getScalarType(); 3940 SDValue VScale = DAG.getNode( 3941 ISD::VSCALE, dl, VScaleTy, 3942 DAG.getConstant(ElementMul.getZExtValue(), dl, VScaleTy)); 3943 if (IsVectorGEP) 3944 VScale = DAG.getSplatVector(N.getValueType(), dl, VScale); 3945 IdxN = DAG.getNode(ISD::MUL, dl, N.getValueType(), IdxN, VScale); 3946 } else { 3947 // If this is a multiply by a power of two, turn it into a shl 3948 // immediately. This is a very common case. 3949 if (ElementMul != 1) { 3950 if (ElementMul.isPowerOf2()) { 3951 unsigned Amt = ElementMul.logBase2(); 3952 IdxN = DAG.getNode(ISD::SHL, dl, 3953 N.getValueType(), IdxN, 3954 DAG.getConstant(Amt, dl, IdxN.getValueType())); 3955 } else { 3956 SDValue Scale = DAG.getConstant(ElementMul.getZExtValue(), dl, 3957 IdxN.getValueType()); 3958 IdxN = DAG.getNode(ISD::MUL, dl, 3959 N.getValueType(), IdxN, Scale); 3960 } 3961 } 3962 } 3963 3964 N = DAG.getNode(ISD::ADD, dl, 3965 N.getValueType(), N, IdxN); 3966 } 3967 } 3968 3969 MVT PtrTy = TLI.getPointerTy(DAG.getDataLayout(), AS); 3970 MVT PtrMemTy = TLI.getPointerMemTy(DAG.getDataLayout(), AS); 3971 if (IsVectorGEP) { 3972 PtrTy = MVT::getVectorVT(PtrTy, VectorElementCount); 3973 PtrMemTy = MVT::getVectorVT(PtrMemTy, VectorElementCount); 3974 } 3975 3976 if (PtrMemTy != PtrTy && !cast<GEPOperator>(I).isInBounds()) 3977 N = DAG.getPtrExtendInReg(N, dl, PtrMemTy); 3978 3979 setValue(&I, N); 3980 } 3981 3982 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) { 3983 // If this is a fixed sized alloca in the entry block of the function, 3984 // allocate it statically on the stack. 3985 if (FuncInfo.StaticAllocaMap.count(&I)) 3986 return; // getValue will auto-populate this. 3987 3988 SDLoc dl = getCurSDLoc(); 3989 Type *Ty = I.getAllocatedType(); 3990 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3991 auto &DL = DAG.getDataLayout(); 3992 TypeSize TySize = DL.getTypeAllocSize(Ty); 3993 MaybeAlign Alignment = std::max(DL.getPrefTypeAlign(Ty), I.getAlign()); 3994 3995 SDValue AllocSize = getValue(I.getArraySize()); 3996 3997 EVT IntPtr = TLI.getPointerTy(DAG.getDataLayout(), DL.getAllocaAddrSpace()); 3998 if (AllocSize.getValueType() != IntPtr) 3999 AllocSize = DAG.getZExtOrTrunc(AllocSize, dl, IntPtr); 4000 4001 if (TySize.isScalable()) 4002 AllocSize = DAG.getNode(ISD::MUL, dl, IntPtr, AllocSize, 4003 DAG.getVScale(dl, IntPtr, 4004 APInt(IntPtr.getScalarSizeInBits(), 4005 TySize.getKnownMinValue()))); 4006 else 4007 AllocSize = 4008 DAG.getNode(ISD::MUL, dl, IntPtr, AllocSize, 4009 DAG.getConstant(TySize.getFixedValue(), dl, IntPtr)); 4010 4011 // Handle alignment. If the requested alignment is less than or equal to 4012 // the stack alignment, ignore it. If the size is greater than or equal to 4013 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node. 4014 Align StackAlign = DAG.getSubtarget().getFrameLowering()->getStackAlign(); 4015 if (*Alignment <= StackAlign) 4016 Alignment = None; 4017 4018 const uint64_t StackAlignMask = StackAlign.value() - 1U; 4019 // Round the size of the allocation up to the stack alignment size 4020 // by add SA-1 to the size. This doesn't overflow because we're computing 4021 // an address inside an alloca. 4022 SDNodeFlags Flags; 4023 Flags.setNoUnsignedWrap(true); 4024 AllocSize = DAG.getNode(ISD::ADD, dl, AllocSize.getValueType(), AllocSize, 4025 DAG.getConstant(StackAlignMask, dl, IntPtr), Flags); 4026 4027 // Mask out the low bits for alignment purposes. 4028 AllocSize = DAG.getNode(ISD::AND, dl, AllocSize.getValueType(), AllocSize, 4029 DAG.getConstant(~StackAlignMask, dl, IntPtr)); 4030 4031 SDValue Ops[] = { 4032 getRoot(), AllocSize, 4033 DAG.getConstant(Alignment ? Alignment->value() : 0, dl, IntPtr)}; 4034 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other); 4035 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, dl, VTs, Ops); 4036 setValue(&I, DSA); 4037 DAG.setRoot(DSA.getValue(1)); 4038 4039 assert(FuncInfo.MF->getFrameInfo().hasVarSizedObjects()); 4040 } 4041 4042 void SelectionDAGBuilder::visitLoad(const LoadInst &I) { 4043 if (I.isAtomic()) 4044 return visitAtomicLoad(I); 4045 4046 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 4047 const Value *SV = I.getOperand(0); 4048 if (TLI.supportSwiftError()) { 4049 // Swifterror values can come from either a function parameter with 4050 // swifterror attribute or an alloca with swifterror attribute. 4051 if (const Argument *Arg = dyn_cast<Argument>(SV)) { 4052 if (Arg->hasSwiftErrorAttr()) 4053 return visitLoadFromSwiftError(I); 4054 } 4055 4056 if (const AllocaInst *Alloca = dyn_cast<AllocaInst>(SV)) { 4057 if (Alloca->isSwiftError()) 4058 return visitLoadFromSwiftError(I); 4059 } 4060 } 4061 4062 SDValue Ptr = getValue(SV); 4063 4064 Type *Ty = I.getType(); 4065 Align Alignment = I.getAlign(); 4066 4067 AAMDNodes AAInfo = I.getAAMetadata(); 4068 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range); 4069 4070 SmallVector<EVT, 4> ValueVTs, MemVTs; 4071 SmallVector<uint64_t, 4> Offsets; 4072 ComputeValueVTs(TLI, DAG.getDataLayout(), Ty, ValueVTs, &MemVTs, &Offsets); 4073 unsigned NumValues = ValueVTs.size(); 4074 if (NumValues == 0) 4075 return; 4076 4077 bool isVolatile = I.isVolatile(); 4078 4079 SDValue Root; 4080 bool ConstantMemory = false; 4081 if (isVolatile) 4082 // Serialize volatile loads with other side effects. 4083 Root = getRoot(); 4084 else if (NumValues > MaxParallelChains) 4085 Root = getMemoryRoot(); 4086 else if (AA && 4087 AA->pointsToConstantMemory(MemoryLocation( 4088 SV, 4089 LocationSize::precise(DAG.getDataLayout().getTypeStoreSize(Ty)), 4090 AAInfo))) { 4091 // Do not serialize (non-volatile) loads of constant memory with anything. 4092 Root = DAG.getEntryNode(); 4093 ConstantMemory = true; 4094 } else { 4095 // Do not serialize non-volatile loads against each other. 4096 Root = DAG.getRoot(); 4097 } 4098 4099 SDLoc dl = getCurSDLoc(); 4100 4101 if (isVolatile) 4102 Root = TLI.prepareVolatileOrAtomicLoad(Root, dl, DAG); 4103 4104 // An aggregate load cannot wrap around the address space, so offsets to its 4105 // parts don't wrap either. 4106 SDNodeFlags Flags; 4107 Flags.setNoUnsignedWrap(true); 4108 4109 SmallVector<SDValue, 4> Values(NumValues); 4110 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues)); 4111 EVT PtrVT = Ptr.getValueType(); 4112 4113 MachineMemOperand::Flags MMOFlags 4114 = TLI.getLoadMemOperandFlags(I, DAG.getDataLayout()); 4115 4116 unsigned ChainI = 0; 4117 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { 4118 // Serializing loads here may result in excessive register pressure, and 4119 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling 4120 // could recover a bit by hoisting nodes upward in the chain by recognizing 4121 // they are side-effect free or do not alias. The optimizer should really 4122 // avoid this case by converting large object/array copies to llvm.memcpy 4123 // (MaxParallelChains should always remain as failsafe). 4124 if (ChainI == MaxParallelChains) { 4125 assert(PendingLoads.empty() && "PendingLoads must be serialized first"); 4126 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 4127 makeArrayRef(Chains.data(), ChainI)); 4128 Root = Chain; 4129 ChainI = 0; 4130 } 4131 SDValue A = DAG.getNode(ISD::ADD, dl, 4132 PtrVT, Ptr, 4133 DAG.getConstant(Offsets[i], dl, PtrVT), 4134 Flags); 4135 4136 SDValue L = DAG.getLoad(MemVTs[i], dl, Root, A, 4137 MachinePointerInfo(SV, Offsets[i]), Alignment, 4138 MMOFlags, AAInfo, Ranges); 4139 Chains[ChainI] = L.getValue(1); 4140 4141 if (MemVTs[i] != ValueVTs[i]) 4142 L = DAG.getZExtOrTrunc(L, dl, ValueVTs[i]); 4143 4144 Values[i] = L; 4145 } 4146 4147 if (!ConstantMemory) { 4148 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 4149 makeArrayRef(Chains.data(), ChainI)); 4150 if (isVolatile) 4151 DAG.setRoot(Chain); 4152 else 4153 PendingLoads.push_back(Chain); 4154 } 4155 4156 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, dl, 4157 DAG.getVTList(ValueVTs), Values)); 4158 } 4159 4160 void SelectionDAGBuilder::visitStoreToSwiftError(const StoreInst &I) { 4161 assert(DAG.getTargetLoweringInfo().supportSwiftError() && 4162 "call visitStoreToSwiftError when backend supports swifterror"); 4163 4164 SmallVector<EVT, 4> ValueVTs; 4165 SmallVector<uint64_t, 4> Offsets; 4166 const Value *SrcV = I.getOperand(0); 4167 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), 4168 SrcV->getType(), ValueVTs, &Offsets); 4169 assert(ValueVTs.size() == 1 && Offsets[0] == 0 && 4170 "expect a single EVT for swifterror"); 4171 4172 SDValue Src = getValue(SrcV); 4173 // Create a virtual register, then update the virtual register. 4174 Register VReg = 4175 SwiftError.getOrCreateVRegDefAt(&I, FuncInfo.MBB, I.getPointerOperand()); 4176 // Chain, DL, Reg, N or Chain, DL, Reg, N, Glue 4177 // Chain can be getRoot or getControlRoot. 4178 SDValue CopyNode = DAG.getCopyToReg(getRoot(), getCurSDLoc(), VReg, 4179 SDValue(Src.getNode(), Src.getResNo())); 4180 DAG.setRoot(CopyNode); 4181 } 4182 4183 void SelectionDAGBuilder::visitLoadFromSwiftError(const LoadInst &I) { 4184 assert(DAG.getTargetLoweringInfo().supportSwiftError() && 4185 "call visitLoadFromSwiftError when backend supports swifterror"); 4186 4187 assert(!I.isVolatile() && 4188 !I.hasMetadata(LLVMContext::MD_nontemporal) && 4189 !I.hasMetadata(LLVMContext::MD_invariant_load) && 4190 "Support volatile, non temporal, invariant for load_from_swift_error"); 4191 4192 const Value *SV = I.getOperand(0); 4193 Type *Ty = I.getType(); 4194 assert( 4195 (!AA || 4196 !AA->pointsToConstantMemory(MemoryLocation( 4197 SV, LocationSize::precise(DAG.getDataLayout().getTypeStoreSize(Ty)), 4198 I.getAAMetadata()))) && 4199 "load_from_swift_error should not be constant memory"); 4200 4201 SmallVector<EVT, 4> ValueVTs; 4202 SmallVector<uint64_t, 4> Offsets; 4203 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), Ty, 4204 ValueVTs, &Offsets); 4205 assert(ValueVTs.size() == 1 && Offsets[0] == 0 && 4206 "expect a single EVT for swifterror"); 4207 4208 // Chain, DL, Reg, VT, Glue or Chain, DL, Reg, VT 4209 SDValue L = DAG.getCopyFromReg( 4210 getRoot(), getCurSDLoc(), 4211 SwiftError.getOrCreateVRegUseAt(&I, FuncInfo.MBB, SV), ValueVTs[0]); 4212 4213 setValue(&I, L); 4214 } 4215 4216 void SelectionDAGBuilder::visitStore(const StoreInst &I) { 4217 if (I.isAtomic()) 4218 return visitAtomicStore(I); 4219 4220 const Value *SrcV = I.getOperand(0); 4221 const Value *PtrV = I.getOperand(1); 4222 4223 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 4224 if (TLI.supportSwiftError()) { 4225 // Swifterror values can come from either a function parameter with 4226 // swifterror attribute or an alloca with swifterror attribute. 4227 if (const Argument *Arg = dyn_cast<Argument>(PtrV)) { 4228 if (Arg->hasSwiftErrorAttr()) 4229 return visitStoreToSwiftError(I); 4230 } 4231 4232 if (const AllocaInst *Alloca = dyn_cast<AllocaInst>(PtrV)) { 4233 if (Alloca->isSwiftError()) 4234 return visitStoreToSwiftError(I); 4235 } 4236 } 4237 4238 SmallVector<EVT, 4> ValueVTs, MemVTs; 4239 SmallVector<uint64_t, 4> Offsets; 4240 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), 4241 SrcV->getType(), ValueVTs, &MemVTs, &Offsets); 4242 unsigned NumValues = ValueVTs.size(); 4243 if (NumValues == 0) 4244 return; 4245 4246 // Get the lowered operands. Note that we do this after 4247 // checking if NumResults is zero, because with zero results 4248 // the operands won't have values in the map. 4249 SDValue Src = getValue(SrcV); 4250 SDValue Ptr = getValue(PtrV); 4251 4252 SDValue Root = I.isVolatile() ? getRoot() : getMemoryRoot(); 4253 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues)); 4254 SDLoc dl = getCurSDLoc(); 4255 Align Alignment = I.getAlign(); 4256 AAMDNodes AAInfo = I.getAAMetadata(); 4257 4258 auto MMOFlags = TLI.getStoreMemOperandFlags(I, DAG.getDataLayout()); 4259 4260 // An aggregate load cannot wrap around the address space, so offsets to its 4261 // parts don't wrap either. 4262 SDNodeFlags Flags; 4263 Flags.setNoUnsignedWrap(true); 4264 4265 unsigned ChainI = 0; 4266 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { 4267 // See visitLoad comments. 4268 if (ChainI == MaxParallelChains) { 4269 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 4270 makeArrayRef(Chains.data(), ChainI)); 4271 Root = Chain; 4272 ChainI = 0; 4273 } 4274 SDValue Add = 4275 DAG.getMemBasePlusOffset(Ptr, TypeSize::Fixed(Offsets[i]), dl, Flags); 4276 SDValue Val = SDValue(Src.getNode(), Src.getResNo() + i); 4277 if (MemVTs[i] != ValueVTs[i]) 4278 Val = DAG.getPtrExtOrTrunc(Val, dl, MemVTs[i]); 4279 SDValue St = 4280 DAG.getStore(Root, dl, Val, Add, MachinePointerInfo(PtrV, Offsets[i]), 4281 Alignment, MMOFlags, AAInfo); 4282 Chains[ChainI] = St; 4283 } 4284 4285 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 4286 makeArrayRef(Chains.data(), ChainI)); 4287 DAG.setRoot(StoreNode); 4288 } 4289 4290 void SelectionDAGBuilder::visitMaskedStore(const CallInst &I, 4291 bool IsCompressing) { 4292 SDLoc sdl = getCurSDLoc(); 4293 4294 auto getMaskedStoreOps = [&](Value *&Ptr, Value *&Mask, Value *&Src0, 4295 MaybeAlign &Alignment) { 4296 // llvm.masked.store.*(Src0, Ptr, alignment, Mask) 4297 Src0 = I.getArgOperand(0); 4298 Ptr = I.getArgOperand(1); 4299 Alignment = cast<ConstantInt>(I.getArgOperand(2))->getMaybeAlignValue(); 4300 Mask = I.getArgOperand(3); 4301 }; 4302 auto getCompressingStoreOps = [&](Value *&Ptr, Value *&Mask, Value *&Src0, 4303 MaybeAlign &Alignment) { 4304 // llvm.masked.compressstore.*(Src0, Ptr, Mask) 4305 Src0 = I.getArgOperand(0); 4306 Ptr = I.getArgOperand(1); 4307 Mask = I.getArgOperand(2); 4308 Alignment = None; 4309 }; 4310 4311 Value *PtrOperand, *MaskOperand, *Src0Operand; 4312 MaybeAlign Alignment; 4313 if (IsCompressing) 4314 getCompressingStoreOps(PtrOperand, MaskOperand, Src0Operand, Alignment); 4315 else 4316 getMaskedStoreOps(PtrOperand, MaskOperand, Src0Operand, Alignment); 4317 4318 SDValue Ptr = getValue(PtrOperand); 4319 SDValue Src0 = getValue(Src0Operand); 4320 SDValue Mask = getValue(MaskOperand); 4321 SDValue Offset = DAG.getUNDEF(Ptr.getValueType()); 4322 4323 EVT VT = Src0.getValueType(); 4324 if (!Alignment) 4325 Alignment = DAG.getEVTAlign(VT); 4326 4327 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand( 4328 MachinePointerInfo(PtrOperand), MachineMemOperand::MOStore, 4329 MemoryLocation::UnknownSize, *Alignment, I.getAAMetadata()); 4330 SDValue StoreNode = 4331 DAG.getMaskedStore(getMemoryRoot(), sdl, Src0, Ptr, Offset, Mask, VT, MMO, 4332 ISD::UNINDEXED, false /* Truncating */, IsCompressing); 4333 DAG.setRoot(StoreNode); 4334 setValue(&I, StoreNode); 4335 } 4336 4337 // Get a uniform base for the Gather/Scatter intrinsic. 4338 // The first argument of the Gather/Scatter intrinsic is a vector of pointers. 4339 // We try to represent it as a base pointer + vector of indices. 4340 // Usually, the vector of pointers comes from a 'getelementptr' instruction. 4341 // The first operand of the GEP may be a single pointer or a vector of pointers 4342 // Example: 4343 // %gep.ptr = getelementptr i32, <8 x i32*> %vptr, <8 x i32> %ind 4344 // or 4345 // %gep.ptr = getelementptr i32, i32* %ptr, <8 x i32> %ind 4346 // %res = call <8 x i32> @llvm.masked.gather.v8i32(<8 x i32*> %gep.ptr, .. 4347 // 4348 // When the first GEP operand is a single pointer - it is the uniform base we 4349 // are looking for. If first operand of the GEP is a splat vector - we 4350 // extract the splat value and use it as a uniform base. 4351 // In all other cases the function returns 'false'. 4352 static bool getUniformBase(const Value *Ptr, SDValue &Base, SDValue &Index, 4353 ISD::MemIndexType &IndexType, SDValue &Scale, 4354 SelectionDAGBuilder *SDB, const BasicBlock *CurBB, 4355 uint64_t ElemSize) { 4356 SelectionDAG& DAG = SDB->DAG; 4357 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 4358 const DataLayout &DL = DAG.getDataLayout(); 4359 4360 assert(Ptr->getType()->isVectorTy() && "Unexpected pointer type"); 4361 4362 // Handle splat constant pointer. 4363 if (auto *C = dyn_cast<Constant>(Ptr)) { 4364 C = C->getSplatValue(); 4365 if (!C) 4366 return false; 4367 4368 Base = SDB->getValue(C); 4369 4370 ElementCount NumElts = cast<VectorType>(Ptr->getType())->getElementCount(); 4371 EVT VT = EVT::getVectorVT(*DAG.getContext(), TLI.getPointerTy(DL), NumElts); 4372 Index = DAG.getConstant(0, SDB->getCurSDLoc(), VT); 4373 IndexType = ISD::SIGNED_SCALED; 4374 Scale = DAG.getTargetConstant(1, SDB->getCurSDLoc(), TLI.getPointerTy(DL)); 4375 return true; 4376 } 4377 4378 const GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr); 4379 if (!GEP || GEP->getParent() != CurBB) 4380 return false; 4381 4382 if (GEP->getNumOperands() != 2) 4383 return false; 4384 4385 const Value *BasePtr = GEP->getPointerOperand(); 4386 const Value *IndexVal = GEP->getOperand(GEP->getNumOperands() - 1); 4387 4388 // Make sure the base is scalar and the index is a vector. 4389 if (BasePtr->getType()->isVectorTy() || !IndexVal->getType()->isVectorTy()) 4390 return false; 4391 4392 Base = SDB->getValue(BasePtr); 4393 Index = SDB->getValue(IndexVal); 4394 IndexType = ISD::SIGNED_SCALED; 4395 4396 // MGATHER/MSCATTER are only required to support scaling by one or by the 4397 // element size. Other scales may be produced using target-specific DAG 4398 // combines. 4399 uint64_t ScaleVal = DL.getTypeAllocSize(GEP->getResultElementType()); 4400 if (ScaleVal != ElemSize && ScaleVal != 1) 4401 return false; 4402 4403 Scale = 4404 DAG.getTargetConstant(ScaleVal, SDB->getCurSDLoc(), TLI.getPointerTy(DL)); 4405 return true; 4406 } 4407 4408 void SelectionDAGBuilder::visitMaskedScatter(const CallInst &I) { 4409 SDLoc sdl = getCurSDLoc(); 4410 4411 // llvm.masked.scatter.*(Src0, Ptrs, alignment, Mask) 4412 const Value *Ptr = I.getArgOperand(1); 4413 SDValue Src0 = getValue(I.getArgOperand(0)); 4414 SDValue Mask = getValue(I.getArgOperand(3)); 4415 EVT VT = Src0.getValueType(); 4416 Align Alignment = cast<ConstantInt>(I.getArgOperand(2)) 4417 ->getMaybeAlignValue() 4418 .value_or(DAG.getEVTAlign(VT.getScalarType())); 4419 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 4420 4421 SDValue Base; 4422 SDValue Index; 4423 ISD::MemIndexType IndexType; 4424 SDValue Scale; 4425 bool UniformBase = getUniformBase(Ptr, Base, Index, IndexType, Scale, this, 4426 I.getParent(), VT.getScalarStoreSize()); 4427 4428 unsigned AS = Ptr->getType()->getScalarType()->getPointerAddressSpace(); 4429 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand( 4430 MachinePointerInfo(AS), MachineMemOperand::MOStore, 4431 // TODO: Make MachineMemOperands aware of scalable 4432 // vectors. 4433 MemoryLocation::UnknownSize, Alignment, I.getAAMetadata()); 4434 if (!UniformBase) { 4435 Base = DAG.getConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout())); 4436 Index = getValue(Ptr); 4437 IndexType = ISD::SIGNED_SCALED; 4438 Scale = DAG.getTargetConstant(1, sdl, TLI.getPointerTy(DAG.getDataLayout())); 4439 } 4440 4441 EVT IdxVT = Index.getValueType(); 4442 EVT EltTy = IdxVT.getVectorElementType(); 4443 if (TLI.shouldExtendGSIndex(IdxVT, EltTy)) { 4444 EVT NewIdxVT = IdxVT.changeVectorElementType(EltTy); 4445 Index = DAG.getNode(ISD::SIGN_EXTEND, sdl, NewIdxVT, Index); 4446 } 4447 4448 SDValue Ops[] = { getMemoryRoot(), Src0, Mask, Base, Index, Scale }; 4449 SDValue Scatter = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), VT, sdl, 4450 Ops, MMO, IndexType, false); 4451 DAG.setRoot(Scatter); 4452 setValue(&I, Scatter); 4453 } 4454 4455 void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I, bool IsExpanding) { 4456 SDLoc sdl = getCurSDLoc(); 4457 4458 auto getMaskedLoadOps = [&](Value *&Ptr, Value *&Mask, Value *&Src0, 4459 MaybeAlign &Alignment) { 4460 // @llvm.masked.load.*(Ptr, alignment, Mask, Src0) 4461 Ptr = I.getArgOperand(0); 4462 Alignment = cast<ConstantInt>(I.getArgOperand(1))->getMaybeAlignValue(); 4463 Mask = I.getArgOperand(2); 4464 Src0 = I.getArgOperand(3); 4465 }; 4466 auto getExpandingLoadOps = [&](Value *&Ptr, Value *&Mask, Value *&Src0, 4467 MaybeAlign &Alignment) { 4468 // @llvm.masked.expandload.*(Ptr, Mask, Src0) 4469 Ptr = I.getArgOperand(0); 4470 Alignment = None; 4471 Mask = I.getArgOperand(1); 4472 Src0 = I.getArgOperand(2); 4473 }; 4474 4475 Value *PtrOperand, *MaskOperand, *Src0Operand; 4476 MaybeAlign Alignment; 4477 if (IsExpanding) 4478 getExpandingLoadOps(PtrOperand, MaskOperand, Src0Operand, Alignment); 4479 else 4480 getMaskedLoadOps(PtrOperand, MaskOperand, Src0Operand, Alignment); 4481 4482 SDValue Ptr = getValue(PtrOperand); 4483 SDValue Src0 = getValue(Src0Operand); 4484 SDValue Mask = getValue(MaskOperand); 4485 SDValue Offset = DAG.getUNDEF(Ptr.getValueType()); 4486 4487 EVT VT = Src0.getValueType(); 4488 if (!Alignment) 4489 Alignment = DAG.getEVTAlign(VT); 4490 4491 AAMDNodes AAInfo = I.getAAMetadata(); 4492 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range); 4493 4494 // Do not serialize masked loads of constant memory with anything. 4495 MemoryLocation ML = MemoryLocation::getAfter(PtrOperand, AAInfo); 4496 bool AddToChain = !AA || !AA->pointsToConstantMemory(ML); 4497 4498 SDValue InChain = AddToChain ? DAG.getRoot() : DAG.getEntryNode(); 4499 4500 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand( 4501 MachinePointerInfo(PtrOperand), MachineMemOperand::MOLoad, 4502 MemoryLocation::UnknownSize, *Alignment, AAInfo, Ranges); 4503 4504 SDValue Load = 4505 DAG.getMaskedLoad(VT, sdl, InChain, Ptr, Offset, Mask, Src0, VT, MMO, 4506 ISD::UNINDEXED, ISD::NON_EXTLOAD, IsExpanding); 4507 if (AddToChain) 4508 PendingLoads.push_back(Load.getValue(1)); 4509 setValue(&I, Load); 4510 } 4511 4512 void SelectionDAGBuilder::visitMaskedGather(const CallInst &I) { 4513 SDLoc sdl = getCurSDLoc(); 4514 4515 // @llvm.masked.gather.*(Ptrs, alignment, Mask, Src0) 4516 const Value *Ptr = I.getArgOperand(0); 4517 SDValue Src0 = getValue(I.getArgOperand(3)); 4518 SDValue Mask = getValue(I.getArgOperand(2)); 4519 4520 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 4521 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType()); 4522 Align Alignment = cast<ConstantInt>(I.getArgOperand(1)) 4523 ->getMaybeAlignValue() 4524 .value_or(DAG.getEVTAlign(VT.getScalarType())); 4525 4526 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range); 4527 4528 SDValue Root = DAG.getRoot(); 4529 SDValue Base; 4530 SDValue Index; 4531 ISD::MemIndexType IndexType; 4532 SDValue Scale; 4533 bool UniformBase = getUniformBase(Ptr, Base, Index, IndexType, Scale, this, 4534 I.getParent(), VT.getScalarStoreSize()); 4535 unsigned AS = Ptr->getType()->getScalarType()->getPointerAddressSpace(); 4536 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand( 4537 MachinePointerInfo(AS), MachineMemOperand::MOLoad, 4538 // TODO: Make MachineMemOperands aware of scalable 4539 // vectors. 4540 MemoryLocation::UnknownSize, Alignment, I.getAAMetadata(), Ranges); 4541 4542 if (!UniformBase) { 4543 Base = DAG.getConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout())); 4544 Index = getValue(Ptr); 4545 IndexType = ISD::SIGNED_SCALED; 4546 Scale = DAG.getTargetConstant(1, sdl, TLI.getPointerTy(DAG.getDataLayout())); 4547 } 4548 4549 EVT IdxVT = Index.getValueType(); 4550 EVT EltTy = IdxVT.getVectorElementType(); 4551 if (TLI.shouldExtendGSIndex(IdxVT, EltTy)) { 4552 EVT NewIdxVT = IdxVT.changeVectorElementType(EltTy); 4553 Index = DAG.getNode(ISD::SIGN_EXTEND, sdl, NewIdxVT, Index); 4554 } 4555 4556 SDValue Ops[] = { Root, Src0, Mask, Base, Index, Scale }; 4557 SDValue Gather = DAG.getMaskedGather(DAG.getVTList(VT, MVT::Other), VT, sdl, 4558 Ops, MMO, IndexType, ISD::NON_EXTLOAD); 4559 4560 PendingLoads.push_back(Gather.getValue(1)); 4561 setValue(&I, Gather); 4562 } 4563 4564 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) { 4565 SDLoc dl = getCurSDLoc(); 4566 AtomicOrdering SuccessOrdering = I.getSuccessOrdering(); 4567 AtomicOrdering FailureOrdering = I.getFailureOrdering(); 4568 SyncScope::ID SSID = I.getSyncScopeID(); 4569 4570 SDValue InChain = getRoot(); 4571 4572 MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType(); 4573 SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other); 4574 4575 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 4576 auto Flags = TLI.getAtomicMemOperandFlags(I, DAG.getDataLayout()); 4577 4578 MachineFunction &MF = DAG.getMachineFunction(); 4579 MachineMemOperand *MMO = MF.getMachineMemOperand( 4580 MachinePointerInfo(I.getPointerOperand()), Flags, MemVT.getStoreSize(), 4581 DAG.getEVTAlign(MemVT), AAMDNodes(), nullptr, SSID, SuccessOrdering, 4582 FailureOrdering); 4583 4584 SDValue L = DAG.getAtomicCmpSwap(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, 4585 dl, MemVT, VTs, InChain, 4586 getValue(I.getPointerOperand()), 4587 getValue(I.getCompareOperand()), 4588 getValue(I.getNewValOperand()), MMO); 4589 4590 SDValue OutChain = L.getValue(2); 4591 4592 setValue(&I, L); 4593 DAG.setRoot(OutChain); 4594 } 4595 4596 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) { 4597 SDLoc dl = getCurSDLoc(); 4598 ISD::NodeType NT; 4599 switch (I.getOperation()) { 4600 default: llvm_unreachable("Unknown atomicrmw operation"); 4601 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break; 4602 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break; 4603 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break; 4604 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break; 4605 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break; 4606 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break; 4607 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break; 4608 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break; 4609 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break; 4610 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break; 4611 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break; 4612 case AtomicRMWInst::FAdd: NT = ISD::ATOMIC_LOAD_FADD; break; 4613 case AtomicRMWInst::FSub: NT = ISD::ATOMIC_LOAD_FSUB; break; 4614 case AtomicRMWInst::FMax: NT = ISD::ATOMIC_LOAD_FMAX; break; 4615 case AtomicRMWInst::FMin: NT = ISD::ATOMIC_LOAD_FMIN; break; 4616 } 4617 AtomicOrdering Ordering = I.getOrdering(); 4618 SyncScope::ID SSID = I.getSyncScopeID(); 4619 4620 SDValue InChain = getRoot(); 4621 4622 auto MemVT = getValue(I.getValOperand()).getSimpleValueType(); 4623 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 4624 auto Flags = TLI.getAtomicMemOperandFlags(I, DAG.getDataLayout()); 4625 4626 MachineFunction &MF = DAG.getMachineFunction(); 4627 MachineMemOperand *MMO = MF.getMachineMemOperand( 4628 MachinePointerInfo(I.getPointerOperand()), Flags, MemVT.getStoreSize(), 4629 DAG.getEVTAlign(MemVT), AAMDNodes(), nullptr, SSID, Ordering); 4630 4631 SDValue L = 4632 DAG.getAtomic(NT, dl, MemVT, InChain, 4633 getValue(I.getPointerOperand()), getValue(I.getValOperand()), 4634 MMO); 4635 4636 SDValue OutChain = L.getValue(1); 4637 4638 setValue(&I, L); 4639 DAG.setRoot(OutChain); 4640 } 4641 4642 void SelectionDAGBuilder::visitFence(const FenceInst &I) { 4643 SDLoc dl = getCurSDLoc(); 4644 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 4645 SDValue Ops[3]; 4646 Ops[0] = getRoot(); 4647 Ops[1] = DAG.getTargetConstant((unsigned)I.getOrdering(), dl, 4648 TLI.getFenceOperandTy(DAG.getDataLayout())); 4649 Ops[2] = DAG.getTargetConstant(I.getSyncScopeID(), dl, 4650 TLI.getFenceOperandTy(DAG.getDataLayout())); 4651 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops)); 4652 } 4653 4654 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) { 4655 SDLoc dl = getCurSDLoc(); 4656 AtomicOrdering Order = I.getOrdering(); 4657 SyncScope::ID SSID = I.getSyncScopeID(); 4658 4659 SDValue InChain = getRoot(); 4660 4661 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 4662 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType()); 4663 EVT MemVT = TLI.getMemValueType(DAG.getDataLayout(), I.getType()); 4664 4665 if (!TLI.supportsUnalignedAtomics() && 4666 I.getAlign().value() < MemVT.getSizeInBits() / 8) 4667 report_fatal_error("Cannot generate unaligned atomic load"); 4668 4669 auto Flags = TLI.getLoadMemOperandFlags(I, DAG.getDataLayout()); 4670 4671 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand( 4672 MachinePointerInfo(I.getPointerOperand()), Flags, MemVT.getStoreSize(), 4673 I.getAlign(), AAMDNodes(), nullptr, SSID, Order); 4674 4675 InChain = TLI.prepareVolatileOrAtomicLoad(InChain, dl, DAG); 4676 4677 SDValue Ptr = getValue(I.getPointerOperand()); 4678 4679 if (TLI.lowerAtomicLoadAsLoadSDNode(I)) { 4680 // TODO: Once this is better exercised by tests, it should be merged with 4681 // the normal path for loads to prevent future divergence. 4682 SDValue L = DAG.getLoad(MemVT, dl, InChain, Ptr, MMO); 4683 if (MemVT != VT) 4684 L = DAG.getPtrExtOrTrunc(L, dl, VT); 4685 4686 setValue(&I, L); 4687 SDValue OutChain = L.getValue(1); 4688 if (!I.isUnordered()) 4689 DAG.setRoot(OutChain); 4690 else 4691 PendingLoads.push_back(OutChain); 4692 return; 4693 } 4694 4695 SDValue L = DAG.getAtomic(ISD::ATOMIC_LOAD, dl, MemVT, MemVT, InChain, 4696 Ptr, MMO); 4697 4698 SDValue OutChain = L.getValue(1); 4699 if (MemVT != VT) 4700 L = DAG.getPtrExtOrTrunc(L, dl, VT); 4701 4702 setValue(&I, L); 4703 DAG.setRoot(OutChain); 4704 } 4705 4706 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) { 4707 SDLoc dl = getCurSDLoc(); 4708 4709 AtomicOrdering Ordering = I.getOrdering(); 4710 SyncScope::ID SSID = I.getSyncScopeID(); 4711 4712 SDValue InChain = getRoot(); 4713 4714 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 4715 EVT MemVT = 4716 TLI.getMemValueType(DAG.getDataLayout(), I.getValueOperand()->getType()); 4717 4718 if (I.getAlign().value() < MemVT.getSizeInBits() / 8) 4719 report_fatal_error("Cannot generate unaligned atomic store"); 4720 4721 auto Flags = TLI.getStoreMemOperandFlags(I, DAG.getDataLayout()); 4722 4723 MachineFunction &MF = DAG.getMachineFunction(); 4724 MachineMemOperand *MMO = MF.getMachineMemOperand( 4725 MachinePointerInfo(I.getPointerOperand()), Flags, MemVT.getStoreSize(), 4726 I.getAlign(), AAMDNodes(), nullptr, SSID, Ordering); 4727 4728 SDValue Val = getValue(I.getValueOperand()); 4729 if (Val.getValueType() != MemVT) 4730 Val = DAG.getPtrExtOrTrunc(Val, dl, MemVT); 4731 SDValue Ptr = getValue(I.getPointerOperand()); 4732 4733 if (TLI.lowerAtomicStoreAsStoreSDNode(I)) { 4734 // TODO: Once this is better exercised by tests, it should be merged with 4735 // the normal path for stores to prevent future divergence. 4736 SDValue S = DAG.getStore(InChain, dl, Val, Ptr, MMO); 4737 DAG.setRoot(S); 4738 return; 4739 } 4740 SDValue OutChain = DAG.getAtomic(ISD::ATOMIC_STORE, dl, MemVT, InChain, 4741 Ptr, Val, MMO); 4742 4743 4744 DAG.setRoot(OutChain); 4745 } 4746 4747 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 4748 /// node. 4749 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I, 4750 unsigned Intrinsic) { 4751 // Ignore the callsite's attributes. A specific call site may be marked with 4752 // readnone, but the lowering code will expect the chain based on the 4753 // definition. 4754 const Function *F = I.getCalledFunction(); 4755 bool HasChain = !F->doesNotAccessMemory(); 4756 bool OnlyLoad = HasChain && F->onlyReadsMemory(); 4757 4758 // Build the operand list. 4759 SmallVector<SDValue, 8> Ops; 4760 if (HasChain) { // If this intrinsic has side-effects, chainify it. 4761 if (OnlyLoad) { 4762 // We don't need to serialize loads against other loads. 4763 Ops.push_back(DAG.getRoot()); 4764 } else { 4765 Ops.push_back(getRoot()); 4766 } 4767 } 4768 4769 // Info is set by getTgtMemIntrinsic 4770 TargetLowering::IntrinsicInfo Info; 4771 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 4772 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, 4773 DAG.getMachineFunction(), 4774 Intrinsic); 4775 4776 // Add the intrinsic ID as an integer operand if it's not a target intrinsic. 4777 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID || 4778 Info.opc == ISD::INTRINSIC_W_CHAIN) 4779 Ops.push_back(DAG.getTargetConstant(Intrinsic, getCurSDLoc(), 4780 TLI.getPointerTy(DAG.getDataLayout()))); 4781 4782 // Add all operands of the call to the operand list. 4783 for (unsigned i = 0, e = I.arg_size(); i != e; ++i) { 4784 const Value *Arg = I.getArgOperand(i); 4785 if (!I.paramHasAttr(i, Attribute::ImmArg)) { 4786 Ops.push_back(getValue(Arg)); 4787 continue; 4788 } 4789 4790 // Use TargetConstant instead of a regular constant for immarg. 4791 EVT VT = TLI.getValueType(DAG.getDataLayout(), Arg->getType(), true); 4792 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Arg)) { 4793 assert(CI->getBitWidth() <= 64 && 4794 "large intrinsic immediates not handled"); 4795 Ops.push_back(DAG.getTargetConstant(*CI, SDLoc(), VT)); 4796 } else { 4797 Ops.push_back( 4798 DAG.getTargetConstantFP(*cast<ConstantFP>(Arg), SDLoc(), VT)); 4799 } 4800 } 4801 4802 SmallVector<EVT, 4> ValueVTs; 4803 ComputeValueVTs(TLI, DAG.getDataLayout(), I.getType(), ValueVTs); 4804 4805 if (HasChain) 4806 ValueVTs.push_back(MVT::Other); 4807 4808 SDVTList VTs = DAG.getVTList(ValueVTs); 4809 4810 // Propagate fast-math-flags from IR to node(s). 4811 SDNodeFlags Flags; 4812 if (auto *FPMO = dyn_cast<FPMathOperator>(&I)) 4813 Flags.copyFMF(*FPMO); 4814 SelectionDAG::FlagInserter FlagsInserter(DAG, Flags); 4815 4816 // Create the node. 4817 SDValue Result; 4818 if (IsTgtIntrinsic) { 4819 // This is target intrinsic that touches memory 4820 Result = 4821 DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(), VTs, Ops, Info.memVT, 4822 MachinePointerInfo(Info.ptrVal, Info.offset), 4823 Info.align, Info.flags, Info.size, 4824 I.getAAMetadata()); 4825 } else if (!HasChain) { 4826 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops); 4827 } else if (!I.getType()->isVoidTy()) { 4828 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops); 4829 } else { 4830 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops); 4831 } 4832 4833 if (HasChain) { 4834 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1); 4835 if (OnlyLoad) 4836 PendingLoads.push_back(Chain); 4837 else 4838 DAG.setRoot(Chain); 4839 } 4840 4841 if (!I.getType()->isVoidTy()) { 4842 if (!isa<VectorType>(I.getType())) 4843 Result = lowerRangeToAssertZExt(DAG, I, Result); 4844 4845 MaybeAlign Alignment = I.getRetAlign(); 4846 if (!Alignment) 4847 Alignment = F->getAttributes().getRetAlignment(); 4848 // Insert `assertalign` node if there's an alignment. 4849 if (InsertAssertAlign && Alignment) { 4850 Result = 4851 DAG.getAssertAlign(getCurSDLoc(), Result, Alignment.valueOrOne()); 4852 } 4853 4854 setValue(&I, Result); 4855 } 4856 } 4857 4858 /// GetSignificand - Get the significand and build it into a floating-point 4859 /// number with exponent of 1: 4860 /// 4861 /// Op = (Op & 0x007fffff) | 0x3f800000; 4862 /// 4863 /// where Op is the hexadecimal representation of floating point value. 4864 static SDValue GetSignificand(SelectionDAG &DAG, SDValue Op, const SDLoc &dl) { 4865 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 4866 DAG.getConstant(0x007fffff, dl, MVT::i32)); 4867 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1, 4868 DAG.getConstant(0x3f800000, dl, MVT::i32)); 4869 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2); 4870 } 4871 4872 /// GetExponent - Get the exponent: 4873 /// 4874 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127); 4875 /// 4876 /// where Op is the hexadecimal representation of floating point value. 4877 static SDValue GetExponent(SelectionDAG &DAG, SDValue Op, 4878 const TargetLowering &TLI, const SDLoc &dl) { 4879 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 4880 DAG.getConstant(0x7f800000, dl, MVT::i32)); 4881 SDValue t1 = DAG.getNode( 4882 ISD::SRL, dl, MVT::i32, t0, 4883 DAG.getConstant(23, dl, 4884 TLI.getShiftAmountTy(MVT::i32, DAG.getDataLayout()))); 4885 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1, 4886 DAG.getConstant(127, dl, MVT::i32)); 4887 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2); 4888 } 4889 4890 /// getF32Constant - Get 32-bit floating point constant. 4891 static SDValue getF32Constant(SelectionDAG &DAG, unsigned Flt, 4892 const SDLoc &dl) { 4893 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle(), APInt(32, Flt)), dl, 4894 MVT::f32); 4895 } 4896 4897 static SDValue getLimitedPrecisionExp2(SDValue t0, const SDLoc &dl, 4898 SelectionDAG &DAG) { 4899 // TODO: What fast-math-flags should be set on the floating-point nodes? 4900 4901 // IntegerPartOfX = ((int32_t)(t0); 4902 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 4903 4904 // FractionalPartOfX = t0 - (float)IntegerPartOfX; 4905 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 4906 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 4907 4908 // IntegerPartOfX <<= 23; 4909 IntegerPartOfX = 4910 DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 4911 DAG.getConstant(23, dl, 4912 DAG.getTargetLoweringInfo().getShiftAmountTy( 4913 MVT::i32, DAG.getDataLayout()))); 4914 4915 SDValue TwoToFractionalPartOfX; 4916 if (LimitFloatPrecision <= 6) { 4917 // For floating-point precision of 6: 4918 // 4919 // TwoToFractionalPartOfX = 4920 // 0.997535578f + 4921 // (0.735607626f + 0.252464424f * x) * x; 4922 // 4923 // error 0.0144103317, which is 6 bits 4924 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4925 getF32Constant(DAG, 0x3e814304, dl)); 4926 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4927 getF32Constant(DAG, 0x3f3c50c8, dl)); 4928 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4929 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4930 getF32Constant(DAG, 0x3f7f5e7e, dl)); 4931 } else if (LimitFloatPrecision <= 12) { 4932 // For floating-point precision of 12: 4933 // 4934 // TwoToFractionalPartOfX = 4935 // 0.999892986f + 4936 // (0.696457318f + 4937 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 4938 // 4939 // error 0.000107046256, which is 13 to 14 bits 4940 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4941 getF32Constant(DAG, 0x3da235e3, dl)); 4942 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4943 getF32Constant(DAG, 0x3e65b8f3, dl)); 4944 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4945 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4946 getF32Constant(DAG, 0x3f324b07, dl)); 4947 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4948 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4949 getF32Constant(DAG, 0x3f7ff8fd, dl)); 4950 } else { // LimitFloatPrecision <= 18 4951 // For floating-point precision of 18: 4952 // 4953 // TwoToFractionalPartOfX = 4954 // 0.999999982f + 4955 // (0.693148872f + 4956 // (0.240227044f + 4957 // (0.554906021e-1f + 4958 // (0.961591928e-2f + 4959 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 4960 // error 2.47208000*10^(-7), which is better than 18 bits 4961 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4962 getF32Constant(DAG, 0x3924b03e, dl)); 4963 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4964 getF32Constant(DAG, 0x3ab24b87, dl)); 4965 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4966 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4967 getF32Constant(DAG, 0x3c1d8c17, dl)); 4968 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4969 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4970 getF32Constant(DAG, 0x3d634a1d, dl)); 4971 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4972 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 4973 getF32Constant(DAG, 0x3e75fe14, dl)); 4974 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 4975 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 4976 getF32Constant(DAG, 0x3f317234, dl)); 4977 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 4978 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 4979 getF32Constant(DAG, 0x3f800000, dl)); 4980 } 4981 4982 // Add the exponent into the result in integer domain. 4983 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFractionalPartOfX); 4984 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, 4985 DAG.getNode(ISD::ADD, dl, MVT::i32, t13, IntegerPartOfX)); 4986 } 4987 4988 /// expandExp - Lower an exp intrinsic. Handles the special sequences for 4989 /// limited-precision mode. 4990 static SDValue expandExp(const SDLoc &dl, SDValue Op, SelectionDAG &DAG, 4991 const TargetLowering &TLI, SDNodeFlags Flags) { 4992 if (Op.getValueType() == MVT::f32 && 4993 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4994 4995 // Put the exponent in the right bit position for later addition to the 4996 // final result: 4997 // 4998 // t0 = Op * log2(e) 4999 5000 // TODO: What fast-math-flags should be set here? 5001 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 5002 DAG.getConstantFP(numbers::log2ef, dl, MVT::f32)); 5003 return getLimitedPrecisionExp2(t0, dl, DAG); 5004 } 5005 5006 // No special expansion. 5007 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op, Flags); 5008 } 5009 5010 /// expandLog - Lower a log intrinsic. Handles the special sequences for 5011 /// limited-precision mode. 5012 static SDValue expandLog(const SDLoc &dl, SDValue Op, SelectionDAG &DAG, 5013 const TargetLowering &TLI, SDNodeFlags Flags) { 5014 // TODO: What fast-math-flags should be set on the floating-point nodes? 5015 5016 if (Op.getValueType() == MVT::f32 && 5017 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 5018 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 5019 5020 // Scale the exponent by log(2). 5021 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 5022 SDValue LogOfExponent = 5023 DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 5024 DAG.getConstantFP(numbers::ln2f, dl, MVT::f32)); 5025 5026 // Get the significand and build it into a floating-point number with 5027 // exponent of 1. 5028 SDValue X = GetSignificand(DAG, Op1, dl); 5029 5030 SDValue LogOfMantissa; 5031 if (LimitFloatPrecision <= 6) { 5032 // For floating-point precision of 6: 5033 // 5034 // LogofMantissa = 5035 // -1.1609546f + 5036 // (1.4034025f - 0.23903021f * x) * x; 5037 // 5038 // error 0.0034276066, which is better than 8 bits 5039 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 5040 getF32Constant(DAG, 0xbe74c456, dl)); 5041 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 5042 getF32Constant(DAG, 0x3fb3a2b1, dl)); 5043 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 5044 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 5045 getF32Constant(DAG, 0x3f949a29, dl)); 5046 } else if (LimitFloatPrecision <= 12) { 5047 // For floating-point precision of 12: 5048 // 5049 // LogOfMantissa = 5050 // -1.7417939f + 5051 // (2.8212026f + 5052 // (-1.4699568f + 5053 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x; 5054 // 5055 // error 0.000061011436, which is 14 bits 5056 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 5057 getF32Constant(DAG, 0xbd67b6d6, dl)); 5058 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 5059 getF32Constant(DAG, 0x3ee4f4b8, dl)); 5060 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 5061 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 5062 getF32Constant(DAG, 0x3fbc278b, dl)); 5063 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 5064 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 5065 getF32Constant(DAG, 0x40348e95, dl)); 5066 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 5067 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 5068 getF32Constant(DAG, 0x3fdef31a, dl)); 5069 } else { // LimitFloatPrecision <= 18 5070 // For floating-point precision of 18: 5071 // 5072 // LogOfMantissa = 5073 // -2.1072184f + 5074 // (4.2372794f + 5075 // (-3.7029485f + 5076 // (2.2781945f + 5077 // (-0.87823314f + 5078 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x; 5079 // 5080 // error 0.0000023660568, which is better than 18 bits 5081 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 5082 getF32Constant(DAG, 0xbc91e5ac, dl)); 5083 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 5084 getF32Constant(DAG, 0x3e4350aa, dl)); 5085 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 5086 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 5087 getF32Constant(DAG, 0x3f60d3e3, dl)); 5088 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 5089 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 5090 getF32Constant(DAG, 0x4011cdf0, dl)); 5091 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 5092 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 5093 getF32Constant(DAG, 0x406cfd1c, dl)); 5094 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 5095 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 5096 getF32Constant(DAG, 0x408797cb, dl)); 5097 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 5098 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 5099 getF32Constant(DAG, 0x4006dcab, dl)); 5100 } 5101 5102 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa); 5103 } 5104 5105 // No special expansion. 5106 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op, Flags); 5107 } 5108 5109 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for 5110 /// limited-precision mode. 5111 static SDValue expandLog2(const SDLoc &dl, SDValue Op, SelectionDAG &DAG, 5112 const TargetLowering &TLI, SDNodeFlags Flags) { 5113 // TODO: What fast-math-flags should be set on the floating-point nodes? 5114 5115 if (Op.getValueType() == MVT::f32 && 5116 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 5117 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 5118 5119 // Get the exponent. 5120 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl); 5121 5122 // Get the significand and build it into a floating-point number with 5123 // exponent of 1. 5124 SDValue X = GetSignificand(DAG, Op1, dl); 5125 5126 // Different possible minimax approximations of significand in 5127 // floating-point for various degrees of accuracy over [1,2]. 5128 SDValue Log2ofMantissa; 5129 if (LimitFloatPrecision <= 6) { 5130 // For floating-point precision of 6: 5131 // 5132 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x; 5133 // 5134 // error 0.0049451742, which is more than 7 bits 5135 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 5136 getF32Constant(DAG, 0xbeb08fe0, dl)); 5137 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 5138 getF32Constant(DAG, 0x40019463, dl)); 5139 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 5140 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 5141 getF32Constant(DAG, 0x3fd6633d, dl)); 5142 } else if (LimitFloatPrecision <= 12) { 5143 // For floating-point precision of 12: 5144 // 5145 // Log2ofMantissa = 5146 // -2.51285454f + 5147 // (4.07009056f + 5148 // (-2.12067489f + 5149 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x; 5150 // 5151 // error 0.0000876136000, which is better than 13 bits 5152 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 5153 getF32Constant(DAG, 0xbda7262e, dl)); 5154 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 5155 getF32Constant(DAG, 0x3f25280b, dl)); 5156 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 5157 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 5158 getF32Constant(DAG, 0x4007b923, dl)); 5159 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 5160 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 5161 getF32Constant(DAG, 0x40823e2f, dl)); 5162 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 5163 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 5164 getF32Constant(DAG, 0x4020d29c, dl)); 5165 } else { // LimitFloatPrecision <= 18 5166 // For floating-point precision of 18: 5167 // 5168 // Log2ofMantissa = 5169 // -3.0400495f + 5170 // (6.1129976f + 5171 // (-5.3420409f + 5172 // (3.2865683f + 5173 // (-1.2669343f + 5174 // (0.27515199f - 5175 // 0.25691327e-1f * x) * x) * x) * x) * x) * x; 5176 // 5177 // error 0.0000018516, which is better than 18 bits 5178 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 5179 getF32Constant(DAG, 0xbcd2769e, dl)); 5180 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 5181 getF32Constant(DAG, 0x3e8ce0b9, dl)); 5182 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 5183 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 5184 getF32Constant(DAG, 0x3fa22ae7, dl)); 5185 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 5186 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 5187 getF32Constant(DAG, 0x40525723, dl)); 5188 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 5189 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 5190 getF32Constant(DAG, 0x40aaf200, dl)); 5191 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 5192 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 5193 getF32Constant(DAG, 0x40c39dad, dl)); 5194 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 5195 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 5196 getF32Constant(DAG, 0x4042902c, dl)); 5197 } 5198 5199 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa); 5200 } 5201 5202 // No special expansion. 5203 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op, Flags); 5204 } 5205 5206 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for 5207 /// limited-precision mode. 5208 static SDValue expandLog10(const SDLoc &dl, SDValue Op, SelectionDAG &DAG, 5209 const TargetLowering &TLI, SDNodeFlags Flags) { 5210 // TODO: What fast-math-flags should be set on the floating-point nodes? 5211 5212 if (Op.getValueType() == MVT::f32 && 5213 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 5214 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 5215 5216 // Scale the exponent by log10(2) [0.30102999f]. 5217 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 5218 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 5219 getF32Constant(DAG, 0x3e9a209a, dl)); 5220 5221 // Get the significand and build it into a floating-point number with 5222 // exponent of 1. 5223 SDValue X = GetSignificand(DAG, Op1, dl); 5224 5225 SDValue Log10ofMantissa; 5226 if (LimitFloatPrecision <= 6) { 5227 // For floating-point precision of 6: 5228 // 5229 // Log10ofMantissa = 5230 // -0.50419619f + 5231 // (0.60948995f - 0.10380950f * x) * x; 5232 // 5233 // error 0.0014886165, which is 6 bits 5234 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 5235 getF32Constant(DAG, 0xbdd49a13, dl)); 5236 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 5237 getF32Constant(DAG, 0x3f1c0789, dl)); 5238 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 5239 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 5240 getF32Constant(DAG, 0x3f011300, dl)); 5241 } else if (LimitFloatPrecision <= 12) { 5242 // For floating-point precision of 12: 5243 // 5244 // Log10ofMantissa = 5245 // -0.64831180f + 5246 // (0.91751397f + 5247 // (-0.31664806f + 0.47637168e-1f * x) * x) * x; 5248 // 5249 // error 0.00019228036, which is better than 12 bits 5250 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 5251 getF32Constant(DAG, 0x3d431f31, dl)); 5252 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 5253 getF32Constant(DAG, 0x3ea21fb2, dl)); 5254 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 5255 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 5256 getF32Constant(DAG, 0x3f6ae232, dl)); 5257 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 5258 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 5259 getF32Constant(DAG, 0x3f25f7c3, dl)); 5260 } else { // LimitFloatPrecision <= 18 5261 // For floating-point precision of 18: 5262 // 5263 // Log10ofMantissa = 5264 // -0.84299375f + 5265 // (1.5327582f + 5266 // (-1.0688956f + 5267 // (0.49102474f + 5268 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x; 5269 // 5270 // error 0.0000037995730, which is better than 18 bits 5271 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 5272 getF32Constant(DAG, 0x3c5d51ce, dl)); 5273 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 5274 getF32Constant(DAG, 0x3e00685a, dl)); 5275 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 5276 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 5277 getF32Constant(DAG, 0x3efb6798, dl)); 5278 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 5279 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 5280 getF32Constant(DAG, 0x3f88d192, dl)); 5281 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 5282 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 5283 getF32Constant(DAG, 0x3fc4316c, dl)); 5284 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 5285 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8, 5286 getF32Constant(DAG, 0x3f57ce70, dl)); 5287 } 5288 5289 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa); 5290 } 5291 5292 // No special expansion. 5293 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op, Flags); 5294 } 5295 5296 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for 5297 /// limited-precision mode. 5298 static SDValue expandExp2(const SDLoc &dl, SDValue Op, SelectionDAG &DAG, 5299 const TargetLowering &TLI, SDNodeFlags Flags) { 5300 if (Op.getValueType() == MVT::f32 && 5301 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) 5302 return getLimitedPrecisionExp2(Op, dl, DAG); 5303 5304 // No special expansion. 5305 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op, Flags); 5306 } 5307 5308 /// visitPow - Lower a pow intrinsic. Handles the special sequences for 5309 /// limited-precision mode with x == 10.0f. 5310 static SDValue expandPow(const SDLoc &dl, SDValue LHS, SDValue RHS, 5311 SelectionDAG &DAG, const TargetLowering &TLI, 5312 SDNodeFlags Flags) { 5313 bool IsExp10 = false; 5314 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 && 5315 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 5316 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) { 5317 APFloat Ten(10.0f); 5318 IsExp10 = LHSC->isExactlyValue(Ten); 5319 } 5320 } 5321 5322 // TODO: What fast-math-flags should be set on the FMUL node? 5323 if (IsExp10) { 5324 // Put the exponent in the right bit position for later addition to the 5325 // final result: 5326 // 5327 // #define LOG2OF10 3.3219281f 5328 // t0 = Op * LOG2OF10; 5329 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS, 5330 getF32Constant(DAG, 0x40549a78, dl)); 5331 return getLimitedPrecisionExp2(t0, dl, DAG); 5332 } 5333 5334 // No special expansion. 5335 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS, Flags); 5336 } 5337 5338 /// ExpandPowI - Expand a llvm.powi intrinsic. 5339 static SDValue ExpandPowI(const SDLoc &DL, SDValue LHS, SDValue RHS, 5340 SelectionDAG &DAG) { 5341 // If RHS is a constant, we can expand this out to a multiplication tree if 5342 // it's beneficial on the target, otherwise we end up lowering to a call to 5343 // __powidf2 (for example). 5344 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 5345 unsigned Val = RHSC->getSExtValue(); 5346 5347 // powi(x, 0) -> 1.0 5348 if (Val == 0) 5349 return DAG.getConstantFP(1.0, DL, LHS.getValueType()); 5350 5351 if (DAG.getTargetLoweringInfo().isBeneficialToExpandPowI( 5352 Val, DAG.shouldOptForSize())) { 5353 // Get the exponent as a positive value. 5354 if ((int)Val < 0) 5355 Val = -Val; 5356 // We use the simple binary decomposition method to generate the multiply 5357 // sequence. There are more optimal ways to do this (for example, 5358 // powi(x,15) generates one more multiply than it should), but this has 5359 // the benefit of being both really simple and much better than a libcall. 5360 SDValue Res; // Logically starts equal to 1.0 5361 SDValue CurSquare = LHS; 5362 // TODO: Intrinsics should have fast-math-flags that propagate to these 5363 // nodes. 5364 while (Val) { 5365 if (Val & 1) { 5366 if (Res.getNode()) 5367 Res = 5368 DAG.getNode(ISD::FMUL, DL, Res.getValueType(), Res, CurSquare); 5369 else 5370 Res = CurSquare; // 1.0*CurSquare. 5371 } 5372 5373 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(), 5374 CurSquare, CurSquare); 5375 Val >>= 1; 5376 } 5377 5378 // If the original was negative, invert the result, producing 1/(x*x*x). 5379 if (RHSC->getSExtValue() < 0) 5380 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(), 5381 DAG.getConstantFP(1.0, DL, LHS.getValueType()), Res); 5382 return Res; 5383 } 5384 } 5385 5386 // Otherwise, expand to a libcall. 5387 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS); 5388 } 5389 5390 static SDValue expandDivFix(unsigned Opcode, const SDLoc &DL, 5391 SDValue LHS, SDValue RHS, SDValue Scale, 5392 SelectionDAG &DAG, const TargetLowering &TLI) { 5393 EVT VT = LHS.getValueType(); 5394 bool Signed = Opcode == ISD::SDIVFIX || Opcode == ISD::SDIVFIXSAT; 5395 bool Saturating = Opcode == ISD::SDIVFIXSAT || Opcode == ISD::UDIVFIXSAT; 5396 LLVMContext &Ctx = *DAG.getContext(); 5397 5398 // If the type is legal but the operation isn't, this node might survive all 5399 // the way to operation legalization. If we end up there and we do not have 5400 // the ability to widen the type (if VT*2 is not legal), we cannot expand the 5401 // node. 5402 5403 // Coax the legalizer into expanding the node during type legalization instead 5404 // by bumping the size by one bit. This will force it to Promote, enabling the 5405 // early expansion and avoiding the need to expand later. 5406 5407 // We don't have to do this if Scale is 0; that can always be expanded, unless 5408 // it's a saturating signed operation. Those can experience true integer 5409 // division overflow, a case which we must avoid. 5410 5411 // FIXME: We wouldn't have to do this (or any of the early 5412 // expansion/promotion) if it was possible to expand a libcall of an 5413 // illegal type during operation legalization. But it's not, so things 5414 // get a bit hacky. 5415 unsigned ScaleInt = cast<ConstantSDNode>(Scale)->getZExtValue(); 5416 if ((ScaleInt > 0 || (Saturating && Signed)) && 5417 (TLI.isTypeLegal(VT) || 5418 (VT.isVector() && TLI.isTypeLegal(VT.getVectorElementType())))) { 5419 TargetLowering::LegalizeAction Action = TLI.getFixedPointOperationAction( 5420 Opcode, VT, ScaleInt); 5421 if (Action != TargetLowering::Legal && Action != TargetLowering::Custom) { 5422 EVT PromVT; 5423 if (VT.isScalarInteger()) 5424 PromVT = EVT::getIntegerVT(Ctx, VT.getSizeInBits() + 1); 5425 else if (VT.isVector()) { 5426 PromVT = VT.getVectorElementType(); 5427 PromVT = EVT::getIntegerVT(Ctx, PromVT.getSizeInBits() + 1); 5428 PromVT = EVT::getVectorVT(Ctx, PromVT, VT.getVectorElementCount()); 5429 } else 5430 llvm_unreachable("Wrong VT for DIVFIX?"); 5431 if (Signed) { 5432 LHS = DAG.getSExtOrTrunc(LHS, DL, PromVT); 5433 RHS = DAG.getSExtOrTrunc(RHS, DL, PromVT); 5434 } else { 5435 LHS = DAG.getZExtOrTrunc(LHS, DL, PromVT); 5436 RHS = DAG.getZExtOrTrunc(RHS, DL, PromVT); 5437 } 5438 EVT ShiftTy = TLI.getShiftAmountTy(PromVT, DAG.getDataLayout()); 5439 // For saturating operations, we need to shift up the LHS to get the 5440 // proper saturation width, and then shift down again afterwards. 5441 if (Saturating) 5442 LHS = DAG.getNode(ISD::SHL, DL, PromVT, LHS, 5443 DAG.getConstant(1, DL, ShiftTy)); 5444 SDValue Res = DAG.getNode(Opcode, DL, PromVT, LHS, RHS, Scale); 5445 if (Saturating) 5446 Res = DAG.getNode(Signed ? ISD::SRA : ISD::SRL, DL, PromVT, Res, 5447 DAG.getConstant(1, DL, ShiftTy)); 5448 return DAG.getZExtOrTrunc(Res, DL, VT); 5449 } 5450 } 5451 5452 return DAG.getNode(Opcode, DL, VT, LHS, RHS, Scale); 5453 } 5454 5455 // getUnderlyingArgRegs - Find underlying registers used for a truncated, 5456 // bitcasted, or split argument. Returns a list of <Register, size in bits> 5457 static void 5458 getUnderlyingArgRegs(SmallVectorImpl<std::pair<unsigned, TypeSize>> &Regs, 5459 const SDValue &N) { 5460 switch (N.getOpcode()) { 5461 case ISD::CopyFromReg: { 5462 SDValue Op = N.getOperand(1); 5463 Regs.emplace_back(cast<RegisterSDNode>(Op)->getReg(), 5464 Op.getValueType().getSizeInBits()); 5465 return; 5466 } 5467 case ISD::BITCAST: 5468 case ISD::AssertZext: 5469 case ISD::AssertSext: 5470 case ISD::TRUNCATE: 5471 getUnderlyingArgRegs(Regs, N.getOperand(0)); 5472 return; 5473 case ISD::BUILD_PAIR: 5474 case ISD::BUILD_VECTOR: 5475 case ISD::CONCAT_VECTORS: 5476 for (SDValue Op : N->op_values()) 5477 getUnderlyingArgRegs(Regs, Op); 5478 return; 5479 default: 5480 return; 5481 } 5482 } 5483 5484 /// If the DbgValueInst is a dbg_value of a function argument, create the 5485 /// corresponding DBG_VALUE machine instruction for it now. At the end of 5486 /// instruction selection, they will be inserted to the entry BB. 5487 /// We don't currently support this for variadic dbg_values, as they shouldn't 5488 /// appear for function arguments or in the prologue. 5489 bool SelectionDAGBuilder::EmitFuncArgumentDbgValue( 5490 const Value *V, DILocalVariable *Variable, DIExpression *Expr, 5491 DILocation *DL, FuncArgumentDbgValueKind Kind, const SDValue &N) { 5492 const Argument *Arg = dyn_cast<Argument>(V); 5493 if (!Arg) 5494 return false; 5495 5496 MachineFunction &MF = DAG.getMachineFunction(); 5497 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo(); 5498 5499 // Helper to create DBG_INSTR_REFs or DBG_VALUEs, depending on what kind 5500 // we've been asked to pursue. 5501 auto MakeVRegDbgValue = [&](Register Reg, DIExpression *FragExpr, 5502 bool Indirect) { 5503 if (Reg.isVirtual() && MF.useDebugInstrRef()) { 5504 // For VRegs, in instruction referencing mode, create a DBG_INSTR_REF 5505 // pointing at the VReg, which will be patched up later. 5506 auto &Inst = TII->get(TargetOpcode::DBG_INSTR_REF); 5507 auto MIB = BuildMI(MF, DL, Inst); 5508 MIB.addReg(Reg); 5509 MIB.addImm(0); 5510 MIB.addMetadata(Variable); 5511 auto *NewDIExpr = FragExpr; 5512 // We don't have an "Indirect" field in DBG_INSTR_REF, fold that into 5513 // the DIExpression. 5514 if (Indirect) 5515 NewDIExpr = DIExpression::prepend(FragExpr, DIExpression::DerefBefore); 5516 MIB.addMetadata(NewDIExpr); 5517 return MIB; 5518 } else { 5519 // Create a completely standard DBG_VALUE. 5520 auto &Inst = TII->get(TargetOpcode::DBG_VALUE); 5521 return BuildMI(MF, DL, Inst, Indirect, Reg, Variable, FragExpr); 5522 } 5523 }; 5524 5525 if (Kind == FuncArgumentDbgValueKind::Value) { 5526 // ArgDbgValues are hoisted to the beginning of the entry block. So we 5527 // should only emit as ArgDbgValue if the dbg.value intrinsic is found in 5528 // the entry block. 5529 bool IsInEntryBlock = FuncInfo.MBB == &FuncInfo.MF->front(); 5530 if (!IsInEntryBlock) 5531 return false; 5532 5533 // ArgDbgValues are hoisted to the beginning of the entry block. So we 5534 // should only emit as ArgDbgValue if the dbg.value intrinsic describes a 5535 // variable that also is a param. 5536 // 5537 // Although, if we are at the top of the entry block already, we can still 5538 // emit using ArgDbgValue. This might catch some situations when the 5539 // dbg.value refers to an argument that isn't used in the entry block, so 5540 // any CopyToReg node would be optimized out and the only way to express 5541 // this DBG_VALUE is by using the physical reg (or FI) as done in this 5542 // method. ArgDbgValues are hoisted to the beginning of the entry block. So 5543 // we should only emit as ArgDbgValue if the Variable is an argument to the 5544 // current function, and the dbg.value intrinsic is found in the entry 5545 // block. 5546 bool VariableIsFunctionInputArg = Variable->isParameter() && 5547 !DL->getInlinedAt(); 5548 bool IsInPrologue = SDNodeOrder == LowestSDNodeOrder; 5549 if (!IsInPrologue && !VariableIsFunctionInputArg) 5550 return false; 5551 5552 // Here we assume that a function argument on IR level only can be used to 5553 // describe one input parameter on source level. If we for example have 5554 // source code like this 5555 // 5556 // struct A { long x, y; }; 5557 // void foo(struct A a, long b) { 5558 // ... 5559 // b = a.x; 5560 // ... 5561 // } 5562 // 5563 // and IR like this 5564 // 5565 // define void @foo(i32 %a1, i32 %a2, i32 %b) { 5566 // entry: 5567 // call void @llvm.dbg.value(metadata i32 %a1, "a", DW_OP_LLVM_fragment 5568 // call void @llvm.dbg.value(metadata i32 %a2, "a", DW_OP_LLVM_fragment 5569 // call void @llvm.dbg.value(metadata i32 %b, "b", 5570 // ... 5571 // call void @llvm.dbg.value(metadata i32 %a1, "b" 5572 // ... 5573 // 5574 // then the last dbg.value is describing a parameter "b" using a value that 5575 // is an argument. But since we already has used %a1 to describe a parameter 5576 // we should not handle that last dbg.value here (that would result in an 5577 // incorrect hoisting of the DBG_VALUE to the function entry). 5578 // Notice that we allow one dbg.value per IR level argument, to accommodate 5579 // for the situation with fragments above. 5580 if (VariableIsFunctionInputArg) { 5581 unsigned ArgNo = Arg->getArgNo(); 5582 if (ArgNo >= FuncInfo.DescribedArgs.size()) 5583 FuncInfo.DescribedArgs.resize(ArgNo + 1, false); 5584 else if (!IsInPrologue && FuncInfo.DescribedArgs.test(ArgNo)) 5585 return false; 5586 FuncInfo.DescribedArgs.set(ArgNo); 5587 } 5588 } 5589 5590 bool IsIndirect = false; 5591 Optional<MachineOperand> Op; 5592 // Some arguments' frame index is recorded during argument lowering. 5593 int FI = FuncInfo.getArgumentFrameIndex(Arg); 5594 if (FI != std::numeric_limits<int>::max()) 5595 Op = MachineOperand::CreateFI(FI); 5596 5597 SmallVector<std::pair<unsigned, TypeSize>, 8> ArgRegsAndSizes; 5598 if (!Op && N.getNode()) { 5599 getUnderlyingArgRegs(ArgRegsAndSizes, N); 5600 Register Reg; 5601 if (ArgRegsAndSizes.size() == 1) 5602 Reg = ArgRegsAndSizes.front().first; 5603 5604 if (Reg && Reg.isVirtual()) { 5605 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 5606 Register PR = RegInfo.getLiveInPhysReg(Reg); 5607 if (PR) 5608 Reg = PR; 5609 } 5610 if (Reg) { 5611 Op = MachineOperand::CreateReg(Reg, false); 5612 IsIndirect = Kind != FuncArgumentDbgValueKind::Value; 5613 } 5614 } 5615 5616 if (!Op && N.getNode()) { 5617 // Check if frame index is available. 5618 SDValue LCandidate = peekThroughBitcasts(N); 5619 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(LCandidate.getNode())) 5620 if (FrameIndexSDNode *FINode = 5621 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) 5622 Op = MachineOperand::CreateFI(FINode->getIndex()); 5623 } 5624 5625 if (!Op) { 5626 // Create a DBG_VALUE for each decomposed value in ArgRegs to cover Reg 5627 auto splitMultiRegDbgValue = [&](ArrayRef<std::pair<unsigned, TypeSize>> 5628 SplitRegs) { 5629 unsigned Offset = 0; 5630 for (const auto &RegAndSize : SplitRegs) { 5631 // If the expression is already a fragment, the current register 5632 // offset+size might extend beyond the fragment. In this case, only 5633 // the register bits that are inside the fragment are relevant. 5634 int RegFragmentSizeInBits = RegAndSize.second; 5635 if (auto ExprFragmentInfo = Expr->getFragmentInfo()) { 5636 uint64_t ExprFragmentSizeInBits = ExprFragmentInfo->SizeInBits; 5637 // The register is entirely outside the expression fragment, 5638 // so is irrelevant for debug info. 5639 if (Offset >= ExprFragmentSizeInBits) 5640 break; 5641 // The register is partially outside the expression fragment, only 5642 // the low bits within the fragment are relevant for debug info. 5643 if (Offset + RegFragmentSizeInBits > ExprFragmentSizeInBits) { 5644 RegFragmentSizeInBits = ExprFragmentSizeInBits - Offset; 5645 } 5646 } 5647 5648 auto FragmentExpr = DIExpression::createFragmentExpression( 5649 Expr, Offset, RegFragmentSizeInBits); 5650 Offset += RegAndSize.second; 5651 // If a valid fragment expression cannot be created, the variable's 5652 // correct value cannot be determined and so it is set as Undef. 5653 if (!FragmentExpr) { 5654 SDDbgValue *SDV = DAG.getConstantDbgValue( 5655 Variable, Expr, UndefValue::get(V->getType()), DL, SDNodeOrder); 5656 DAG.AddDbgValue(SDV, false); 5657 continue; 5658 } 5659 MachineInstr *NewMI = 5660 MakeVRegDbgValue(RegAndSize.first, *FragmentExpr, 5661 Kind != FuncArgumentDbgValueKind::Value); 5662 FuncInfo.ArgDbgValues.push_back(NewMI); 5663 } 5664 }; 5665 5666 // Check if ValueMap has reg number. 5667 DenseMap<const Value *, Register>::const_iterator 5668 VMI = FuncInfo.ValueMap.find(V); 5669 if (VMI != FuncInfo.ValueMap.end()) { 5670 const auto &TLI = DAG.getTargetLoweringInfo(); 5671 RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), VMI->second, 5672 V->getType(), None); 5673 if (RFV.occupiesMultipleRegs()) { 5674 splitMultiRegDbgValue(RFV.getRegsAndSizes()); 5675 return true; 5676 } 5677 5678 Op = MachineOperand::CreateReg(VMI->second, false); 5679 IsIndirect = Kind != FuncArgumentDbgValueKind::Value; 5680 } else if (ArgRegsAndSizes.size() > 1) { 5681 // This was split due to the calling convention, and no virtual register 5682 // mapping exists for the value. 5683 splitMultiRegDbgValue(ArgRegsAndSizes); 5684 return true; 5685 } 5686 } 5687 5688 if (!Op) 5689 return false; 5690 5691 assert(Variable->isValidLocationForIntrinsic(DL) && 5692 "Expected inlined-at fields to agree"); 5693 MachineInstr *NewMI = nullptr; 5694 5695 if (Op->isReg()) 5696 NewMI = MakeVRegDbgValue(Op->getReg(), Expr, IsIndirect); 5697 else 5698 NewMI = BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE), true, *Op, 5699 Variable, Expr); 5700 5701 // Otherwise, use ArgDbgValues. 5702 FuncInfo.ArgDbgValues.push_back(NewMI); 5703 return true; 5704 } 5705 5706 /// Return the appropriate SDDbgValue based on N. 5707 SDDbgValue *SelectionDAGBuilder::getDbgValue(SDValue N, 5708 DILocalVariable *Variable, 5709 DIExpression *Expr, 5710 const DebugLoc &dl, 5711 unsigned DbgSDNodeOrder) { 5712 if (auto *FISDN = dyn_cast<FrameIndexSDNode>(N.getNode())) { 5713 // Construct a FrameIndexDbgValue for FrameIndexSDNodes so we can describe 5714 // stack slot locations. 5715 // 5716 // Consider "int x = 0; int *px = &x;". There are two kinds of interesting 5717 // debug values here after optimization: 5718 // 5719 // dbg.value(i32* %px, !"int *px", !DIExpression()), and 5720 // dbg.value(i32* %px, !"int x", !DIExpression(DW_OP_deref)) 5721 // 5722 // Both describe the direct values of their associated variables. 5723 return DAG.getFrameIndexDbgValue(Variable, Expr, FISDN->getIndex(), 5724 /*IsIndirect*/ false, dl, DbgSDNodeOrder); 5725 } 5726 return DAG.getDbgValue(Variable, Expr, N.getNode(), N.getResNo(), 5727 /*IsIndirect*/ false, dl, DbgSDNodeOrder); 5728 } 5729 5730 static unsigned FixedPointIntrinsicToOpcode(unsigned Intrinsic) { 5731 switch (Intrinsic) { 5732 case Intrinsic::smul_fix: 5733 return ISD::SMULFIX; 5734 case Intrinsic::umul_fix: 5735 return ISD::UMULFIX; 5736 case Intrinsic::smul_fix_sat: 5737 return ISD::SMULFIXSAT; 5738 case Intrinsic::umul_fix_sat: 5739 return ISD::UMULFIXSAT; 5740 case Intrinsic::sdiv_fix: 5741 return ISD::SDIVFIX; 5742 case Intrinsic::udiv_fix: 5743 return ISD::UDIVFIX; 5744 case Intrinsic::sdiv_fix_sat: 5745 return ISD::SDIVFIXSAT; 5746 case Intrinsic::udiv_fix_sat: 5747 return ISD::UDIVFIXSAT; 5748 default: 5749 llvm_unreachable("Unhandled fixed point intrinsic"); 5750 } 5751 } 5752 5753 void SelectionDAGBuilder::lowerCallToExternalSymbol(const CallInst &I, 5754 const char *FunctionName) { 5755 assert(FunctionName && "FunctionName must not be nullptr"); 5756 SDValue Callee = DAG.getExternalSymbol( 5757 FunctionName, 5758 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout())); 5759 LowerCallTo(I, Callee, I.isTailCall(), I.isMustTailCall()); 5760 } 5761 5762 /// Given a @llvm.call.preallocated.setup, return the corresponding 5763 /// preallocated call. 5764 static const CallBase *FindPreallocatedCall(const Value *PreallocatedSetup) { 5765 assert(cast<CallBase>(PreallocatedSetup) 5766 ->getCalledFunction() 5767 ->getIntrinsicID() == Intrinsic::call_preallocated_setup && 5768 "expected call_preallocated_setup Value"); 5769 for (auto *U : PreallocatedSetup->users()) { 5770 auto *UseCall = cast<CallBase>(U); 5771 const Function *Fn = UseCall->getCalledFunction(); 5772 if (!Fn || Fn->getIntrinsicID() != Intrinsic::call_preallocated_arg) { 5773 return UseCall; 5774 } 5775 } 5776 llvm_unreachable("expected corresponding call to preallocated setup/arg"); 5777 } 5778 5779 /// Lower the call to the specified intrinsic function. 5780 void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, 5781 unsigned Intrinsic) { 5782 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 5783 SDLoc sdl = getCurSDLoc(); 5784 DebugLoc dl = getCurDebugLoc(); 5785 SDValue Res; 5786 5787 SDNodeFlags Flags; 5788 if (auto *FPOp = dyn_cast<FPMathOperator>(&I)) 5789 Flags.copyFMF(*FPOp); 5790 5791 switch (Intrinsic) { 5792 default: 5793 // By default, turn this into a target intrinsic node. 5794 visitTargetIntrinsic(I, Intrinsic); 5795 return; 5796 case Intrinsic::vscale: { 5797 match(&I, m_VScale(DAG.getDataLayout())); 5798 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType()); 5799 setValue(&I, DAG.getVScale(sdl, VT, APInt(VT.getSizeInBits(), 1))); 5800 return; 5801 } 5802 case Intrinsic::vastart: visitVAStart(I); return; 5803 case Intrinsic::vaend: visitVAEnd(I); return; 5804 case Intrinsic::vacopy: visitVACopy(I); return; 5805 case Intrinsic::returnaddress: 5806 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl, 5807 TLI.getValueType(DAG.getDataLayout(), I.getType()), 5808 getValue(I.getArgOperand(0)))); 5809 return; 5810 case Intrinsic::addressofreturnaddress: 5811 setValue(&I, 5812 DAG.getNode(ISD::ADDROFRETURNADDR, sdl, 5813 TLI.getValueType(DAG.getDataLayout(), I.getType()))); 5814 return; 5815 case Intrinsic::sponentry: 5816 setValue(&I, 5817 DAG.getNode(ISD::SPONENTRY, sdl, 5818 TLI.getValueType(DAG.getDataLayout(), I.getType()))); 5819 return; 5820 case Intrinsic::frameaddress: 5821 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl, 5822 TLI.getFrameIndexTy(DAG.getDataLayout()), 5823 getValue(I.getArgOperand(0)))); 5824 return; 5825 case Intrinsic::read_volatile_register: 5826 case Intrinsic::read_register: { 5827 Value *Reg = I.getArgOperand(0); 5828 SDValue Chain = getRoot(); 5829 SDValue RegName = 5830 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata())); 5831 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType()); 5832 Res = DAG.getNode(ISD::READ_REGISTER, sdl, 5833 DAG.getVTList(VT, MVT::Other), Chain, RegName); 5834 setValue(&I, Res); 5835 DAG.setRoot(Res.getValue(1)); 5836 return; 5837 } 5838 case Intrinsic::write_register: { 5839 Value *Reg = I.getArgOperand(0); 5840 Value *RegValue = I.getArgOperand(1); 5841 SDValue Chain = getRoot(); 5842 SDValue RegName = 5843 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata())); 5844 DAG.setRoot(DAG.getNode(ISD::WRITE_REGISTER, sdl, MVT::Other, Chain, 5845 RegName, getValue(RegValue))); 5846 return; 5847 } 5848 case Intrinsic::memcpy: { 5849 const auto &MCI = cast<MemCpyInst>(I); 5850 SDValue Op1 = getValue(I.getArgOperand(0)); 5851 SDValue Op2 = getValue(I.getArgOperand(1)); 5852 SDValue Op3 = getValue(I.getArgOperand(2)); 5853 // @llvm.memcpy defines 0 and 1 to both mean no alignment. 5854 Align DstAlign = MCI.getDestAlign().valueOrOne(); 5855 Align SrcAlign = MCI.getSourceAlign().valueOrOne(); 5856 Align Alignment = std::min(DstAlign, SrcAlign); 5857 bool isVol = MCI.isVolatile(); 5858 bool isTC = I.isTailCall() && isInTailCallPosition(I, DAG.getTarget()); 5859 // FIXME: Support passing different dest/src alignments to the memcpy DAG 5860 // node. 5861 SDValue Root = isVol ? getRoot() : getMemoryRoot(); 5862 SDValue MC = DAG.getMemcpy(Root, sdl, Op1, Op2, Op3, Alignment, isVol, 5863 /* AlwaysInline */ false, isTC, 5864 MachinePointerInfo(I.getArgOperand(0)), 5865 MachinePointerInfo(I.getArgOperand(1)), 5866 I.getAAMetadata()); 5867 updateDAGForMaybeTailCall(MC); 5868 return; 5869 } 5870 case Intrinsic::memcpy_inline: { 5871 const auto &MCI = cast<MemCpyInlineInst>(I); 5872 SDValue Dst = getValue(I.getArgOperand(0)); 5873 SDValue Src = getValue(I.getArgOperand(1)); 5874 SDValue Size = getValue(I.getArgOperand(2)); 5875 assert(isa<ConstantSDNode>(Size) && "memcpy_inline needs constant size"); 5876 // @llvm.memcpy.inline defines 0 and 1 to both mean no alignment. 5877 Align DstAlign = MCI.getDestAlign().valueOrOne(); 5878 Align SrcAlign = MCI.getSourceAlign().valueOrOne(); 5879 Align Alignment = std::min(DstAlign, SrcAlign); 5880 bool isVol = MCI.isVolatile(); 5881 bool isTC = I.isTailCall() && isInTailCallPosition(I, DAG.getTarget()); 5882 // FIXME: Support passing different dest/src alignments to the memcpy DAG 5883 // node. 5884 SDValue MC = DAG.getMemcpy(getRoot(), sdl, Dst, Src, Size, Alignment, isVol, 5885 /* AlwaysInline */ true, isTC, 5886 MachinePointerInfo(I.getArgOperand(0)), 5887 MachinePointerInfo(I.getArgOperand(1)), 5888 I.getAAMetadata()); 5889 updateDAGForMaybeTailCall(MC); 5890 return; 5891 } 5892 case Intrinsic::memset: { 5893 const auto &MSI = cast<MemSetInst>(I); 5894 SDValue Op1 = getValue(I.getArgOperand(0)); 5895 SDValue Op2 = getValue(I.getArgOperand(1)); 5896 SDValue Op3 = getValue(I.getArgOperand(2)); 5897 // @llvm.memset defines 0 and 1 to both mean no alignment. 5898 Align Alignment = MSI.getDestAlign().valueOrOne(); 5899 bool isVol = MSI.isVolatile(); 5900 bool isTC = I.isTailCall() && isInTailCallPosition(I, DAG.getTarget()); 5901 SDValue Root = isVol ? getRoot() : getMemoryRoot(); 5902 SDValue MS = DAG.getMemset( 5903 Root, sdl, Op1, Op2, Op3, Alignment, isVol, /* AlwaysInline */ false, 5904 isTC, MachinePointerInfo(I.getArgOperand(0)), I.getAAMetadata()); 5905 updateDAGForMaybeTailCall(MS); 5906 return; 5907 } 5908 case Intrinsic::memset_inline: { 5909 const auto &MSII = cast<MemSetInlineInst>(I); 5910 SDValue Dst = getValue(I.getArgOperand(0)); 5911 SDValue Value = getValue(I.getArgOperand(1)); 5912 SDValue Size = getValue(I.getArgOperand(2)); 5913 assert(isa<ConstantSDNode>(Size) && "memset_inline needs constant size"); 5914 // @llvm.memset defines 0 and 1 to both mean no alignment. 5915 Align DstAlign = MSII.getDestAlign().valueOrOne(); 5916 bool isVol = MSII.isVolatile(); 5917 bool isTC = I.isTailCall() && isInTailCallPosition(I, DAG.getTarget()); 5918 SDValue Root = isVol ? getRoot() : getMemoryRoot(); 5919 SDValue MC = DAG.getMemset(Root, sdl, Dst, Value, Size, DstAlign, isVol, 5920 /* AlwaysInline */ true, isTC, 5921 MachinePointerInfo(I.getArgOperand(0)), 5922 I.getAAMetadata()); 5923 updateDAGForMaybeTailCall(MC); 5924 return; 5925 } 5926 case Intrinsic::memmove: { 5927 const auto &MMI = cast<MemMoveInst>(I); 5928 SDValue Op1 = getValue(I.getArgOperand(0)); 5929 SDValue Op2 = getValue(I.getArgOperand(1)); 5930 SDValue Op3 = getValue(I.getArgOperand(2)); 5931 // @llvm.memmove defines 0 and 1 to both mean no alignment. 5932 Align DstAlign = MMI.getDestAlign().valueOrOne(); 5933 Align SrcAlign = MMI.getSourceAlign().valueOrOne(); 5934 Align Alignment = std::min(DstAlign, SrcAlign); 5935 bool isVol = MMI.isVolatile(); 5936 bool isTC = I.isTailCall() && isInTailCallPosition(I, DAG.getTarget()); 5937 // FIXME: Support passing different dest/src alignments to the memmove DAG 5938 // node. 5939 SDValue Root = isVol ? getRoot() : getMemoryRoot(); 5940 SDValue MM = DAG.getMemmove(Root, sdl, Op1, Op2, Op3, Alignment, isVol, 5941 isTC, MachinePointerInfo(I.getArgOperand(0)), 5942 MachinePointerInfo(I.getArgOperand(1)), 5943 I.getAAMetadata()); 5944 updateDAGForMaybeTailCall(MM); 5945 return; 5946 } 5947 case Intrinsic::memcpy_element_unordered_atomic: { 5948 const AtomicMemCpyInst &MI = cast<AtomicMemCpyInst>(I); 5949 SDValue Dst = getValue(MI.getRawDest()); 5950 SDValue Src = getValue(MI.getRawSource()); 5951 SDValue Length = getValue(MI.getLength()); 5952 5953 Type *LengthTy = MI.getLength()->getType(); 5954 unsigned ElemSz = MI.getElementSizeInBytes(); 5955 bool isTC = I.isTailCall() && isInTailCallPosition(I, DAG.getTarget()); 5956 SDValue MC = 5957 DAG.getAtomicMemcpy(getRoot(), sdl, Dst, Src, Length, LengthTy, ElemSz, 5958 isTC, MachinePointerInfo(MI.getRawDest()), 5959 MachinePointerInfo(MI.getRawSource())); 5960 updateDAGForMaybeTailCall(MC); 5961 return; 5962 } 5963 case Intrinsic::memmove_element_unordered_atomic: { 5964 auto &MI = cast<AtomicMemMoveInst>(I); 5965 SDValue Dst = getValue(MI.getRawDest()); 5966 SDValue Src = getValue(MI.getRawSource()); 5967 SDValue Length = getValue(MI.getLength()); 5968 5969 Type *LengthTy = MI.getLength()->getType(); 5970 unsigned ElemSz = MI.getElementSizeInBytes(); 5971 bool isTC = I.isTailCall() && isInTailCallPosition(I, DAG.getTarget()); 5972 SDValue MC = 5973 DAG.getAtomicMemmove(getRoot(), sdl, Dst, Src, Length, LengthTy, ElemSz, 5974 isTC, MachinePointerInfo(MI.getRawDest()), 5975 MachinePointerInfo(MI.getRawSource())); 5976 updateDAGForMaybeTailCall(MC); 5977 return; 5978 } 5979 case Intrinsic::memset_element_unordered_atomic: { 5980 auto &MI = cast<AtomicMemSetInst>(I); 5981 SDValue Dst = getValue(MI.getRawDest()); 5982 SDValue Val = getValue(MI.getValue()); 5983 SDValue Length = getValue(MI.getLength()); 5984 5985 Type *LengthTy = MI.getLength()->getType(); 5986 unsigned ElemSz = MI.getElementSizeInBytes(); 5987 bool isTC = I.isTailCall() && isInTailCallPosition(I, DAG.getTarget()); 5988 SDValue MC = 5989 DAG.getAtomicMemset(getRoot(), sdl, Dst, Val, Length, LengthTy, ElemSz, 5990 isTC, MachinePointerInfo(MI.getRawDest())); 5991 updateDAGForMaybeTailCall(MC); 5992 return; 5993 } 5994 case Intrinsic::call_preallocated_setup: { 5995 const CallBase *PreallocatedCall = FindPreallocatedCall(&I); 5996 SDValue SrcValue = DAG.getSrcValue(PreallocatedCall); 5997 SDValue Res = DAG.getNode(ISD::PREALLOCATED_SETUP, sdl, MVT::Other, 5998 getRoot(), SrcValue); 5999 setValue(&I, Res); 6000 DAG.setRoot(Res); 6001 return; 6002 } 6003 case Intrinsic::call_preallocated_arg: { 6004 const CallBase *PreallocatedCall = FindPreallocatedCall(I.getOperand(0)); 6005 SDValue SrcValue = DAG.getSrcValue(PreallocatedCall); 6006 SDValue Ops[3]; 6007 Ops[0] = getRoot(); 6008 Ops[1] = SrcValue; 6009 Ops[2] = DAG.getTargetConstant(*cast<ConstantInt>(I.getArgOperand(1)), sdl, 6010 MVT::i32); // arg index 6011 SDValue Res = DAG.getNode( 6012 ISD::PREALLOCATED_ARG, sdl, 6013 DAG.getVTList(TLI.getPointerTy(DAG.getDataLayout()), MVT::Other), Ops); 6014 setValue(&I, Res); 6015 DAG.setRoot(Res.getValue(1)); 6016 return; 6017 } 6018 case Intrinsic::dbg_addr: 6019 case Intrinsic::dbg_declare: { 6020 // Assume dbg.addr and dbg.declare can not currently use DIArgList, i.e. 6021 // they are non-variadic. 6022 const auto &DI = cast<DbgVariableIntrinsic>(I); 6023 assert(!DI.hasArgList() && "Only dbg.value should currently use DIArgList"); 6024 DILocalVariable *Variable = DI.getVariable(); 6025 DIExpression *Expression = DI.getExpression(); 6026 dropDanglingDebugInfo(Variable, Expression); 6027 assert(Variable && "Missing variable"); 6028 LLVM_DEBUG(dbgs() << "SelectionDAG visiting debug intrinsic: " << DI 6029 << "\n"); 6030 // Check if address has undef value. 6031 const Value *Address = DI.getVariableLocationOp(0); 6032 if (!Address || isa<UndefValue>(Address) || 6033 (Address->use_empty() && !isa<Argument>(Address))) { 6034 LLVM_DEBUG(dbgs() << "Dropping debug info for " << DI 6035 << " (bad/undef/unused-arg address)\n"); 6036 return; 6037 } 6038 6039 bool isParameter = Variable->isParameter() || isa<Argument>(Address); 6040 6041 // Check if this variable can be described by a frame index, typically 6042 // either as a static alloca or a byval parameter. 6043 int FI = std::numeric_limits<int>::max(); 6044 if (const auto *AI = 6045 dyn_cast<AllocaInst>(Address->stripInBoundsConstantOffsets())) { 6046 if (AI->isStaticAlloca()) { 6047 auto I = FuncInfo.StaticAllocaMap.find(AI); 6048 if (I != FuncInfo.StaticAllocaMap.end()) 6049 FI = I->second; 6050 } 6051 } else if (const auto *Arg = dyn_cast<Argument>( 6052 Address->stripInBoundsConstantOffsets())) { 6053 FI = FuncInfo.getArgumentFrameIndex(Arg); 6054 } 6055 6056 // llvm.dbg.addr is control dependent and always generates indirect 6057 // DBG_VALUE instructions. llvm.dbg.declare is handled as a frame index in 6058 // the MachineFunction variable table. 6059 if (FI != std::numeric_limits<int>::max()) { 6060 if (Intrinsic == Intrinsic::dbg_addr) { 6061 SDDbgValue *SDV = DAG.getFrameIndexDbgValue( 6062 Variable, Expression, FI, getRoot().getNode(), /*IsIndirect*/ true, 6063 dl, SDNodeOrder); 6064 DAG.AddDbgValue(SDV, isParameter); 6065 } else { 6066 LLVM_DEBUG(dbgs() << "Skipping " << DI 6067 << " (variable info stashed in MF side table)\n"); 6068 } 6069 return; 6070 } 6071 6072 SDValue &N = NodeMap[Address]; 6073 if (!N.getNode() && isa<Argument>(Address)) 6074 // Check unused arguments map. 6075 N = UnusedArgNodeMap[Address]; 6076 SDDbgValue *SDV; 6077 if (N.getNode()) { 6078 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address)) 6079 Address = BCI->getOperand(0); 6080 // Parameters are handled specially. 6081 auto FINode = dyn_cast<FrameIndexSDNode>(N.getNode()); 6082 if (isParameter && FINode) { 6083 // Byval parameter. We have a frame index at this point. 6084 SDV = 6085 DAG.getFrameIndexDbgValue(Variable, Expression, FINode->getIndex(), 6086 /*IsIndirect*/ true, dl, SDNodeOrder); 6087 } else if (isa<Argument>(Address)) { 6088 // Address is an argument, so try to emit its dbg value using 6089 // virtual register info from the FuncInfo.ValueMap. 6090 EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 6091 FuncArgumentDbgValueKind::Declare, N); 6092 return; 6093 } else { 6094 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(), 6095 true, dl, SDNodeOrder); 6096 } 6097 DAG.AddDbgValue(SDV, isParameter); 6098 } else { 6099 // If Address is an argument then try to emit its dbg value using 6100 // virtual register info from the FuncInfo.ValueMap. 6101 if (!EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 6102 FuncArgumentDbgValueKind::Declare, N)) { 6103 LLVM_DEBUG(dbgs() << "Dropping debug info for " << DI 6104 << " (could not emit func-arg dbg_value)\n"); 6105 } 6106 } 6107 return; 6108 } 6109 case Intrinsic::dbg_label: { 6110 const DbgLabelInst &DI = cast<DbgLabelInst>(I); 6111 DILabel *Label = DI.getLabel(); 6112 assert(Label && "Missing label"); 6113 6114 SDDbgLabel *SDV; 6115 SDV = DAG.getDbgLabel(Label, dl, SDNodeOrder); 6116 DAG.AddDbgLabel(SDV); 6117 return; 6118 } 6119 case Intrinsic::dbg_value: { 6120 const DbgValueInst &DI = cast<DbgValueInst>(I); 6121 assert(DI.getVariable() && "Missing variable"); 6122 6123 DILocalVariable *Variable = DI.getVariable(); 6124 DIExpression *Expression = DI.getExpression(); 6125 dropDanglingDebugInfo(Variable, Expression); 6126 SmallVector<Value *, 4> Values(DI.getValues()); 6127 if (Values.empty()) 6128 return; 6129 6130 if (llvm::is_contained(Values, nullptr)) 6131 return; 6132 6133 bool IsVariadic = DI.hasArgList(); 6134 if (!handleDebugValue(Values, Variable, Expression, dl, DI.getDebugLoc(), 6135 SDNodeOrder, IsVariadic)) 6136 addDanglingDebugInfo(&DI, dl, SDNodeOrder); 6137 return; 6138 } 6139 6140 case Intrinsic::eh_typeid_for: { 6141 // Find the type id for the given typeinfo. 6142 GlobalValue *GV = ExtractTypeInfo(I.getArgOperand(0)); 6143 unsigned TypeID = DAG.getMachineFunction().getTypeIDFor(GV); 6144 Res = DAG.getConstant(TypeID, sdl, MVT::i32); 6145 setValue(&I, Res); 6146 return; 6147 } 6148 6149 case Intrinsic::eh_return_i32: 6150 case Intrinsic::eh_return_i64: 6151 DAG.getMachineFunction().setCallsEHReturn(true); 6152 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl, 6153 MVT::Other, 6154 getControlRoot(), 6155 getValue(I.getArgOperand(0)), 6156 getValue(I.getArgOperand(1)))); 6157 return; 6158 case Intrinsic::eh_unwind_init: 6159 DAG.getMachineFunction().setCallsUnwindInit(true); 6160 return; 6161 case Intrinsic::eh_dwarf_cfa: 6162 setValue(&I, DAG.getNode(ISD::EH_DWARF_CFA, sdl, 6163 TLI.getPointerTy(DAG.getDataLayout()), 6164 getValue(I.getArgOperand(0)))); 6165 return; 6166 case Intrinsic::eh_sjlj_callsite: { 6167 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 6168 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(0)); 6169 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!"); 6170 6171 MMI.setCurrentCallSite(CI->getZExtValue()); 6172 return; 6173 } 6174 case Intrinsic::eh_sjlj_functioncontext: { 6175 // Get and store the index of the function context. 6176 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); 6177 AllocaInst *FnCtx = 6178 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts()); 6179 int FI = FuncInfo.StaticAllocaMap[FnCtx]; 6180 MFI.setFunctionContextIndex(FI); 6181 return; 6182 } 6183 case Intrinsic::eh_sjlj_setjmp: { 6184 SDValue Ops[2]; 6185 Ops[0] = getRoot(); 6186 Ops[1] = getValue(I.getArgOperand(0)); 6187 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl, 6188 DAG.getVTList(MVT::i32, MVT::Other), Ops); 6189 setValue(&I, Op.getValue(0)); 6190 DAG.setRoot(Op.getValue(1)); 6191 return; 6192 } 6193 case Intrinsic::eh_sjlj_longjmp: 6194 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other, 6195 getRoot(), getValue(I.getArgOperand(0)))); 6196 return; 6197 case Intrinsic::eh_sjlj_setup_dispatch: 6198 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_SETUP_DISPATCH, sdl, MVT::Other, 6199 getRoot())); 6200 return; 6201 case Intrinsic::masked_gather: 6202 visitMaskedGather(I); 6203 return; 6204 case Intrinsic::masked_load: 6205 visitMaskedLoad(I); 6206 return; 6207 case Intrinsic::masked_scatter: 6208 visitMaskedScatter(I); 6209 return; 6210 case Intrinsic::masked_store: 6211 visitMaskedStore(I); 6212 return; 6213 case Intrinsic::masked_expandload: 6214 visitMaskedLoad(I, true /* IsExpanding */); 6215 return; 6216 case Intrinsic::masked_compressstore: 6217 visitMaskedStore(I, true /* IsCompressing */); 6218 return; 6219 case Intrinsic::powi: 6220 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)), 6221 getValue(I.getArgOperand(1)), DAG)); 6222 return; 6223 case Intrinsic::log: 6224 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, TLI, Flags)); 6225 return; 6226 case Intrinsic::log2: 6227 setValue(&I, 6228 expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, TLI, Flags)); 6229 return; 6230 case Intrinsic::log10: 6231 setValue(&I, 6232 expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, TLI, Flags)); 6233 return; 6234 case Intrinsic::exp: 6235 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, TLI, Flags)); 6236 return; 6237 case Intrinsic::exp2: 6238 setValue(&I, 6239 expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, TLI, Flags)); 6240 return; 6241 case Intrinsic::pow: 6242 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)), 6243 getValue(I.getArgOperand(1)), DAG, TLI, Flags)); 6244 return; 6245 case Intrinsic::sqrt: 6246 case Intrinsic::fabs: 6247 case Intrinsic::sin: 6248 case Intrinsic::cos: 6249 case Intrinsic::floor: 6250 case Intrinsic::ceil: 6251 case Intrinsic::trunc: 6252 case Intrinsic::rint: 6253 case Intrinsic::nearbyint: 6254 case Intrinsic::round: 6255 case Intrinsic::roundeven: 6256 case Intrinsic::canonicalize: { 6257 unsigned Opcode; 6258 switch (Intrinsic) { 6259 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 6260 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break; 6261 case Intrinsic::fabs: Opcode = ISD::FABS; break; 6262 case Intrinsic::sin: Opcode = ISD::FSIN; break; 6263 case Intrinsic::cos: Opcode = ISD::FCOS; break; 6264 case Intrinsic::floor: Opcode = ISD::FFLOOR; break; 6265 case Intrinsic::ceil: Opcode = ISD::FCEIL; break; 6266 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break; 6267 case Intrinsic::rint: Opcode = ISD::FRINT; break; 6268 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break; 6269 case Intrinsic::round: Opcode = ISD::FROUND; break; 6270 case Intrinsic::roundeven: Opcode = ISD::FROUNDEVEN; break; 6271 case Intrinsic::canonicalize: Opcode = ISD::FCANONICALIZE; break; 6272 } 6273 6274 setValue(&I, DAG.getNode(Opcode, sdl, 6275 getValue(I.getArgOperand(0)).getValueType(), 6276 getValue(I.getArgOperand(0)), Flags)); 6277 return; 6278 } 6279 case Intrinsic::lround: 6280 case Intrinsic::llround: 6281 case Intrinsic::lrint: 6282 case Intrinsic::llrint: { 6283 unsigned Opcode; 6284 switch (Intrinsic) { 6285 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 6286 case Intrinsic::lround: Opcode = ISD::LROUND; break; 6287 case Intrinsic::llround: Opcode = ISD::LLROUND; break; 6288 case Intrinsic::lrint: Opcode = ISD::LRINT; break; 6289 case Intrinsic::llrint: Opcode = ISD::LLRINT; break; 6290 } 6291 6292 EVT RetVT = TLI.getValueType(DAG.getDataLayout(), I.getType()); 6293 setValue(&I, DAG.getNode(Opcode, sdl, RetVT, 6294 getValue(I.getArgOperand(0)))); 6295 return; 6296 } 6297 case Intrinsic::minnum: 6298 setValue(&I, DAG.getNode(ISD::FMINNUM, sdl, 6299 getValue(I.getArgOperand(0)).getValueType(), 6300 getValue(I.getArgOperand(0)), 6301 getValue(I.getArgOperand(1)), Flags)); 6302 return; 6303 case Intrinsic::maxnum: 6304 setValue(&I, DAG.getNode(ISD::FMAXNUM, sdl, 6305 getValue(I.getArgOperand(0)).getValueType(), 6306 getValue(I.getArgOperand(0)), 6307 getValue(I.getArgOperand(1)), Flags)); 6308 return; 6309 case Intrinsic::minimum: 6310 setValue(&I, DAG.getNode(ISD::FMINIMUM, sdl, 6311 getValue(I.getArgOperand(0)).getValueType(), 6312 getValue(I.getArgOperand(0)), 6313 getValue(I.getArgOperand(1)), Flags)); 6314 return; 6315 case Intrinsic::maximum: 6316 setValue(&I, DAG.getNode(ISD::FMAXIMUM, sdl, 6317 getValue(I.getArgOperand(0)).getValueType(), 6318 getValue(I.getArgOperand(0)), 6319 getValue(I.getArgOperand(1)), Flags)); 6320 return; 6321 case Intrinsic::copysign: 6322 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl, 6323 getValue(I.getArgOperand(0)).getValueType(), 6324 getValue(I.getArgOperand(0)), 6325 getValue(I.getArgOperand(1)), Flags)); 6326 return; 6327 case Intrinsic::arithmetic_fence: { 6328 setValue(&I, DAG.getNode(ISD::ARITH_FENCE, sdl, 6329 getValue(I.getArgOperand(0)).getValueType(), 6330 getValue(I.getArgOperand(0)), Flags)); 6331 return; 6332 } 6333 case Intrinsic::fma: 6334 setValue(&I, DAG.getNode( 6335 ISD::FMA, sdl, getValue(I.getArgOperand(0)).getValueType(), 6336 getValue(I.getArgOperand(0)), getValue(I.getArgOperand(1)), 6337 getValue(I.getArgOperand(2)), Flags)); 6338 return; 6339 #define INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC) \ 6340 case Intrinsic::INTRINSIC: 6341 #include "llvm/IR/ConstrainedOps.def" 6342 visitConstrainedFPIntrinsic(cast<ConstrainedFPIntrinsic>(I)); 6343 return; 6344 #define BEGIN_REGISTER_VP_INTRINSIC(VPID, ...) case Intrinsic::VPID: 6345 #include "llvm/IR/VPIntrinsics.def" 6346 visitVectorPredicationIntrinsic(cast<VPIntrinsic>(I)); 6347 return; 6348 case Intrinsic::fptrunc_round: { 6349 // Get the last argument, the metadata and convert it to an integer in the 6350 // call 6351 Metadata *MD = cast<MetadataAsValue>(I.getArgOperand(1))->getMetadata(); 6352 Optional<RoundingMode> RoundMode = 6353 convertStrToRoundingMode(cast<MDString>(MD)->getString()); 6354 6355 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType()); 6356 6357 // Propagate fast-math-flags from IR to node(s). 6358 SDNodeFlags Flags; 6359 Flags.copyFMF(*cast<FPMathOperator>(&I)); 6360 SelectionDAG::FlagInserter FlagsInserter(DAG, Flags); 6361 6362 SDValue Result; 6363 Result = DAG.getNode( 6364 ISD::FPTRUNC_ROUND, sdl, VT, getValue(I.getArgOperand(0)), 6365 DAG.getTargetConstant((int)*RoundMode, sdl, 6366 TLI.getPointerTy(DAG.getDataLayout()))); 6367 setValue(&I, Result); 6368 6369 return; 6370 } 6371 case Intrinsic::fmuladd: { 6372 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType()); 6373 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict && 6374 TLI.isFMAFasterThanFMulAndFAdd(DAG.getMachineFunction(), VT)) { 6375 setValue(&I, DAG.getNode(ISD::FMA, sdl, 6376 getValue(I.getArgOperand(0)).getValueType(), 6377 getValue(I.getArgOperand(0)), 6378 getValue(I.getArgOperand(1)), 6379 getValue(I.getArgOperand(2)), Flags)); 6380 } else { 6381 // TODO: Intrinsic calls should have fast-math-flags. 6382 SDValue Mul = DAG.getNode( 6383 ISD::FMUL, sdl, getValue(I.getArgOperand(0)).getValueType(), 6384 getValue(I.getArgOperand(0)), getValue(I.getArgOperand(1)), Flags); 6385 SDValue Add = DAG.getNode(ISD::FADD, sdl, 6386 getValue(I.getArgOperand(0)).getValueType(), 6387 Mul, getValue(I.getArgOperand(2)), Flags); 6388 setValue(&I, Add); 6389 } 6390 return; 6391 } 6392 case Intrinsic::convert_to_fp16: 6393 setValue(&I, DAG.getNode(ISD::BITCAST, sdl, MVT::i16, 6394 DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16, 6395 getValue(I.getArgOperand(0)), 6396 DAG.getTargetConstant(0, sdl, 6397 MVT::i32)))); 6398 return; 6399 case Intrinsic::convert_from_fp16: 6400 setValue(&I, DAG.getNode(ISD::FP_EXTEND, sdl, 6401 TLI.getValueType(DAG.getDataLayout(), I.getType()), 6402 DAG.getNode(ISD::BITCAST, sdl, MVT::f16, 6403 getValue(I.getArgOperand(0))))); 6404 return; 6405 case Intrinsic::fptosi_sat: { 6406 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType()); 6407 setValue(&I, DAG.getNode(ISD::FP_TO_SINT_SAT, sdl, VT, 6408 getValue(I.getArgOperand(0)), 6409 DAG.getValueType(VT.getScalarType()))); 6410 return; 6411 } 6412 case Intrinsic::fptoui_sat: { 6413 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType()); 6414 setValue(&I, DAG.getNode(ISD::FP_TO_UINT_SAT, sdl, VT, 6415 getValue(I.getArgOperand(0)), 6416 DAG.getValueType(VT.getScalarType()))); 6417 return; 6418 } 6419 case Intrinsic::set_rounding: 6420 Res = DAG.getNode(ISD::SET_ROUNDING, sdl, MVT::Other, 6421 {getRoot(), getValue(I.getArgOperand(0))}); 6422 setValue(&I, Res); 6423 DAG.setRoot(Res.getValue(0)); 6424 return; 6425 case Intrinsic::is_fpclass: { 6426 const DataLayout DLayout = DAG.getDataLayout(); 6427 EVT DestVT = TLI.getValueType(DLayout, I.getType()); 6428 EVT ArgVT = TLI.getValueType(DLayout, I.getArgOperand(0)->getType()); 6429 unsigned Test = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue(); 6430 MachineFunction &MF = DAG.getMachineFunction(); 6431 const Function &F = MF.getFunction(); 6432 SDValue Op = getValue(I.getArgOperand(0)); 6433 SDNodeFlags Flags; 6434 Flags.setNoFPExcept( 6435 !F.getAttributes().hasFnAttr(llvm::Attribute::StrictFP)); 6436 // If ISD::IS_FPCLASS should be expanded, do it right now, because the 6437 // expansion can use illegal types. Making expansion early allows 6438 // legalizing these types prior to selection. 6439 if (!TLI.isOperationLegalOrCustom(ISD::IS_FPCLASS, ArgVT)) { 6440 SDValue Result = TLI.expandIS_FPCLASS(DestVT, Op, Test, Flags, sdl, DAG); 6441 setValue(&I, Result); 6442 return; 6443 } 6444 6445 SDValue Check = DAG.getTargetConstant(Test, sdl, MVT::i32); 6446 SDValue V = DAG.getNode(ISD::IS_FPCLASS, sdl, DestVT, {Op, Check}, Flags); 6447 setValue(&I, V); 6448 return; 6449 } 6450 case Intrinsic::pcmarker: { 6451 SDValue Tmp = getValue(I.getArgOperand(0)); 6452 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp)); 6453 return; 6454 } 6455 case Intrinsic::readcyclecounter: { 6456 SDValue Op = getRoot(); 6457 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl, 6458 DAG.getVTList(MVT::i64, MVT::Other), Op); 6459 setValue(&I, Res); 6460 DAG.setRoot(Res.getValue(1)); 6461 return; 6462 } 6463 case Intrinsic::bitreverse: 6464 setValue(&I, DAG.getNode(ISD::BITREVERSE, sdl, 6465 getValue(I.getArgOperand(0)).getValueType(), 6466 getValue(I.getArgOperand(0)))); 6467 return; 6468 case Intrinsic::bswap: 6469 setValue(&I, DAG.getNode(ISD::BSWAP, sdl, 6470 getValue(I.getArgOperand(0)).getValueType(), 6471 getValue(I.getArgOperand(0)))); 6472 return; 6473 case Intrinsic::cttz: { 6474 SDValue Arg = getValue(I.getArgOperand(0)); 6475 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1)); 6476 EVT Ty = Arg.getValueType(); 6477 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF, 6478 sdl, Ty, Arg)); 6479 return; 6480 } 6481 case Intrinsic::ctlz: { 6482 SDValue Arg = getValue(I.getArgOperand(0)); 6483 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1)); 6484 EVT Ty = Arg.getValueType(); 6485 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF, 6486 sdl, Ty, Arg)); 6487 return; 6488 } 6489 case Intrinsic::ctpop: { 6490 SDValue Arg = getValue(I.getArgOperand(0)); 6491 EVT Ty = Arg.getValueType(); 6492 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg)); 6493 return; 6494 } 6495 case Intrinsic::fshl: 6496 case Intrinsic::fshr: { 6497 bool IsFSHL = Intrinsic == Intrinsic::fshl; 6498 SDValue X = getValue(I.getArgOperand(0)); 6499 SDValue Y = getValue(I.getArgOperand(1)); 6500 SDValue Z = getValue(I.getArgOperand(2)); 6501 EVT VT = X.getValueType(); 6502 6503 if (X == Y) { 6504 auto RotateOpcode = IsFSHL ? ISD::ROTL : ISD::ROTR; 6505 setValue(&I, DAG.getNode(RotateOpcode, sdl, VT, X, Z)); 6506 } else { 6507 auto FunnelOpcode = IsFSHL ? ISD::FSHL : ISD::FSHR; 6508 setValue(&I, DAG.getNode(FunnelOpcode, sdl, VT, X, Y, Z)); 6509 } 6510 return; 6511 } 6512 case Intrinsic::sadd_sat: { 6513 SDValue Op1 = getValue(I.getArgOperand(0)); 6514 SDValue Op2 = getValue(I.getArgOperand(1)); 6515 setValue(&I, DAG.getNode(ISD::SADDSAT, sdl, Op1.getValueType(), Op1, Op2)); 6516 return; 6517 } 6518 case Intrinsic::uadd_sat: { 6519 SDValue Op1 = getValue(I.getArgOperand(0)); 6520 SDValue Op2 = getValue(I.getArgOperand(1)); 6521 setValue(&I, DAG.getNode(ISD::UADDSAT, sdl, Op1.getValueType(), Op1, Op2)); 6522 return; 6523 } 6524 case Intrinsic::ssub_sat: { 6525 SDValue Op1 = getValue(I.getArgOperand(0)); 6526 SDValue Op2 = getValue(I.getArgOperand(1)); 6527 setValue(&I, DAG.getNode(ISD::SSUBSAT, sdl, Op1.getValueType(), Op1, Op2)); 6528 return; 6529 } 6530 case Intrinsic::usub_sat: { 6531 SDValue Op1 = getValue(I.getArgOperand(0)); 6532 SDValue Op2 = getValue(I.getArgOperand(1)); 6533 setValue(&I, DAG.getNode(ISD::USUBSAT, sdl, Op1.getValueType(), Op1, Op2)); 6534 return; 6535 } 6536 case Intrinsic::sshl_sat: { 6537 SDValue Op1 = getValue(I.getArgOperand(0)); 6538 SDValue Op2 = getValue(I.getArgOperand(1)); 6539 setValue(&I, DAG.getNode(ISD::SSHLSAT, sdl, Op1.getValueType(), Op1, Op2)); 6540 return; 6541 } 6542 case Intrinsic::ushl_sat: { 6543 SDValue Op1 = getValue(I.getArgOperand(0)); 6544 SDValue Op2 = getValue(I.getArgOperand(1)); 6545 setValue(&I, DAG.getNode(ISD::USHLSAT, sdl, Op1.getValueType(), Op1, Op2)); 6546 return; 6547 } 6548 case Intrinsic::smul_fix: 6549 case Intrinsic::umul_fix: 6550 case Intrinsic::smul_fix_sat: 6551 case Intrinsic::umul_fix_sat: { 6552 SDValue Op1 = getValue(I.getArgOperand(0)); 6553 SDValue Op2 = getValue(I.getArgOperand(1)); 6554 SDValue Op3 = getValue(I.getArgOperand(2)); 6555 setValue(&I, DAG.getNode(FixedPointIntrinsicToOpcode(Intrinsic), sdl, 6556 Op1.getValueType(), Op1, Op2, Op3)); 6557 return; 6558 } 6559 case Intrinsic::sdiv_fix: 6560 case Intrinsic::udiv_fix: 6561 case Intrinsic::sdiv_fix_sat: 6562 case Intrinsic::udiv_fix_sat: { 6563 SDValue Op1 = getValue(I.getArgOperand(0)); 6564 SDValue Op2 = getValue(I.getArgOperand(1)); 6565 SDValue Op3 = getValue(I.getArgOperand(2)); 6566 setValue(&I, expandDivFix(FixedPointIntrinsicToOpcode(Intrinsic), sdl, 6567 Op1, Op2, Op3, DAG, TLI)); 6568 return; 6569 } 6570 case Intrinsic::smax: { 6571 SDValue Op1 = getValue(I.getArgOperand(0)); 6572 SDValue Op2 = getValue(I.getArgOperand(1)); 6573 setValue(&I, DAG.getNode(ISD::SMAX, sdl, Op1.getValueType(), Op1, Op2)); 6574 return; 6575 } 6576 case Intrinsic::smin: { 6577 SDValue Op1 = getValue(I.getArgOperand(0)); 6578 SDValue Op2 = getValue(I.getArgOperand(1)); 6579 setValue(&I, DAG.getNode(ISD::SMIN, sdl, Op1.getValueType(), Op1, Op2)); 6580 return; 6581 } 6582 case Intrinsic::umax: { 6583 SDValue Op1 = getValue(I.getArgOperand(0)); 6584 SDValue Op2 = getValue(I.getArgOperand(1)); 6585 setValue(&I, DAG.getNode(ISD::UMAX, sdl, Op1.getValueType(), Op1, Op2)); 6586 return; 6587 } 6588 case Intrinsic::umin: { 6589 SDValue Op1 = getValue(I.getArgOperand(0)); 6590 SDValue Op2 = getValue(I.getArgOperand(1)); 6591 setValue(&I, DAG.getNode(ISD::UMIN, sdl, Op1.getValueType(), Op1, Op2)); 6592 return; 6593 } 6594 case Intrinsic::abs: { 6595 // TODO: Preserve "int min is poison" arg in SDAG? 6596 SDValue Op1 = getValue(I.getArgOperand(0)); 6597 setValue(&I, DAG.getNode(ISD::ABS, sdl, Op1.getValueType(), Op1)); 6598 return; 6599 } 6600 case Intrinsic::stacksave: { 6601 SDValue Op = getRoot(); 6602 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType()); 6603 Res = DAG.getNode(ISD::STACKSAVE, sdl, DAG.getVTList(VT, MVT::Other), Op); 6604 setValue(&I, Res); 6605 DAG.setRoot(Res.getValue(1)); 6606 return; 6607 } 6608 case Intrinsic::stackrestore: 6609 Res = getValue(I.getArgOperand(0)); 6610 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res)); 6611 return; 6612 case Intrinsic::get_dynamic_area_offset: { 6613 SDValue Op = getRoot(); 6614 EVT PtrTy = TLI.getFrameIndexTy(DAG.getDataLayout()); 6615 EVT ResTy = TLI.getValueType(DAG.getDataLayout(), I.getType()); 6616 // Result type for @llvm.get.dynamic.area.offset should match PtrTy for 6617 // target. 6618 if (PtrTy.getFixedSizeInBits() < ResTy.getFixedSizeInBits()) 6619 report_fatal_error("Wrong result type for @llvm.get.dynamic.area.offset" 6620 " intrinsic!"); 6621 Res = DAG.getNode(ISD::GET_DYNAMIC_AREA_OFFSET, sdl, DAG.getVTList(ResTy), 6622 Op); 6623 DAG.setRoot(Op); 6624 setValue(&I, Res); 6625 return; 6626 } 6627 case Intrinsic::stackguard: { 6628 MachineFunction &MF = DAG.getMachineFunction(); 6629 const Module &M = *MF.getFunction().getParent(); 6630 SDValue Chain = getRoot(); 6631 if (TLI.useLoadStackGuardNode()) { 6632 Res = getLoadStackGuard(DAG, sdl, Chain); 6633 } else { 6634 EVT PtrTy = TLI.getValueType(DAG.getDataLayout(), I.getType()); 6635 const Value *Global = TLI.getSDagStackGuard(M); 6636 Align Align = DAG.getDataLayout().getPrefTypeAlign(Global->getType()); 6637 Res = DAG.getLoad(PtrTy, sdl, Chain, getValue(Global), 6638 MachinePointerInfo(Global, 0), Align, 6639 MachineMemOperand::MOVolatile); 6640 } 6641 if (TLI.useStackGuardXorFP()) 6642 Res = TLI.emitStackGuardXorFP(DAG, Res, sdl); 6643 DAG.setRoot(Chain); 6644 setValue(&I, Res); 6645 return; 6646 } 6647 case Intrinsic::stackprotector: { 6648 // Emit code into the DAG to store the stack guard onto the stack. 6649 MachineFunction &MF = DAG.getMachineFunction(); 6650 MachineFrameInfo &MFI = MF.getFrameInfo(); 6651 SDValue Src, Chain = getRoot(); 6652 6653 if (TLI.useLoadStackGuardNode()) 6654 Src = getLoadStackGuard(DAG, sdl, Chain); 6655 else 6656 Src = getValue(I.getArgOperand(0)); // The guard's value. 6657 6658 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1)); 6659 6660 int FI = FuncInfo.StaticAllocaMap[Slot]; 6661 MFI.setStackProtectorIndex(FI); 6662 EVT PtrTy = TLI.getFrameIndexTy(DAG.getDataLayout()); 6663 6664 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 6665 6666 // Store the stack protector onto the stack. 6667 Res = DAG.getStore( 6668 Chain, sdl, Src, FIN, 6669 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), 6670 MaybeAlign(), MachineMemOperand::MOVolatile); 6671 setValue(&I, Res); 6672 DAG.setRoot(Res); 6673 return; 6674 } 6675 case Intrinsic::objectsize: 6676 llvm_unreachable("llvm.objectsize.* should have been lowered already"); 6677 6678 case Intrinsic::is_constant: 6679 llvm_unreachable("llvm.is.constant.* should have been lowered already"); 6680 6681 case Intrinsic::annotation: 6682 case Intrinsic::ptr_annotation: 6683 case Intrinsic::launder_invariant_group: 6684 case Intrinsic::strip_invariant_group: 6685 // Drop the intrinsic, but forward the value 6686 setValue(&I, getValue(I.getOperand(0))); 6687 return; 6688 6689 case Intrinsic::assume: 6690 case Intrinsic::experimental_noalias_scope_decl: 6691 case Intrinsic::var_annotation: 6692 case Intrinsic::sideeffect: 6693 // Discard annotate attributes, noalias scope declarations, assumptions, and 6694 // artificial side-effects. 6695 return; 6696 6697 case Intrinsic::codeview_annotation: { 6698 // Emit a label associated with this metadata. 6699 MachineFunction &MF = DAG.getMachineFunction(); 6700 MCSymbol *Label = 6701 MF.getMMI().getContext().createTempSymbol("annotation", true); 6702 Metadata *MD = cast<MetadataAsValue>(I.getArgOperand(0))->getMetadata(); 6703 MF.addCodeViewAnnotation(Label, cast<MDNode>(MD)); 6704 Res = DAG.getLabelNode(ISD::ANNOTATION_LABEL, sdl, getRoot(), Label); 6705 DAG.setRoot(Res); 6706 return; 6707 } 6708 6709 case Intrinsic::init_trampoline: { 6710 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts()); 6711 6712 SDValue Ops[6]; 6713 Ops[0] = getRoot(); 6714 Ops[1] = getValue(I.getArgOperand(0)); 6715 Ops[2] = getValue(I.getArgOperand(1)); 6716 Ops[3] = getValue(I.getArgOperand(2)); 6717 Ops[4] = DAG.getSrcValue(I.getArgOperand(0)); 6718 Ops[5] = DAG.getSrcValue(F); 6719 6720 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops); 6721 6722 DAG.setRoot(Res); 6723 return; 6724 } 6725 case Intrinsic::adjust_trampoline: 6726 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl, 6727 TLI.getPointerTy(DAG.getDataLayout()), 6728 getValue(I.getArgOperand(0)))); 6729 return; 6730 case Intrinsic::gcroot: { 6731 assert(DAG.getMachineFunction().getFunction().hasGC() && 6732 "only valid in functions with gc specified, enforced by Verifier"); 6733 assert(GFI && "implied by previous"); 6734 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts(); 6735 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1)); 6736 6737 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode()); 6738 GFI->addStackRoot(FI->getIndex(), TypeMap); 6739 return; 6740 } 6741 case Intrinsic::gcread: 6742 case Intrinsic::gcwrite: 6743 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!"); 6744 case Intrinsic::flt_rounds: 6745 Res = DAG.getNode(ISD::FLT_ROUNDS_, sdl, {MVT::i32, MVT::Other}, getRoot()); 6746 setValue(&I, Res); 6747 DAG.setRoot(Res.getValue(1)); 6748 return; 6749 6750 case Intrinsic::expect: 6751 // Just replace __builtin_expect(exp, c) with EXP. 6752 setValue(&I, getValue(I.getArgOperand(0))); 6753 return; 6754 6755 case Intrinsic::ubsantrap: 6756 case Intrinsic::debugtrap: 6757 case Intrinsic::trap: { 6758 StringRef TrapFuncName = 6759 I.getAttributes().getFnAttr("trap-func-name").getValueAsString(); 6760 if (TrapFuncName.empty()) { 6761 switch (Intrinsic) { 6762 case Intrinsic::trap: 6763 DAG.setRoot(DAG.getNode(ISD::TRAP, sdl, MVT::Other, getRoot())); 6764 break; 6765 case Intrinsic::debugtrap: 6766 DAG.setRoot(DAG.getNode(ISD::DEBUGTRAP, sdl, MVT::Other, getRoot())); 6767 break; 6768 case Intrinsic::ubsantrap: 6769 DAG.setRoot(DAG.getNode( 6770 ISD::UBSANTRAP, sdl, MVT::Other, getRoot(), 6771 DAG.getTargetConstant( 6772 cast<ConstantInt>(I.getArgOperand(0))->getZExtValue(), sdl, 6773 MVT::i32))); 6774 break; 6775 default: llvm_unreachable("unknown trap intrinsic"); 6776 } 6777 return; 6778 } 6779 TargetLowering::ArgListTy Args; 6780 if (Intrinsic == Intrinsic::ubsantrap) { 6781 Args.push_back(TargetLoweringBase::ArgListEntry()); 6782 Args[0].Val = I.getArgOperand(0); 6783 Args[0].Node = getValue(Args[0].Val); 6784 Args[0].Ty = Args[0].Val->getType(); 6785 } 6786 6787 TargetLowering::CallLoweringInfo CLI(DAG); 6788 CLI.setDebugLoc(sdl).setChain(getRoot()).setLibCallee( 6789 CallingConv::C, I.getType(), 6790 DAG.getExternalSymbol(TrapFuncName.data(), 6791 TLI.getPointerTy(DAG.getDataLayout())), 6792 std::move(Args)); 6793 6794 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI); 6795 DAG.setRoot(Result.second); 6796 return; 6797 } 6798 6799 case Intrinsic::uadd_with_overflow: 6800 case Intrinsic::sadd_with_overflow: 6801 case Intrinsic::usub_with_overflow: 6802 case Intrinsic::ssub_with_overflow: 6803 case Intrinsic::umul_with_overflow: 6804 case Intrinsic::smul_with_overflow: { 6805 ISD::NodeType Op; 6806 switch (Intrinsic) { 6807 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 6808 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break; 6809 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break; 6810 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break; 6811 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break; 6812 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break; 6813 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break; 6814 } 6815 SDValue Op1 = getValue(I.getArgOperand(0)); 6816 SDValue Op2 = getValue(I.getArgOperand(1)); 6817 6818 EVT ResultVT = Op1.getValueType(); 6819 EVT OverflowVT = MVT::i1; 6820 if (ResultVT.isVector()) 6821 OverflowVT = EVT::getVectorVT( 6822 *Context, OverflowVT, ResultVT.getVectorElementCount()); 6823 6824 SDVTList VTs = DAG.getVTList(ResultVT, OverflowVT); 6825 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2)); 6826 return; 6827 } 6828 case Intrinsic::prefetch: { 6829 SDValue Ops[5]; 6830 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue(); 6831 auto Flags = rw == 0 ? MachineMemOperand::MOLoad :MachineMemOperand::MOStore; 6832 Ops[0] = DAG.getRoot(); 6833 Ops[1] = getValue(I.getArgOperand(0)); 6834 Ops[2] = getValue(I.getArgOperand(1)); 6835 Ops[3] = getValue(I.getArgOperand(2)); 6836 Ops[4] = getValue(I.getArgOperand(3)); 6837 SDValue Result = DAG.getMemIntrinsicNode( 6838 ISD::PREFETCH, sdl, DAG.getVTList(MVT::Other), Ops, 6839 EVT::getIntegerVT(*Context, 8), MachinePointerInfo(I.getArgOperand(0)), 6840 /* align */ None, Flags); 6841 6842 // Chain the prefetch in parallell with any pending loads, to stay out of 6843 // the way of later optimizations. 6844 PendingLoads.push_back(Result); 6845 Result = getRoot(); 6846 DAG.setRoot(Result); 6847 return; 6848 } 6849 case Intrinsic::lifetime_start: 6850 case Intrinsic::lifetime_end: { 6851 bool IsStart = (Intrinsic == Intrinsic::lifetime_start); 6852 // Stack coloring is not enabled in O0, discard region information. 6853 if (TM.getOptLevel() == CodeGenOpt::None) 6854 return; 6855 6856 const int64_t ObjectSize = 6857 cast<ConstantInt>(I.getArgOperand(0))->getSExtValue(); 6858 Value *const ObjectPtr = I.getArgOperand(1); 6859 SmallVector<const Value *, 4> Allocas; 6860 getUnderlyingObjects(ObjectPtr, Allocas); 6861 6862 for (const Value *Alloca : Allocas) { 6863 const AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(Alloca); 6864 6865 // Could not find an Alloca. 6866 if (!LifetimeObject) 6867 continue; 6868 6869 // First check that the Alloca is static, otherwise it won't have a 6870 // valid frame index. 6871 auto SI = FuncInfo.StaticAllocaMap.find(LifetimeObject); 6872 if (SI == FuncInfo.StaticAllocaMap.end()) 6873 return; 6874 6875 const int FrameIndex = SI->second; 6876 int64_t Offset; 6877 if (GetPointerBaseWithConstantOffset( 6878 ObjectPtr, Offset, DAG.getDataLayout()) != LifetimeObject) 6879 Offset = -1; // Cannot determine offset from alloca to lifetime object. 6880 Res = DAG.getLifetimeNode(IsStart, sdl, getRoot(), FrameIndex, ObjectSize, 6881 Offset); 6882 DAG.setRoot(Res); 6883 } 6884 return; 6885 } 6886 case Intrinsic::pseudoprobe: { 6887 auto Guid = cast<ConstantInt>(I.getArgOperand(0))->getZExtValue(); 6888 auto Index = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue(); 6889 auto Attr = cast<ConstantInt>(I.getArgOperand(2))->getZExtValue(); 6890 Res = DAG.getPseudoProbeNode(sdl, getRoot(), Guid, Index, Attr); 6891 DAG.setRoot(Res); 6892 return; 6893 } 6894 case Intrinsic::invariant_start: 6895 // Discard region information. 6896 setValue(&I, 6897 DAG.getUNDEF(TLI.getValueType(DAG.getDataLayout(), I.getType()))); 6898 return; 6899 case Intrinsic::invariant_end: 6900 // Discard region information. 6901 return; 6902 case Intrinsic::clear_cache: 6903 /// FunctionName may be null. 6904 if (const char *FunctionName = TLI.getClearCacheBuiltinName()) 6905 lowerCallToExternalSymbol(I, FunctionName); 6906 return; 6907 case Intrinsic::donothing: 6908 case Intrinsic::seh_try_begin: 6909 case Intrinsic::seh_scope_begin: 6910 case Intrinsic::seh_try_end: 6911 case Intrinsic::seh_scope_end: 6912 // ignore 6913 return; 6914 case Intrinsic::experimental_stackmap: 6915 visitStackmap(I); 6916 return; 6917 case Intrinsic::experimental_patchpoint_void: 6918 case Intrinsic::experimental_patchpoint_i64: 6919 visitPatchpoint(I); 6920 return; 6921 case Intrinsic::experimental_gc_statepoint: 6922 LowerStatepoint(cast<GCStatepointInst>(I)); 6923 return; 6924 case Intrinsic::experimental_gc_result: 6925 visitGCResult(cast<GCResultInst>(I)); 6926 return; 6927 case Intrinsic::experimental_gc_relocate: 6928 visitGCRelocate(cast<GCRelocateInst>(I)); 6929 return; 6930 case Intrinsic::instrprof_cover: 6931 llvm_unreachable("instrprof failed to lower a cover"); 6932 case Intrinsic::instrprof_increment: 6933 llvm_unreachable("instrprof failed to lower an increment"); 6934 case Intrinsic::instrprof_value_profile: 6935 llvm_unreachable("instrprof failed to lower a value profiling call"); 6936 case Intrinsic::localescape: { 6937 MachineFunction &MF = DAG.getMachineFunction(); 6938 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo(); 6939 6940 // Directly emit some LOCAL_ESCAPE machine instrs. Label assignment emission 6941 // is the same on all targets. 6942 for (unsigned Idx = 0, E = I.arg_size(); Idx < E; ++Idx) { 6943 Value *Arg = I.getArgOperand(Idx)->stripPointerCasts(); 6944 if (isa<ConstantPointerNull>(Arg)) 6945 continue; // Skip null pointers. They represent a hole in index space. 6946 AllocaInst *Slot = cast<AllocaInst>(Arg); 6947 assert(FuncInfo.StaticAllocaMap.count(Slot) && 6948 "can only escape static allocas"); 6949 int FI = FuncInfo.StaticAllocaMap[Slot]; 6950 MCSymbol *FrameAllocSym = 6951 MF.getMMI().getContext().getOrCreateFrameAllocSymbol( 6952 GlobalValue::dropLLVMManglingEscape(MF.getName()), Idx); 6953 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, dl, 6954 TII->get(TargetOpcode::LOCAL_ESCAPE)) 6955 .addSym(FrameAllocSym) 6956 .addFrameIndex(FI); 6957 } 6958 6959 return; 6960 } 6961 6962 case Intrinsic::localrecover: { 6963 // i8* @llvm.localrecover(i8* %fn, i8* %fp, i32 %idx) 6964 MachineFunction &MF = DAG.getMachineFunction(); 6965 6966 // Get the symbol that defines the frame offset. 6967 auto *Fn = cast<Function>(I.getArgOperand(0)->stripPointerCasts()); 6968 auto *Idx = cast<ConstantInt>(I.getArgOperand(2)); 6969 unsigned IdxVal = 6970 unsigned(Idx->getLimitedValue(std::numeric_limits<int>::max())); 6971 MCSymbol *FrameAllocSym = 6972 MF.getMMI().getContext().getOrCreateFrameAllocSymbol( 6973 GlobalValue::dropLLVMManglingEscape(Fn->getName()), IdxVal); 6974 6975 Value *FP = I.getArgOperand(1); 6976 SDValue FPVal = getValue(FP); 6977 EVT PtrVT = FPVal.getValueType(); 6978 6979 // Create a MCSymbol for the label to avoid any target lowering 6980 // that would make this PC relative. 6981 SDValue OffsetSym = DAG.getMCSymbol(FrameAllocSym, PtrVT); 6982 SDValue OffsetVal = 6983 DAG.getNode(ISD::LOCAL_RECOVER, sdl, PtrVT, OffsetSym); 6984 6985 // Add the offset to the FP. 6986 SDValue Add = DAG.getMemBasePlusOffset(FPVal, OffsetVal, sdl); 6987 setValue(&I, Add); 6988 6989 return; 6990 } 6991 6992 case Intrinsic::eh_exceptionpointer: 6993 case Intrinsic::eh_exceptioncode: { 6994 // Get the exception pointer vreg, copy from it, and resize it to fit. 6995 const auto *CPI = cast<CatchPadInst>(I.getArgOperand(0)); 6996 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout()); 6997 const TargetRegisterClass *PtrRC = TLI.getRegClassFor(PtrVT); 6998 unsigned VReg = FuncInfo.getCatchPadExceptionPointerVReg(CPI, PtrRC); 6999 SDValue N = DAG.getCopyFromReg(DAG.getEntryNode(), sdl, VReg, PtrVT); 7000 if (Intrinsic == Intrinsic::eh_exceptioncode) 7001 N = DAG.getZExtOrTrunc(N, sdl, MVT::i32); 7002 setValue(&I, N); 7003 return; 7004 } 7005 case Intrinsic::xray_customevent: { 7006 // Here we want to make sure that the intrinsic behaves as if it has a 7007 // specific calling convention, and only for x86_64. 7008 // FIXME: Support other platforms later. 7009 const auto &Triple = DAG.getTarget().getTargetTriple(); 7010 if (Triple.getArch() != Triple::x86_64) 7011 return; 7012 7013 SmallVector<SDValue, 8> Ops; 7014 7015 // We want to say that we always want the arguments in registers. 7016 SDValue LogEntryVal = getValue(I.getArgOperand(0)); 7017 SDValue StrSizeVal = getValue(I.getArgOperand(1)); 7018 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 7019 SDValue Chain = getRoot(); 7020 Ops.push_back(LogEntryVal); 7021 Ops.push_back(StrSizeVal); 7022 Ops.push_back(Chain); 7023 7024 // We need to enforce the calling convention for the callsite, so that 7025 // argument ordering is enforced correctly, and that register allocation can 7026 // see that some registers may be assumed clobbered and have to preserve 7027 // them across calls to the intrinsic. 7028 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHABLE_EVENT_CALL, 7029 sdl, NodeTys, Ops); 7030 SDValue patchableNode = SDValue(MN, 0); 7031 DAG.setRoot(patchableNode); 7032 setValue(&I, patchableNode); 7033 return; 7034 } 7035 case Intrinsic::xray_typedevent: { 7036 // Here we want to make sure that the intrinsic behaves as if it has a 7037 // specific calling convention, and only for x86_64. 7038 // FIXME: Support other platforms later. 7039 const auto &Triple = DAG.getTarget().getTargetTriple(); 7040 if (Triple.getArch() != Triple::x86_64) 7041 return; 7042 7043 SmallVector<SDValue, 8> Ops; 7044 7045 // We want to say that we always want the arguments in registers. 7046 // It's unclear to me how manipulating the selection DAG here forces callers 7047 // to provide arguments in registers instead of on the stack. 7048 SDValue LogTypeId = getValue(I.getArgOperand(0)); 7049 SDValue LogEntryVal = getValue(I.getArgOperand(1)); 7050 SDValue StrSizeVal = getValue(I.getArgOperand(2)); 7051 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 7052 SDValue Chain = getRoot(); 7053 Ops.push_back(LogTypeId); 7054 Ops.push_back(LogEntryVal); 7055 Ops.push_back(StrSizeVal); 7056 Ops.push_back(Chain); 7057 7058 // We need to enforce the calling convention for the callsite, so that 7059 // argument ordering is enforced correctly, and that register allocation can 7060 // see that some registers may be assumed clobbered and have to preserve 7061 // them across calls to the intrinsic. 7062 MachineSDNode *MN = DAG.getMachineNode( 7063 TargetOpcode::PATCHABLE_TYPED_EVENT_CALL, sdl, NodeTys, Ops); 7064 SDValue patchableNode = SDValue(MN, 0); 7065 DAG.setRoot(patchableNode); 7066 setValue(&I, patchableNode); 7067 return; 7068 } 7069 case Intrinsic::experimental_deoptimize: 7070 LowerDeoptimizeCall(&I); 7071 return; 7072 case Intrinsic::experimental_stepvector: 7073 visitStepVector(I); 7074 return; 7075 case Intrinsic::vector_reduce_fadd: 7076 case Intrinsic::vector_reduce_fmul: 7077 case Intrinsic::vector_reduce_add: 7078 case Intrinsic::vector_reduce_mul: 7079 case Intrinsic::vector_reduce_and: 7080 case Intrinsic::vector_reduce_or: 7081 case Intrinsic::vector_reduce_xor: 7082 case Intrinsic::vector_reduce_smax: 7083 case Intrinsic::vector_reduce_smin: 7084 case Intrinsic::vector_reduce_umax: 7085 case Intrinsic::vector_reduce_umin: 7086 case Intrinsic::vector_reduce_fmax: 7087 case Intrinsic::vector_reduce_fmin: 7088 visitVectorReduce(I, Intrinsic); 7089 return; 7090 7091 case Intrinsic::icall_branch_funnel: { 7092 SmallVector<SDValue, 16> Ops; 7093 Ops.push_back(getValue(I.getArgOperand(0))); 7094 7095 int64_t Offset; 7096 auto *Base = dyn_cast<GlobalObject>(GetPointerBaseWithConstantOffset( 7097 I.getArgOperand(1), Offset, DAG.getDataLayout())); 7098 if (!Base) 7099 report_fatal_error( 7100 "llvm.icall.branch.funnel operand must be a GlobalValue"); 7101 Ops.push_back(DAG.getTargetGlobalAddress(Base, sdl, MVT::i64, 0)); 7102 7103 struct BranchFunnelTarget { 7104 int64_t Offset; 7105 SDValue Target; 7106 }; 7107 SmallVector<BranchFunnelTarget, 8> Targets; 7108 7109 for (unsigned Op = 1, N = I.arg_size(); Op != N; Op += 2) { 7110 auto *ElemBase = dyn_cast<GlobalObject>(GetPointerBaseWithConstantOffset( 7111 I.getArgOperand(Op), Offset, DAG.getDataLayout())); 7112 if (ElemBase != Base) 7113 report_fatal_error("all llvm.icall.branch.funnel operands must refer " 7114 "to the same GlobalValue"); 7115 7116 SDValue Val = getValue(I.getArgOperand(Op + 1)); 7117 auto *GA = dyn_cast<GlobalAddressSDNode>(Val); 7118 if (!GA) 7119 report_fatal_error( 7120 "llvm.icall.branch.funnel operand must be a GlobalValue"); 7121 Targets.push_back({Offset, DAG.getTargetGlobalAddress( 7122 GA->getGlobal(), sdl, Val.getValueType(), 7123 GA->getOffset())}); 7124 } 7125 llvm::sort(Targets, 7126 [](const BranchFunnelTarget &T1, const BranchFunnelTarget &T2) { 7127 return T1.Offset < T2.Offset; 7128 }); 7129 7130 for (auto &T : Targets) { 7131 Ops.push_back(DAG.getTargetConstant(T.Offset, sdl, MVT::i32)); 7132 Ops.push_back(T.Target); 7133 } 7134 7135 Ops.push_back(DAG.getRoot()); // Chain 7136 SDValue N(DAG.getMachineNode(TargetOpcode::ICALL_BRANCH_FUNNEL, sdl, 7137 MVT::Other, Ops), 7138 0); 7139 DAG.setRoot(N); 7140 setValue(&I, N); 7141 HasTailCall = true; 7142 return; 7143 } 7144 7145 case Intrinsic::wasm_landingpad_index: 7146 // Information this intrinsic contained has been transferred to 7147 // MachineFunction in SelectionDAGISel::PrepareEHLandingPad. We can safely 7148 // delete it now. 7149 return; 7150 7151 case Intrinsic::aarch64_settag: 7152 case Intrinsic::aarch64_settag_zero: { 7153 const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo(); 7154 bool ZeroMemory = Intrinsic == Intrinsic::aarch64_settag_zero; 7155 SDValue Val = TSI.EmitTargetCodeForSetTag( 7156 DAG, sdl, getRoot(), getValue(I.getArgOperand(0)), 7157 getValue(I.getArgOperand(1)), MachinePointerInfo(I.getArgOperand(0)), 7158 ZeroMemory); 7159 DAG.setRoot(Val); 7160 setValue(&I, Val); 7161 return; 7162 } 7163 case Intrinsic::ptrmask: { 7164 SDValue Ptr = getValue(I.getOperand(0)); 7165 SDValue Const = getValue(I.getOperand(1)); 7166 7167 EVT PtrVT = Ptr.getValueType(); 7168 setValue(&I, DAG.getNode(ISD::AND, sdl, PtrVT, Ptr, 7169 DAG.getZExtOrTrunc(Const, sdl, PtrVT))); 7170 return; 7171 } 7172 case Intrinsic::get_active_lane_mask: { 7173 EVT CCVT = TLI.getValueType(DAG.getDataLayout(), I.getType()); 7174 SDValue Index = getValue(I.getOperand(0)); 7175 EVT ElementVT = Index.getValueType(); 7176 7177 if (!TLI.shouldExpandGetActiveLaneMask(CCVT, ElementVT)) { 7178 visitTargetIntrinsic(I, Intrinsic); 7179 return; 7180 } 7181 7182 SDValue TripCount = getValue(I.getOperand(1)); 7183 auto VecTy = CCVT.changeVectorElementType(ElementVT); 7184 7185 SDValue VectorIndex, VectorTripCount; 7186 if (VecTy.isScalableVector()) { 7187 VectorIndex = DAG.getSplatVector(VecTy, sdl, Index); 7188 VectorTripCount = DAG.getSplatVector(VecTy, sdl, TripCount); 7189 } else { 7190 VectorIndex = DAG.getSplatBuildVector(VecTy, sdl, Index); 7191 VectorTripCount = DAG.getSplatBuildVector(VecTy, sdl, TripCount); 7192 } 7193 SDValue VectorStep = DAG.getStepVector(sdl, VecTy); 7194 SDValue VectorInduction = DAG.getNode( 7195 ISD::UADDSAT, sdl, VecTy, VectorIndex, VectorStep); 7196 SDValue SetCC = DAG.getSetCC(sdl, CCVT, VectorInduction, 7197 VectorTripCount, ISD::CondCode::SETULT); 7198 setValue(&I, SetCC); 7199 return; 7200 } 7201 case Intrinsic::vector_insert: { 7202 SDValue Vec = getValue(I.getOperand(0)); 7203 SDValue SubVec = getValue(I.getOperand(1)); 7204 SDValue Index = getValue(I.getOperand(2)); 7205 7206 // The intrinsic's index type is i64, but the SDNode requires an index type 7207 // suitable for the target. Convert the index as required. 7208 MVT VectorIdxTy = TLI.getVectorIdxTy(DAG.getDataLayout()); 7209 if (Index.getValueType() != VectorIdxTy) 7210 Index = DAG.getVectorIdxConstant( 7211 cast<ConstantSDNode>(Index)->getZExtValue(), sdl); 7212 7213 EVT ResultVT = TLI.getValueType(DAG.getDataLayout(), I.getType()); 7214 setValue(&I, DAG.getNode(ISD::INSERT_SUBVECTOR, sdl, ResultVT, Vec, SubVec, 7215 Index)); 7216 return; 7217 } 7218 case Intrinsic::vector_extract: { 7219 SDValue Vec = getValue(I.getOperand(0)); 7220 SDValue Index = getValue(I.getOperand(1)); 7221 EVT ResultVT = TLI.getValueType(DAG.getDataLayout(), I.getType()); 7222 7223 // The intrinsic's index type is i64, but the SDNode requires an index type 7224 // suitable for the target. Convert the index as required. 7225 MVT VectorIdxTy = TLI.getVectorIdxTy(DAG.getDataLayout()); 7226 if (Index.getValueType() != VectorIdxTy) 7227 Index = DAG.getVectorIdxConstant( 7228 cast<ConstantSDNode>(Index)->getZExtValue(), sdl); 7229 7230 setValue(&I, 7231 DAG.getNode(ISD::EXTRACT_SUBVECTOR, sdl, ResultVT, Vec, Index)); 7232 return; 7233 } 7234 case Intrinsic::experimental_vector_reverse: 7235 visitVectorReverse(I); 7236 return; 7237 case Intrinsic::experimental_vector_splice: 7238 visitVectorSplice(I); 7239 return; 7240 } 7241 } 7242 7243 void SelectionDAGBuilder::visitConstrainedFPIntrinsic( 7244 const ConstrainedFPIntrinsic &FPI) { 7245 SDLoc sdl = getCurSDLoc(); 7246 7247 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 7248 SmallVector<EVT, 4> ValueVTs; 7249 ComputeValueVTs(TLI, DAG.getDataLayout(), FPI.getType(), ValueVTs); 7250 ValueVTs.push_back(MVT::Other); // Out chain 7251 7252 // We do not need to serialize constrained FP intrinsics against 7253 // each other or against (nonvolatile) loads, so they can be 7254 // chained like loads. 7255 SDValue Chain = DAG.getRoot(); 7256 SmallVector<SDValue, 4> Opers; 7257 Opers.push_back(Chain); 7258 if (FPI.isUnaryOp()) { 7259 Opers.push_back(getValue(FPI.getArgOperand(0))); 7260 } else if (FPI.isTernaryOp()) { 7261 Opers.push_back(getValue(FPI.getArgOperand(0))); 7262 Opers.push_back(getValue(FPI.getArgOperand(1))); 7263 Opers.push_back(getValue(FPI.getArgOperand(2))); 7264 } else { 7265 Opers.push_back(getValue(FPI.getArgOperand(0))); 7266 Opers.push_back(getValue(FPI.getArgOperand(1))); 7267 } 7268 7269 auto pushOutChain = [this](SDValue Result, fp::ExceptionBehavior EB) { 7270 assert(Result.getNode()->getNumValues() == 2); 7271 7272 // Push node to the appropriate list so that future instructions can be 7273 // chained up correctly. 7274 SDValue OutChain = Result.getValue(1); 7275 switch (EB) { 7276 case fp::ExceptionBehavior::ebIgnore: 7277 // The only reason why ebIgnore nodes still need to be chained is that 7278 // they might depend on the current rounding mode, and therefore must 7279 // not be moved across instruction that may change that mode. 7280 LLVM_FALLTHROUGH; 7281 case fp::ExceptionBehavior::ebMayTrap: 7282 // These must not be moved across calls or instructions that may change 7283 // floating-point exception masks. 7284 PendingConstrainedFP.push_back(OutChain); 7285 break; 7286 case fp::ExceptionBehavior::ebStrict: 7287 // These must not be moved across calls or instructions that may change 7288 // floating-point exception masks or read floating-point exception flags. 7289 // In addition, they cannot be optimized out even if unused. 7290 PendingConstrainedFPStrict.push_back(OutChain); 7291 break; 7292 } 7293 }; 7294 7295 SDVTList VTs = DAG.getVTList(ValueVTs); 7296 fp::ExceptionBehavior EB = *FPI.getExceptionBehavior(); 7297 7298 SDNodeFlags Flags; 7299 if (EB == fp::ExceptionBehavior::ebIgnore) 7300 Flags.setNoFPExcept(true); 7301 7302 if (auto *FPOp = dyn_cast<FPMathOperator>(&FPI)) 7303 Flags.copyFMF(*FPOp); 7304 7305 unsigned Opcode; 7306 switch (FPI.getIntrinsicID()) { 7307 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 7308 #define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \ 7309 case Intrinsic::INTRINSIC: \ 7310 Opcode = ISD::STRICT_##DAGN; \ 7311 break; 7312 #include "llvm/IR/ConstrainedOps.def" 7313 case Intrinsic::experimental_constrained_fmuladd: { 7314 Opcode = ISD::STRICT_FMA; 7315 // Break fmuladd into fmul and fadd. 7316 if (TM.Options.AllowFPOpFusion == FPOpFusion::Strict || 7317 !TLI.isFMAFasterThanFMulAndFAdd(DAG.getMachineFunction(), 7318 ValueVTs[0])) { 7319 Opers.pop_back(); 7320 SDValue Mul = DAG.getNode(ISD::STRICT_FMUL, sdl, VTs, Opers, Flags); 7321 pushOutChain(Mul, EB); 7322 Opcode = ISD::STRICT_FADD; 7323 Opers.clear(); 7324 Opers.push_back(Mul.getValue(1)); 7325 Opers.push_back(Mul.getValue(0)); 7326 Opers.push_back(getValue(FPI.getArgOperand(2))); 7327 } 7328 break; 7329 } 7330 } 7331 7332 // A few strict DAG nodes carry additional operands that are not 7333 // set up by the default code above. 7334 switch (Opcode) { 7335 default: break; 7336 case ISD::STRICT_FP_ROUND: 7337 Opers.push_back( 7338 DAG.getTargetConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()))); 7339 break; 7340 case ISD::STRICT_FSETCC: 7341 case ISD::STRICT_FSETCCS: { 7342 auto *FPCmp = dyn_cast<ConstrainedFPCmpIntrinsic>(&FPI); 7343 ISD::CondCode Condition = getFCmpCondCode(FPCmp->getPredicate()); 7344 if (TM.Options.NoNaNsFPMath) 7345 Condition = getFCmpCodeWithoutNaN(Condition); 7346 Opers.push_back(DAG.getCondCode(Condition)); 7347 break; 7348 } 7349 } 7350 7351 SDValue Result = DAG.getNode(Opcode, sdl, VTs, Opers, Flags); 7352 pushOutChain(Result, EB); 7353 7354 SDValue FPResult = Result.getValue(0); 7355 setValue(&FPI, FPResult); 7356 } 7357 7358 static unsigned getISDForVPIntrinsic(const VPIntrinsic &VPIntrin) { 7359 Optional<unsigned> ResOPC; 7360 switch (VPIntrin.getIntrinsicID()) { 7361 #define HELPER_MAP_VPID_TO_VPSD(VPID, VPSD) \ 7362 case Intrinsic::VPID: \ 7363 ResOPC = ISD::VPSD; \ 7364 break; 7365 #include "llvm/IR/VPIntrinsics.def" 7366 } 7367 7368 if (!ResOPC) 7369 llvm_unreachable( 7370 "Inconsistency: no SDNode available for this VPIntrinsic!"); 7371 7372 if (*ResOPC == ISD::VP_REDUCE_SEQ_FADD || 7373 *ResOPC == ISD::VP_REDUCE_SEQ_FMUL) { 7374 if (VPIntrin.getFastMathFlags().allowReassoc()) 7375 return *ResOPC == ISD::VP_REDUCE_SEQ_FADD ? ISD::VP_REDUCE_FADD 7376 : ISD::VP_REDUCE_FMUL; 7377 } 7378 7379 return *ResOPC; 7380 } 7381 7382 void SelectionDAGBuilder::visitVPLoadGather(const VPIntrinsic &VPIntrin, EVT VT, 7383 SmallVector<SDValue, 7> &OpValues, 7384 bool IsGather) { 7385 SDLoc DL = getCurSDLoc(); 7386 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 7387 Value *PtrOperand = VPIntrin.getArgOperand(0); 7388 MaybeAlign Alignment = VPIntrin.getPointerAlignment(); 7389 AAMDNodes AAInfo = VPIntrin.getAAMetadata(); 7390 const MDNode *Ranges = VPIntrin.getMetadata(LLVMContext::MD_range); 7391 SDValue LD; 7392 bool AddToChain = true; 7393 if (!IsGather) { 7394 // Do not serialize variable-length loads of constant memory with 7395 // anything. 7396 if (!Alignment) 7397 Alignment = DAG.getEVTAlign(VT); 7398 MemoryLocation ML = MemoryLocation::getAfter(PtrOperand, AAInfo); 7399 AddToChain = !AA || !AA->pointsToConstantMemory(ML); 7400 SDValue InChain = AddToChain ? DAG.getRoot() : DAG.getEntryNode(); 7401 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand( 7402 MachinePointerInfo(PtrOperand), MachineMemOperand::MOLoad, 7403 MemoryLocation::UnknownSize, *Alignment, AAInfo, Ranges); 7404 LD = DAG.getLoadVP(VT, DL, InChain, OpValues[0], OpValues[1], OpValues[2], 7405 MMO, false /*IsExpanding */); 7406 } else { 7407 if (!Alignment) 7408 Alignment = DAG.getEVTAlign(VT.getScalarType()); 7409 unsigned AS = 7410 PtrOperand->getType()->getScalarType()->getPointerAddressSpace(); 7411 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand( 7412 MachinePointerInfo(AS), MachineMemOperand::MOLoad, 7413 MemoryLocation::UnknownSize, *Alignment, AAInfo, Ranges); 7414 SDValue Base, Index, Scale; 7415 ISD::MemIndexType IndexType; 7416 bool UniformBase = getUniformBase(PtrOperand, Base, Index, IndexType, Scale, 7417 this, VPIntrin.getParent(), 7418 VT.getScalarStoreSize()); 7419 if (!UniformBase) { 7420 Base = DAG.getConstant(0, DL, TLI.getPointerTy(DAG.getDataLayout())); 7421 Index = getValue(PtrOperand); 7422 IndexType = ISD::SIGNED_SCALED; 7423 Scale = 7424 DAG.getTargetConstant(1, DL, TLI.getPointerTy(DAG.getDataLayout())); 7425 } 7426 EVT IdxVT = Index.getValueType(); 7427 EVT EltTy = IdxVT.getVectorElementType(); 7428 if (TLI.shouldExtendGSIndex(IdxVT, EltTy)) { 7429 EVT NewIdxVT = IdxVT.changeVectorElementType(EltTy); 7430 Index = DAG.getNode(ISD::SIGN_EXTEND, DL, NewIdxVT, Index); 7431 } 7432 LD = DAG.getGatherVP( 7433 DAG.getVTList(VT, MVT::Other), VT, DL, 7434 {DAG.getRoot(), Base, Index, Scale, OpValues[1], OpValues[2]}, MMO, 7435 IndexType); 7436 } 7437 if (AddToChain) 7438 PendingLoads.push_back(LD.getValue(1)); 7439 setValue(&VPIntrin, LD); 7440 } 7441 7442 void SelectionDAGBuilder::visitVPStoreScatter(const VPIntrinsic &VPIntrin, 7443 SmallVector<SDValue, 7> &OpValues, 7444 bool IsScatter) { 7445 SDLoc DL = getCurSDLoc(); 7446 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 7447 Value *PtrOperand = VPIntrin.getArgOperand(1); 7448 EVT VT = OpValues[0].getValueType(); 7449 MaybeAlign Alignment = VPIntrin.getPointerAlignment(); 7450 AAMDNodes AAInfo = VPIntrin.getAAMetadata(); 7451 SDValue ST; 7452 if (!IsScatter) { 7453 if (!Alignment) 7454 Alignment = DAG.getEVTAlign(VT); 7455 SDValue Ptr = OpValues[1]; 7456 SDValue Offset = DAG.getUNDEF(Ptr.getValueType()); 7457 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand( 7458 MachinePointerInfo(PtrOperand), MachineMemOperand::MOStore, 7459 MemoryLocation::UnknownSize, *Alignment, AAInfo); 7460 ST = DAG.getStoreVP(getMemoryRoot(), DL, OpValues[0], Ptr, Offset, 7461 OpValues[2], OpValues[3], VT, MMO, ISD::UNINDEXED, 7462 /* IsTruncating */ false, /*IsCompressing*/ false); 7463 } else { 7464 if (!Alignment) 7465 Alignment = DAG.getEVTAlign(VT.getScalarType()); 7466 unsigned AS = 7467 PtrOperand->getType()->getScalarType()->getPointerAddressSpace(); 7468 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand( 7469 MachinePointerInfo(AS), MachineMemOperand::MOStore, 7470 MemoryLocation::UnknownSize, *Alignment, AAInfo); 7471 SDValue Base, Index, Scale; 7472 ISD::MemIndexType IndexType; 7473 bool UniformBase = getUniformBase(PtrOperand, Base, Index, IndexType, Scale, 7474 this, VPIntrin.getParent(), 7475 VT.getScalarStoreSize()); 7476 if (!UniformBase) { 7477 Base = DAG.getConstant(0, DL, TLI.getPointerTy(DAG.getDataLayout())); 7478 Index = getValue(PtrOperand); 7479 IndexType = ISD::SIGNED_SCALED; 7480 Scale = 7481 DAG.getTargetConstant(1, DL, TLI.getPointerTy(DAG.getDataLayout())); 7482 } 7483 EVT IdxVT = Index.getValueType(); 7484 EVT EltTy = IdxVT.getVectorElementType(); 7485 if (TLI.shouldExtendGSIndex(IdxVT, EltTy)) { 7486 EVT NewIdxVT = IdxVT.changeVectorElementType(EltTy); 7487 Index = DAG.getNode(ISD::SIGN_EXTEND, DL, NewIdxVT, Index); 7488 } 7489 ST = DAG.getScatterVP(DAG.getVTList(MVT::Other), VT, DL, 7490 {getMemoryRoot(), OpValues[0], Base, Index, Scale, 7491 OpValues[2], OpValues[3]}, 7492 MMO, IndexType); 7493 } 7494 DAG.setRoot(ST); 7495 setValue(&VPIntrin, ST); 7496 } 7497 7498 void SelectionDAGBuilder::visitVPStridedLoad( 7499 const VPIntrinsic &VPIntrin, EVT VT, SmallVectorImpl<SDValue> &OpValues) { 7500 SDLoc DL = getCurSDLoc(); 7501 Value *PtrOperand = VPIntrin.getArgOperand(0); 7502 MaybeAlign Alignment = VPIntrin.getPointerAlignment(); 7503 if (!Alignment) 7504 Alignment = DAG.getEVTAlign(VT.getScalarType()); 7505 AAMDNodes AAInfo = VPIntrin.getAAMetadata(); 7506 const MDNode *Ranges = VPIntrin.getMetadata(LLVMContext::MD_range); 7507 MemoryLocation ML = MemoryLocation::getAfter(PtrOperand, AAInfo); 7508 bool AddToChain = !AA || !AA->pointsToConstantMemory(ML); 7509 SDValue InChain = AddToChain ? DAG.getRoot() : DAG.getEntryNode(); 7510 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand( 7511 MachinePointerInfo(PtrOperand), MachineMemOperand::MOLoad, 7512 MemoryLocation::UnknownSize, *Alignment, AAInfo, Ranges); 7513 7514 SDValue LD = DAG.getStridedLoadVP(VT, DL, InChain, OpValues[0], OpValues[1], 7515 OpValues[2], OpValues[3], MMO, 7516 false /*IsExpanding*/); 7517 7518 if (AddToChain) 7519 PendingLoads.push_back(LD.getValue(1)); 7520 setValue(&VPIntrin, LD); 7521 } 7522 7523 void SelectionDAGBuilder::visitVPStridedStore( 7524 const VPIntrinsic &VPIntrin, SmallVectorImpl<SDValue> &OpValues) { 7525 SDLoc DL = getCurSDLoc(); 7526 Value *PtrOperand = VPIntrin.getArgOperand(1); 7527 EVT VT = OpValues[0].getValueType(); 7528 MaybeAlign Alignment = VPIntrin.getPointerAlignment(); 7529 if (!Alignment) 7530 Alignment = DAG.getEVTAlign(VT.getScalarType()); 7531 AAMDNodes AAInfo = VPIntrin.getAAMetadata(); 7532 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand( 7533 MachinePointerInfo(PtrOperand), MachineMemOperand::MOStore, 7534 MemoryLocation::UnknownSize, *Alignment, AAInfo); 7535 7536 SDValue ST = DAG.getStridedStoreVP( 7537 getMemoryRoot(), DL, OpValues[0], OpValues[1], 7538 DAG.getUNDEF(OpValues[1].getValueType()), OpValues[2], OpValues[3], 7539 OpValues[4], VT, MMO, ISD::UNINDEXED, /*IsTruncating*/ false, 7540 /*IsCompressing*/ false); 7541 7542 DAG.setRoot(ST); 7543 setValue(&VPIntrin, ST); 7544 } 7545 7546 void SelectionDAGBuilder::visitVPCmp(const VPCmpIntrinsic &VPIntrin) { 7547 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 7548 SDLoc DL = getCurSDLoc(); 7549 7550 ISD::CondCode Condition; 7551 CmpInst::Predicate CondCode = VPIntrin.getPredicate(); 7552 bool IsFP = VPIntrin.getOperand(0)->getType()->isFPOrFPVectorTy(); 7553 if (IsFP) { 7554 // FIXME: Regular fcmps are FPMathOperators which may have fast-math (nnan) 7555 // flags, but calls that don't return floating-point types can't be 7556 // FPMathOperators, like vp.fcmp. This affects constrained fcmp too. 7557 Condition = getFCmpCondCode(CondCode); 7558 if (TM.Options.NoNaNsFPMath) 7559 Condition = getFCmpCodeWithoutNaN(Condition); 7560 } else { 7561 Condition = getICmpCondCode(CondCode); 7562 } 7563 7564 SDValue Op1 = getValue(VPIntrin.getOperand(0)); 7565 SDValue Op2 = getValue(VPIntrin.getOperand(1)); 7566 // #2 is the condition code 7567 SDValue MaskOp = getValue(VPIntrin.getOperand(3)); 7568 SDValue EVL = getValue(VPIntrin.getOperand(4)); 7569 MVT EVLParamVT = TLI.getVPExplicitVectorLengthTy(); 7570 assert(EVLParamVT.isScalarInteger() && EVLParamVT.bitsGE(MVT::i32) && 7571 "Unexpected target EVL type"); 7572 EVL = DAG.getNode(ISD::ZERO_EXTEND, DL, EVLParamVT, EVL); 7573 7574 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), 7575 VPIntrin.getType()); 7576 setValue(&VPIntrin, 7577 DAG.getSetCCVP(DL, DestVT, Op1, Op2, Condition, MaskOp, EVL)); 7578 } 7579 7580 void SelectionDAGBuilder::visitVectorPredicationIntrinsic( 7581 const VPIntrinsic &VPIntrin) { 7582 SDLoc DL = getCurSDLoc(); 7583 unsigned Opcode = getISDForVPIntrinsic(VPIntrin); 7584 7585 auto IID = VPIntrin.getIntrinsicID(); 7586 7587 if (const auto *CmpI = dyn_cast<VPCmpIntrinsic>(&VPIntrin)) 7588 return visitVPCmp(*CmpI); 7589 7590 SmallVector<EVT, 4> ValueVTs; 7591 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 7592 ComputeValueVTs(TLI, DAG.getDataLayout(), VPIntrin.getType(), ValueVTs); 7593 SDVTList VTs = DAG.getVTList(ValueVTs); 7594 7595 auto EVLParamPos = VPIntrinsic::getVectorLengthParamPos(IID); 7596 7597 MVT EVLParamVT = TLI.getVPExplicitVectorLengthTy(); 7598 assert(EVLParamVT.isScalarInteger() && EVLParamVT.bitsGE(MVT::i32) && 7599 "Unexpected target EVL type"); 7600 7601 // Request operands. 7602 SmallVector<SDValue, 7> OpValues; 7603 for (unsigned I = 0; I < VPIntrin.arg_size(); ++I) { 7604 auto Op = getValue(VPIntrin.getArgOperand(I)); 7605 if (I == EVLParamPos) 7606 Op = DAG.getNode(ISD::ZERO_EXTEND, DL, EVLParamVT, Op); 7607 OpValues.push_back(Op); 7608 } 7609 7610 switch (Opcode) { 7611 default: { 7612 SDNodeFlags SDFlags; 7613 if (auto *FPMO = dyn_cast<FPMathOperator>(&VPIntrin)) 7614 SDFlags.copyFMF(*FPMO); 7615 SDValue Result = DAG.getNode(Opcode, DL, VTs, OpValues, SDFlags); 7616 setValue(&VPIntrin, Result); 7617 break; 7618 } 7619 case ISD::VP_LOAD: 7620 case ISD::VP_GATHER: 7621 visitVPLoadGather(VPIntrin, ValueVTs[0], OpValues, 7622 Opcode == ISD::VP_GATHER); 7623 break; 7624 case ISD::EXPERIMENTAL_VP_STRIDED_LOAD: 7625 visitVPStridedLoad(VPIntrin, ValueVTs[0], OpValues); 7626 break; 7627 case ISD::VP_STORE: 7628 case ISD::VP_SCATTER: 7629 visitVPStoreScatter(VPIntrin, OpValues, Opcode == ISD::VP_SCATTER); 7630 break; 7631 case ISD::EXPERIMENTAL_VP_STRIDED_STORE: 7632 visitVPStridedStore(VPIntrin, OpValues); 7633 break; 7634 } 7635 } 7636 7637 SDValue SelectionDAGBuilder::lowerStartEH(SDValue Chain, 7638 const BasicBlock *EHPadBB, 7639 MCSymbol *&BeginLabel) { 7640 MachineFunction &MF = DAG.getMachineFunction(); 7641 MachineModuleInfo &MMI = MF.getMMI(); 7642 7643 // Insert a label before the invoke call to mark the try range. This can be 7644 // used to detect deletion of the invoke via the MachineModuleInfo. 7645 BeginLabel = MMI.getContext().createTempSymbol(); 7646 7647 // For SjLj, keep track of which landing pads go with which invokes 7648 // so as to maintain the ordering of pads in the LSDA. 7649 unsigned CallSiteIndex = MMI.getCurrentCallSite(); 7650 if (CallSiteIndex) { 7651 MF.setCallSiteBeginLabel(BeginLabel, CallSiteIndex); 7652 LPadToCallSiteMap[FuncInfo.MBBMap[EHPadBB]].push_back(CallSiteIndex); 7653 7654 // Now that the call site is handled, stop tracking it. 7655 MMI.setCurrentCallSite(0); 7656 } 7657 7658 return DAG.getEHLabel(getCurSDLoc(), Chain, BeginLabel); 7659 } 7660 7661 SDValue SelectionDAGBuilder::lowerEndEH(SDValue Chain, const InvokeInst *II, 7662 const BasicBlock *EHPadBB, 7663 MCSymbol *BeginLabel) { 7664 assert(BeginLabel && "BeginLabel should've been set"); 7665 7666 MachineFunction &MF = DAG.getMachineFunction(); 7667 MachineModuleInfo &MMI = MF.getMMI(); 7668 7669 // Insert a label at the end of the invoke call to mark the try range. This 7670 // can be used to detect deletion of the invoke via the MachineModuleInfo. 7671 MCSymbol *EndLabel = MMI.getContext().createTempSymbol(); 7672 Chain = DAG.getEHLabel(getCurSDLoc(), Chain, EndLabel); 7673 7674 // Inform MachineModuleInfo of range. 7675 auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn()); 7676 // There is a platform (e.g. wasm) that uses funclet style IR but does not 7677 // actually use outlined funclets and their LSDA info style. 7678 if (MF.hasEHFunclets() && isFuncletEHPersonality(Pers)) { 7679 assert(II && "II should've been set"); 7680 WinEHFuncInfo *EHInfo = MF.getWinEHFuncInfo(); 7681 EHInfo->addIPToStateRange(II, BeginLabel, EndLabel); 7682 } else if (!isScopedEHPersonality(Pers)) { 7683 assert(EHPadBB); 7684 MF.addInvoke(FuncInfo.MBBMap[EHPadBB], BeginLabel, EndLabel); 7685 } 7686 7687 return Chain; 7688 } 7689 7690 std::pair<SDValue, SDValue> 7691 SelectionDAGBuilder::lowerInvokable(TargetLowering::CallLoweringInfo &CLI, 7692 const BasicBlock *EHPadBB) { 7693 MCSymbol *BeginLabel = nullptr; 7694 7695 if (EHPadBB) { 7696 // Both PendingLoads and PendingExports must be flushed here; 7697 // this call might not return. 7698 (void)getRoot(); 7699 DAG.setRoot(lowerStartEH(getControlRoot(), EHPadBB, BeginLabel)); 7700 CLI.setChain(getRoot()); 7701 } 7702 7703 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 7704 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI); 7705 7706 assert((CLI.IsTailCall || Result.second.getNode()) && 7707 "Non-null chain expected with non-tail call!"); 7708 assert((Result.second.getNode() || !Result.first.getNode()) && 7709 "Null value expected with tail call!"); 7710 7711 if (!Result.second.getNode()) { 7712 // As a special case, a null chain means that a tail call has been emitted 7713 // and the DAG root is already updated. 7714 HasTailCall = true; 7715 7716 // Since there's no actual continuation from this block, nothing can be 7717 // relying on us setting vregs for them. 7718 PendingExports.clear(); 7719 } else { 7720 DAG.setRoot(Result.second); 7721 } 7722 7723 if (EHPadBB) { 7724 DAG.setRoot(lowerEndEH(getRoot(), cast_or_null<InvokeInst>(CLI.CB), EHPadBB, 7725 BeginLabel)); 7726 } 7727 7728 return Result; 7729 } 7730 7731 void SelectionDAGBuilder::LowerCallTo(const CallBase &CB, SDValue Callee, 7732 bool isTailCall, 7733 bool isMustTailCall, 7734 const BasicBlock *EHPadBB) { 7735 auto &DL = DAG.getDataLayout(); 7736 FunctionType *FTy = CB.getFunctionType(); 7737 Type *RetTy = CB.getType(); 7738 7739 TargetLowering::ArgListTy Args; 7740 Args.reserve(CB.arg_size()); 7741 7742 const Value *SwiftErrorVal = nullptr; 7743 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 7744 7745 if (isTailCall) { 7746 // Avoid emitting tail calls in functions with the disable-tail-calls 7747 // attribute. 7748 auto *Caller = CB.getParent()->getParent(); 7749 if (Caller->getFnAttribute("disable-tail-calls").getValueAsString() == 7750 "true" && !isMustTailCall) 7751 isTailCall = false; 7752 7753 // We can't tail call inside a function with a swifterror argument. Lowering 7754 // does not support this yet. It would have to move into the swifterror 7755 // register before the call. 7756 if (TLI.supportSwiftError() && 7757 Caller->getAttributes().hasAttrSomewhere(Attribute::SwiftError)) 7758 isTailCall = false; 7759 } 7760 7761 for (auto I = CB.arg_begin(), E = CB.arg_end(); I != E; ++I) { 7762 TargetLowering::ArgListEntry Entry; 7763 const Value *V = *I; 7764 7765 // Skip empty types 7766 if (V->getType()->isEmptyTy()) 7767 continue; 7768 7769 SDValue ArgNode = getValue(V); 7770 Entry.Node = ArgNode; Entry.Ty = V->getType(); 7771 7772 Entry.setAttributes(&CB, I - CB.arg_begin()); 7773 7774 // Use swifterror virtual register as input to the call. 7775 if (Entry.IsSwiftError && TLI.supportSwiftError()) { 7776 SwiftErrorVal = V; 7777 // We find the virtual register for the actual swifterror argument. 7778 // Instead of using the Value, we use the virtual register instead. 7779 Entry.Node = 7780 DAG.getRegister(SwiftError.getOrCreateVRegUseAt(&CB, FuncInfo.MBB, V), 7781 EVT(TLI.getPointerTy(DL))); 7782 } 7783 7784 Args.push_back(Entry); 7785 7786 // If we have an explicit sret argument that is an Instruction, (i.e., it 7787 // might point to function-local memory), we can't meaningfully tail-call. 7788 if (Entry.IsSRet && isa<Instruction>(V)) 7789 isTailCall = false; 7790 } 7791 7792 // If call site has a cfguardtarget operand bundle, create and add an 7793 // additional ArgListEntry. 7794 if (auto Bundle = CB.getOperandBundle(LLVMContext::OB_cfguardtarget)) { 7795 TargetLowering::ArgListEntry Entry; 7796 Value *V = Bundle->Inputs[0]; 7797 SDValue ArgNode = getValue(V); 7798 Entry.Node = ArgNode; 7799 Entry.Ty = V->getType(); 7800 Entry.IsCFGuardTarget = true; 7801 Args.push_back(Entry); 7802 } 7803 7804 // Check if target-independent constraints permit a tail call here. 7805 // Target-dependent constraints are checked within TLI->LowerCallTo. 7806 if (isTailCall && !isInTailCallPosition(CB, DAG.getTarget())) 7807 isTailCall = false; 7808 7809 // Disable tail calls if there is an swifterror argument. Targets have not 7810 // been updated to support tail calls. 7811 if (TLI.supportSwiftError() && SwiftErrorVal) 7812 isTailCall = false; 7813 7814 TargetLowering::CallLoweringInfo CLI(DAG); 7815 CLI.setDebugLoc(getCurSDLoc()) 7816 .setChain(getRoot()) 7817 .setCallee(RetTy, FTy, Callee, std::move(Args), CB) 7818 .setTailCall(isTailCall) 7819 .setConvergent(CB.isConvergent()) 7820 .setIsPreallocated( 7821 CB.countOperandBundlesOfType(LLVMContext::OB_preallocated) != 0); 7822 std::pair<SDValue, SDValue> Result = lowerInvokable(CLI, EHPadBB); 7823 7824 if (Result.first.getNode()) { 7825 Result.first = lowerRangeToAssertZExt(DAG, CB, Result.first); 7826 setValue(&CB, Result.first); 7827 } 7828 7829 // The last element of CLI.InVals has the SDValue for swifterror return. 7830 // Here we copy it to a virtual register and update SwiftErrorMap for 7831 // book-keeping. 7832 if (SwiftErrorVal && TLI.supportSwiftError()) { 7833 // Get the last element of InVals. 7834 SDValue Src = CLI.InVals.back(); 7835 Register VReg = 7836 SwiftError.getOrCreateVRegDefAt(&CB, FuncInfo.MBB, SwiftErrorVal); 7837 SDValue CopyNode = CLI.DAG.getCopyToReg(Result.second, CLI.DL, VReg, Src); 7838 DAG.setRoot(CopyNode); 7839 } 7840 } 7841 7842 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT, 7843 SelectionDAGBuilder &Builder) { 7844 // Check to see if this load can be trivially constant folded, e.g. if the 7845 // input is from a string literal. 7846 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) { 7847 // Cast pointer to the type we really want to load. 7848 Type *LoadTy = 7849 Type::getIntNTy(PtrVal->getContext(), LoadVT.getScalarSizeInBits()); 7850 if (LoadVT.isVector()) 7851 LoadTy = FixedVectorType::get(LoadTy, LoadVT.getVectorNumElements()); 7852 7853 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput), 7854 PointerType::getUnqual(LoadTy)); 7855 7856 if (const Constant *LoadCst = 7857 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput), 7858 LoadTy, Builder.DAG.getDataLayout())) 7859 return Builder.getValue(LoadCst); 7860 } 7861 7862 // Otherwise, we have to emit the load. If the pointer is to unfoldable but 7863 // still constant memory, the input chain can be the entry node. 7864 SDValue Root; 7865 bool ConstantMemory = false; 7866 7867 // Do not serialize (non-volatile) loads of constant memory with anything. 7868 if (Builder.AA && Builder.AA->pointsToConstantMemory(PtrVal)) { 7869 Root = Builder.DAG.getEntryNode(); 7870 ConstantMemory = true; 7871 } else { 7872 // Do not serialize non-volatile loads against each other. 7873 Root = Builder.DAG.getRoot(); 7874 } 7875 7876 SDValue Ptr = Builder.getValue(PtrVal); 7877 SDValue LoadVal = 7878 Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root, Ptr, 7879 MachinePointerInfo(PtrVal), Align(1)); 7880 7881 if (!ConstantMemory) 7882 Builder.PendingLoads.push_back(LoadVal.getValue(1)); 7883 return LoadVal; 7884 } 7885 7886 /// Record the value for an instruction that produces an integer result, 7887 /// converting the type where necessary. 7888 void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I, 7889 SDValue Value, 7890 bool IsSigned) { 7891 EVT VT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), 7892 I.getType(), true); 7893 if (IsSigned) 7894 Value = DAG.getSExtOrTrunc(Value, getCurSDLoc(), VT); 7895 else 7896 Value = DAG.getZExtOrTrunc(Value, getCurSDLoc(), VT); 7897 setValue(&I, Value); 7898 } 7899 7900 /// See if we can lower a memcmp/bcmp call into an optimized form. If so, return 7901 /// true and lower it. Otherwise return false, and it will be lowered like a 7902 /// normal call. 7903 /// The caller already checked that \p I calls the appropriate LibFunc with a 7904 /// correct prototype. 7905 bool SelectionDAGBuilder::visitMemCmpBCmpCall(const CallInst &I) { 7906 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1); 7907 const Value *Size = I.getArgOperand(2); 7908 const ConstantSDNode *CSize = dyn_cast<ConstantSDNode>(getValue(Size)); 7909 if (CSize && CSize->getZExtValue() == 0) { 7910 EVT CallVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), 7911 I.getType(), true); 7912 setValue(&I, DAG.getConstant(0, getCurSDLoc(), CallVT)); 7913 return true; 7914 } 7915 7916 const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo(); 7917 std::pair<SDValue, SDValue> Res = TSI.EmitTargetCodeForMemcmp( 7918 DAG, getCurSDLoc(), DAG.getRoot(), getValue(LHS), getValue(RHS), 7919 getValue(Size), MachinePointerInfo(LHS), MachinePointerInfo(RHS)); 7920 if (Res.first.getNode()) { 7921 processIntegerCallValue(I, Res.first, true); 7922 PendingLoads.push_back(Res.second); 7923 return true; 7924 } 7925 7926 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0 7927 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0 7928 if (!CSize || !isOnlyUsedInZeroEqualityComparison(&I)) 7929 return false; 7930 7931 // If the target has a fast compare for the given size, it will return a 7932 // preferred load type for that size. Require that the load VT is legal and 7933 // that the target supports unaligned loads of that type. Otherwise, return 7934 // INVALID. 7935 auto hasFastLoadsAndCompare = [&](unsigned NumBits) { 7936 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 7937 MVT LVT = TLI.hasFastEqualityCompare(NumBits); 7938 if (LVT != MVT::INVALID_SIMPLE_VALUE_TYPE) { 7939 // TODO: Handle 5 byte compare as 4-byte + 1 byte. 7940 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads. 7941 // TODO: Check alignment of src and dest ptrs. 7942 unsigned DstAS = LHS->getType()->getPointerAddressSpace(); 7943 unsigned SrcAS = RHS->getType()->getPointerAddressSpace(); 7944 if (!TLI.isTypeLegal(LVT) || 7945 !TLI.allowsMisalignedMemoryAccesses(LVT, SrcAS) || 7946 !TLI.allowsMisalignedMemoryAccesses(LVT, DstAS)) 7947 LVT = MVT::INVALID_SIMPLE_VALUE_TYPE; 7948 } 7949 7950 return LVT; 7951 }; 7952 7953 // This turns into unaligned loads. We only do this if the target natively 7954 // supports the MVT we'll be loading or if it is small enough (<= 4) that 7955 // we'll only produce a small number of byte loads. 7956 MVT LoadVT; 7957 unsigned NumBitsToCompare = CSize->getZExtValue() * 8; 7958 switch (NumBitsToCompare) { 7959 default: 7960 return false; 7961 case 16: 7962 LoadVT = MVT::i16; 7963 break; 7964 case 32: 7965 LoadVT = MVT::i32; 7966 break; 7967 case 64: 7968 case 128: 7969 case 256: 7970 LoadVT = hasFastLoadsAndCompare(NumBitsToCompare); 7971 break; 7972 } 7973 7974 if (LoadVT == MVT::INVALID_SIMPLE_VALUE_TYPE) 7975 return false; 7976 7977 SDValue LoadL = getMemCmpLoad(LHS, LoadVT, *this); 7978 SDValue LoadR = getMemCmpLoad(RHS, LoadVT, *this); 7979 7980 // Bitcast to a wide integer type if the loads are vectors. 7981 if (LoadVT.isVector()) { 7982 EVT CmpVT = EVT::getIntegerVT(LHS->getContext(), LoadVT.getSizeInBits()); 7983 LoadL = DAG.getBitcast(CmpVT, LoadL); 7984 LoadR = DAG.getBitcast(CmpVT, LoadR); 7985 } 7986 7987 SDValue Cmp = DAG.getSetCC(getCurSDLoc(), MVT::i1, LoadL, LoadR, ISD::SETNE); 7988 processIntegerCallValue(I, Cmp, false); 7989 return true; 7990 } 7991 7992 /// See if we can lower a memchr call into an optimized form. If so, return 7993 /// true and lower it. Otherwise return false, and it will be lowered like a 7994 /// normal call. 7995 /// The caller already checked that \p I calls the appropriate LibFunc with a 7996 /// correct prototype. 7997 bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) { 7998 const Value *Src = I.getArgOperand(0); 7999 const Value *Char = I.getArgOperand(1); 8000 const Value *Length = I.getArgOperand(2); 8001 8002 const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo(); 8003 std::pair<SDValue, SDValue> Res = 8004 TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(), 8005 getValue(Src), getValue(Char), getValue(Length), 8006 MachinePointerInfo(Src)); 8007 if (Res.first.getNode()) { 8008 setValue(&I, Res.first); 8009 PendingLoads.push_back(Res.second); 8010 return true; 8011 } 8012 8013 return false; 8014 } 8015 8016 /// See if we can lower a mempcpy call into an optimized form. If so, return 8017 /// true and lower it. Otherwise return false, and it will be lowered like a 8018 /// normal call. 8019 /// The caller already checked that \p I calls the appropriate LibFunc with a 8020 /// correct prototype. 8021 bool SelectionDAGBuilder::visitMemPCpyCall(const CallInst &I) { 8022 SDValue Dst = getValue(I.getArgOperand(0)); 8023 SDValue Src = getValue(I.getArgOperand(1)); 8024 SDValue Size = getValue(I.getArgOperand(2)); 8025 8026 Align DstAlign = DAG.InferPtrAlign(Dst).valueOrOne(); 8027 Align SrcAlign = DAG.InferPtrAlign(Src).valueOrOne(); 8028 // DAG::getMemcpy needs Alignment to be defined. 8029 Align Alignment = std::min(DstAlign, SrcAlign); 8030 8031 bool isVol = false; 8032 SDLoc sdl = getCurSDLoc(); 8033 8034 // In the mempcpy context we need to pass in a false value for isTailCall 8035 // because the return pointer needs to be adjusted by the size of 8036 // the copied memory. 8037 SDValue Root = isVol ? getRoot() : getMemoryRoot(); 8038 SDValue MC = DAG.getMemcpy(Root, sdl, Dst, Src, Size, Alignment, isVol, false, 8039 /*isTailCall=*/false, 8040 MachinePointerInfo(I.getArgOperand(0)), 8041 MachinePointerInfo(I.getArgOperand(1)), 8042 I.getAAMetadata()); 8043 assert(MC.getNode() != nullptr && 8044 "** memcpy should not be lowered as TailCall in mempcpy context **"); 8045 DAG.setRoot(MC); 8046 8047 // Check if Size needs to be truncated or extended. 8048 Size = DAG.getSExtOrTrunc(Size, sdl, Dst.getValueType()); 8049 8050 // Adjust return pointer to point just past the last dst byte. 8051 SDValue DstPlusSize = DAG.getNode(ISD::ADD, sdl, Dst.getValueType(), 8052 Dst, Size); 8053 setValue(&I, DstPlusSize); 8054 return true; 8055 } 8056 8057 /// See if we can lower a strcpy call into an optimized form. If so, return 8058 /// true and lower it, otherwise return false and it will be lowered like a 8059 /// normal call. 8060 /// The caller already checked that \p I calls the appropriate LibFunc with a 8061 /// correct prototype. 8062 bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) { 8063 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1); 8064 8065 const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo(); 8066 std::pair<SDValue, SDValue> Res = 8067 TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(), 8068 getValue(Arg0), getValue(Arg1), 8069 MachinePointerInfo(Arg0), 8070 MachinePointerInfo(Arg1), isStpcpy); 8071 if (Res.first.getNode()) { 8072 setValue(&I, Res.first); 8073 DAG.setRoot(Res.second); 8074 return true; 8075 } 8076 8077 return false; 8078 } 8079 8080 /// See if we can lower a strcmp call into an optimized form. If so, return 8081 /// true and lower it, otherwise return false and it will be lowered like a 8082 /// normal call. 8083 /// The caller already checked that \p I calls the appropriate LibFunc with a 8084 /// correct prototype. 8085 bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) { 8086 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1); 8087 8088 const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo(); 8089 std::pair<SDValue, SDValue> Res = 8090 TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(), 8091 getValue(Arg0), getValue(Arg1), 8092 MachinePointerInfo(Arg0), 8093 MachinePointerInfo(Arg1)); 8094 if (Res.first.getNode()) { 8095 processIntegerCallValue(I, Res.first, true); 8096 PendingLoads.push_back(Res.second); 8097 return true; 8098 } 8099 8100 return false; 8101 } 8102 8103 /// See if we can lower a strlen call into an optimized form. If so, return 8104 /// true and lower it, otherwise return false and it will be lowered like a 8105 /// normal call. 8106 /// The caller already checked that \p I calls the appropriate LibFunc with a 8107 /// correct prototype. 8108 bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) { 8109 const Value *Arg0 = I.getArgOperand(0); 8110 8111 const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo(); 8112 std::pair<SDValue, SDValue> Res = 8113 TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(), 8114 getValue(Arg0), MachinePointerInfo(Arg0)); 8115 if (Res.first.getNode()) { 8116 processIntegerCallValue(I, Res.first, false); 8117 PendingLoads.push_back(Res.second); 8118 return true; 8119 } 8120 8121 return false; 8122 } 8123 8124 /// See if we can lower a strnlen call into an optimized form. If so, return 8125 /// true and lower it, otherwise return false and it will be lowered like a 8126 /// normal call. 8127 /// The caller already checked that \p I calls the appropriate LibFunc with a 8128 /// correct prototype. 8129 bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) { 8130 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1); 8131 8132 const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo(); 8133 std::pair<SDValue, SDValue> Res = 8134 TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(), 8135 getValue(Arg0), getValue(Arg1), 8136 MachinePointerInfo(Arg0)); 8137 if (Res.first.getNode()) { 8138 processIntegerCallValue(I, Res.first, false); 8139 PendingLoads.push_back(Res.second); 8140 return true; 8141 } 8142 8143 return false; 8144 } 8145 8146 /// See if we can lower a unary floating-point operation into an SDNode with 8147 /// the specified Opcode. If so, return true and lower it, otherwise return 8148 /// false and it will be lowered like a normal call. 8149 /// The caller already checked that \p I calls the appropriate LibFunc with a 8150 /// correct prototype. 8151 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I, 8152 unsigned Opcode) { 8153 // We already checked this call's prototype; verify it doesn't modify errno. 8154 if (!I.onlyReadsMemory()) 8155 return false; 8156 8157 SDNodeFlags Flags; 8158 Flags.copyFMF(cast<FPMathOperator>(I)); 8159 8160 SDValue Tmp = getValue(I.getArgOperand(0)); 8161 setValue(&I, 8162 DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp, Flags)); 8163 return true; 8164 } 8165 8166 /// See if we can lower a binary floating-point operation into an SDNode with 8167 /// the specified Opcode. If so, return true and lower it. Otherwise return 8168 /// false, and it will be lowered like a normal call. 8169 /// The caller already checked that \p I calls the appropriate LibFunc with a 8170 /// correct prototype. 8171 bool SelectionDAGBuilder::visitBinaryFloatCall(const CallInst &I, 8172 unsigned Opcode) { 8173 // We already checked this call's prototype; verify it doesn't modify errno. 8174 if (!I.onlyReadsMemory()) 8175 return false; 8176 8177 SDNodeFlags Flags; 8178 Flags.copyFMF(cast<FPMathOperator>(I)); 8179 8180 SDValue Tmp0 = getValue(I.getArgOperand(0)); 8181 SDValue Tmp1 = getValue(I.getArgOperand(1)); 8182 EVT VT = Tmp0.getValueType(); 8183 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), VT, Tmp0, Tmp1, Flags)); 8184 return true; 8185 } 8186 8187 void SelectionDAGBuilder::visitCall(const CallInst &I) { 8188 // Handle inline assembly differently. 8189 if (I.isInlineAsm()) { 8190 visitInlineAsm(I); 8191 return; 8192 } 8193 8194 if (Function *F = I.getCalledFunction()) { 8195 diagnoseDontCall(I); 8196 8197 if (F->isDeclaration()) { 8198 // Is this an LLVM intrinsic or a target-specific intrinsic? 8199 unsigned IID = F->getIntrinsicID(); 8200 if (!IID) 8201 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) 8202 IID = II->getIntrinsicID(F); 8203 8204 if (IID) { 8205 visitIntrinsicCall(I, IID); 8206 return; 8207 } 8208 } 8209 8210 // Check for well-known libc/libm calls. If the function is internal, it 8211 // can't be a library call. Don't do the check if marked as nobuiltin for 8212 // some reason or the call site requires strict floating point semantics. 8213 LibFunc Func; 8214 if (!I.isNoBuiltin() && !I.isStrictFP() && !F->hasLocalLinkage() && 8215 F->hasName() && LibInfo->getLibFunc(*F, Func) && 8216 LibInfo->hasOptimizedCodeGen(Func)) { 8217 switch (Func) { 8218 default: break; 8219 case LibFunc_bcmp: 8220 if (visitMemCmpBCmpCall(I)) 8221 return; 8222 break; 8223 case LibFunc_copysign: 8224 case LibFunc_copysignf: 8225 case LibFunc_copysignl: 8226 // We already checked this call's prototype; verify it doesn't modify 8227 // errno. 8228 if (I.onlyReadsMemory()) { 8229 SDValue LHS = getValue(I.getArgOperand(0)); 8230 SDValue RHS = getValue(I.getArgOperand(1)); 8231 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(), 8232 LHS.getValueType(), LHS, RHS)); 8233 return; 8234 } 8235 break; 8236 case LibFunc_fabs: 8237 case LibFunc_fabsf: 8238 case LibFunc_fabsl: 8239 if (visitUnaryFloatCall(I, ISD::FABS)) 8240 return; 8241 break; 8242 case LibFunc_fmin: 8243 case LibFunc_fminf: 8244 case LibFunc_fminl: 8245 if (visitBinaryFloatCall(I, ISD::FMINNUM)) 8246 return; 8247 break; 8248 case LibFunc_fmax: 8249 case LibFunc_fmaxf: 8250 case LibFunc_fmaxl: 8251 if (visitBinaryFloatCall(I, ISD::FMAXNUM)) 8252 return; 8253 break; 8254 case LibFunc_sin: 8255 case LibFunc_sinf: 8256 case LibFunc_sinl: 8257 if (visitUnaryFloatCall(I, ISD::FSIN)) 8258 return; 8259 break; 8260 case LibFunc_cos: 8261 case LibFunc_cosf: 8262 case LibFunc_cosl: 8263 if (visitUnaryFloatCall(I, ISD::FCOS)) 8264 return; 8265 break; 8266 case LibFunc_sqrt: 8267 case LibFunc_sqrtf: 8268 case LibFunc_sqrtl: 8269 case LibFunc_sqrt_finite: 8270 case LibFunc_sqrtf_finite: 8271 case LibFunc_sqrtl_finite: 8272 if (visitUnaryFloatCall(I, ISD::FSQRT)) 8273 return; 8274 break; 8275 case LibFunc_floor: 8276 case LibFunc_floorf: 8277 case LibFunc_floorl: 8278 if (visitUnaryFloatCall(I, ISD::FFLOOR)) 8279 return; 8280 break; 8281 case LibFunc_nearbyint: 8282 case LibFunc_nearbyintf: 8283 case LibFunc_nearbyintl: 8284 if (visitUnaryFloatCall(I, ISD::FNEARBYINT)) 8285 return; 8286 break; 8287 case LibFunc_ceil: 8288 case LibFunc_ceilf: 8289 case LibFunc_ceill: 8290 if (visitUnaryFloatCall(I, ISD::FCEIL)) 8291 return; 8292 break; 8293 case LibFunc_rint: 8294 case LibFunc_rintf: 8295 case LibFunc_rintl: 8296 if (visitUnaryFloatCall(I, ISD::FRINT)) 8297 return; 8298 break; 8299 case LibFunc_round: 8300 case LibFunc_roundf: 8301 case LibFunc_roundl: 8302 if (visitUnaryFloatCall(I, ISD::FROUND)) 8303 return; 8304 break; 8305 case LibFunc_trunc: 8306 case LibFunc_truncf: 8307 case LibFunc_truncl: 8308 if (visitUnaryFloatCall(I, ISD::FTRUNC)) 8309 return; 8310 break; 8311 case LibFunc_log2: 8312 case LibFunc_log2f: 8313 case LibFunc_log2l: 8314 if (visitUnaryFloatCall(I, ISD::FLOG2)) 8315 return; 8316 break; 8317 case LibFunc_exp2: 8318 case LibFunc_exp2f: 8319 case LibFunc_exp2l: 8320 if (visitUnaryFloatCall(I, ISD::FEXP2)) 8321 return; 8322 break; 8323 case LibFunc_memcmp: 8324 if (visitMemCmpBCmpCall(I)) 8325 return; 8326 break; 8327 case LibFunc_mempcpy: 8328 if (visitMemPCpyCall(I)) 8329 return; 8330 break; 8331 case LibFunc_memchr: 8332 if (visitMemChrCall(I)) 8333 return; 8334 break; 8335 case LibFunc_strcpy: 8336 if (visitStrCpyCall(I, false)) 8337 return; 8338 break; 8339 case LibFunc_stpcpy: 8340 if (visitStrCpyCall(I, true)) 8341 return; 8342 break; 8343 case LibFunc_strcmp: 8344 if (visitStrCmpCall(I)) 8345 return; 8346 break; 8347 case LibFunc_strlen: 8348 if (visitStrLenCall(I)) 8349 return; 8350 break; 8351 case LibFunc_strnlen: 8352 if (visitStrNLenCall(I)) 8353 return; 8354 break; 8355 } 8356 } 8357 } 8358 8359 // Deopt bundles are lowered in LowerCallSiteWithDeoptBundle, and we don't 8360 // have to do anything here to lower funclet bundles. 8361 // CFGuardTarget bundles are lowered in LowerCallTo. 8362 assert(!I.hasOperandBundlesOtherThan( 8363 {LLVMContext::OB_deopt, LLVMContext::OB_funclet, 8364 LLVMContext::OB_cfguardtarget, LLVMContext::OB_preallocated, 8365 LLVMContext::OB_clang_arc_attachedcall}) && 8366 "Cannot lower calls with arbitrary operand bundles!"); 8367 8368 SDValue Callee = getValue(I.getCalledOperand()); 8369 8370 if (I.countOperandBundlesOfType(LLVMContext::OB_deopt)) 8371 LowerCallSiteWithDeoptBundle(&I, Callee, nullptr); 8372 else 8373 // Check if we can potentially perform a tail call. More detailed checking 8374 // is be done within LowerCallTo, after more information about the call is 8375 // known. 8376 LowerCallTo(I, Callee, I.isTailCall(), I.isMustTailCall()); 8377 } 8378 8379 namespace { 8380 8381 /// AsmOperandInfo - This contains information for each constraint that we are 8382 /// lowering. 8383 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo { 8384 public: 8385 /// CallOperand - If this is the result output operand or a clobber 8386 /// this is null, otherwise it is the incoming operand to the CallInst. 8387 /// This gets modified as the asm is processed. 8388 SDValue CallOperand; 8389 8390 /// AssignedRegs - If this is a register or register class operand, this 8391 /// contains the set of register corresponding to the operand. 8392 RegsForValue AssignedRegs; 8393 8394 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info) 8395 : TargetLowering::AsmOperandInfo(info), CallOperand(nullptr, 0) { 8396 } 8397 8398 /// Whether or not this operand accesses memory 8399 bool hasMemory(const TargetLowering &TLI) const { 8400 // Indirect operand accesses access memory. 8401 if (isIndirect) 8402 return true; 8403 8404 for (const auto &Code : Codes) 8405 if (TLI.getConstraintType(Code) == TargetLowering::C_Memory) 8406 return true; 8407 8408 return false; 8409 } 8410 }; 8411 8412 8413 } // end anonymous namespace 8414 8415 /// Make sure that the output operand \p OpInfo and its corresponding input 8416 /// operand \p MatchingOpInfo have compatible constraint types (otherwise error 8417 /// out). 8418 static void patchMatchingInput(const SDISelAsmOperandInfo &OpInfo, 8419 SDISelAsmOperandInfo &MatchingOpInfo, 8420 SelectionDAG &DAG) { 8421 if (OpInfo.ConstraintVT == MatchingOpInfo.ConstraintVT) 8422 return; 8423 8424 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo(); 8425 const auto &TLI = DAG.getTargetLoweringInfo(); 8426 8427 std::pair<unsigned, const TargetRegisterClass *> MatchRC = 8428 TLI.getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode, 8429 OpInfo.ConstraintVT); 8430 std::pair<unsigned, const TargetRegisterClass *> InputRC = 8431 TLI.getRegForInlineAsmConstraint(TRI, MatchingOpInfo.ConstraintCode, 8432 MatchingOpInfo.ConstraintVT); 8433 if ((OpInfo.ConstraintVT.isInteger() != 8434 MatchingOpInfo.ConstraintVT.isInteger()) || 8435 (MatchRC.second != InputRC.second)) { 8436 // FIXME: error out in a more elegant fashion 8437 report_fatal_error("Unsupported asm: input constraint" 8438 " with a matching output constraint of" 8439 " incompatible type!"); 8440 } 8441 MatchingOpInfo.ConstraintVT = OpInfo.ConstraintVT; 8442 } 8443 8444 /// Get a direct memory input to behave well as an indirect operand. 8445 /// This may introduce stores, hence the need for a \p Chain. 8446 /// \return The (possibly updated) chain. 8447 static SDValue getAddressForMemoryInput(SDValue Chain, const SDLoc &Location, 8448 SDISelAsmOperandInfo &OpInfo, 8449 SelectionDAG &DAG) { 8450 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 8451 8452 // If we don't have an indirect input, put it in the constpool if we can, 8453 // otherwise spill it to a stack slot. 8454 // TODO: This isn't quite right. We need to handle these according to 8455 // the addressing mode that the constraint wants. Also, this may take 8456 // an additional register for the computation and we don't want that 8457 // either. 8458 8459 // If the operand is a float, integer, or vector constant, spill to a 8460 // constant pool entry to get its address. 8461 const Value *OpVal = OpInfo.CallOperandVal; 8462 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) || 8463 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) { 8464 OpInfo.CallOperand = DAG.getConstantPool( 8465 cast<Constant>(OpVal), TLI.getPointerTy(DAG.getDataLayout())); 8466 return Chain; 8467 } 8468 8469 // Otherwise, create a stack slot and emit a store to it before the asm. 8470 Type *Ty = OpVal->getType(); 8471 auto &DL = DAG.getDataLayout(); 8472 uint64_t TySize = DL.getTypeAllocSize(Ty); 8473 MachineFunction &MF = DAG.getMachineFunction(); 8474 int SSFI = MF.getFrameInfo().CreateStackObject( 8475 TySize, DL.getPrefTypeAlign(Ty), false); 8476 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getFrameIndexTy(DL)); 8477 Chain = DAG.getTruncStore(Chain, Location, OpInfo.CallOperand, StackSlot, 8478 MachinePointerInfo::getFixedStack(MF, SSFI), 8479 TLI.getMemValueType(DL, Ty)); 8480 OpInfo.CallOperand = StackSlot; 8481 8482 return Chain; 8483 } 8484 8485 /// GetRegistersForValue - Assign registers (virtual or physical) for the 8486 /// specified operand. We prefer to assign virtual registers, to allow the 8487 /// register allocator to handle the assignment process. However, if the asm 8488 /// uses features that we can't model on machineinstrs, we have SDISel do the 8489 /// allocation. This produces generally horrible, but correct, code. 8490 /// 8491 /// OpInfo describes the operand 8492 /// RefOpInfo describes the matching operand if any, the operand otherwise 8493 static llvm::Optional<unsigned> 8494 getRegistersForValue(SelectionDAG &DAG, const SDLoc &DL, 8495 SDISelAsmOperandInfo &OpInfo, 8496 SDISelAsmOperandInfo &RefOpInfo) { 8497 LLVMContext &Context = *DAG.getContext(); 8498 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 8499 8500 MachineFunction &MF = DAG.getMachineFunction(); 8501 SmallVector<unsigned, 4> Regs; 8502 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); 8503 8504 // No work to do for memory/address operands. 8505 if (OpInfo.ConstraintType == TargetLowering::C_Memory || 8506 OpInfo.ConstraintType == TargetLowering::C_Address) 8507 return None; 8508 8509 // If this is a constraint for a single physreg, or a constraint for a 8510 // register class, find it. 8511 unsigned AssignedReg; 8512 const TargetRegisterClass *RC; 8513 std::tie(AssignedReg, RC) = TLI.getRegForInlineAsmConstraint( 8514 &TRI, RefOpInfo.ConstraintCode, RefOpInfo.ConstraintVT); 8515 // RC is unset only on failure. Return immediately. 8516 if (!RC) 8517 return None; 8518 8519 // Get the actual register value type. This is important, because the user 8520 // may have asked for (e.g.) the AX register in i32 type. We need to 8521 // remember that AX is actually i16 to get the right extension. 8522 const MVT RegVT = *TRI.legalclasstypes_begin(*RC); 8523 8524 if (OpInfo.ConstraintVT != MVT::Other && RegVT != MVT::Untyped) { 8525 // If this is an FP operand in an integer register (or visa versa), or more 8526 // generally if the operand value disagrees with the register class we plan 8527 // to stick it in, fix the operand type. 8528 // 8529 // If this is an input value, the bitcast to the new type is done now. 8530 // Bitcast for output value is done at the end of visitInlineAsm(). 8531 if ((OpInfo.Type == InlineAsm::isOutput || 8532 OpInfo.Type == InlineAsm::isInput) && 8533 !TRI.isTypeLegalForClass(*RC, OpInfo.ConstraintVT)) { 8534 // Try to convert to the first EVT that the reg class contains. If the 8535 // types are identical size, use a bitcast to convert (e.g. two differing 8536 // vector types). Note: output bitcast is done at the end of 8537 // visitInlineAsm(). 8538 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) { 8539 // Exclude indirect inputs while they are unsupported because the code 8540 // to perform the load is missing and thus OpInfo.CallOperand still 8541 // refers to the input address rather than the pointed-to value. 8542 if (OpInfo.Type == InlineAsm::isInput && !OpInfo.isIndirect) 8543 OpInfo.CallOperand = 8544 DAG.getNode(ISD::BITCAST, DL, RegVT, OpInfo.CallOperand); 8545 OpInfo.ConstraintVT = RegVT; 8546 // If the operand is an FP value and we want it in integer registers, 8547 // use the corresponding integer type. This turns an f64 value into 8548 // i64, which can be passed with two i32 values on a 32-bit machine. 8549 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) { 8550 MVT VT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits()); 8551 if (OpInfo.Type == InlineAsm::isInput) 8552 OpInfo.CallOperand = 8553 DAG.getNode(ISD::BITCAST, DL, VT, OpInfo.CallOperand); 8554 OpInfo.ConstraintVT = VT; 8555 } 8556 } 8557 } 8558 8559 // No need to allocate a matching input constraint since the constraint it's 8560 // matching to has already been allocated. 8561 if (OpInfo.isMatchingInputConstraint()) 8562 return None; 8563 8564 EVT ValueVT = OpInfo.ConstraintVT; 8565 if (OpInfo.ConstraintVT == MVT::Other) 8566 ValueVT = RegVT; 8567 8568 // Initialize NumRegs. 8569 unsigned NumRegs = 1; 8570 if (OpInfo.ConstraintVT != MVT::Other) 8571 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT, RegVT); 8572 8573 // If this is a constraint for a specific physical register, like {r17}, 8574 // assign it now. 8575 8576 // If this associated to a specific register, initialize iterator to correct 8577 // place. If virtual, make sure we have enough registers 8578 8579 // Initialize iterator if necessary 8580 TargetRegisterClass::iterator I = RC->begin(); 8581 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 8582 8583 // Do not check for single registers. 8584 if (AssignedReg) { 8585 I = std::find(I, RC->end(), AssignedReg); 8586 if (I == RC->end()) { 8587 // RC does not contain the selected register, which indicates a 8588 // mismatch between the register and the required type/bitwidth. 8589 return {AssignedReg}; 8590 } 8591 } 8592 8593 for (; NumRegs; --NumRegs, ++I) { 8594 assert(I != RC->end() && "Ran out of registers to allocate!"); 8595 Register R = AssignedReg ? Register(*I) : RegInfo.createVirtualRegister(RC); 8596 Regs.push_back(R); 8597 } 8598 8599 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 8600 return None; 8601 } 8602 8603 static unsigned 8604 findMatchingInlineAsmOperand(unsigned OperandNo, 8605 const std::vector<SDValue> &AsmNodeOperands) { 8606 // Scan until we find the definition we already emitted of this operand. 8607 unsigned CurOp = InlineAsm::Op_FirstOperand; 8608 for (; OperandNo; --OperandNo) { 8609 // Advance to the next operand. 8610 unsigned OpFlag = 8611 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 8612 assert((InlineAsm::isRegDefKind(OpFlag) || 8613 InlineAsm::isRegDefEarlyClobberKind(OpFlag) || 8614 InlineAsm::isMemKind(OpFlag)) && 8615 "Skipped past definitions?"); 8616 CurOp += InlineAsm::getNumOperandRegisters(OpFlag) + 1; 8617 } 8618 return CurOp; 8619 } 8620 8621 namespace { 8622 8623 class ExtraFlags { 8624 unsigned Flags = 0; 8625 8626 public: 8627 explicit ExtraFlags(const CallBase &Call) { 8628 const InlineAsm *IA = cast<InlineAsm>(Call.getCalledOperand()); 8629 if (IA->hasSideEffects()) 8630 Flags |= InlineAsm::Extra_HasSideEffects; 8631 if (IA->isAlignStack()) 8632 Flags |= InlineAsm::Extra_IsAlignStack; 8633 if (Call.isConvergent()) 8634 Flags |= InlineAsm::Extra_IsConvergent; 8635 Flags |= IA->getDialect() * InlineAsm::Extra_AsmDialect; 8636 } 8637 8638 void update(const TargetLowering::AsmOperandInfo &OpInfo) { 8639 // Ideally, we would only check against memory constraints. However, the 8640 // meaning of an Other constraint can be target-specific and we can't easily 8641 // reason about it. Therefore, be conservative and set MayLoad/MayStore 8642 // for Other constraints as well. 8643 if (OpInfo.ConstraintType == TargetLowering::C_Memory || 8644 OpInfo.ConstraintType == TargetLowering::C_Other) { 8645 if (OpInfo.Type == InlineAsm::isInput) 8646 Flags |= InlineAsm::Extra_MayLoad; 8647 else if (OpInfo.Type == InlineAsm::isOutput) 8648 Flags |= InlineAsm::Extra_MayStore; 8649 else if (OpInfo.Type == InlineAsm::isClobber) 8650 Flags |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore); 8651 } 8652 } 8653 8654 unsigned get() const { return Flags; } 8655 }; 8656 8657 } // end anonymous namespace 8658 8659 /// visitInlineAsm - Handle a call to an InlineAsm object. 8660 void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call, 8661 const BasicBlock *EHPadBB) { 8662 const InlineAsm *IA = cast<InlineAsm>(Call.getCalledOperand()); 8663 8664 /// ConstraintOperands - Information about all of the constraints. 8665 SmallVector<SDISelAsmOperandInfo, 16> ConstraintOperands; 8666 8667 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 8668 TargetLowering::AsmOperandInfoVector TargetConstraints = TLI.ParseConstraints( 8669 DAG.getDataLayout(), DAG.getSubtarget().getRegisterInfo(), Call); 8670 8671 // First Pass: Calculate HasSideEffects and ExtraFlags (AlignStack, 8672 // AsmDialect, MayLoad, MayStore). 8673 bool HasSideEffect = IA->hasSideEffects(); 8674 ExtraFlags ExtraInfo(Call); 8675 8676 for (auto &T : TargetConstraints) { 8677 ConstraintOperands.push_back(SDISelAsmOperandInfo(T)); 8678 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back(); 8679 8680 if (OpInfo.CallOperandVal) 8681 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); 8682 8683 if (!HasSideEffect) 8684 HasSideEffect = OpInfo.hasMemory(TLI); 8685 8686 // Determine if this InlineAsm MayLoad or MayStore based on the constraints. 8687 // FIXME: Could we compute this on OpInfo rather than T? 8688 8689 // Compute the constraint code and ConstraintType to use. 8690 TLI.ComputeConstraintToUse(T, SDValue()); 8691 8692 if (T.ConstraintType == TargetLowering::C_Immediate && 8693 OpInfo.CallOperand && !isa<ConstantSDNode>(OpInfo.CallOperand)) 8694 // We've delayed emitting a diagnostic like the "n" constraint because 8695 // inlining could cause an integer showing up. 8696 return emitInlineAsmError(Call, "constraint '" + Twine(T.ConstraintCode) + 8697 "' expects an integer constant " 8698 "expression"); 8699 8700 ExtraInfo.update(T); 8701 } 8702 8703 // We won't need to flush pending loads if this asm doesn't touch 8704 // memory and is nonvolatile. 8705 SDValue Flag, Chain = (HasSideEffect) ? getRoot() : DAG.getRoot(); 8706 8707 bool EmitEHLabels = isa<InvokeInst>(Call) && IA->canThrow(); 8708 if (EmitEHLabels) { 8709 assert(EHPadBB && "InvokeInst must have an EHPadBB"); 8710 } 8711 bool IsCallBr = isa<CallBrInst>(Call); 8712 8713 if (IsCallBr || EmitEHLabels) { 8714 // If this is a callbr or invoke we need to flush pending exports since 8715 // inlineasm_br and invoke are terminators. 8716 // We need to do this before nodes are glued to the inlineasm_br node. 8717 Chain = getControlRoot(); 8718 } 8719 8720 MCSymbol *BeginLabel = nullptr; 8721 if (EmitEHLabels) { 8722 Chain = lowerStartEH(Chain, EHPadBB, BeginLabel); 8723 } 8724 8725 // Second pass over the constraints: compute which constraint option to use. 8726 for (SDISelAsmOperandInfo &OpInfo : ConstraintOperands) { 8727 // If this is an output operand with a matching input operand, look up the 8728 // matching input. If their types mismatch, e.g. one is an integer, the 8729 // other is floating point, or their sizes are different, flag it as an 8730 // error. 8731 if (OpInfo.hasMatchingInput()) { 8732 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 8733 patchMatchingInput(OpInfo, Input, DAG); 8734 } 8735 8736 // Compute the constraint code and ConstraintType to use. 8737 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG); 8738 8739 if ((OpInfo.ConstraintType == TargetLowering::C_Memory && 8740 OpInfo.Type == InlineAsm::isClobber) || 8741 OpInfo.ConstraintType == TargetLowering::C_Address) 8742 continue; 8743 8744 // If this is a memory input, and if the operand is not indirect, do what we 8745 // need to provide an address for the memory input. 8746 if (OpInfo.ConstraintType == TargetLowering::C_Memory && 8747 !OpInfo.isIndirect) { 8748 assert((OpInfo.isMultipleAlternative || 8749 (OpInfo.Type == InlineAsm::isInput)) && 8750 "Can only indirectify direct input operands!"); 8751 8752 // Memory operands really want the address of the value. 8753 Chain = getAddressForMemoryInput(Chain, getCurSDLoc(), OpInfo, DAG); 8754 8755 // There is no longer a Value* corresponding to this operand. 8756 OpInfo.CallOperandVal = nullptr; 8757 8758 // It is now an indirect operand. 8759 OpInfo.isIndirect = true; 8760 } 8761 8762 } 8763 8764 // AsmNodeOperands - The operands for the ISD::INLINEASM node. 8765 std::vector<SDValue> AsmNodeOperands; 8766 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain 8767 AsmNodeOperands.push_back(DAG.getTargetExternalSymbol( 8768 IA->getAsmString().c_str(), TLI.getProgramPointerTy(DAG.getDataLayout()))); 8769 8770 // If we have a !srcloc metadata node associated with it, we want to attach 8771 // this to the ultimately generated inline asm machineinstr. To do this, we 8772 // pass in the third operand as this (potentially null) inline asm MDNode. 8773 const MDNode *SrcLoc = Call.getMetadata("srcloc"); 8774 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc)); 8775 8776 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore 8777 // bits as operand 3. 8778 AsmNodeOperands.push_back(DAG.getTargetConstant( 8779 ExtraInfo.get(), getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout()))); 8780 8781 // Third pass: Loop over operands to prepare DAG-level operands.. As part of 8782 // this, assign virtual and physical registers for inputs and otput. 8783 for (SDISelAsmOperandInfo &OpInfo : ConstraintOperands) { 8784 // Assign Registers. 8785 SDISelAsmOperandInfo &RefOpInfo = 8786 OpInfo.isMatchingInputConstraint() 8787 ? ConstraintOperands[OpInfo.getMatchedOperand()] 8788 : OpInfo; 8789 const auto RegError = 8790 getRegistersForValue(DAG, getCurSDLoc(), OpInfo, RefOpInfo); 8791 if (RegError) { 8792 const MachineFunction &MF = DAG.getMachineFunction(); 8793 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); 8794 const char *RegName = TRI.getName(RegError.value()); 8795 emitInlineAsmError(Call, "register '" + Twine(RegName) + 8796 "' allocated for constraint '" + 8797 Twine(OpInfo.ConstraintCode) + 8798 "' does not match required type"); 8799 return; 8800 } 8801 8802 auto DetectWriteToReservedRegister = [&]() { 8803 const MachineFunction &MF = DAG.getMachineFunction(); 8804 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); 8805 for (unsigned Reg : OpInfo.AssignedRegs.Regs) { 8806 if (Register::isPhysicalRegister(Reg) && 8807 TRI.isInlineAsmReadOnlyReg(MF, Reg)) { 8808 const char *RegName = TRI.getName(Reg); 8809 emitInlineAsmError(Call, "write to reserved register '" + 8810 Twine(RegName) + "'"); 8811 return true; 8812 } 8813 } 8814 return false; 8815 }; 8816 assert((OpInfo.ConstraintType != TargetLowering::C_Address || 8817 (OpInfo.Type == InlineAsm::isInput && 8818 !OpInfo.isMatchingInputConstraint())) && 8819 "Only address as input operand is allowed."); 8820 8821 switch (OpInfo.Type) { 8822 case InlineAsm::isOutput: 8823 if (OpInfo.ConstraintType == TargetLowering::C_Memory) { 8824 unsigned ConstraintID = 8825 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode); 8826 assert(ConstraintID != InlineAsm::Constraint_Unknown && 8827 "Failed to convert memory constraint code to constraint id."); 8828 8829 // Add information to the INLINEASM node to know about this output. 8830 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 8831 OpFlags = InlineAsm::getFlagWordForMem(OpFlags, ConstraintID); 8832 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, getCurSDLoc(), 8833 MVT::i32)); 8834 AsmNodeOperands.push_back(OpInfo.CallOperand); 8835 } else { 8836 // Otherwise, this outputs to a register (directly for C_Register / 8837 // C_RegisterClass, and a target-defined fashion for 8838 // C_Immediate/C_Other). Find a register that we can use. 8839 if (OpInfo.AssignedRegs.Regs.empty()) { 8840 emitInlineAsmError( 8841 Call, "couldn't allocate output register for constraint '" + 8842 Twine(OpInfo.ConstraintCode) + "'"); 8843 return; 8844 } 8845 8846 if (DetectWriteToReservedRegister()) 8847 return; 8848 8849 // Add information to the INLINEASM node to know that this register is 8850 // set. 8851 OpInfo.AssignedRegs.AddInlineAsmOperands( 8852 OpInfo.isEarlyClobber ? InlineAsm::Kind_RegDefEarlyClobber 8853 : InlineAsm::Kind_RegDef, 8854 false, 0, getCurSDLoc(), DAG, AsmNodeOperands); 8855 } 8856 break; 8857 8858 case InlineAsm::isInput: { 8859 SDValue InOperandVal = OpInfo.CallOperand; 8860 8861 if (OpInfo.isMatchingInputConstraint()) { 8862 // If this is required to match an output register we have already set, 8863 // just use its register. 8864 auto CurOp = findMatchingInlineAsmOperand(OpInfo.getMatchedOperand(), 8865 AsmNodeOperands); 8866 unsigned OpFlag = 8867 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 8868 if (InlineAsm::isRegDefKind(OpFlag) || 8869 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) { 8870 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs. 8871 if (OpInfo.isIndirect) { 8872 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c 8873 emitInlineAsmError(Call, "inline asm not supported yet: " 8874 "don't know how to handle tied " 8875 "indirect register inputs"); 8876 return; 8877 } 8878 8879 SmallVector<unsigned, 4> Regs; 8880 MachineFunction &MF = DAG.getMachineFunction(); 8881 MachineRegisterInfo &MRI = MF.getRegInfo(); 8882 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); 8883 auto *R = cast<RegisterSDNode>(AsmNodeOperands[CurOp+1]); 8884 Register TiedReg = R->getReg(); 8885 MVT RegVT = R->getSimpleValueType(0); 8886 const TargetRegisterClass *RC = 8887 TiedReg.isVirtual() ? MRI.getRegClass(TiedReg) 8888 : RegVT != MVT::Untyped ? TLI.getRegClassFor(RegVT) 8889 : TRI.getMinimalPhysRegClass(TiedReg); 8890 unsigned NumRegs = InlineAsm::getNumOperandRegisters(OpFlag); 8891 for (unsigned i = 0; i != NumRegs; ++i) 8892 Regs.push_back(MRI.createVirtualRegister(RC)); 8893 8894 RegsForValue MatchedRegs(Regs, RegVT, InOperandVal.getValueType()); 8895 8896 SDLoc dl = getCurSDLoc(); 8897 // Use the produced MatchedRegs object to 8898 MatchedRegs.getCopyToRegs(InOperandVal, DAG, dl, Chain, &Flag, &Call); 8899 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, 8900 true, OpInfo.getMatchedOperand(), dl, 8901 DAG, AsmNodeOperands); 8902 break; 8903 } 8904 8905 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!"); 8906 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 && 8907 "Unexpected number of operands"); 8908 // Add information to the INLINEASM node to know about this input. 8909 // See InlineAsm.h isUseOperandTiedToDef. 8910 OpFlag = InlineAsm::convertMemFlagWordToMatchingFlagWord(OpFlag); 8911 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag, 8912 OpInfo.getMatchedOperand()); 8913 AsmNodeOperands.push_back(DAG.getTargetConstant( 8914 OpFlag, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout()))); 8915 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]); 8916 break; 8917 } 8918 8919 // Treat indirect 'X' constraint as memory. 8920 if (OpInfo.ConstraintType == TargetLowering::C_Other && 8921 OpInfo.isIndirect) 8922 OpInfo.ConstraintType = TargetLowering::C_Memory; 8923 8924 if (OpInfo.ConstraintType == TargetLowering::C_Immediate || 8925 OpInfo.ConstraintType == TargetLowering::C_Other) { 8926 std::vector<SDValue> Ops; 8927 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode, 8928 Ops, DAG); 8929 if (Ops.empty()) { 8930 if (OpInfo.ConstraintType == TargetLowering::C_Immediate) 8931 if (isa<ConstantSDNode>(InOperandVal)) { 8932 emitInlineAsmError(Call, "value out of range for constraint '" + 8933 Twine(OpInfo.ConstraintCode) + "'"); 8934 return; 8935 } 8936 8937 emitInlineAsmError(Call, 8938 "invalid operand for inline asm constraint '" + 8939 Twine(OpInfo.ConstraintCode) + "'"); 8940 return; 8941 } 8942 8943 // Add information to the INLINEASM node to know about this input. 8944 unsigned ResOpType = 8945 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size()); 8946 AsmNodeOperands.push_back(DAG.getTargetConstant( 8947 ResOpType, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout()))); 8948 llvm::append_range(AsmNodeOperands, Ops); 8949 break; 8950 } 8951 8952 if (OpInfo.ConstraintType == TargetLowering::C_Memory || 8953 OpInfo.ConstraintType == TargetLowering::C_Address) { 8954 assert((OpInfo.isIndirect || 8955 OpInfo.ConstraintType != TargetLowering::C_Memory) && 8956 "Operand must be indirect to be a mem!"); 8957 assert(InOperandVal.getValueType() == 8958 TLI.getPointerTy(DAG.getDataLayout()) && 8959 "Memory operands expect pointer values"); 8960 8961 unsigned ConstraintID = 8962 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode); 8963 assert(ConstraintID != InlineAsm::Constraint_Unknown && 8964 "Failed to convert memory constraint code to constraint id."); 8965 8966 // Add information to the INLINEASM node to know about this input. 8967 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 8968 ResOpType = InlineAsm::getFlagWordForMem(ResOpType, ConstraintID); 8969 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 8970 getCurSDLoc(), 8971 MVT::i32)); 8972 AsmNodeOperands.push_back(InOperandVal); 8973 break; 8974 } 8975 8976 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass || 8977 OpInfo.ConstraintType == TargetLowering::C_Register) && 8978 "Unknown constraint type!"); 8979 8980 // TODO: Support this. 8981 if (OpInfo.isIndirect) { 8982 emitInlineAsmError( 8983 Call, "Don't know how to handle indirect register inputs yet " 8984 "for constraint '" + 8985 Twine(OpInfo.ConstraintCode) + "'"); 8986 return; 8987 } 8988 8989 // Copy the input into the appropriate registers. 8990 if (OpInfo.AssignedRegs.Regs.empty()) { 8991 emitInlineAsmError(Call, 8992 "couldn't allocate input reg for constraint '" + 8993 Twine(OpInfo.ConstraintCode) + "'"); 8994 return; 8995 } 8996 8997 if (DetectWriteToReservedRegister()) 8998 return; 8999 9000 SDLoc dl = getCurSDLoc(); 9001 9002 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, dl, Chain, &Flag, 9003 &Call); 9004 9005 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0, 9006 dl, DAG, AsmNodeOperands); 9007 break; 9008 } 9009 case InlineAsm::isClobber: 9010 // Add the clobbered value to the operand list, so that the register 9011 // allocator is aware that the physreg got clobbered. 9012 if (!OpInfo.AssignedRegs.Regs.empty()) 9013 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber, 9014 false, 0, getCurSDLoc(), DAG, 9015 AsmNodeOperands); 9016 break; 9017 } 9018 } 9019 9020 // Finish up input operands. Set the input chain and add the flag last. 9021 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain; 9022 if (Flag.getNode()) AsmNodeOperands.push_back(Flag); 9023 9024 unsigned ISDOpc = IsCallBr ? ISD::INLINEASM_BR : ISD::INLINEASM; 9025 Chain = DAG.getNode(ISDOpc, getCurSDLoc(), 9026 DAG.getVTList(MVT::Other, MVT::Glue), AsmNodeOperands); 9027 Flag = Chain.getValue(1); 9028 9029 // Do additional work to generate outputs. 9030 9031 SmallVector<EVT, 1> ResultVTs; 9032 SmallVector<SDValue, 1> ResultValues; 9033 SmallVector<SDValue, 8> OutChains; 9034 9035 llvm::Type *CallResultType = Call.getType(); 9036 ArrayRef<Type *> ResultTypes; 9037 if (StructType *StructResult = dyn_cast<StructType>(CallResultType)) 9038 ResultTypes = StructResult->elements(); 9039 else if (!CallResultType->isVoidTy()) 9040 ResultTypes = makeArrayRef(CallResultType); 9041 9042 auto CurResultType = ResultTypes.begin(); 9043 auto handleRegAssign = [&](SDValue V) { 9044 assert(CurResultType != ResultTypes.end() && "Unexpected value"); 9045 assert((*CurResultType)->isSized() && "Unexpected unsized type"); 9046 EVT ResultVT = TLI.getValueType(DAG.getDataLayout(), *CurResultType); 9047 ++CurResultType; 9048 // If the type of the inline asm call site return value is different but has 9049 // same size as the type of the asm output bitcast it. One example of this 9050 // is for vectors with different width / number of elements. This can 9051 // happen for register classes that can contain multiple different value 9052 // types. The preg or vreg allocated may not have the same VT as was 9053 // expected. 9054 // 9055 // This can also happen for a return value that disagrees with the register 9056 // class it is put in, eg. a double in a general-purpose register on a 9057 // 32-bit machine. 9058 if (ResultVT != V.getValueType() && 9059 ResultVT.getSizeInBits() == V.getValueSizeInBits()) 9060 V = DAG.getNode(ISD::BITCAST, getCurSDLoc(), ResultVT, V); 9061 else if (ResultVT != V.getValueType() && ResultVT.isInteger() && 9062 V.getValueType().isInteger()) { 9063 // If a result value was tied to an input value, the computed result 9064 // may have a wider width than the expected result. Extract the 9065 // relevant portion. 9066 V = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultVT, V); 9067 } 9068 assert(ResultVT == V.getValueType() && "Asm result value mismatch!"); 9069 ResultVTs.push_back(ResultVT); 9070 ResultValues.push_back(V); 9071 }; 9072 9073 // Deal with output operands. 9074 for (SDISelAsmOperandInfo &OpInfo : ConstraintOperands) { 9075 if (OpInfo.Type == InlineAsm::isOutput) { 9076 SDValue Val; 9077 // Skip trivial output operands. 9078 if (OpInfo.AssignedRegs.Regs.empty()) 9079 continue; 9080 9081 switch (OpInfo.ConstraintType) { 9082 case TargetLowering::C_Register: 9083 case TargetLowering::C_RegisterClass: 9084 Val = OpInfo.AssignedRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), 9085 Chain, &Flag, &Call); 9086 break; 9087 case TargetLowering::C_Immediate: 9088 case TargetLowering::C_Other: 9089 Val = TLI.LowerAsmOutputForConstraint(Chain, Flag, getCurSDLoc(), 9090 OpInfo, DAG); 9091 break; 9092 case TargetLowering::C_Memory: 9093 break; // Already handled. 9094 case TargetLowering::C_Address: 9095 break; // Silence warning. 9096 case TargetLowering::C_Unknown: 9097 assert(false && "Unexpected unknown constraint"); 9098 } 9099 9100 // Indirect output manifest as stores. Record output chains. 9101 if (OpInfo.isIndirect) { 9102 const Value *Ptr = OpInfo.CallOperandVal; 9103 assert(Ptr && "Expected value CallOperandVal for indirect asm operand"); 9104 SDValue Store = DAG.getStore(Chain, getCurSDLoc(), Val, getValue(Ptr), 9105 MachinePointerInfo(Ptr)); 9106 OutChains.push_back(Store); 9107 } else { 9108 // generate CopyFromRegs to associated registers. 9109 assert(!Call.getType()->isVoidTy() && "Bad inline asm!"); 9110 if (Val.getOpcode() == ISD::MERGE_VALUES) { 9111 for (const SDValue &V : Val->op_values()) 9112 handleRegAssign(V); 9113 } else 9114 handleRegAssign(Val); 9115 } 9116 } 9117 } 9118 9119 // Set results. 9120 if (!ResultValues.empty()) { 9121 assert(CurResultType == ResultTypes.end() && 9122 "Mismatch in number of ResultTypes"); 9123 assert(ResultValues.size() == ResultTypes.size() && 9124 "Mismatch in number of output operands in asm result"); 9125 9126 SDValue V = DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), 9127 DAG.getVTList(ResultVTs), ResultValues); 9128 setValue(&Call, V); 9129 } 9130 9131 // Collect store chains. 9132 if (!OutChains.empty()) 9133 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, OutChains); 9134 9135 if (EmitEHLabels) { 9136 Chain = lowerEndEH(Chain, cast<InvokeInst>(&Call), EHPadBB, BeginLabel); 9137 } 9138 9139 // Only Update Root if inline assembly has a memory effect. 9140 if (ResultValues.empty() || HasSideEffect || !OutChains.empty() || IsCallBr || 9141 EmitEHLabels) 9142 DAG.setRoot(Chain); 9143 } 9144 9145 void SelectionDAGBuilder::emitInlineAsmError(const CallBase &Call, 9146 const Twine &Message) { 9147 LLVMContext &Ctx = *DAG.getContext(); 9148 Ctx.emitError(&Call, Message); 9149 9150 // Make sure we leave the DAG in a valid state 9151 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 9152 SmallVector<EVT, 1> ValueVTs; 9153 ComputeValueVTs(TLI, DAG.getDataLayout(), Call.getType(), ValueVTs); 9154 9155 if (ValueVTs.empty()) 9156 return; 9157 9158 SmallVector<SDValue, 1> Ops; 9159 for (unsigned i = 0, e = ValueVTs.size(); i != e; ++i) 9160 Ops.push_back(DAG.getUNDEF(ValueVTs[i])); 9161 9162 setValue(&Call, DAG.getMergeValues(Ops, getCurSDLoc())); 9163 } 9164 9165 void SelectionDAGBuilder::visitVAStart(const CallInst &I) { 9166 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(), 9167 MVT::Other, getRoot(), 9168 getValue(I.getArgOperand(0)), 9169 DAG.getSrcValue(I.getArgOperand(0)))); 9170 } 9171 9172 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) { 9173 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 9174 const DataLayout &DL = DAG.getDataLayout(); 9175 SDValue V = DAG.getVAArg( 9176 TLI.getMemValueType(DAG.getDataLayout(), I.getType()), getCurSDLoc(), 9177 getRoot(), getValue(I.getOperand(0)), DAG.getSrcValue(I.getOperand(0)), 9178 DL.getABITypeAlign(I.getType()).value()); 9179 DAG.setRoot(V.getValue(1)); 9180 9181 if (I.getType()->isPointerTy()) 9182 V = DAG.getPtrExtOrTrunc( 9183 V, getCurSDLoc(), TLI.getValueType(DAG.getDataLayout(), I.getType())); 9184 setValue(&I, V); 9185 } 9186 9187 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) { 9188 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(), 9189 MVT::Other, getRoot(), 9190 getValue(I.getArgOperand(0)), 9191 DAG.getSrcValue(I.getArgOperand(0)))); 9192 } 9193 9194 void SelectionDAGBuilder::visitVACopy(const CallInst &I) { 9195 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(), 9196 MVT::Other, getRoot(), 9197 getValue(I.getArgOperand(0)), 9198 getValue(I.getArgOperand(1)), 9199 DAG.getSrcValue(I.getArgOperand(0)), 9200 DAG.getSrcValue(I.getArgOperand(1)))); 9201 } 9202 9203 SDValue SelectionDAGBuilder::lowerRangeToAssertZExt(SelectionDAG &DAG, 9204 const Instruction &I, 9205 SDValue Op) { 9206 const MDNode *Range = I.getMetadata(LLVMContext::MD_range); 9207 if (!Range) 9208 return Op; 9209 9210 ConstantRange CR = getConstantRangeFromMetadata(*Range); 9211 if (CR.isFullSet() || CR.isEmptySet() || CR.isUpperWrapped()) 9212 return Op; 9213 9214 APInt Lo = CR.getUnsignedMin(); 9215 if (!Lo.isMinValue()) 9216 return Op; 9217 9218 APInt Hi = CR.getUnsignedMax(); 9219 unsigned Bits = std::max(Hi.getActiveBits(), 9220 static_cast<unsigned>(IntegerType::MIN_INT_BITS)); 9221 9222 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), Bits); 9223 9224 SDLoc SL = getCurSDLoc(); 9225 9226 SDValue ZExt = DAG.getNode(ISD::AssertZext, SL, Op.getValueType(), Op, 9227 DAG.getValueType(SmallVT)); 9228 unsigned NumVals = Op.getNode()->getNumValues(); 9229 if (NumVals == 1) 9230 return ZExt; 9231 9232 SmallVector<SDValue, 4> Ops; 9233 9234 Ops.push_back(ZExt); 9235 for (unsigned I = 1; I != NumVals; ++I) 9236 Ops.push_back(Op.getValue(I)); 9237 9238 return DAG.getMergeValues(Ops, SL); 9239 } 9240 9241 /// Populate a CallLowerinInfo (into \p CLI) based on the properties of 9242 /// the call being lowered. 9243 /// 9244 /// This is a helper for lowering intrinsics that follow a target calling 9245 /// convention or require stack pointer adjustment. Only a subset of the 9246 /// intrinsic's operands need to participate in the calling convention. 9247 void SelectionDAGBuilder::populateCallLoweringInfo( 9248 TargetLowering::CallLoweringInfo &CLI, const CallBase *Call, 9249 unsigned ArgIdx, unsigned NumArgs, SDValue Callee, Type *ReturnTy, 9250 bool IsPatchPoint) { 9251 TargetLowering::ArgListTy Args; 9252 Args.reserve(NumArgs); 9253 9254 // Populate the argument list. 9255 // Attributes for args start at offset 1, after the return attribute. 9256 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs; 9257 ArgI != ArgE; ++ArgI) { 9258 const Value *V = Call->getOperand(ArgI); 9259 9260 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic."); 9261 9262 TargetLowering::ArgListEntry Entry; 9263 Entry.Node = getValue(V); 9264 Entry.Ty = V->getType(); 9265 Entry.setAttributes(Call, ArgI); 9266 Args.push_back(Entry); 9267 } 9268 9269 CLI.setDebugLoc(getCurSDLoc()) 9270 .setChain(getRoot()) 9271 .setCallee(Call->getCallingConv(), ReturnTy, Callee, std::move(Args)) 9272 .setDiscardResult(Call->use_empty()) 9273 .setIsPatchPoint(IsPatchPoint) 9274 .setIsPreallocated( 9275 Call->countOperandBundlesOfType(LLVMContext::OB_preallocated) != 0); 9276 } 9277 9278 /// Add a stack map intrinsic call's live variable operands to a stackmap 9279 /// or patchpoint target node's operand list. 9280 /// 9281 /// Constants are converted to TargetConstants purely as an optimization to 9282 /// avoid constant materialization and register allocation. 9283 /// 9284 /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not 9285 /// generate addess computation nodes, and so FinalizeISel can convert the 9286 /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids 9287 /// address materialization and register allocation, but may also be required 9288 /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an 9289 /// alloca in the entry block, then the runtime may assume that the alloca's 9290 /// StackMap location can be read immediately after compilation and that the 9291 /// location is valid at any point during execution (this is similar to the 9292 /// assumption made by the llvm.gcroot intrinsic). If the alloca's location were 9293 /// only available in a register, then the runtime would need to trap when 9294 /// execution reaches the StackMap in order to read the alloca's location. 9295 static void addStackMapLiveVars(const CallBase &Call, unsigned StartIdx, 9296 const SDLoc &DL, SmallVectorImpl<SDValue> &Ops, 9297 SelectionDAGBuilder &Builder) { 9298 for (unsigned i = StartIdx, e = Call.arg_size(); i != e; ++i) { 9299 SDValue OpVal = Builder.getValue(Call.getArgOperand(i)); 9300 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) { 9301 Ops.push_back( 9302 Builder.DAG.getTargetConstant(StackMaps::ConstantOp, DL, MVT::i64)); 9303 Ops.push_back( 9304 Builder.DAG.getTargetConstant(C->getSExtValue(), DL, MVT::i64)); 9305 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(OpVal)) { 9306 const TargetLowering &TLI = Builder.DAG.getTargetLoweringInfo(); 9307 Ops.push_back(Builder.DAG.getTargetFrameIndex( 9308 FI->getIndex(), TLI.getFrameIndexTy(Builder.DAG.getDataLayout()))); 9309 } else 9310 Ops.push_back(OpVal); 9311 } 9312 } 9313 9314 /// Lower llvm.experimental.stackmap. 9315 void SelectionDAGBuilder::visitStackmap(const CallInst &CI) { 9316 // void @llvm.experimental.stackmap(i64 <id>, i32 <numShadowBytes>, 9317 // [live variables...]) 9318 9319 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value."); 9320 9321 SDValue Chain, InFlag, Callee, NullPtr; 9322 SmallVector<SDValue, 32> Ops; 9323 9324 SDLoc DL = getCurSDLoc(); 9325 Callee = getValue(CI.getCalledOperand()); 9326 NullPtr = DAG.getIntPtrConstant(0, DL, true); 9327 9328 // The stackmap intrinsic only records the live variables (the arguments 9329 // passed to it) and emits NOPS (if requested). Unlike the patchpoint 9330 // intrinsic, this won't be lowered to a function call. This means we don't 9331 // have to worry about calling conventions and target specific lowering code. 9332 // Instead we perform the call lowering right here. 9333 // 9334 // chain, flag = CALLSEQ_START(chain, 0, 0) 9335 // chain, flag = STACKMAP(id, nbytes, ..., chain, flag) 9336 // chain, flag = CALLSEQ_END(chain, 0, 0, flag) 9337 // 9338 Chain = DAG.getCALLSEQ_START(getRoot(), 0, 0, DL); 9339 InFlag = Chain.getValue(1); 9340 9341 // Add the STACKMAP operands, starting with DAG house-keeping. 9342 Ops.push_back(Chain); 9343 Ops.push_back(InFlag); 9344 9345 // Add the <id>, <numShadowBytes> operands. 9346 // 9347 // These do not require legalisation, and can be emitted directly to target 9348 // constant nodes. 9349 SDValue ID = getValue(CI.getArgOperand(0)); 9350 assert(ID.getValueType() == MVT::i64); 9351 SDValue IDConst = DAG.getTargetConstant( 9352 cast<ConstantSDNode>(ID)->getZExtValue(), DL, ID.getValueType()); 9353 Ops.push_back(IDConst); 9354 9355 SDValue Shad = getValue(CI.getArgOperand(1)); 9356 assert(Shad.getValueType() == MVT::i32); 9357 SDValue ShadConst = DAG.getTargetConstant( 9358 cast<ConstantSDNode>(Shad)->getZExtValue(), DL, Shad.getValueType()); 9359 Ops.push_back(ShadConst); 9360 9361 // Add the live variables. 9362 for (unsigned I = 2; I < CI.arg_size(); I++) { 9363 SDValue Op = getValue(CI.getArgOperand(I)); 9364 9365 // Things on the stack are pointer-typed, meaning that they are already 9366 // legal and can be emitted directly to target nodes. 9367 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) { 9368 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 9369 Ops.push_back(DAG.getTargetFrameIndex( 9370 FI->getIndex(), TLI.getFrameIndexTy(DAG.getDataLayout()))); 9371 } else { 9372 // Otherwise emit a target independent node to be legalised. 9373 Ops.push_back(getValue(CI.getArgOperand(I))); 9374 } 9375 } 9376 9377 // Create the STACKMAP node. 9378 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 9379 Chain = DAG.getNode(ISD::STACKMAP, DL, NodeTys, Ops); 9380 InFlag = Chain.getValue(1); 9381 9382 Chain = DAG.getCALLSEQ_END(Chain, NullPtr, NullPtr, InFlag, DL); 9383 9384 // Stackmaps don't generate values, so nothing goes into the NodeMap. 9385 9386 // Set the root to the target-lowered call chain. 9387 DAG.setRoot(Chain); 9388 9389 // Inform the Frame Information that we have a stackmap in this function. 9390 FuncInfo.MF->getFrameInfo().setHasStackMap(); 9391 } 9392 9393 /// Lower llvm.experimental.patchpoint directly to its target opcode. 9394 void SelectionDAGBuilder::visitPatchpoint(const CallBase &CB, 9395 const BasicBlock *EHPadBB) { 9396 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>, 9397 // i32 <numBytes>, 9398 // i8* <target>, 9399 // i32 <numArgs>, 9400 // [Args...], 9401 // [live variables...]) 9402 9403 CallingConv::ID CC = CB.getCallingConv(); 9404 bool IsAnyRegCC = CC == CallingConv::AnyReg; 9405 bool HasDef = !CB.getType()->isVoidTy(); 9406 SDLoc dl = getCurSDLoc(); 9407 SDValue Callee = getValue(CB.getArgOperand(PatchPointOpers::TargetPos)); 9408 9409 // Handle immediate and symbolic callees. 9410 if (auto* ConstCallee = dyn_cast<ConstantSDNode>(Callee)) 9411 Callee = DAG.getIntPtrConstant(ConstCallee->getZExtValue(), dl, 9412 /*isTarget=*/true); 9413 else if (auto* SymbolicCallee = dyn_cast<GlobalAddressSDNode>(Callee)) 9414 Callee = DAG.getTargetGlobalAddress(SymbolicCallee->getGlobal(), 9415 SDLoc(SymbolicCallee), 9416 SymbolicCallee->getValueType(0)); 9417 9418 // Get the real number of arguments participating in the call <numArgs> 9419 SDValue NArgVal = getValue(CB.getArgOperand(PatchPointOpers::NArgPos)); 9420 unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue(); 9421 9422 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs> 9423 // Intrinsics include all meta-operands up to but not including CC. 9424 unsigned NumMetaOpers = PatchPointOpers::CCPos; 9425 assert(CB.arg_size() >= NumMetaOpers + NumArgs && 9426 "Not enough arguments provided to the patchpoint intrinsic"); 9427 9428 // For AnyRegCC the arguments are lowered later on manually. 9429 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs; 9430 Type *ReturnTy = 9431 IsAnyRegCC ? Type::getVoidTy(*DAG.getContext()) : CB.getType(); 9432 9433 TargetLowering::CallLoweringInfo CLI(DAG); 9434 populateCallLoweringInfo(CLI, &CB, NumMetaOpers, NumCallArgs, Callee, 9435 ReturnTy, true); 9436 std::pair<SDValue, SDValue> Result = lowerInvokable(CLI, EHPadBB); 9437 9438 SDNode *CallEnd = Result.second.getNode(); 9439 if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg)) 9440 CallEnd = CallEnd->getOperand(0).getNode(); 9441 9442 /// Get a call instruction from the call sequence chain. 9443 /// Tail calls are not allowed. 9444 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END && 9445 "Expected a callseq node."); 9446 SDNode *Call = CallEnd->getOperand(0).getNode(); 9447 bool HasGlue = Call->getGluedNode(); 9448 9449 // Replace the target specific call node with the patchable intrinsic. 9450 SmallVector<SDValue, 8> Ops; 9451 9452 // Add the <id> and <numBytes> constants. 9453 SDValue IDVal = getValue(CB.getArgOperand(PatchPointOpers::IDPos)); 9454 Ops.push_back(DAG.getTargetConstant( 9455 cast<ConstantSDNode>(IDVal)->getZExtValue(), dl, MVT::i64)); 9456 SDValue NBytesVal = getValue(CB.getArgOperand(PatchPointOpers::NBytesPos)); 9457 Ops.push_back(DAG.getTargetConstant( 9458 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), dl, 9459 MVT::i32)); 9460 9461 // Add the callee. 9462 Ops.push_back(Callee); 9463 9464 // Adjust <numArgs> to account for any arguments that have been passed on the 9465 // stack instead. 9466 // Call Node: Chain, Target, {Args}, RegMask, [Glue] 9467 unsigned NumCallRegArgs = Call->getNumOperands() - (HasGlue ? 4 : 3); 9468 NumCallRegArgs = IsAnyRegCC ? NumArgs : NumCallRegArgs; 9469 Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, dl, MVT::i32)); 9470 9471 // Add the calling convention 9472 Ops.push_back(DAG.getTargetConstant((unsigned)CC, dl, MVT::i32)); 9473 9474 // Add the arguments we omitted previously. The register allocator should 9475 // place these in any free register. 9476 if (IsAnyRegCC) 9477 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i) 9478 Ops.push_back(getValue(CB.getArgOperand(i))); 9479 9480 // Push the arguments from the call instruction up to the register mask. 9481 SDNode::op_iterator e = HasGlue ? Call->op_end()-2 : Call->op_end()-1; 9482 Ops.append(Call->op_begin() + 2, e); 9483 9484 // Push live variables for the stack map. 9485 addStackMapLiveVars(CB, NumMetaOpers + NumArgs, dl, Ops, *this); 9486 9487 // Push the register mask info. 9488 if (HasGlue) 9489 Ops.push_back(*(Call->op_end()-2)); 9490 else 9491 Ops.push_back(*(Call->op_end()-1)); 9492 9493 // Push the chain (this is originally the first operand of the call, but 9494 // becomes now the last or second to last operand). 9495 Ops.push_back(*(Call->op_begin())); 9496 9497 // Push the glue flag (last operand). 9498 if (HasGlue) 9499 Ops.push_back(*(Call->op_end()-1)); 9500 9501 SDVTList NodeTys; 9502 if (IsAnyRegCC && HasDef) { 9503 // Create the return types based on the intrinsic definition 9504 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 9505 SmallVector<EVT, 3> ValueVTs; 9506 ComputeValueVTs(TLI, DAG.getDataLayout(), CB.getType(), ValueVTs); 9507 assert(ValueVTs.size() == 1 && "Expected only one return value type."); 9508 9509 // There is always a chain and a glue type at the end 9510 ValueVTs.push_back(MVT::Other); 9511 ValueVTs.push_back(MVT::Glue); 9512 NodeTys = DAG.getVTList(ValueVTs); 9513 } else 9514 NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 9515 9516 // Replace the target specific call node with a PATCHPOINT node. 9517 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHPOINT, 9518 dl, NodeTys, Ops); 9519 9520 // Update the NodeMap. 9521 if (HasDef) { 9522 if (IsAnyRegCC) 9523 setValue(&CB, SDValue(MN, 0)); 9524 else 9525 setValue(&CB, Result.first); 9526 } 9527 9528 // Fixup the consumers of the intrinsic. The chain and glue may be used in the 9529 // call sequence. Furthermore the location of the chain and glue can change 9530 // when the AnyReg calling convention is used and the intrinsic returns a 9531 // value. 9532 if (IsAnyRegCC && HasDef) { 9533 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)}; 9534 SDValue To[] = {SDValue(MN, 1), SDValue(MN, 2)}; 9535 DAG.ReplaceAllUsesOfValuesWith(From, To, 2); 9536 } else 9537 DAG.ReplaceAllUsesWith(Call, MN); 9538 DAG.DeleteNode(Call); 9539 9540 // Inform the Frame Information that we have a patchpoint in this function. 9541 FuncInfo.MF->getFrameInfo().setHasPatchPoint(); 9542 } 9543 9544 void SelectionDAGBuilder::visitVectorReduce(const CallInst &I, 9545 unsigned Intrinsic) { 9546 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 9547 SDValue Op1 = getValue(I.getArgOperand(0)); 9548 SDValue Op2; 9549 if (I.arg_size() > 1) 9550 Op2 = getValue(I.getArgOperand(1)); 9551 SDLoc dl = getCurSDLoc(); 9552 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType()); 9553 SDValue Res; 9554 SDNodeFlags SDFlags; 9555 if (auto *FPMO = dyn_cast<FPMathOperator>(&I)) 9556 SDFlags.copyFMF(*FPMO); 9557 9558 switch (Intrinsic) { 9559 case Intrinsic::vector_reduce_fadd: 9560 if (SDFlags.hasAllowReassociation()) 9561 Res = DAG.getNode(ISD::FADD, dl, VT, Op1, 9562 DAG.getNode(ISD::VECREDUCE_FADD, dl, VT, Op2, SDFlags), 9563 SDFlags); 9564 else 9565 Res = DAG.getNode(ISD::VECREDUCE_SEQ_FADD, dl, VT, Op1, Op2, SDFlags); 9566 break; 9567 case Intrinsic::vector_reduce_fmul: 9568 if (SDFlags.hasAllowReassociation()) 9569 Res = DAG.getNode(ISD::FMUL, dl, VT, Op1, 9570 DAG.getNode(ISD::VECREDUCE_FMUL, dl, VT, Op2, SDFlags), 9571 SDFlags); 9572 else 9573 Res = DAG.getNode(ISD::VECREDUCE_SEQ_FMUL, dl, VT, Op1, Op2, SDFlags); 9574 break; 9575 case Intrinsic::vector_reduce_add: 9576 Res = DAG.getNode(ISD::VECREDUCE_ADD, dl, VT, Op1); 9577 break; 9578 case Intrinsic::vector_reduce_mul: 9579 Res = DAG.getNode(ISD::VECREDUCE_MUL, dl, VT, Op1); 9580 break; 9581 case Intrinsic::vector_reduce_and: 9582 Res = DAG.getNode(ISD::VECREDUCE_AND, dl, VT, Op1); 9583 break; 9584 case Intrinsic::vector_reduce_or: 9585 Res = DAG.getNode(ISD::VECREDUCE_OR, dl, VT, Op1); 9586 break; 9587 case Intrinsic::vector_reduce_xor: 9588 Res = DAG.getNode(ISD::VECREDUCE_XOR, dl, VT, Op1); 9589 break; 9590 case Intrinsic::vector_reduce_smax: 9591 Res = DAG.getNode(ISD::VECREDUCE_SMAX, dl, VT, Op1); 9592 break; 9593 case Intrinsic::vector_reduce_smin: 9594 Res = DAG.getNode(ISD::VECREDUCE_SMIN, dl, VT, Op1); 9595 break; 9596 case Intrinsic::vector_reduce_umax: 9597 Res = DAG.getNode(ISD::VECREDUCE_UMAX, dl, VT, Op1); 9598 break; 9599 case Intrinsic::vector_reduce_umin: 9600 Res = DAG.getNode(ISD::VECREDUCE_UMIN, dl, VT, Op1); 9601 break; 9602 case Intrinsic::vector_reduce_fmax: 9603 Res = DAG.getNode(ISD::VECREDUCE_FMAX, dl, VT, Op1, SDFlags); 9604 break; 9605 case Intrinsic::vector_reduce_fmin: 9606 Res = DAG.getNode(ISD::VECREDUCE_FMIN, dl, VT, Op1, SDFlags); 9607 break; 9608 default: 9609 llvm_unreachable("Unhandled vector reduce intrinsic"); 9610 } 9611 setValue(&I, Res); 9612 } 9613 9614 /// Returns an AttributeList representing the attributes applied to the return 9615 /// value of the given call. 9616 static AttributeList getReturnAttrs(TargetLowering::CallLoweringInfo &CLI) { 9617 SmallVector<Attribute::AttrKind, 2> Attrs; 9618 if (CLI.RetSExt) 9619 Attrs.push_back(Attribute::SExt); 9620 if (CLI.RetZExt) 9621 Attrs.push_back(Attribute::ZExt); 9622 if (CLI.IsInReg) 9623 Attrs.push_back(Attribute::InReg); 9624 9625 return AttributeList::get(CLI.RetTy->getContext(), AttributeList::ReturnIndex, 9626 Attrs); 9627 } 9628 9629 /// TargetLowering::LowerCallTo - This is the default LowerCallTo 9630 /// implementation, which just calls LowerCall. 9631 /// FIXME: When all targets are 9632 /// migrated to using LowerCall, this hook should be integrated into SDISel. 9633 std::pair<SDValue, SDValue> 9634 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const { 9635 // Handle the incoming return values from the call. 9636 CLI.Ins.clear(); 9637 Type *OrigRetTy = CLI.RetTy; 9638 SmallVector<EVT, 4> RetTys; 9639 SmallVector<uint64_t, 4> Offsets; 9640 auto &DL = CLI.DAG.getDataLayout(); 9641 ComputeValueVTs(*this, DL, CLI.RetTy, RetTys, &Offsets); 9642 9643 if (CLI.IsPostTypeLegalization) { 9644 // If we are lowering a libcall after legalization, split the return type. 9645 SmallVector<EVT, 4> OldRetTys; 9646 SmallVector<uint64_t, 4> OldOffsets; 9647 RetTys.swap(OldRetTys); 9648 Offsets.swap(OldOffsets); 9649 9650 for (size_t i = 0, e = OldRetTys.size(); i != e; ++i) { 9651 EVT RetVT = OldRetTys[i]; 9652 uint64_t Offset = OldOffsets[i]; 9653 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), RetVT); 9654 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), RetVT); 9655 unsigned RegisterVTByteSZ = RegisterVT.getSizeInBits() / 8; 9656 RetTys.append(NumRegs, RegisterVT); 9657 for (unsigned j = 0; j != NumRegs; ++j) 9658 Offsets.push_back(Offset + j * RegisterVTByteSZ); 9659 } 9660 } 9661 9662 SmallVector<ISD::OutputArg, 4> Outs; 9663 GetReturnInfo(CLI.CallConv, CLI.RetTy, getReturnAttrs(CLI), Outs, *this, DL); 9664 9665 bool CanLowerReturn = 9666 this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(), 9667 CLI.IsVarArg, Outs, CLI.RetTy->getContext()); 9668 9669 SDValue DemoteStackSlot; 9670 int DemoteStackIdx = -100; 9671 if (!CanLowerReturn) { 9672 // FIXME: equivalent assert? 9673 // assert(!CS.hasInAllocaArgument() && 9674 // "sret demotion is incompatible with inalloca"); 9675 uint64_t TySize = DL.getTypeAllocSize(CLI.RetTy); 9676 Align Alignment = DL.getPrefTypeAlign(CLI.RetTy); 9677 MachineFunction &MF = CLI.DAG.getMachineFunction(); 9678 DemoteStackIdx = 9679 MF.getFrameInfo().CreateStackObject(TySize, Alignment, false); 9680 Type *StackSlotPtrType = PointerType::get(CLI.RetTy, 9681 DL.getAllocaAddrSpace()); 9682 9683 DemoteStackSlot = CLI.DAG.getFrameIndex(DemoteStackIdx, getFrameIndexTy(DL)); 9684 ArgListEntry Entry; 9685 Entry.Node = DemoteStackSlot; 9686 Entry.Ty = StackSlotPtrType; 9687 Entry.IsSExt = false; 9688 Entry.IsZExt = false; 9689 Entry.IsInReg = false; 9690 Entry.IsSRet = true; 9691 Entry.IsNest = false; 9692 Entry.IsByVal = false; 9693 Entry.IsByRef = false; 9694 Entry.IsReturned = false; 9695 Entry.IsSwiftSelf = false; 9696 Entry.IsSwiftAsync = false; 9697 Entry.IsSwiftError = false; 9698 Entry.IsCFGuardTarget = false; 9699 Entry.Alignment = Alignment; 9700 CLI.getArgs().insert(CLI.getArgs().begin(), Entry); 9701 CLI.NumFixedArgs += 1; 9702 CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext()); 9703 9704 // sret demotion isn't compatible with tail-calls, since the sret argument 9705 // points into the callers stack frame. 9706 CLI.IsTailCall = false; 9707 } else { 9708 bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters( 9709 CLI.RetTy, CLI.CallConv, CLI.IsVarArg, DL); 9710 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 9711 ISD::ArgFlagsTy Flags; 9712 if (NeedsRegBlock) { 9713 Flags.setInConsecutiveRegs(); 9714 if (I == RetTys.size() - 1) 9715 Flags.setInConsecutiveRegsLast(); 9716 } 9717 EVT VT = RetTys[I]; 9718 MVT RegisterVT = getRegisterTypeForCallingConv(CLI.RetTy->getContext(), 9719 CLI.CallConv, VT); 9720 unsigned NumRegs = getNumRegistersForCallingConv(CLI.RetTy->getContext(), 9721 CLI.CallConv, VT); 9722 for (unsigned i = 0; i != NumRegs; ++i) { 9723 ISD::InputArg MyFlags; 9724 MyFlags.Flags = Flags; 9725 MyFlags.VT = RegisterVT; 9726 MyFlags.ArgVT = VT; 9727 MyFlags.Used = CLI.IsReturnValueUsed; 9728 if (CLI.RetTy->isPointerTy()) { 9729 MyFlags.Flags.setPointer(); 9730 MyFlags.Flags.setPointerAddrSpace( 9731 cast<PointerType>(CLI.RetTy)->getAddressSpace()); 9732 } 9733 if (CLI.RetSExt) 9734 MyFlags.Flags.setSExt(); 9735 if (CLI.RetZExt) 9736 MyFlags.Flags.setZExt(); 9737 if (CLI.IsInReg) 9738 MyFlags.Flags.setInReg(); 9739 CLI.Ins.push_back(MyFlags); 9740 } 9741 } 9742 } 9743 9744 // We push in swifterror return as the last element of CLI.Ins. 9745 ArgListTy &Args = CLI.getArgs(); 9746 if (supportSwiftError()) { 9747 for (const ArgListEntry &Arg : Args) { 9748 if (Arg.IsSwiftError) { 9749 ISD::InputArg MyFlags; 9750 MyFlags.VT = getPointerTy(DL); 9751 MyFlags.ArgVT = EVT(getPointerTy(DL)); 9752 MyFlags.Flags.setSwiftError(); 9753 CLI.Ins.push_back(MyFlags); 9754 } 9755 } 9756 } 9757 9758 // Handle all of the outgoing arguments. 9759 CLI.Outs.clear(); 9760 CLI.OutVals.clear(); 9761 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 9762 SmallVector<EVT, 4> ValueVTs; 9763 ComputeValueVTs(*this, DL, Args[i].Ty, ValueVTs); 9764 // FIXME: Split arguments if CLI.IsPostTypeLegalization 9765 Type *FinalType = Args[i].Ty; 9766 if (Args[i].IsByVal) 9767 FinalType = Args[i].IndirectType; 9768 bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters( 9769 FinalType, CLI.CallConv, CLI.IsVarArg, DL); 9770 for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues; 9771 ++Value) { 9772 EVT VT = ValueVTs[Value]; 9773 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext()); 9774 SDValue Op = SDValue(Args[i].Node.getNode(), 9775 Args[i].Node.getResNo() + Value); 9776 ISD::ArgFlagsTy Flags; 9777 9778 // Certain targets (such as MIPS), may have a different ABI alignment 9779 // for a type depending on the context. Give the target a chance to 9780 // specify the alignment it wants. 9781 const Align OriginalAlignment(getABIAlignmentForCallingConv(ArgTy, DL)); 9782 Flags.setOrigAlign(OriginalAlignment); 9783 9784 if (Args[i].Ty->isPointerTy()) { 9785 Flags.setPointer(); 9786 Flags.setPointerAddrSpace( 9787 cast<PointerType>(Args[i].Ty)->getAddressSpace()); 9788 } 9789 if (Args[i].IsZExt) 9790 Flags.setZExt(); 9791 if (Args[i].IsSExt) 9792 Flags.setSExt(); 9793 if (Args[i].IsInReg) { 9794 // If we are using vectorcall calling convention, a structure that is 9795 // passed InReg - is surely an HVA 9796 if (CLI.CallConv == CallingConv::X86_VectorCall && 9797 isa<StructType>(FinalType)) { 9798 // The first value of a structure is marked 9799 if (0 == Value) 9800 Flags.setHvaStart(); 9801 Flags.setHva(); 9802 } 9803 // Set InReg Flag 9804 Flags.setInReg(); 9805 } 9806 if (Args[i].IsSRet) 9807 Flags.setSRet(); 9808 if (Args[i].IsSwiftSelf) 9809 Flags.setSwiftSelf(); 9810 if (Args[i].IsSwiftAsync) 9811 Flags.setSwiftAsync(); 9812 if (Args[i].IsSwiftError) 9813 Flags.setSwiftError(); 9814 if (Args[i].IsCFGuardTarget) 9815 Flags.setCFGuardTarget(); 9816 if (Args[i].IsByVal) 9817 Flags.setByVal(); 9818 if (Args[i].IsByRef) 9819 Flags.setByRef(); 9820 if (Args[i].IsPreallocated) { 9821 Flags.setPreallocated(); 9822 // Set the byval flag for CCAssignFn callbacks that don't know about 9823 // preallocated. This way we can know how many bytes we should've 9824 // allocated and how many bytes a callee cleanup function will pop. If 9825 // we port preallocated to more targets, we'll have to add custom 9826 // preallocated handling in the various CC lowering callbacks. 9827 Flags.setByVal(); 9828 } 9829 if (Args[i].IsInAlloca) { 9830 Flags.setInAlloca(); 9831 // Set the byval flag for CCAssignFn callbacks that don't know about 9832 // inalloca. This way we can know how many bytes we should've allocated 9833 // and how many bytes a callee cleanup function will pop. If we port 9834 // inalloca to more targets, we'll have to add custom inalloca handling 9835 // in the various CC lowering callbacks. 9836 Flags.setByVal(); 9837 } 9838 Align MemAlign; 9839 if (Args[i].IsByVal || Args[i].IsInAlloca || Args[i].IsPreallocated) { 9840 unsigned FrameSize = DL.getTypeAllocSize(Args[i].IndirectType); 9841 Flags.setByValSize(FrameSize); 9842 9843 // info is not there but there are cases it cannot get right. 9844 if (auto MA = Args[i].Alignment) 9845 MemAlign = *MA; 9846 else 9847 MemAlign = Align(getByValTypeAlignment(Args[i].IndirectType, DL)); 9848 } else if (auto MA = Args[i].Alignment) { 9849 MemAlign = *MA; 9850 } else { 9851 MemAlign = OriginalAlignment; 9852 } 9853 Flags.setMemAlign(MemAlign); 9854 if (Args[i].IsNest) 9855 Flags.setNest(); 9856 if (NeedsRegBlock) 9857 Flags.setInConsecutiveRegs(); 9858 9859 MVT PartVT = getRegisterTypeForCallingConv(CLI.RetTy->getContext(), 9860 CLI.CallConv, VT); 9861 unsigned NumParts = getNumRegistersForCallingConv(CLI.RetTy->getContext(), 9862 CLI.CallConv, VT); 9863 SmallVector<SDValue, 4> Parts(NumParts); 9864 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 9865 9866 if (Args[i].IsSExt) 9867 ExtendKind = ISD::SIGN_EXTEND; 9868 else if (Args[i].IsZExt) 9869 ExtendKind = ISD::ZERO_EXTEND; 9870 9871 // Conservatively only handle 'returned' on non-vectors that can be lowered, 9872 // for now. 9873 if (Args[i].IsReturned && !Op.getValueType().isVector() && 9874 CanLowerReturn) { 9875 assert((CLI.RetTy == Args[i].Ty || 9876 (CLI.RetTy->isPointerTy() && Args[i].Ty->isPointerTy() && 9877 CLI.RetTy->getPointerAddressSpace() == 9878 Args[i].Ty->getPointerAddressSpace())) && 9879 RetTys.size() == NumValues && "unexpected use of 'returned'"); 9880 // Before passing 'returned' to the target lowering code, ensure that 9881 // either the register MVT and the actual EVT are the same size or that 9882 // the return value and argument are extended in the same way; in these 9883 // cases it's safe to pass the argument register value unchanged as the 9884 // return register value (although it's at the target's option whether 9885 // to do so) 9886 // TODO: allow code generation to take advantage of partially preserved 9887 // registers rather than clobbering the entire register when the 9888 // parameter extension method is not compatible with the return 9889 // extension method 9890 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) || 9891 (ExtendKind != ISD::ANY_EXTEND && CLI.RetSExt == Args[i].IsSExt && 9892 CLI.RetZExt == Args[i].IsZExt)) 9893 Flags.setReturned(); 9894 } 9895 9896 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT, CLI.CB, 9897 CLI.CallConv, ExtendKind); 9898 9899 for (unsigned j = 0; j != NumParts; ++j) { 9900 // if it isn't first piece, alignment must be 1 9901 // For scalable vectors the scalable part is currently handled 9902 // by individual targets, so we just use the known minimum size here. 9903 ISD::OutputArg MyFlags( 9904 Flags, Parts[j].getValueType().getSimpleVT(), VT, 9905 i < CLI.NumFixedArgs, i, 9906 j * Parts[j].getValueType().getStoreSize().getKnownMinSize()); 9907 if (NumParts > 1 && j == 0) 9908 MyFlags.Flags.setSplit(); 9909 else if (j != 0) { 9910 MyFlags.Flags.setOrigAlign(Align(1)); 9911 if (j == NumParts - 1) 9912 MyFlags.Flags.setSplitEnd(); 9913 } 9914 9915 CLI.Outs.push_back(MyFlags); 9916 CLI.OutVals.push_back(Parts[j]); 9917 } 9918 9919 if (NeedsRegBlock && Value == NumValues - 1) 9920 CLI.Outs[CLI.Outs.size() - 1].Flags.setInConsecutiveRegsLast(); 9921 } 9922 } 9923 9924 SmallVector<SDValue, 4> InVals; 9925 CLI.Chain = LowerCall(CLI, InVals); 9926 9927 // Update CLI.InVals to use outside of this function. 9928 CLI.InVals = InVals; 9929 9930 // Verify that the target's LowerCall behaved as expected. 9931 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other && 9932 "LowerCall didn't return a valid chain!"); 9933 assert((!CLI.IsTailCall || InVals.empty()) && 9934 "LowerCall emitted a return value for a tail call!"); 9935 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) && 9936 "LowerCall didn't emit the correct number of values!"); 9937 9938 // For a tail call, the return value is merely live-out and there aren't 9939 // any nodes in the DAG representing it. Return a special value to 9940 // indicate that a tail call has been emitted and no more Instructions 9941 // should be processed in the current block. 9942 if (CLI.IsTailCall) { 9943 CLI.DAG.setRoot(CLI.Chain); 9944 return std::make_pair(SDValue(), SDValue()); 9945 } 9946 9947 #ifndef NDEBUG 9948 for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) { 9949 assert(InVals[i].getNode() && "LowerCall emitted a null value!"); 9950 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() && 9951 "LowerCall emitted a value with the wrong type!"); 9952 } 9953 #endif 9954 9955 SmallVector<SDValue, 4> ReturnValues; 9956 if (!CanLowerReturn) { 9957 // The instruction result is the result of loading from the 9958 // hidden sret parameter. 9959 SmallVector<EVT, 1> PVTs; 9960 Type *PtrRetTy = OrigRetTy->getPointerTo(DL.getAllocaAddrSpace()); 9961 9962 ComputeValueVTs(*this, DL, PtrRetTy, PVTs); 9963 assert(PVTs.size() == 1 && "Pointers should fit in one register"); 9964 EVT PtrVT = PVTs[0]; 9965 9966 unsigned NumValues = RetTys.size(); 9967 ReturnValues.resize(NumValues); 9968 SmallVector<SDValue, 4> Chains(NumValues); 9969 9970 // An aggregate return value cannot wrap around the address space, so 9971 // offsets to its parts don't wrap either. 9972 SDNodeFlags Flags; 9973 Flags.setNoUnsignedWrap(true); 9974 9975 MachineFunction &MF = CLI.DAG.getMachineFunction(); 9976 Align HiddenSRetAlign = MF.getFrameInfo().getObjectAlign(DemoteStackIdx); 9977 for (unsigned i = 0; i < NumValues; ++i) { 9978 SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot, 9979 CLI.DAG.getConstant(Offsets[i], CLI.DL, 9980 PtrVT), Flags); 9981 SDValue L = CLI.DAG.getLoad( 9982 RetTys[i], CLI.DL, CLI.Chain, Add, 9983 MachinePointerInfo::getFixedStack(CLI.DAG.getMachineFunction(), 9984 DemoteStackIdx, Offsets[i]), 9985 HiddenSRetAlign); 9986 ReturnValues[i] = L; 9987 Chains[i] = L.getValue(1); 9988 } 9989 9990 CLI.Chain = CLI.DAG.getNode(ISD::TokenFactor, CLI.DL, MVT::Other, Chains); 9991 } else { 9992 // Collect the legal value parts into potentially illegal values 9993 // that correspond to the original function's return values. 9994 Optional<ISD::NodeType> AssertOp; 9995 if (CLI.RetSExt) 9996 AssertOp = ISD::AssertSext; 9997 else if (CLI.RetZExt) 9998 AssertOp = ISD::AssertZext; 9999 unsigned CurReg = 0; 10000 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 10001 EVT VT = RetTys[I]; 10002 MVT RegisterVT = getRegisterTypeForCallingConv(CLI.RetTy->getContext(), 10003 CLI.CallConv, VT); 10004 unsigned NumRegs = getNumRegistersForCallingConv(CLI.RetTy->getContext(), 10005 CLI.CallConv, VT); 10006 10007 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg], 10008 NumRegs, RegisterVT, VT, nullptr, 10009 CLI.CallConv, AssertOp)); 10010 CurReg += NumRegs; 10011 } 10012 10013 // For a function returning void, there is no return value. We can't create 10014 // such a node, so we just return a null return value in that case. In 10015 // that case, nothing will actually look at the value. 10016 if (ReturnValues.empty()) 10017 return std::make_pair(SDValue(), CLI.Chain); 10018 } 10019 10020 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL, 10021 CLI.DAG.getVTList(RetTys), ReturnValues); 10022 return std::make_pair(Res, CLI.Chain); 10023 } 10024 10025 /// Places new result values for the node in Results (their number 10026 /// and types must exactly match those of the original return values of 10027 /// the node), or leaves Results empty, which indicates that the node is not 10028 /// to be custom lowered after all. 10029 void TargetLowering::LowerOperationWrapper(SDNode *N, 10030 SmallVectorImpl<SDValue> &Results, 10031 SelectionDAG &DAG) const { 10032 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 10033 10034 if (!Res.getNode()) 10035 return; 10036 10037 // If the original node has one result, take the return value from 10038 // LowerOperation as is. It might not be result number 0. 10039 if (N->getNumValues() == 1) { 10040 Results.push_back(Res); 10041 return; 10042 } 10043 10044 // If the original node has multiple results, then the return node should 10045 // have the same number of results. 10046 assert((N->getNumValues() == Res->getNumValues()) && 10047 "Lowering returned the wrong number of results!"); 10048 10049 // Places new result values base on N result number. 10050 for (unsigned I = 0, E = N->getNumValues(); I != E; ++I) 10051 Results.push_back(Res.getValue(I)); 10052 } 10053 10054 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 10055 llvm_unreachable("LowerOperation not implemented for this target!"); 10056 } 10057 10058 void SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, 10059 unsigned Reg, 10060 ISD::NodeType ExtendType) { 10061 SDValue Op = getNonRegisterValue(V); 10062 assert((Op.getOpcode() != ISD::CopyFromReg || 10063 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 10064 "Copy from a reg to the same reg!"); 10065 assert(!Register::isPhysicalRegister(Reg) && "Is a physreg"); 10066 10067 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 10068 // If this is an InlineAsm we have to match the registers required, not the 10069 // notional registers required by the type. 10070 10071 RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), Reg, V->getType(), 10072 None); // This is not an ABI copy. 10073 SDValue Chain = DAG.getEntryNode(); 10074 10075 if (ExtendType == ISD::ANY_EXTEND) { 10076 auto PreferredExtendIt = FuncInfo.PreferredExtendType.find(V); 10077 if (PreferredExtendIt != FuncInfo.PreferredExtendType.end()) 10078 ExtendType = PreferredExtendIt->second; 10079 } 10080 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, nullptr, V, ExtendType); 10081 PendingExports.push_back(Chain); 10082 } 10083 10084 #include "llvm/CodeGen/SelectionDAGISel.h" 10085 10086 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the 10087 /// entry block, return true. This includes arguments used by switches, since 10088 /// the switch may expand into multiple basic blocks. 10089 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) { 10090 // With FastISel active, we may be splitting blocks, so force creation 10091 // of virtual registers for all non-dead arguments. 10092 if (FastISel) 10093 return A->use_empty(); 10094 10095 const BasicBlock &Entry = A->getParent()->front(); 10096 for (const User *U : A->users()) 10097 if (cast<Instruction>(U)->getParent() != &Entry || isa<SwitchInst>(U)) 10098 return false; // Use not in entry block. 10099 10100 return true; 10101 } 10102 10103 using ArgCopyElisionMapTy = 10104 DenseMap<const Argument *, 10105 std::pair<const AllocaInst *, const StoreInst *>>; 10106 10107 /// Scan the entry block of the function in FuncInfo for arguments that look 10108 /// like copies into a local alloca. Record any copied arguments in 10109 /// ArgCopyElisionCandidates. 10110 static void 10111 findArgumentCopyElisionCandidates(const DataLayout &DL, 10112 FunctionLoweringInfo *FuncInfo, 10113 ArgCopyElisionMapTy &ArgCopyElisionCandidates) { 10114 // Record the state of every static alloca used in the entry block. Argument 10115 // allocas are all used in the entry block, so we need approximately as many 10116 // entries as we have arguments. 10117 enum StaticAllocaInfo { Unknown, Clobbered, Elidable }; 10118 SmallDenseMap<const AllocaInst *, StaticAllocaInfo, 8> StaticAllocas; 10119 unsigned NumArgs = FuncInfo->Fn->arg_size(); 10120 StaticAllocas.reserve(NumArgs * 2); 10121 10122 auto GetInfoIfStaticAlloca = [&](const Value *V) -> StaticAllocaInfo * { 10123 if (!V) 10124 return nullptr; 10125 V = V->stripPointerCasts(); 10126 const auto *AI = dyn_cast<AllocaInst>(V); 10127 if (!AI || !AI->isStaticAlloca() || !FuncInfo->StaticAllocaMap.count(AI)) 10128 return nullptr; 10129 auto Iter = StaticAllocas.insert({AI, Unknown}); 10130 return &Iter.first->second; 10131 }; 10132 10133 // Look for stores of arguments to static allocas. Look through bitcasts and 10134 // GEPs to handle type coercions, as long as the alloca is fully initialized 10135 // by the store. Any non-store use of an alloca escapes it and any subsequent 10136 // unanalyzed store might write it. 10137 // FIXME: Handle structs initialized with multiple stores. 10138 for (const Instruction &I : FuncInfo->Fn->getEntryBlock()) { 10139 // Look for stores, and handle non-store uses conservatively. 10140 const auto *SI = dyn_cast<StoreInst>(&I); 10141 if (!SI) { 10142 // We will look through cast uses, so ignore them completely. 10143 if (I.isCast()) 10144 continue; 10145 // Ignore debug info and pseudo op intrinsics, they don't escape or store 10146 // to allocas. 10147 if (I.isDebugOrPseudoInst()) 10148 continue; 10149 // This is an unknown instruction. Assume it escapes or writes to all 10150 // static alloca operands. 10151 for (const Use &U : I.operands()) { 10152 if (StaticAllocaInfo *Info = GetInfoIfStaticAlloca(U)) 10153 *Info = StaticAllocaInfo::Clobbered; 10154 } 10155 continue; 10156 } 10157 10158 // If the stored value is a static alloca, mark it as escaped. 10159 if (StaticAllocaInfo *Info = GetInfoIfStaticAlloca(SI->getValueOperand())) 10160 *Info = StaticAllocaInfo::Clobbered; 10161 10162 // Check if the destination is a static alloca. 10163 const Value *Dst = SI->getPointerOperand()->stripPointerCasts(); 10164 StaticAllocaInfo *Info = GetInfoIfStaticAlloca(Dst); 10165 if (!Info) 10166 continue; 10167 const AllocaInst *AI = cast<AllocaInst>(Dst); 10168 10169 // Skip allocas that have been initialized or clobbered. 10170 if (*Info != StaticAllocaInfo::Unknown) 10171 continue; 10172 10173 // Check if the stored value is an argument, and that this store fully 10174 // initializes the alloca. 10175 // If the argument type has padding bits we can't directly forward a pointer 10176 // as the upper bits may contain garbage. 10177 // Don't elide copies from the same argument twice. 10178 const Value *Val = SI->getValueOperand()->stripPointerCasts(); 10179 const auto *Arg = dyn_cast<Argument>(Val); 10180 if (!Arg || Arg->hasPassPointeeByValueCopyAttr() || 10181 Arg->getType()->isEmptyTy() || 10182 DL.getTypeStoreSize(Arg->getType()) != 10183 DL.getTypeAllocSize(AI->getAllocatedType()) || 10184 !DL.typeSizeEqualsStoreSize(Arg->getType()) || 10185 ArgCopyElisionCandidates.count(Arg)) { 10186 *Info = StaticAllocaInfo::Clobbered; 10187 continue; 10188 } 10189 10190 LLVM_DEBUG(dbgs() << "Found argument copy elision candidate: " << *AI 10191 << '\n'); 10192 10193 // Mark this alloca and store for argument copy elision. 10194 *Info = StaticAllocaInfo::Elidable; 10195 ArgCopyElisionCandidates.insert({Arg, {AI, SI}}); 10196 10197 // Stop scanning if we've seen all arguments. This will happen early in -O0 10198 // builds, which is useful, because -O0 builds have large entry blocks and 10199 // many allocas. 10200 if (ArgCopyElisionCandidates.size() == NumArgs) 10201 break; 10202 } 10203 } 10204 10205 /// Try to elide argument copies from memory into a local alloca. Succeeds if 10206 /// ArgVal is a load from a suitable fixed stack object. 10207 static void tryToElideArgumentCopy( 10208 FunctionLoweringInfo &FuncInfo, SmallVectorImpl<SDValue> &Chains, 10209 DenseMap<int, int> &ArgCopyElisionFrameIndexMap, 10210 SmallPtrSetImpl<const Instruction *> &ElidedArgCopyInstrs, 10211 ArgCopyElisionMapTy &ArgCopyElisionCandidates, const Argument &Arg, 10212 SDValue ArgVal, bool &ArgHasUses) { 10213 // Check if this is a load from a fixed stack object. 10214 auto *LNode = dyn_cast<LoadSDNode>(ArgVal); 10215 if (!LNode) 10216 return; 10217 auto *FINode = dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()); 10218 if (!FINode) 10219 return; 10220 10221 // Check that the fixed stack object is the right size and alignment. 10222 // Look at the alignment that the user wrote on the alloca instead of looking 10223 // at the stack object. 10224 auto ArgCopyIter = ArgCopyElisionCandidates.find(&Arg); 10225 assert(ArgCopyIter != ArgCopyElisionCandidates.end()); 10226 const AllocaInst *AI = ArgCopyIter->second.first; 10227 int FixedIndex = FINode->getIndex(); 10228 int &AllocaIndex = FuncInfo.StaticAllocaMap[AI]; 10229 int OldIndex = AllocaIndex; 10230 MachineFrameInfo &MFI = FuncInfo.MF->getFrameInfo(); 10231 if (MFI.getObjectSize(FixedIndex) != MFI.getObjectSize(OldIndex)) { 10232 LLVM_DEBUG( 10233 dbgs() << " argument copy elision failed due to bad fixed stack " 10234 "object size\n"); 10235 return; 10236 } 10237 Align RequiredAlignment = AI->getAlign(); 10238 if (MFI.getObjectAlign(FixedIndex) < RequiredAlignment) { 10239 LLVM_DEBUG(dbgs() << " argument copy elision failed: alignment of alloca " 10240 "greater than stack argument alignment (" 10241 << DebugStr(RequiredAlignment) << " vs " 10242 << DebugStr(MFI.getObjectAlign(FixedIndex)) << ")\n"); 10243 return; 10244 } 10245 10246 // Perform the elision. Delete the old stack object and replace its only use 10247 // in the variable info map. Mark the stack object as mutable. 10248 LLVM_DEBUG({ 10249 dbgs() << "Eliding argument copy from " << Arg << " to " << *AI << '\n' 10250 << " Replacing frame index " << OldIndex << " with " << FixedIndex 10251 << '\n'; 10252 }); 10253 MFI.RemoveStackObject(OldIndex); 10254 MFI.setIsImmutableObjectIndex(FixedIndex, false); 10255 AllocaIndex = FixedIndex; 10256 ArgCopyElisionFrameIndexMap.insert({OldIndex, FixedIndex}); 10257 Chains.push_back(ArgVal.getValue(1)); 10258 10259 // Avoid emitting code for the store implementing the copy. 10260 const StoreInst *SI = ArgCopyIter->second.second; 10261 ElidedArgCopyInstrs.insert(SI); 10262 10263 // Check for uses of the argument again so that we can avoid exporting ArgVal 10264 // if it is't used by anything other than the store. 10265 for (const Value *U : Arg.users()) { 10266 if (U != SI) { 10267 ArgHasUses = true; 10268 break; 10269 } 10270 } 10271 } 10272 10273 void SelectionDAGISel::LowerArguments(const Function &F) { 10274 SelectionDAG &DAG = SDB->DAG; 10275 SDLoc dl = SDB->getCurSDLoc(); 10276 const DataLayout &DL = DAG.getDataLayout(); 10277 SmallVector<ISD::InputArg, 16> Ins; 10278 10279 // In Naked functions we aren't going to save any registers. 10280 if (F.hasFnAttribute(Attribute::Naked)) 10281 return; 10282 10283 if (!FuncInfo->CanLowerReturn) { 10284 // Put in an sret pointer parameter before all the other parameters. 10285 SmallVector<EVT, 1> ValueVTs; 10286 ComputeValueVTs(*TLI, DAG.getDataLayout(), 10287 F.getReturnType()->getPointerTo( 10288 DAG.getDataLayout().getAllocaAddrSpace()), 10289 ValueVTs); 10290 10291 // NOTE: Assuming that a pointer will never break down to more than one VT 10292 // or one register. 10293 ISD::ArgFlagsTy Flags; 10294 Flags.setSRet(); 10295 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]); 10296 ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true, 10297 ISD::InputArg::NoArgIndex, 0); 10298 Ins.push_back(RetArg); 10299 } 10300 10301 // Look for stores of arguments to static allocas. Mark such arguments with a 10302 // flag to ask the target to give us the memory location of that argument if 10303 // available. 10304 ArgCopyElisionMapTy ArgCopyElisionCandidates; 10305 findArgumentCopyElisionCandidates(DL, FuncInfo.get(), 10306 ArgCopyElisionCandidates); 10307 10308 // Set up the incoming argument description vector. 10309 for (const Argument &Arg : F.args()) { 10310 unsigned ArgNo = Arg.getArgNo(); 10311 SmallVector<EVT, 4> ValueVTs; 10312 ComputeValueVTs(*TLI, DAG.getDataLayout(), Arg.getType(), ValueVTs); 10313 bool isArgValueUsed = !Arg.use_empty(); 10314 unsigned PartBase = 0; 10315 Type *FinalType = Arg.getType(); 10316 if (Arg.hasAttribute(Attribute::ByVal)) 10317 FinalType = Arg.getParamByValType(); 10318 bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters( 10319 FinalType, F.getCallingConv(), F.isVarArg(), DL); 10320 for (unsigned Value = 0, NumValues = ValueVTs.size(); 10321 Value != NumValues; ++Value) { 10322 EVT VT = ValueVTs[Value]; 10323 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext()); 10324 ISD::ArgFlagsTy Flags; 10325 10326 10327 if (Arg.getType()->isPointerTy()) { 10328 Flags.setPointer(); 10329 Flags.setPointerAddrSpace( 10330 cast<PointerType>(Arg.getType())->getAddressSpace()); 10331 } 10332 if (Arg.hasAttribute(Attribute::ZExt)) 10333 Flags.setZExt(); 10334 if (Arg.hasAttribute(Attribute::SExt)) 10335 Flags.setSExt(); 10336 if (Arg.hasAttribute(Attribute::InReg)) { 10337 // If we are using vectorcall calling convention, a structure that is 10338 // passed InReg - is surely an HVA 10339 if (F.getCallingConv() == CallingConv::X86_VectorCall && 10340 isa<StructType>(Arg.getType())) { 10341 // The first value of a structure is marked 10342 if (0 == Value) 10343 Flags.setHvaStart(); 10344 Flags.setHva(); 10345 } 10346 // Set InReg Flag 10347 Flags.setInReg(); 10348 } 10349 if (Arg.hasAttribute(Attribute::StructRet)) 10350 Flags.setSRet(); 10351 if (Arg.hasAttribute(Attribute::SwiftSelf)) 10352 Flags.setSwiftSelf(); 10353 if (Arg.hasAttribute(Attribute::SwiftAsync)) 10354 Flags.setSwiftAsync(); 10355 if (Arg.hasAttribute(Attribute::SwiftError)) 10356 Flags.setSwiftError(); 10357 if (Arg.hasAttribute(Attribute::ByVal)) 10358 Flags.setByVal(); 10359 if (Arg.hasAttribute(Attribute::ByRef)) 10360 Flags.setByRef(); 10361 if (Arg.hasAttribute(Attribute::InAlloca)) { 10362 Flags.setInAlloca(); 10363 // Set the byval flag for CCAssignFn callbacks that don't know about 10364 // inalloca. This way we can know how many bytes we should've allocated 10365 // and how many bytes a callee cleanup function will pop. If we port 10366 // inalloca to more targets, we'll have to add custom inalloca handling 10367 // in the various CC lowering callbacks. 10368 Flags.setByVal(); 10369 } 10370 if (Arg.hasAttribute(Attribute::Preallocated)) { 10371 Flags.setPreallocated(); 10372 // Set the byval flag for CCAssignFn callbacks that don't know about 10373 // preallocated. This way we can know how many bytes we should've 10374 // allocated and how many bytes a callee cleanup function will pop. If 10375 // we port preallocated to more targets, we'll have to add custom 10376 // preallocated handling in the various CC lowering callbacks. 10377 Flags.setByVal(); 10378 } 10379 10380 // Certain targets (such as MIPS), may have a different ABI alignment 10381 // for a type depending on the context. Give the target a chance to 10382 // specify the alignment it wants. 10383 const Align OriginalAlignment( 10384 TLI->getABIAlignmentForCallingConv(ArgTy, DL)); 10385 Flags.setOrigAlign(OriginalAlignment); 10386 10387 Align MemAlign; 10388 Type *ArgMemTy = nullptr; 10389 if (Flags.isByVal() || Flags.isInAlloca() || Flags.isPreallocated() || 10390 Flags.isByRef()) { 10391 if (!ArgMemTy) 10392 ArgMemTy = Arg.getPointeeInMemoryValueType(); 10393 10394 uint64_t MemSize = DL.getTypeAllocSize(ArgMemTy); 10395 10396 // For in-memory arguments, size and alignment should be passed from FE. 10397 // BE will guess if this info is not there but there are cases it cannot 10398 // get right. 10399 if (auto ParamAlign = Arg.getParamStackAlign()) 10400 MemAlign = *ParamAlign; 10401 else if ((ParamAlign = Arg.getParamAlign())) 10402 MemAlign = *ParamAlign; 10403 else 10404 MemAlign = Align(TLI->getByValTypeAlignment(ArgMemTy, DL)); 10405 if (Flags.isByRef()) 10406 Flags.setByRefSize(MemSize); 10407 else 10408 Flags.setByValSize(MemSize); 10409 } else if (auto ParamAlign = Arg.getParamStackAlign()) { 10410 MemAlign = *ParamAlign; 10411 } else { 10412 MemAlign = OriginalAlignment; 10413 } 10414 Flags.setMemAlign(MemAlign); 10415 10416 if (Arg.hasAttribute(Attribute::Nest)) 10417 Flags.setNest(); 10418 if (NeedsRegBlock) 10419 Flags.setInConsecutiveRegs(); 10420 if (ArgCopyElisionCandidates.count(&Arg)) 10421 Flags.setCopyElisionCandidate(); 10422 if (Arg.hasAttribute(Attribute::Returned)) 10423 Flags.setReturned(); 10424 10425 MVT RegisterVT = TLI->getRegisterTypeForCallingConv( 10426 *CurDAG->getContext(), F.getCallingConv(), VT); 10427 unsigned NumRegs = TLI->getNumRegistersForCallingConv( 10428 *CurDAG->getContext(), F.getCallingConv(), VT); 10429 for (unsigned i = 0; i != NumRegs; ++i) { 10430 // For scalable vectors, use the minimum size; individual targets 10431 // are responsible for handling scalable vector arguments and 10432 // return values. 10433 ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed, 10434 ArgNo, PartBase+i*RegisterVT.getStoreSize().getKnownMinSize()); 10435 if (NumRegs > 1 && i == 0) 10436 MyFlags.Flags.setSplit(); 10437 // if it isn't first piece, alignment must be 1 10438 else if (i > 0) { 10439 MyFlags.Flags.setOrigAlign(Align(1)); 10440 if (i == NumRegs - 1) 10441 MyFlags.Flags.setSplitEnd(); 10442 } 10443 Ins.push_back(MyFlags); 10444 } 10445 if (NeedsRegBlock && Value == NumValues - 1) 10446 Ins[Ins.size() - 1].Flags.setInConsecutiveRegsLast(); 10447 PartBase += VT.getStoreSize().getKnownMinSize(); 10448 } 10449 } 10450 10451 // Call the target to set up the argument values. 10452 SmallVector<SDValue, 8> InVals; 10453 SDValue NewRoot = TLI->LowerFormalArguments( 10454 DAG.getRoot(), F.getCallingConv(), F.isVarArg(), Ins, dl, DAG, InVals); 10455 10456 // Verify that the target's LowerFormalArguments behaved as expected. 10457 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other && 10458 "LowerFormalArguments didn't return a valid chain!"); 10459 assert(InVals.size() == Ins.size() && 10460 "LowerFormalArguments didn't emit the correct number of values!"); 10461 LLVM_DEBUG({ 10462 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 10463 assert(InVals[i].getNode() && 10464 "LowerFormalArguments emitted a null value!"); 10465 assert(EVT(Ins[i].VT) == InVals[i].getValueType() && 10466 "LowerFormalArguments emitted a value with the wrong type!"); 10467 } 10468 }); 10469 10470 // Update the DAG with the new chain value resulting from argument lowering. 10471 DAG.setRoot(NewRoot); 10472 10473 // Set up the argument values. 10474 unsigned i = 0; 10475 if (!FuncInfo->CanLowerReturn) { 10476 // Create a virtual register for the sret pointer, and put in a copy 10477 // from the sret argument into it. 10478 SmallVector<EVT, 1> ValueVTs; 10479 ComputeValueVTs(*TLI, DAG.getDataLayout(), 10480 F.getReturnType()->getPointerTo( 10481 DAG.getDataLayout().getAllocaAddrSpace()), 10482 ValueVTs); 10483 MVT VT = ValueVTs[0].getSimpleVT(); 10484 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT); 10485 Optional<ISD::NodeType> AssertOp = None; 10486 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1, RegVT, VT, 10487 nullptr, F.getCallingConv(), AssertOp); 10488 10489 MachineFunction& MF = SDB->DAG.getMachineFunction(); 10490 MachineRegisterInfo& RegInfo = MF.getRegInfo(); 10491 Register SRetReg = 10492 RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT)); 10493 FuncInfo->DemoteRegister = SRetReg; 10494 NewRoot = 10495 SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(), SRetReg, ArgValue); 10496 DAG.setRoot(NewRoot); 10497 10498 // i indexes lowered arguments. Bump it past the hidden sret argument. 10499 ++i; 10500 } 10501 10502 SmallVector<SDValue, 4> Chains; 10503 DenseMap<int, int> ArgCopyElisionFrameIndexMap; 10504 for (const Argument &Arg : F.args()) { 10505 SmallVector<SDValue, 4> ArgValues; 10506 SmallVector<EVT, 4> ValueVTs; 10507 ComputeValueVTs(*TLI, DAG.getDataLayout(), Arg.getType(), ValueVTs); 10508 unsigned NumValues = ValueVTs.size(); 10509 if (NumValues == 0) 10510 continue; 10511 10512 bool ArgHasUses = !Arg.use_empty(); 10513 10514 // Elide the copying store if the target loaded this argument from a 10515 // suitable fixed stack object. 10516 if (Ins[i].Flags.isCopyElisionCandidate()) { 10517 tryToElideArgumentCopy(*FuncInfo, Chains, ArgCopyElisionFrameIndexMap, 10518 ElidedArgCopyInstrs, ArgCopyElisionCandidates, Arg, 10519 InVals[i], ArgHasUses); 10520 } 10521 10522 // If this argument is unused then remember its value. It is used to generate 10523 // debugging information. 10524 bool isSwiftErrorArg = 10525 TLI->supportSwiftError() && 10526 Arg.hasAttribute(Attribute::SwiftError); 10527 if (!ArgHasUses && !isSwiftErrorArg) { 10528 SDB->setUnusedArgValue(&Arg, InVals[i]); 10529 10530 // Also remember any frame index for use in FastISel. 10531 if (FrameIndexSDNode *FI = 10532 dyn_cast<FrameIndexSDNode>(InVals[i].getNode())) 10533 FuncInfo->setArgumentFrameIndex(&Arg, FI->getIndex()); 10534 } 10535 10536 for (unsigned Val = 0; Val != NumValues; ++Val) { 10537 EVT VT = ValueVTs[Val]; 10538 MVT PartVT = TLI->getRegisterTypeForCallingConv(*CurDAG->getContext(), 10539 F.getCallingConv(), VT); 10540 unsigned NumParts = TLI->getNumRegistersForCallingConv( 10541 *CurDAG->getContext(), F.getCallingConv(), VT); 10542 10543 // Even an apparent 'unused' swifterror argument needs to be returned. So 10544 // we do generate a copy for it that can be used on return from the 10545 // function. 10546 if (ArgHasUses || isSwiftErrorArg) { 10547 Optional<ISD::NodeType> AssertOp; 10548 if (Arg.hasAttribute(Attribute::SExt)) 10549 AssertOp = ISD::AssertSext; 10550 else if (Arg.hasAttribute(Attribute::ZExt)) 10551 AssertOp = ISD::AssertZext; 10552 10553 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i], NumParts, 10554 PartVT, VT, nullptr, 10555 F.getCallingConv(), AssertOp)); 10556 } 10557 10558 i += NumParts; 10559 } 10560 10561 // We don't need to do anything else for unused arguments. 10562 if (ArgValues.empty()) 10563 continue; 10564 10565 // Note down frame index. 10566 if (FrameIndexSDNode *FI = 10567 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode())) 10568 FuncInfo->setArgumentFrameIndex(&Arg, FI->getIndex()); 10569 10570 SDValue Res = DAG.getMergeValues(makeArrayRef(ArgValues.data(), NumValues), 10571 SDB->getCurSDLoc()); 10572 10573 SDB->setValue(&Arg, Res); 10574 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) { 10575 // We want to associate the argument with the frame index, among 10576 // involved operands, that correspond to the lowest address. The 10577 // getCopyFromParts function, called earlier, is swapping the order of 10578 // the operands to BUILD_PAIR depending on endianness. The result of 10579 // that swapping is that the least significant bits of the argument will 10580 // be in the first operand of the BUILD_PAIR node, and the most 10581 // significant bits will be in the second operand. 10582 unsigned LowAddressOp = DAG.getDataLayout().isBigEndian() ? 1 : 0; 10583 if (LoadSDNode *LNode = 10584 dyn_cast<LoadSDNode>(Res.getOperand(LowAddressOp).getNode())) 10585 if (FrameIndexSDNode *FI = 10586 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) 10587 FuncInfo->setArgumentFrameIndex(&Arg, FI->getIndex()); 10588 } 10589 10590 // Analyses past this point are naive and don't expect an assertion. 10591 if (Res.getOpcode() == ISD::AssertZext) 10592 Res = Res.getOperand(0); 10593 10594 // Update the SwiftErrorVRegDefMap. 10595 if (Res.getOpcode() == ISD::CopyFromReg && isSwiftErrorArg) { 10596 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg(); 10597 if (Register::isVirtualRegister(Reg)) 10598 SwiftError->setCurrentVReg(FuncInfo->MBB, SwiftError->getFunctionArg(), 10599 Reg); 10600 } 10601 10602 // If this argument is live outside of the entry block, insert a copy from 10603 // wherever we got it to the vreg that other BB's will reference it as. 10604 if (Res.getOpcode() == ISD::CopyFromReg) { 10605 // If we can, though, try to skip creating an unnecessary vreg. 10606 // FIXME: This isn't very clean... it would be nice to make this more 10607 // general. 10608 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg(); 10609 if (Register::isVirtualRegister(Reg)) { 10610 FuncInfo->ValueMap[&Arg] = Reg; 10611 continue; 10612 } 10613 } 10614 if (!isOnlyUsedInEntryBlock(&Arg, TM.Options.EnableFastISel)) { 10615 FuncInfo->InitializeRegForValue(&Arg); 10616 SDB->CopyToExportRegsIfNeeded(&Arg); 10617 } 10618 } 10619 10620 if (!Chains.empty()) { 10621 Chains.push_back(NewRoot); 10622 NewRoot = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains); 10623 } 10624 10625 DAG.setRoot(NewRoot); 10626 10627 assert(i == InVals.size() && "Argument register count mismatch!"); 10628 10629 // If any argument copy elisions occurred and we have debug info, update the 10630 // stale frame indices used in the dbg.declare variable info table. 10631 MachineFunction::VariableDbgInfoMapTy &DbgDeclareInfo = MF->getVariableDbgInfo(); 10632 if (!DbgDeclareInfo.empty() && !ArgCopyElisionFrameIndexMap.empty()) { 10633 for (MachineFunction::VariableDbgInfo &VI : DbgDeclareInfo) { 10634 auto I = ArgCopyElisionFrameIndexMap.find(VI.Slot); 10635 if (I != ArgCopyElisionFrameIndexMap.end()) 10636 VI.Slot = I->second; 10637 } 10638 } 10639 10640 // Finally, if the target has anything special to do, allow it to do so. 10641 emitFunctionEntryCode(); 10642 } 10643 10644 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 10645 /// ensure constants are generated when needed. Remember the virtual registers 10646 /// that need to be added to the Machine PHI nodes as input. We cannot just 10647 /// directly add them, because expansion might result in multiple MBB's for one 10648 /// BB. As such, the start of the BB might correspond to a different MBB than 10649 /// the end. 10650 void 10651 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) { 10652 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 10653 const Instruction *TI = LLVMBB->getTerminator(); 10654 10655 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled; 10656 10657 // Check PHI nodes in successors that expect a value to be available from this 10658 // block. 10659 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 10660 const BasicBlock *SuccBB = TI->getSuccessor(succ); 10661 if (!isa<PHINode>(SuccBB->begin())) continue; 10662 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 10663 10664 // If this terminator has multiple identical successors (common for 10665 // switches), only handle each succ once. 10666 if (!SuccsHandled.insert(SuccMBB).second) 10667 continue; 10668 10669 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 10670 10671 // At this point we know that there is a 1-1 correspondence between LLVM PHI 10672 // nodes and Machine PHI nodes, but the incoming operands have not been 10673 // emitted yet. 10674 for (const PHINode &PN : SuccBB->phis()) { 10675 // Ignore dead phi's. 10676 if (PN.use_empty()) 10677 continue; 10678 10679 // Skip empty types 10680 if (PN.getType()->isEmptyTy()) 10681 continue; 10682 10683 unsigned Reg; 10684 const Value *PHIOp = PN.getIncomingValueForBlock(LLVMBB); 10685 10686 if (const Constant *C = dyn_cast<Constant>(PHIOp)) { 10687 unsigned &RegOut = ConstantsOut[C]; 10688 if (RegOut == 0) { 10689 RegOut = FuncInfo.CreateRegs(C); 10690 // We need to zero/sign extend ConstantInt phi operands to match 10691 // assumptions in FunctionLoweringInfo::ComputePHILiveOutRegInfo. 10692 ISD::NodeType ExtendType = ISD::ANY_EXTEND; 10693 if (auto *CI = dyn_cast<ConstantInt>(C)) 10694 ExtendType = TLI.signExtendConstant(CI) ? ISD::SIGN_EXTEND 10695 : ISD::ZERO_EXTEND; 10696 CopyValueToVirtualRegister(C, RegOut, ExtendType); 10697 } 10698 Reg = RegOut; 10699 } else { 10700 DenseMap<const Value *, Register>::iterator I = 10701 FuncInfo.ValueMap.find(PHIOp); 10702 if (I != FuncInfo.ValueMap.end()) 10703 Reg = I->second; 10704 else { 10705 assert(isa<AllocaInst>(PHIOp) && 10706 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 10707 "Didn't codegen value into a register!??"); 10708 Reg = FuncInfo.CreateRegs(PHIOp); 10709 CopyValueToVirtualRegister(PHIOp, Reg); 10710 } 10711 } 10712 10713 // Remember that this register needs to added to the machine PHI node as 10714 // the input for this MBB. 10715 SmallVector<EVT, 4> ValueVTs; 10716 ComputeValueVTs(TLI, DAG.getDataLayout(), PN.getType(), ValueVTs); 10717 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) { 10718 EVT VT = ValueVTs[vti]; 10719 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT); 10720 for (unsigned i = 0, e = NumRegisters; i != e; ++i) 10721 FuncInfo.PHINodesToUpdate.push_back( 10722 std::make_pair(&*MBBI++, Reg + i)); 10723 Reg += NumRegisters; 10724 } 10725 } 10726 } 10727 10728 ConstantsOut.clear(); 10729 } 10730 10731 MachineBasicBlock *SelectionDAGBuilder::NextBlock(MachineBasicBlock *MBB) { 10732 MachineFunction::iterator I(MBB); 10733 if (++I == FuncInfo.MF->end()) 10734 return nullptr; 10735 return &*I; 10736 } 10737 10738 /// During lowering new call nodes can be created (such as memset, etc.). 10739 /// Those will become new roots of the current DAG, but complications arise 10740 /// when they are tail calls. In such cases, the call lowering will update 10741 /// the root, but the builder still needs to know that a tail call has been 10742 /// lowered in order to avoid generating an additional return. 10743 void SelectionDAGBuilder::updateDAGForMaybeTailCall(SDValue MaybeTC) { 10744 // If the node is null, we do have a tail call. 10745 if (MaybeTC.getNode() != nullptr) 10746 DAG.setRoot(MaybeTC); 10747 else 10748 HasTailCall = true; 10749 } 10750 10751 void SelectionDAGBuilder::lowerWorkItem(SwitchWorkListItem W, Value *Cond, 10752 MachineBasicBlock *SwitchMBB, 10753 MachineBasicBlock *DefaultMBB) { 10754 MachineFunction *CurMF = FuncInfo.MF; 10755 MachineBasicBlock *NextMBB = nullptr; 10756 MachineFunction::iterator BBI(W.MBB); 10757 if (++BBI != FuncInfo.MF->end()) 10758 NextMBB = &*BBI; 10759 10760 unsigned Size = W.LastCluster - W.FirstCluster + 1; 10761 10762 BranchProbabilityInfo *BPI = FuncInfo.BPI; 10763 10764 if (Size == 2 && W.MBB == SwitchMBB) { 10765 // If any two of the cases has the same destination, and if one value 10766 // is the same as the other, but has one bit unset that the other has set, 10767 // use bit manipulation to do two compares at once. For example: 10768 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" 10769 // TODO: This could be extended to merge any 2 cases in switches with 3 10770 // cases. 10771 // TODO: Handle cases where W.CaseBB != SwitchBB. 10772 CaseCluster &Small = *W.FirstCluster; 10773 CaseCluster &Big = *W.LastCluster; 10774 10775 if (Small.Low == Small.High && Big.Low == Big.High && 10776 Small.MBB == Big.MBB) { 10777 const APInt &SmallValue = Small.Low->getValue(); 10778 const APInt &BigValue = Big.Low->getValue(); 10779 10780 // Check that there is only one bit different. 10781 APInt CommonBit = BigValue ^ SmallValue; 10782 if (CommonBit.isPowerOf2()) { 10783 SDValue CondLHS = getValue(Cond); 10784 EVT VT = CondLHS.getValueType(); 10785 SDLoc DL = getCurSDLoc(); 10786 10787 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS, 10788 DAG.getConstant(CommonBit, DL, VT)); 10789 SDValue Cond = DAG.getSetCC( 10790 DL, MVT::i1, Or, DAG.getConstant(BigValue | SmallValue, DL, VT), 10791 ISD::SETEQ); 10792 10793 // Update successor info. 10794 // Both Small and Big will jump to Small.BB, so we sum up the 10795 // probabilities. 10796 addSuccessorWithProb(SwitchMBB, Small.MBB, Small.Prob + Big.Prob); 10797 if (BPI) 10798 addSuccessorWithProb( 10799 SwitchMBB, DefaultMBB, 10800 // The default destination is the first successor in IR. 10801 BPI->getEdgeProbability(SwitchMBB->getBasicBlock(), (unsigned)0)); 10802 else 10803 addSuccessorWithProb(SwitchMBB, DefaultMBB); 10804 10805 // Insert the true branch. 10806 SDValue BrCond = 10807 DAG.getNode(ISD::BRCOND, DL, MVT::Other, getControlRoot(), Cond, 10808 DAG.getBasicBlock(Small.MBB)); 10809 // Insert the false branch. 10810 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond, 10811 DAG.getBasicBlock(DefaultMBB)); 10812 10813 DAG.setRoot(BrCond); 10814 return; 10815 } 10816 } 10817 } 10818 10819 if (TM.getOptLevel() != CodeGenOpt::None) { 10820 // Here, we order cases by probability so the most likely case will be 10821 // checked first. However, two clusters can have the same probability in 10822 // which case their relative ordering is non-deterministic. So we use Low 10823 // as a tie-breaker as clusters are guaranteed to never overlap. 10824 llvm::sort(W.FirstCluster, W.LastCluster + 1, 10825 [](const CaseCluster &a, const CaseCluster &b) { 10826 return a.Prob != b.Prob ? 10827 a.Prob > b.Prob : 10828 a.Low->getValue().slt(b.Low->getValue()); 10829 }); 10830 10831 // Rearrange the case blocks so that the last one falls through if possible 10832 // without changing the order of probabilities. 10833 for (CaseClusterIt I = W.LastCluster; I > W.FirstCluster; ) { 10834 --I; 10835 if (I->Prob > W.LastCluster->Prob) 10836 break; 10837 if (I->Kind == CC_Range && I->MBB == NextMBB) { 10838 std::swap(*I, *W.LastCluster); 10839 break; 10840 } 10841 } 10842 } 10843 10844 // Compute total probability. 10845 BranchProbability DefaultProb = W.DefaultProb; 10846 BranchProbability UnhandledProbs = DefaultProb; 10847 for (CaseClusterIt I = W.FirstCluster; I <= W.LastCluster; ++I) 10848 UnhandledProbs += I->Prob; 10849 10850 MachineBasicBlock *CurMBB = W.MBB; 10851 for (CaseClusterIt I = W.FirstCluster, E = W.LastCluster; I <= E; ++I) { 10852 bool FallthroughUnreachable = false; 10853 MachineBasicBlock *Fallthrough; 10854 if (I == W.LastCluster) { 10855 // For the last cluster, fall through to the default destination. 10856 Fallthrough = DefaultMBB; 10857 FallthroughUnreachable = isa<UnreachableInst>( 10858 DefaultMBB->getBasicBlock()->getFirstNonPHIOrDbg()); 10859 } else { 10860 Fallthrough = CurMF->CreateMachineBasicBlock(CurMBB->getBasicBlock()); 10861 CurMF->insert(BBI, Fallthrough); 10862 // Put Cond in a virtual register to make it available from the new blocks. 10863 ExportFromCurrentBlock(Cond); 10864 } 10865 UnhandledProbs -= I->Prob; 10866 10867 switch (I->Kind) { 10868 case CC_JumpTable: { 10869 // FIXME: Optimize away range check based on pivot comparisons. 10870 JumpTableHeader *JTH = &SL->JTCases[I->JTCasesIndex].first; 10871 SwitchCG::JumpTable *JT = &SL->JTCases[I->JTCasesIndex].second; 10872 10873 // The jump block hasn't been inserted yet; insert it here. 10874 MachineBasicBlock *JumpMBB = JT->MBB; 10875 CurMF->insert(BBI, JumpMBB); 10876 10877 auto JumpProb = I->Prob; 10878 auto FallthroughProb = UnhandledProbs; 10879 10880 // If the default statement is a target of the jump table, we evenly 10881 // distribute the default probability to successors of CurMBB. Also 10882 // update the probability on the edge from JumpMBB to Fallthrough. 10883 for (MachineBasicBlock::succ_iterator SI = JumpMBB->succ_begin(), 10884 SE = JumpMBB->succ_end(); 10885 SI != SE; ++SI) { 10886 if (*SI == DefaultMBB) { 10887 JumpProb += DefaultProb / 2; 10888 FallthroughProb -= DefaultProb / 2; 10889 JumpMBB->setSuccProbability(SI, DefaultProb / 2); 10890 JumpMBB->normalizeSuccProbs(); 10891 break; 10892 } 10893 } 10894 10895 if (FallthroughUnreachable) 10896 JTH->FallthroughUnreachable = true; 10897 10898 if (!JTH->FallthroughUnreachable) 10899 addSuccessorWithProb(CurMBB, Fallthrough, FallthroughProb); 10900 addSuccessorWithProb(CurMBB, JumpMBB, JumpProb); 10901 CurMBB->normalizeSuccProbs(); 10902 10903 // The jump table header will be inserted in our current block, do the 10904 // range check, and fall through to our fallthrough block. 10905 JTH->HeaderBB = CurMBB; 10906 JT->Default = Fallthrough; // FIXME: Move Default to JumpTableHeader. 10907 10908 // If we're in the right place, emit the jump table header right now. 10909 if (CurMBB == SwitchMBB) { 10910 visitJumpTableHeader(*JT, *JTH, SwitchMBB); 10911 JTH->Emitted = true; 10912 } 10913 break; 10914 } 10915 case CC_BitTests: { 10916 // FIXME: Optimize away range check based on pivot comparisons. 10917 BitTestBlock *BTB = &SL->BitTestCases[I->BTCasesIndex]; 10918 10919 // The bit test blocks haven't been inserted yet; insert them here. 10920 for (BitTestCase &BTC : BTB->Cases) 10921 CurMF->insert(BBI, BTC.ThisBB); 10922 10923 // Fill in fields of the BitTestBlock. 10924 BTB->Parent = CurMBB; 10925 BTB->Default = Fallthrough; 10926 10927 BTB->DefaultProb = UnhandledProbs; 10928 // If the cases in bit test don't form a contiguous range, we evenly 10929 // distribute the probability on the edge to Fallthrough to two 10930 // successors of CurMBB. 10931 if (!BTB->ContiguousRange) { 10932 BTB->Prob += DefaultProb / 2; 10933 BTB->DefaultProb -= DefaultProb / 2; 10934 } 10935 10936 if (FallthroughUnreachable) 10937 BTB->FallthroughUnreachable = true; 10938 10939 // If we're in the right place, emit the bit test header right now. 10940 if (CurMBB == SwitchMBB) { 10941 visitBitTestHeader(*BTB, SwitchMBB); 10942 BTB->Emitted = true; 10943 } 10944 break; 10945 } 10946 case CC_Range: { 10947 const Value *RHS, *LHS, *MHS; 10948 ISD::CondCode CC; 10949 if (I->Low == I->High) { 10950 // Check Cond == I->Low. 10951 CC = ISD::SETEQ; 10952 LHS = Cond; 10953 RHS=I->Low; 10954 MHS = nullptr; 10955 } else { 10956 // Check I->Low <= Cond <= I->High. 10957 CC = ISD::SETLE; 10958 LHS = I->Low; 10959 MHS = Cond; 10960 RHS = I->High; 10961 } 10962 10963 // If Fallthrough is unreachable, fold away the comparison. 10964 if (FallthroughUnreachable) 10965 CC = ISD::SETTRUE; 10966 10967 // The false probability is the sum of all unhandled cases. 10968 CaseBlock CB(CC, LHS, RHS, MHS, I->MBB, Fallthrough, CurMBB, 10969 getCurSDLoc(), I->Prob, UnhandledProbs); 10970 10971 if (CurMBB == SwitchMBB) 10972 visitSwitchCase(CB, SwitchMBB); 10973 else 10974 SL->SwitchCases.push_back(CB); 10975 10976 break; 10977 } 10978 } 10979 CurMBB = Fallthrough; 10980 } 10981 } 10982 10983 unsigned SelectionDAGBuilder::caseClusterRank(const CaseCluster &CC, 10984 CaseClusterIt First, 10985 CaseClusterIt Last) { 10986 return std::count_if(First, Last + 1, [&](const CaseCluster &X) { 10987 if (X.Prob != CC.Prob) 10988 return X.Prob > CC.Prob; 10989 10990 // Ties are broken by comparing the case value. 10991 return X.Low->getValue().slt(CC.Low->getValue()); 10992 }); 10993 } 10994 10995 void SelectionDAGBuilder::splitWorkItem(SwitchWorkList &WorkList, 10996 const SwitchWorkListItem &W, 10997 Value *Cond, 10998 MachineBasicBlock *SwitchMBB) { 10999 assert(W.FirstCluster->Low->getValue().slt(W.LastCluster->Low->getValue()) && 11000 "Clusters not sorted?"); 11001 11002 assert(W.LastCluster - W.FirstCluster + 1 >= 2 && "Too small to split!"); 11003 11004 // Balance the tree based on branch probabilities to create a near-optimal (in 11005 // terms of search time given key frequency) binary search tree. See e.g. Kurt 11006 // Mehlhorn "Nearly Optimal Binary Search Trees" (1975). 11007 CaseClusterIt LastLeft = W.FirstCluster; 11008 CaseClusterIt FirstRight = W.LastCluster; 11009 auto LeftProb = LastLeft->Prob + W.DefaultProb / 2; 11010 auto RightProb = FirstRight->Prob + W.DefaultProb / 2; 11011 11012 // Move LastLeft and FirstRight towards each other from opposite directions to 11013 // find a partitioning of the clusters which balances the probability on both 11014 // sides. If LeftProb and RightProb are equal, alternate which side is 11015 // taken to ensure 0-probability nodes are distributed evenly. 11016 unsigned I = 0; 11017 while (LastLeft + 1 < FirstRight) { 11018 if (LeftProb < RightProb || (LeftProb == RightProb && (I & 1))) 11019 LeftProb += (++LastLeft)->Prob; 11020 else 11021 RightProb += (--FirstRight)->Prob; 11022 I++; 11023 } 11024 11025 while (true) { 11026 // Our binary search tree differs from a typical BST in that ours can have up 11027 // to three values in each leaf. The pivot selection above doesn't take that 11028 // into account, which means the tree might require more nodes and be less 11029 // efficient. We compensate for this here. 11030 11031 unsigned NumLeft = LastLeft - W.FirstCluster + 1; 11032 unsigned NumRight = W.LastCluster - FirstRight + 1; 11033 11034 if (std::min(NumLeft, NumRight) < 3 && std::max(NumLeft, NumRight) > 3) { 11035 // If one side has less than 3 clusters, and the other has more than 3, 11036 // consider taking a cluster from the other side. 11037 11038 if (NumLeft < NumRight) { 11039 // Consider moving the first cluster on the right to the left side. 11040 CaseCluster &CC = *FirstRight; 11041 unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster); 11042 unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft); 11043 if (LeftSideRank <= RightSideRank) { 11044 // Moving the cluster to the left does not demote it. 11045 ++LastLeft; 11046 ++FirstRight; 11047 continue; 11048 } 11049 } else { 11050 assert(NumRight < NumLeft); 11051 // Consider moving the last element on the left to the right side. 11052 CaseCluster &CC = *LastLeft; 11053 unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft); 11054 unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster); 11055 if (RightSideRank <= LeftSideRank) { 11056 // Moving the cluster to the right does not demot it. 11057 --LastLeft; 11058 --FirstRight; 11059 continue; 11060 } 11061 } 11062 } 11063 break; 11064 } 11065 11066 assert(LastLeft + 1 == FirstRight); 11067 assert(LastLeft >= W.FirstCluster); 11068 assert(FirstRight <= W.LastCluster); 11069 11070 // Use the first element on the right as pivot since we will make less-than 11071 // comparisons against it. 11072 CaseClusterIt PivotCluster = FirstRight; 11073 assert(PivotCluster > W.FirstCluster); 11074 assert(PivotCluster <= W.LastCluster); 11075 11076 CaseClusterIt FirstLeft = W.FirstCluster; 11077 CaseClusterIt LastRight = W.LastCluster; 11078 11079 const ConstantInt *Pivot = PivotCluster->Low; 11080 11081 // New blocks will be inserted immediately after the current one. 11082 MachineFunction::iterator BBI(W.MBB); 11083 ++BBI; 11084 11085 // We will branch to the LHS if Value < Pivot. If LHS is a single cluster, 11086 // we can branch to its destination directly if it's squeezed exactly in 11087 // between the known lower bound and Pivot - 1. 11088 MachineBasicBlock *LeftMBB; 11089 if (FirstLeft == LastLeft && FirstLeft->Kind == CC_Range && 11090 FirstLeft->Low == W.GE && 11091 (FirstLeft->High->getValue() + 1LL) == Pivot->getValue()) { 11092 LeftMBB = FirstLeft->MBB; 11093 } else { 11094 LeftMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock()); 11095 FuncInfo.MF->insert(BBI, LeftMBB); 11096 WorkList.push_back( 11097 {LeftMBB, FirstLeft, LastLeft, W.GE, Pivot, W.DefaultProb / 2}); 11098 // Put Cond in a virtual register to make it available from the new blocks. 11099 ExportFromCurrentBlock(Cond); 11100 } 11101 11102 // Similarly, we will branch to the RHS if Value >= Pivot. If RHS is a 11103 // single cluster, RHS.Low == Pivot, and we can branch to its destination 11104 // directly if RHS.High equals the current upper bound. 11105 MachineBasicBlock *RightMBB; 11106 if (FirstRight == LastRight && FirstRight->Kind == CC_Range && 11107 W.LT && (FirstRight->High->getValue() + 1ULL) == W.LT->getValue()) { 11108 RightMBB = FirstRight->MBB; 11109 } else { 11110 RightMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock()); 11111 FuncInfo.MF->insert(BBI, RightMBB); 11112 WorkList.push_back( 11113 {RightMBB, FirstRight, LastRight, Pivot, W.LT, W.DefaultProb / 2}); 11114 // Put Cond in a virtual register to make it available from the new blocks. 11115 ExportFromCurrentBlock(Cond); 11116 } 11117 11118 // Create the CaseBlock record that will be used to lower the branch. 11119 CaseBlock CB(ISD::SETLT, Cond, Pivot, nullptr, LeftMBB, RightMBB, W.MBB, 11120 getCurSDLoc(), LeftProb, RightProb); 11121 11122 if (W.MBB == SwitchMBB) 11123 visitSwitchCase(CB, SwitchMBB); 11124 else 11125 SL->SwitchCases.push_back(CB); 11126 } 11127 11128 // Scale CaseProb after peeling a case with the probablity of PeeledCaseProb 11129 // from the swith statement. 11130 static BranchProbability scaleCaseProbality(BranchProbability CaseProb, 11131 BranchProbability PeeledCaseProb) { 11132 if (PeeledCaseProb == BranchProbability::getOne()) 11133 return BranchProbability::getZero(); 11134 BranchProbability SwitchProb = PeeledCaseProb.getCompl(); 11135 11136 uint32_t Numerator = CaseProb.getNumerator(); 11137 uint32_t Denominator = SwitchProb.scale(CaseProb.getDenominator()); 11138 return BranchProbability(Numerator, std::max(Numerator, Denominator)); 11139 } 11140 11141 // Try to peel the top probability case if it exceeds the threshold. 11142 // Return current MachineBasicBlock for the switch statement if the peeling 11143 // does not occur. 11144 // If the peeling is performed, return the newly created MachineBasicBlock 11145 // for the peeled switch statement. Also update Clusters to remove the peeled 11146 // case. PeeledCaseProb is the BranchProbability for the peeled case. 11147 MachineBasicBlock *SelectionDAGBuilder::peelDominantCaseCluster( 11148 const SwitchInst &SI, CaseClusterVector &Clusters, 11149 BranchProbability &PeeledCaseProb) { 11150 MachineBasicBlock *SwitchMBB = FuncInfo.MBB; 11151 // Don't perform if there is only one cluster or optimizing for size. 11152 if (SwitchPeelThreshold > 100 || !FuncInfo.BPI || Clusters.size() < 2 || 11153 TM.getOptLevel() == CodeGenOpt::None || 11154 SwitchMBB->getParent()->getFunction().hasMinSize()) 11155 return SwitchMBB; 11156 11157 BranchProbability TopCaseProb = BranchProbability(SwitchPeelThreshold, 100); 11158 unsigned PeeledCaseIndex = 0; 11159 bool SwitchPeeled = false; 11160 for (unsigned Index = 0; Index < Clusters.size(); ++Index) { 11161 CaseCluster &CC = Clusters[Index]; 11162 if (CC.Prob < TopCaseProb) 11163 continue; 11164 TopCaseProb = CC.Prob; 11165 PeeledCaseIndex = Index; 11166 SwitchPeeled = true; 11167 } 11168 if (!SwitchPeeled) 11169 return SwitchMBB; 11170 11171 LLVM_DEBUG(dbgs() << "Peeled one top case in switch stmt, prob: " 11172 << TopCaseProb << "\n"); 11173 11174 // Record the MBB for the peeled switch statement. 11175 MachineFunction::iterator BBI(SwitchMBB); 11176 ++BBI; 11177 MachineBasicBlock *PeeledSwitchMBB = 11178 FuncInfo.MF->CreateMachineBasicBlock(SwitchMBB->getBasicBlock()); 11179 FuncInfo.MF->insert(BBI, PeeledSwitchMBB); 11180 11181 ExportFromCurrentBlock(SI.getCondition()); 11182 auto PeeledCaseIt = Clusters.begin() + PeeledCaseIndex; 11183 SwitchWorkListItem W = {SwitchMBB, PeeledCaseIt, PeeledCaseIt, 11184 nullptr, nullptr, TopCaseProb.getCompl()}; 11185 lowerWorkItem(W, SI.getCondition(), SwitchMBB, PeeledSwitchMBB); 11186 11187 Clusters.erase(PeeledCaseIt); 11188 for (CaseCluster &CC : Clusters) { 11189 LLVM_DEBUG( 11190 dbgs() << "Scale the probablity for one cluster, before scaling: " 11191 << CC.Prob << "\n"); 11192 CC.Prob = scaleCaseProbality(CC.Prob, TopCaseProb); 11193 LLVM_DEBUG(dbgs() << "After scaling: " << CC.Prob << "\n"); 11194 } 11195 PeeledCaseProb = TopCaseProb; 11196 return PeeledSwitchMBB; 11197 } 11198 11199 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) { 11200 // Extract cases from the switch. 11201 BranchProbabilityInfo *BPI = FuncInfo.BPI; 11202 CaseClusterVector Clusters; 11203 Clusters.reserve(SI.getNumCases()); 11204 for (auto I : SI.cases()) { 11205 MachineBasicBlock *Succ = FuncInfo.MBBMap[I.getCaseSuccessor()]; 11206 const ConstantInt *CaseVal = I.getCaseValue(); 11207 BranchProbability Prob = 11208 BPI ? BPI->getEdgeProbability(SI.getParent(), I.getSuccessorIndex()) 11209 : BranchProbability(1, SI.getNumCases() + 1); 11210 Clusters.push_back(CaseCluster::range(CaseVal, CaseVal, Succ, Prob)); 11211 } 11212 11213 MachineBasicBlock *DefaultMBB = FuncInfo.MBBMap[SI.getDefaultDest()]; 11214 11215 // Cluster adjacent cases with the same destination. We do this at all 11216 // optimization levels because it's cheap to do and will make codegen faster 11217 // if there are many clusters. 11218 sortAndRangeify(Clusters); 11219 11220 // The branch probablity of the peeled case. 11221 BranchProbability PeeledCaseProb = BranchProbability::getZero(); 11222 MachineBasicBlock *PeeledSwitchMBB = 11223 peelDominantCaseCluster(SI, Clusters, PeeledCaseProb); 11224 11225 // If there is only the default destination, jump there directly. 11226 MachineBasicBlock *SwitchMBB = FuncInfo.MBB; 11227 if (Clusters.empty()) { 11228 assert(PeeledSwitchMBB == SwitchMBB); 11229 SwitchMBB->addSuccessor(DefaultMBB); 11230 if (DefaultMBB != NextBlock(SwitchMBB)) { 11231 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, 11232 getControlRoot(), DAG.getBasicBlock(DefaultMBB))); 11233 } 11234 return; 11235 } 11236 11237 SL->findJumpTables(Clusters, &SI, DefaultMBB, DAG.getPSI(), DAG.getBFI()); 11238 SL->findBitTestClusters(Clusters, &SI); 11239 11240 LLVM_DEBUG({ 11241 dbgs() << "Case clusters: "; 11242 for (const CaseCluster &C : Clusters) { 11243 if (C.Kind == CC_JumpTable) 11244 dbgs() << "JT:"; 11245 if (C.Kind == CC_BitTests) 11246 dbgs() << "BT:"; 11247 11248 C.Low->getValue().print(dbgs(), true); 11249 if (C.Low != C.High) { 11250 dbgs() << '-'; 11251 C.High->getValue().print(dbgs(), true); 11252 } 11253 dbgs() << ' '; 11254 } 11255 dbgs() << '\n'; 11256 }); 11257 11258 assert(!Clusters.empty()); 11259 SwitchWorkList WorkList; 11260 CaseClusterIt First = Clusters.begin(); 11261 CaseClusterIt Last = Clusters.end() - 1; 11262 auto DefaultProb = getEdgeProbability(PeeledSwitchMBB, DefaultMBB); 11263 // Scale the branchprobability for DefaultMBB if the peel occurs and 11264 // DefaultMBB is not replaced. 11265 if (PeeledCaseProb != BranchProbability::getZero() && 11266 DefaultMBB == FuncInfo.MBBMap[SI.getDefaultDest()]) 11267 DefaultProb = scaleCaseProbality(DefaultProb, PeeledCaseProb); 11268 WorkList.push_back( 11269 {PeeledSwitchMBB, First, Last, nullptr, nullptr, DefaultProb}); 11270 11271 while (!WorkList.empty()) { 11272 SwitchWorkListItem W = WorkList.pop_back_val(); 11273 unsigned NumClusters = W.LastCluster - W.FirstCluster + 1; 11274 11275 if (NumClusters > 3 && TM.getOptLevel() != CodeGenOpt::None && 11276 !DefaultMBB->getParent()->getFunction().hasMinSize()) { 11277 // For optimized builds, lower large range as a balanced binary tree. 11278 splitWorkItem(WorkList, W, SI.getCondition(), SwitchMBB); 11279 continue; 11280 } 11281 11282 lowerWorkItem(W, SI.getCondition(), SwitchMBB, DefaultMBB); 11283 } 11284 } 11285 11286 void SelectionDAGBuilder::visitStepVector(const CallInst &I) { 11287 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 11288 auto DL = getCurSDLoc(); 11289 EVT ResultVT = TLI.getValueType(DAG.getDataLayout(), I.getType()); 11290 setValue(&I, DAG.getStepVector(DL, ResultVT)); 11291 } 11292 11293 void SelectionDAGBuilder::visitVectorReverse(const CallInst &I) { 11294 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 11295 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType()); 11296 11297 SDLoc DL = getCurSDLoc(); 11298 SDValue V = getValue(I.getOperand(0)); 11299 assert(VT == V.getValueType() && "Malformed vector.reverse!"); 11300 11301 if (VT.isScalableVector()) { 11302 setValue(&I, DAG.getNode(ISD::VECTOR_REVERSE, DL, VT, V)); 11303 return; 11304 } 11305 11306 // Use VECTOR_SHUFFLE for the fixed-length vector 11307 // to maintain existing behavior. 11308 SmallVector<int, 8> Mask; 11309 unsigned NumElts = VT.getVectorMinNumElements(); 11310 for (unsigned i = 0; i != NumElts; ++i) 11311 Mask.push_back(NumElts - 1 - i); 11312 11313 setValue(&I, DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), Mask)); 11314 } 11315 11316 void SelectionDAGBuilder::visitFreeze(const FreezeInst &I) { 11317 SmallVector<EVT, 4> ValueVTs; 11318 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), I.getType(), 11319 ValueVTs); 11320 unsigned NumValues = ValueVTs.size(); 11321 if (NumValues == 0) return; 11322 11323 SmallVector<SDValue, 4> Values(NumValues); 11324 SDValue Op = getValue(I.getOperand(0)); 11325 11326 for (unsigned i = 0; i != NumValues; ++i) 11327 Values[i] = DAG.getNode(ISD::FREEZE, getCurSDLoc(), ValueVTs[i], 11328 SDValue(Op.getNode(), Op.getResNo() + i)); 11329 11330 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), 11331 DAG.getVTList(ValueVTs), Values)); 11332 } 11333 11334 void SelectionDAGBuilder::visitVectorSplice(const CallInst &I) { 11335 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 11336 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType()); 11337 11338 SDLoc DL = getCurSDLoc(); 11339 SDValue V1 = getValue(I.getOperand(0)); 11340 SDValue V2 = getValue(I.getOperand(1)); 11341 int64_t Imm = cast<ConstantInt>(I.getOperand(2))->getSExtValue(); 11342 11343 // VECTOR_SHUFFLE doesn't support a scalable mask so use a dedicated node. 11344 if (VT.isScalableVector()) { 11345 MVT IdxVT = TLI.getVectorIdxTy(DAG.getDataLayout()); 11346 setValue(&I, DAG.getNode(ISD::VECTOR_SPLICE, DL, VT, V1, V2, 11347 DAG.getConstant(Imm, DL, IdxVT))); 11348 return; 11349 } 11350 11351 unsigned NumElts = VT.getVectorNumElements(); 11352 11353 uint64_t Idx = (NumElts + Imm) % NumElts; 11354 11355 // Use VECTOR_SHUFFLE to maintain original behaviour for fixed-length vectors. 11356 SmallVector<int, 8> Mask; 11357 for (unsigned i = 0; i < NumElts; ++i) 11358 Mask.push_back(Idx + i); 11359 setValue(&I, DAG.getVectorShuffle(VT, DL, V1, V2, Mask)); 11360 } 11361