1 //===-- DWARFExpression.cpp -----------------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "llvm/DebugInfo/DWARF/DWARFExpression.h"
10 #include "llvm/DebugInfo/DWARF/DWARFUnit.h"
11 #include "llvm/MC/MCRegisterInfo.h"
12 #include "llvm/Support/Format.h"
13 #include <cassert>
14 #include <cstdint>
15 #include <vector>
16 
17 using namespace llvm;
18 using namespace dwarf;
19 
20 namespace llvm {
21 
22 typedef std::vector<DWARFExpression::Operation::Description> DescVector;
23 
24 static DescVector getDescriptions() {
25   DescVector Descriptions;
26   typedef DWARFExpression::Operation Op;
27   typedef Op::Description Desc;
28 
29   Descriptions.resize(0xff);
30   Descriptions[DW_OP_addr] = Desc(Op::Dwarf2, Op::SizeAddr);
31   Descriptions[DW_OP_deref] = Desc(Op::Dwarf2);
32   Descriptions[DW_OP_const1u] = Desc(Op::Dwarf2, Op::Size1);
33   Descriptions[DW_OP_const1s] = Desc(Op::Dwarf2, Op::SignedSize1);
34   Descriptions[DW_OP_const2u] = Desc(Op::Dwarf2, Op::Size2);
35   Descriptions[DW_OP_const2s] = Desc(Op::Dwarf2, Op::SignedSize2);
36   Descriptions[DW_OP_const4u] = Desc(Op::Dwarf2, Op::Size4);
37   Descriptions[DW_OP_const4s] = Desc(Op::Dwarf2, Op::SignedSize4);
38   Descriptions[DW_OP_const8u] = Desc(Op::Dwarf2, Op::Size8);
39   Descriptions[DW_OP_const8s] = Desc(Op::Dwarf2, Op::SignedSize8);
40   Descriptions[DW_OP_constu] = Desc(Op::Dwarf2, Op::SizeLEB);
41   Descriptions[DW_OP_consts] = Desc(Op::Dwarf2, Op::SignedSizeLEB);
42   Descriptions[DW_OP_dup] = Desc(Op::Dwarf2);
43   Descriptions[DW_OP_drop] = Desc(Op::Dwarf2);
44   Descriptions[DW_OP_over] = Desc(Op::Dwarf2);
45   Descriptions[DW_OP_pick] = Desc(Op::Dwarf2, Op::Size1);
46   Descriptions[DW_OP_swap] = Desc(Op::Dwarf2);
47   Descriptions[DW_OP_rot] = Desc(Op::Dwarf2);
48   Descriptions[DW_OP_xderef] = Desc(Op::Dwarf2);
49   Descriptions[DW_OP_abs] = Desc(Op::Dwarf2);
50   Descriptions[DW_OP_and] = Desc(Op::Dwarf2);
51   Descriptions[DW_OP_div] = Desc(Op::Dwarf2);
52   Descriptions[DW_OP_minus] = Desc(Op::Dwarf2);
53   Descriptions[DW_OP_mod] = Desc(Op::Dwarf2);
54   Descriptions[DW_OP_mul] = Desc(Op::Dwarf2);
55   Descriptions[DW_OP_neg] = Desc(Op::Dwarf2);
56   Descriptions[DW_OP_not] = Desc(Op::Dwarf2);
57   Descriptions[DW_OP_or] = Desc(Op::Dwarf2);
58   Descriptions[DW_OP_plus] = Desc(Op::Dwarf2);
59   Descriptions[DW_OP_plus_uconst] = Desc(Op::Dwarf2, Op::SizeLEB);
60   Descriptions[DW_OP_shl] = Desc(Op::Dwarf2);
61   Descriptions[DW_OP_shr] = Desc(Op::Dwarf2);
62   Descriptions[DW_OP_shra] = Desc(Op::Dwarf2);
63   Descriptions[DW_OP_xor] = Desc(Op::Dwarf2);
64   Descriptions[DW_OP_skip] = Desc(Op::Dwarf2, Op::SignedSize2);
65   Descriptions[DW_OP_bra] = Desc(Op::Dwarf2, Op::SignedSize2);
66   Descriptions[DW_OP_eq] = Desc(Op::Dwarf2);
67   Descriptions[DW_OP_ge] = Desc(Op::Dwarf2);
68   Descriptions[DW_OP_gt] = Desc(Op::Dwarf2);
69   Descriptions[DW_OP_le] = Desc(Op::Dwarf2);
70   Descriptions[DW_OP_lt] = Desc(Op::Dwarf2);
71   Descriptions[DW_OP_ne] = Desc(Op::Dwarf2);
72   for (uint16_t LA = DW_OP_lit0; LA <= DW_OP_lit31; ++LA)
73     Descriptions[LA] = Desc(Op::Dwarf2);
74   for (uint16_t LA = DW_OP_reg0; LA <= DW_OP_reg31; ++LA)
75     Descriptions[LA] = Desc(Op::Dwarf2);
76   for (uint16_t LA = DW_OP_breg0; LA <= DW_OP_breg31; ++LA)
77     Descriptions[LA] = Desc(Op::Dwarf2, Op::SignedSizeLEB);
78   Descriptions[DW_OP_regx] = Desc(Op::Dwarf2, Op::SizeLEB);
79   Descriptions[DW_OP_fbreg] = Desc(Op::Dwarf2, Op::SignedSizeLEB);
80   Descriptions[DW_OP_bregx] = Desc(Op::Dwarf2, Op::SizeLEB, Op::SignedSizeLEB);
81   Descriptions[DW_OP_piece] = Desc(Op::Dwarf2, Op::SizeLEB);
82   Descriptions[DW_OP_deref_size] = Desc(Op::Dwarf2, Op::Size1);
83   Descriptions[DW_OP_xderef_size] = Desc(Op::Dwarf2, Op::Size1);
84   Descriptions[DW_OP_nop] = Desc(Op::Dwarf2);
85   Descriptions[DW_OP_push_object_address] = Desc(Op::Dwarf3);
86   Descriptions[DW_OP_call2] = Desc(Op::Dwarf3, Op::Size2);
87   Descriptions[DW_OP_call4] = Desc(Op::Dwarf3, Op::Size4);
88   Descriptions[DW_OP_call_ref] = Desc(Op::Dwarf3, Op::SizeRefAddr);
89   Descriptions[DW_OP_form_tls_address] = Desc(Op::Dwarf3);
90   Descriptions[DW_OP_call_frame_cfa] = Desc(Op::Dwarf3);
91   Descriptions[DW_OP_bit_piece] = Desc(Op::Dwarf3, Op::SizeLEB, Op::SizeLEB);
92   Descriptions[DW_OP_implicit_value] =
93       Desc(Op::Dwarf3, Op::SizeLEB, Op::SizeBlock);
94   Descriptions[DW_OP_stack_value] = Desc(Op::Dwarf3);
95   Descriptions[DW_OP_WASM_location] =
96       Desc(Op::Dwarf4, Op::SizeLEB, Op::WasmLocationArg);
97   Descriptions[DW_OP_GNU_push_tls_address] = Desc(Op::Dwarf3);
98   Descriptions[DW_OP_addrx] = Desc(Op::Dwarf4, Op::SizeLEB);
99   Descriptions[DW_OP_GNU_addr_index] = Desc(Op::Dwarf4, Op::SizeLEB);
100   Descriptions[DW_OP_GNU_const_index] = Desc(Op::Dwarf4, Op::SizeLEB);
101   Descriptions[DW_OP_GNU_entry_value] = Desc(Op::Dwarf4, Op::SizeLEB);
102 
103   Descriptions[DW_OP_convert] = Desc(Op::Dwarf5, Op::BaseTypeRef);
104   Descriptions[DW_OP_entry_value] = Desc(Op::Dwarf5, Op::SizeLEB);
105   Descriptions[DW_OP_regval_type] =
106       Desc(Op::Dwarf5, Op::SizeLEB, Op::BaseTypeRef);
107 
108   return Descriptions;
109 }
110 
111 static DWARFExpression::Operation::Description getOpDesc(unsigned OpCode) {
112   // FIXME: Make this constexpr once all compilers are smart enough to do it.
113   static DescVector Descriptions = getDescriptions();
114   // Handle possible corrupted or unsupported operation.
115   if (OpCode >= Descriptions.size())
116     return {};
117   return Descriptions[OpCode];
118 }
119 
120 bool DWARFExpression::Operation::extract(DataExtractor Data,
121                                          uint8_t AddressSize, uint64_t Offset,
122                                          Optional<DwarfFormat> Format) {
123   EndOffset = Offset;
124   Opcode = Data.getU8(&Offset);
125 
126   Desc = getOpDesc(Opcode);
127   if (Desc.Version == Operation::DwarfNA)
128     return false;
129 
130   for (unsigned Operand = 0; Operand < 2; ++Operand) {
131     unsigned Size = Desc.Op[Operand];
132     unsigned Signed = Size & Operation::SignBit;
133 
134     if (Size == Operation::SizeNA)
135       break;
136 
137     switch (Size & ~Operation::SignBit) {
138     case Operation::Size1:
139       Operands[Operand] = Data.getU8(&Offset);
140       if (Signed)
141         Operands[Operand] = (int8_t)Operands[Operand];
142       break;
143     case Operation::Size2:
144       Operands[Operand] = Data.getU16(&Offset);
145       if (Signed)
146         Operands[Operand] = (int16_t)Operands[Operand];
147       break;
148     case Operation::Size4:
149       Operands[Operand] = Data.getU32(&Offset);
150       if (Signed)
151         Operands[Operand] = (int32_t)Operands[Operand];
152       break;
153     case Operation::Size8:
154       Operands[Operand] = Data.getU64(&Offset);
155       break;
156     case Operation::SizeAddr:
157       Operands[Operand] = Data.getUnsigned(&Offset, AddressSize);
158       break;
159     case Operation::SizeRefAddr:
160       if (!Format)
161         return false;
162       Operands[Operand] =
163           Data.getUnsigned(&Offset, dwarf::getDwarfOffsetByteSize(*Format));
164       break;
165     case Operation::SizeLEB:
166       if (Signed)
167         Operands[Operand] = Data.getSLEB128(&Offset);
168       else
169         Operands[Operand] = Data.getULEB128(&Offset);
170       break;
171     case Operation::BaseTypeRef:
172       Operands[Operand] = Data.getULEB128(&Offset);
173       break;
174     case Operation::WasmLocationArg:
175       assert(Operand == 1);
176       switch (Operands[0]) {
177       case 0:
178       case 1:
179       case 2:
180       case 4:
181         Operands[Operand] = Data.getULEB128(&Offset);
182         break;
183       case 3: // global as uint32
184          Operands[Operand] = Data.getU32(&Offset);
185          break;
186       default:
187         return false; // Unknown Wasm location
188       }
189       break;
190     case Operation::SizeBlock:
191       // We need a size, so this cannot be the first operand
192       if (Operand == 0)
193         return false;
194       // Store the offset of the block as the value.
195       Operands[Operand] = Offset;
196       Offset += Operands[Operand - 1];
197       break;
198     default:
199       llvm_unreachable("Unknown DWARFExpression Op size");
200     }
201 
202     OperandEndOffsets[Operand] = Offset;
203   }
204 
205   EndOffset = Offset;
206   return true;
207 }
208 
209 static void prettyPrintBaseTypeRef(DWARFUnit *U, raw_ostream &OS,
210                                    DIDumpOptions DumpOpts,
211                                    const uint64_t Operands[2],
212                                    unsigned Operand) {
213   assert(Operand < 2 && "operand out of bounds");
214   auto Die = U->getDIEForOffset(U->getOffset() + Operands[Operand]);
215   if (Die && Die.getTag() == dwarf::DW_TAG_base_type) {
216     OS << " (";
217     if (DumpOpts.Verbose)
218       OS << format("0x%08" PRIx64 " -> ", Operands[Operand]);
219     OS << format("0x%08" PRIx64 ")", U->getOffset() + Operands[Operand]);
220     if (auto Name = dwarf::toString(Die.find(dwarf::DW_AT_name)))
221       OS << " \"" << *Name << "\"";
222   } else {
223     OS << format(" <invalid base_type ref: 0x%" PRIx64 ">",
224                  Operands[Operand]);
225   }
226 }
227 
228 static bool prettyPrintRegisterOp(DWARFUnit *U, raw_ostream &OS,
229                                   DIDumpOptions DumpOpts, uint8_t Opcode,
230                                   const uint64_t Operands[2],
231                                   const MCRegisterInfo *MRI, bool isEH) {
232   if (!MRI)
233     return false;
234 
235   uint64_t DwarfRegNum;
236   unsigned OpNum = 0;
237 
238   if (Opcode == DW_OP_bregx || Opcode == DW_OP_regx ||
239       Opcode == DW_OP_regval_type)
240     DwarfRegNum = Operands[OpNum++];
241   else if (Opcode >= DW_OP_breg0 && Opcode < DW_OP_bregx)
242     DwarfRegNum = Opcode - DW_OP_breg0;
243   else
244     DwarfRegNum = Opcode - DW_OP_reg0;
245 
246   if (Optional<unsigned> LLVMRegNum = MRI->getLLVMRegNum(DwarfRegNum, isEH)) {
247     if (const char *RegName = MRI->getName(*LLVMRegNum)) {
248       if ((Opcode >= DW_OP_breg0 && Opcode <= DW_OP_breg31) ||
249           Opcode == DW_OP_bregx)
250         OS << format(" %s%+" PRId64, RegName, Operands[OpNum]);
251       else
252         OS << ' ' << RegName;
253 
254       if (Opcode == DW_OP_regval_type)
255         prettyPrintBaseTypeRef(U, OS, DumpOpts, Operands, 1);
256       return true;
257     }
258   }
259 
260   return false;
261 }
262 
263 bool DWARFExpression::Operation::print(raw_ostream &OS, DIDumpOptions DumpOpts,
264                                        const DWARFExpression *Expr,
265                                        const MCRegisterInfo *RegInfo,
266                                        DWARFUnit *U, bool isEH) const {
267   if (Error) {
268     OS << "<decoding error>";
269     return false;
270   }
271 
272   StringRef Name = OperationEncodingString(Opcode);
273   assert(!Name.empty() && "DW_OP has no name!");
274   OS << Name;
275 
276   if ((Opcode >= DW_OP_breg0 && Opcode <= DW_OP_breg31) ||
277       (Opcode >= DW_OP_reg0 && Opcode <= DW_OP_reg31) ||
278       Opcode == DW_OP_bregx || Opcode == DW_OP_regx ||
279       Opcode == DW_OP_regval_type)
280     if (prettyPrintRegisterOp(U, OS, DumpOpts, Opcode, Operands, RegInfo, isEH))
281       return true;
282 
283   for (unsigned Operand = 0; Operand < 2; ++Operand) {
284     unsigned Size = Desc.Op[Operand];
285     unsigned Signed = Size & Operation::SignBit;
286 
287     if (Size == Operation::SizeNA)
288       break;
289 
290     if (Size == Operation::BaseTypeRef && U) {
291       // For DW_OP_convert the operand may be 0 to indicate that conversion to
292       // the generic type should be done. The same holds for DW_OP_reinterpret,
293       // which is currently not supported.
294       if (Opcode == DW_OP_convert && Operands[Operand] == 0)
295         OS << " 0x0";
296       else
297         prettyPrintBaseTypeRef(U, OS, DumpOpts, Operands, Operand);
298     } else if (Size == Operation::WasmLocationArg) {
299       assert(Operand == 1);
300       switch (Operands[0]) {
301       case 0:
302       case 1:
303       case 2:
304       case 3: // global as uint32
305       case 4:
306         OS << format(" 0x%" PRIx64, Operands[Operand]);
307         break;
308       default: assert(false);
309       }
310     } else if (Size == Operation::SizeBlock) {
311       uint64_t Offset = Operands[Operand];
312       for (unsigned i = 0; i < Operands[Operand - 1]; ++i)
313         OS << format(" 0x%02x", Expr->Data.getU8(&Offset));
314     } else {
315       if (Signed)
316         OS << format(" %+" PRId64, (int64_t)Operands[Operand]);
317       else if (Opcode != DW_OP_entry_value &&
318                Opcode != DW_OP_GNU_entry_value)
319         OS << format(" 0x%" PRIx64, Operands[Operand]);
320     }
321   }
322   return true;
323 }
324 
325 void DWARFExpression::print(raw_ostream &OS, DIDumpOptions DumpOpts,
326                             const MCRegisterInfo *RegInfo, DWARFUnit *U,
327                             bool IsEH) const {
328   uint32_t EntryValExprSize = 0;
329   uint64_t EntryValStartOffset = 0;
330   if (Data.getData().empty())
331     OS << "<empty>";
332 
333   for (auto &Op : *this) {
334     if (!Op.print(OS, DumpOpts, this, RegInfo, U, IsEH)) {
335       uint64_t FailOffset = Op.getEndOffset();
336       while (FailOffset < Data.getData().size())
337         OS << format(" %02x", Data.getU8(&FailOffset));
338       return;
339     }
340 
341     if (Op.getCode() == DW_OP_entry_value ||
342         Op.getCode() == DW_OP_GNU_entry_value) {
343       OS << "(";
344       EntryValExprSize = Op.getRawOperand(0);
345       EntryValStartOffset = Op.getEndOffset();
346       continue;
347     }
348 
349     if (EntryValExprSize) {
350       EntryValExprSize -= Op.getEndOffset() - EntryValStartOffset;
351       if (EntryValExprSize == 0)
352         OS << ")";
353     }
354 
355     if (Op.getEndOffset() < Data.getData().size())
356       OS << ", ";
357   }
358 }
359 
360 bool DWARFExpression::Operation::verify(const Operation &Op, DWARFUnit *U) {
361   for (unsigned Operand = 0; Operand < 2; ++Operand) {
362     unsigned Size = Op.Desc.Op[Operand];
363 
364     if (Size == Operation::SizeNA)
365       break;
366 
367     if (Size == Operation::BaseTypeRef) {
368       // For DW_OP_convert the operand may be 0 to indicate that conversion to
369       // the generic type should be done, so don't look up a base type in that
370       // case. The same holds for DW_OP_reinterpret, which is currently not
371       // supported.
372       if (Op.Opcode == DW_OP_convert && Op.Operands[Operand] == 0)
373         continue;
374       auto Die = U->getDIEForOffset(U->getOffset() + Op.Operands[Operand]);
375       if (!Die || Die.getTag() != dwarf::DW_TAG_base_type)
376         return false;
377     }
378   }
379 
380   return true;
381 }
382 
383 bool DWARFExpression::verify(DWARFUnit *U) {
384   for (auto &Op : *this)
385     if (!Operation::verify(Op, U))
386       return false;
387 
388   return true;
389 }
390 
391 /// A user-facing string representation of a DWARF expression. This might be an
392 /// Address expression, in which case it will be implicitly dereferenced, or a
393 /// Value expression.
394 struct PrintedExpr {
395   enum ExprKind {
396     Address,
397     Value,
398   };
399   ExprKind Kind;
400   SmallString<16> String;
401 
402   PrintedExpr(ExprKind K = Address) : Kind(K) {}
403 };
404 
405 static bool printCompactDWARFExpr(raw_ostream &OS, DWARFExpression::iterator I,
406                                   const DWARFExpression::iterator E,
407                                   const MCRegisterInfo &MRI) {
408   SmallVector<PrintedExpr, 4> Stack;
409 
410   while (I != E) {
411     const DWARFExpression::Operation &Op = *I;
412     uint8_t Opcode = Op.getCode();
413     switch (Opcode) {
414     case dwarf::DW_OP_regx: {
415       // DW_OP_regx: A register, with the register num given as an operand.
416       // Printed as the plain register name.
417       uint64_t DwarfRegNum = Op.getRawOperand(0);
418       Optional<unsigned> LLVMRegNum = MRI.getLLVMRegNum(DwarfRegNum, false);
419       if (!LLVMRegNum) {
420         OS << "<unknown register " << DwarfRegNum << ">";
421         return false;
422       }
423       raw_svector_ostream S(Stack.emplace_back(PrintedExpr::Value).String);
424       S << MRI.getName(*LLVMRegNum);
425       break;
426     }
427     case dwarf::DW_OP_bregx: {
428       int DwarfRegNum = Op.getRawOperand(0);
429       int64_t Offset = Op.getRawOperand(1);
430       Optional<unsigned> LLVMRegNum = MRI.getLLVMRegNum(DwarfRegNum, false);
431       if (!LLVMRegNum) {
432         OS << "<unknown register " << DwarfRegNum << ">";
433         return false;
434       }
435       raw_svector_ostream S(Stack.emplace_back().String);
436       S << MRI.getName(*LLVMRegNum);
437       if (Offset)
438         S << format("%+" PRId64, Offset);
439       break;
440     }
441     case dwarf::DW_OP_entry_value:
442     case dwarf::DW_OP_GNU_entry_value: {
443       // DW_OP_entry_value contains a sub-expression which must be rendered
444       // separately.
445       uint64_t SubExprLength = Op.getRawOperand(0);
446       DWARFExpression::iterator SubExprEnd = I.skipBytes(SubExprLength);
447       ++I;
448       raw_svector_ostream S(Stack.emplace_back().String);
449       S << "entry(";
450       printCompactDWARFExpr(S, I, SubExprEnd, MRI);
451       S << ")";
452       I = SubExprEnd;
453       continue;
454     }
455     case dwarf::DW_OP_stack_value: {
456       // The top stack entry should be treated as the actual value of tne
457       // variable, rather than the address of the variable in memory.
458       assert(!Stack.empty());
459       Stack.back().Kind = PrintedExpr::Value;
460       break;
461     }
462     default:
463       if (Opcode >= dwarf::DW_OP_reg0 && Opcode <= dwarf::DW_OP_reg31) {
464         // DW_OP_reg<N>: A register, with the register num implied by the
465         // opcode. Printed as the plain register name.
466         uint64_t DwarfRegNum = Opcode - dwarf::DW_OP_reg0;
467         Optional<unsigned> LLVMRegNum = MRI.getLLVMRegNum(DwarfRegNum, false);
468         if (!LLVMRegNum) {
469           OS << "<unknown register " << DwarfRegNum << ">";
470           return false;
471         }
472         raw_svector_ostream S(Stack.emplace_back(PrintedExpr::Value).String);
473         S << MRI.getName(*LLVMRegNum);
474       } else if (Opcode >= dwarf::DW_OP_breg0 &&
475                  Opcode <= dwarf::DW_OP_breg31) {
476         int DwarfRegNum = Opcode - dwarf::DW_OP_breg0;
477         int64_t Offset = Op.getRawOperand(0);
478         Optional<unsigned> LLVMRegNum = MRI.getLLVMRegNum(DwarfRegNum, false);
479         if (!LLVMRegNum) {
480           OS << "<unknown register " << DwarfRegNum << ">";
481           return false;
482         }
483         raw_svector_ostream S(Stack.emplace_back().String);
484         S << MRI.getName(*LLVMRegNum);
485         if (Offset)
486           S << format("%+" PRId64, Offset);
487       } else {
488         // If we hit an unknown operand, we don't know its effect on the stack,
489         // so bail out on the whole expression.
490         OS << "<unknown op " << dwarf::OperationEncodingString(Opcode) << " ("
491            << (int)Opcode << ")>";
492         return false;
493       }
494       break;
495     }
496     ++I;
497   }
498 
499   assert(Stack.size() == 1 && "expected one value on stack");
500 
501   if (Stack.front().Kind == PrintedExpr::Address)
502     OS << "[" << Stack.front().String << "]";
503   else
504     OS << Stack.front().String;
505 
506   return true;
507 }
508 
509 bool DWARFExpression::printCompact(raw_ostream &OS, const MCRegisterInfo &MRI) {
510   return printCompactDWARFExpr(OS, begin(), end(), MRI);
511 }
512 
513 bool DWARFExpression::operator==(const DWARFExpression &RHS) const {
514   if (AddressSize != RHS.AddressSize || Format != RHS.Format)
515     return false;
516   return Data.getData() == RHS.Data.getData();
517 }
518 
519 } // namespace llvm
520