1//=- AArch64.td - Describe the AArch64 Target Machine --------*- tablegen -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9//
10//===----------------------------------------------------------------------===//
11
12//===----------------------------------------------------------------------===//
13// Target-independent interfaces which we are implementing.
14//===----------------------------------------------------------------------===//
15
16include "llvm/Target/Target.td"
17
18//===----------------------------------------------------------------------===//
19// AArch64 Subtarget features.
20//
21
22def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true",
23                                       "Enable ARMv8 FP">;
24
25def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
26  "Enable Advanced SIMD instructions", [FeatureFPARMv8]>;
27
28def FeatureSM4 : SubtargetFeature<
29    "sm4", "HasSM4", "true",
30    "Enable SM3 and SM4 support", [FeatureNEON]>;
31
32def FeatureSHA2 : SubtargetFeature<
33    "sha2", "HasSHA2", "true",
34    "Enable SHA1 and SHA256 support", [FeatureNEON]>;
35
36def FeatureSHA3 : SubtargetFeature<
37    "sha3", "HasSHA3", "true",
38    "Enable SHA512 and SHA3 support", [FeatureNEON, FeatureSHA2]>;
39
40def FeatureAES : SubtargetFeature<
41    "aes", "HasAES", "true",
42    "Enable AES support", [FeatureNEON]>;
43
44// Crypto has been split up and any combination is now valid (see the
45// crypto definitions above). Also, crypto is now context sensitive:
46// it has a different meaning for e.g. Armv8.4 than it has for Armv8.2.
47// Therefore, we rely on Clang, the user interacing tool, to pass on the
48// appropriate crypto options. But here in the backend, crypto has very little
49// meaning anymore. We kept the Crypto definition here for backward
50// compatibility, and now imply features SHA2 and AES, which was the
51// "traditional" meaning of Crypto.
52def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
53  "Enable cryptographic instructions", [FeatureNEON, FeatureSHA2, FeatureAES]>;
54
55def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
56  "Enable ARMv8 CRC-32 checksum instructions">;
57
58def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true",
59  "Enable ARMv8 Reliability, Availability and Serviceability Extensions">;
60
61def FeatureLSE : SubtargetFeature<"lse", "HasLSE", "true",
62  "Enable ARMv8.1 Large System Extension (LSE) atomic instructions">;
63
64def FeatureLSE2 : SubtargetFeature<"lse2", "HasLSE2", "true",
65  "Enable ARMv8.4 Large System Extension 2 (LSE2) atomicity rules">;
66
67def FeatureOutlineAtomics : SubtargetFeature<"outline-atomics", "OutlineAtomics", "true",
68  "Enable out of line atomics to support LSE instructions">;
69
70def FeatureRDM : SubtargetFeature<"rdm", "HasRDM", "true",
71  "Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions">;
72
73def FeaturePAN : SubtargetFeature<
74    "pan", "HasPAN", "true",
75    "Enables ARM v8.1 Privileged Access-Never extension">;
76
77def FeatureLOR : SubtargetFeature<
78    "lor", "HasLOR", "true",
79    "Enables ARM v8.1 Limited Ordering Regions extension">;
80
81def FeatureCONTEXTIDREL2 : SubtargetFeature<"CONTEXTIDREL2", "HasCONTEXTIDREL2",
82    "true", "Enable RW operand CONTEXTIDR_EL2" >;
83
84def FeatureVH : SubtargetFeature<"vh", "HasVH", "true",
85    "Enables ARM v8.1 Virtual Host extension", [FeatureCONTEXTIDREL2] >;
86
87def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
88  "Enable ARMv8 PMUv3 Performance Monitors extension">;
89
90def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
91  "Full FP16", [FeatureFPARMv8]>;
92
93def FeatureFP16FML : SubtargetFeature<"fp16fml", "HasFP16FML", "true",
94  "Enable FP16 FML instructions", [FeatureFullFP16]>;
95
96def FeatureSPE : SubtargetFeature<"spe", "HasSPE", "true",
97  "Enable Statistical Profiling extension">;
98
99def FeaturePAN_RWV : SubtargetFeature<
100    "pan-rwv", "HasPAN_RWV", "true",
101    "Enable v8.2 PAN s1e1R and s1e1W Variants",
102    [FeaturePAN]>;
103
104// UAO PState
105def FeaturePsUAO : SubtargetFeature< "uaops", "HasPsUAO", "true",
106    "Enable v8.2 UAO PState">;
107
108def FeatureCCPP : SubtargetFeature<"ccpp", "HasCCPP",
109    "true", "Enable v8.2 data Cache Clean to Point of Persistence" >;
110
111def FeatureSVE : SubtargetFeature<"sve", "HasSVE", "true",
112  "Enable Scalable Vector Extension (SVE) instructions", [FeatureFullFP16]>;
113
114// This flag is currently still labeled as Experimental, but when fully
115// implemented this should tell the compiler to use the zeroing pseudos to
116// benefit from the reverse instructions (e.g. SUB vs SUBR) if the inactive
117// lanes are known to be zero. The pseudos will then be expanded using the
118// MOVPRFX instruction to zero the inactive lanes. This feature should only be
119// enabled if MOVPRFX instructions are known to merge with the destructive
120// operations they prefix.
121//
122// This feature could similarly be extended to support cheap merging of _any_
123// value into the inactive lanes using the MOVPRFX instruction that uses
124// merging-predication.
125def FeatureExperimentalZeroingPseudos
126    : SubtargetFeature<"use-experimental-zeroing-pseudos",
127                       "UseExperimentalZeroingPseudos", "true",
128                       "Hint to the compiler that the MOVPRFX instruction is "
129                       "merged with destructive operations",
130                       []>;
131
132def FeatureUseScalarIncVL : SubtargetFeature<"use-scalar-inc-vl",
133  "UseScalarIncVL", "true", "Prefer inc/dec over add+cnt">;
134
135def FeatureSVE2 : SubtargetFeature<"sve2", "HasSVE2", "true",
136  "Enable Scalable Vector Extension 2 (SVE2) instructions",
137  [FeatureSVE, FeatureUseScalarIncVL]>;
138
139def FeatureSVE2AES : SubtargetFeature<"sve2-aes", "HasSVE2AES", "true",
140  "Enable AES SVE2 instructions", [FeatureSVE2, FeatureAES]>;
141
142def FeatureSVE2SM4 : SubtargetFeature<"sve2-sm4", "HasSVE2SM4", "true",
143  "Enable SM4 SVE2 instructions", [FeatureSVE2, FeatureSM4]>;
144
145def FeatureSVE2SHA3 : SubtargetFeature<"sve2-sha3", "HasSVE2SHA3", "true",
146  "Enable SHA3 SVE2 instructions", [FeatureSVE2, FeatureSHA3]>;
147
148def FeatureSVE2BitPerm : SubtargetFeature<"sve2-bitperm", "HasSVE2BitPerm", "true",
149  "Enable bit permutation SVE2 instructions", [FeatureSVE2]>;
150
151def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
152                                        "Has zero-cycle register moves">;
153
154def FeatureZCZeroingGP : SubtargetFeature<"zcz-gp", "HasZeroCycleZeroingGP", "true",
155                                        "Has zero-cycle zeroing instructions for generic registers">;
156
157def FeatureNoZCZeroingFP : SubtargetFeature<"no-zcz-fp", "HasZeroCycleZeroingFP", "false",
158                                        "Has no zero-cycle zeroing instructions for FP registers">;
159
160def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
161                                        "Has zero-cycle zeroing instructions",
162                                        [FeatureZCZeroingGP]>;
163
164/// ... but the floating-point version doesn't quite work in rare cases on older
165/// CPUs.
166def FeatureZCZeroingFPWorkaround : SubtargetFeature<"zcz-fp-workaround",
167    "HasZeroCycleZeroingFPWorkaround", "true",
168    "The zero-cycle floating-point zeroing instruction has a bug">;
169
170def FeatureStrictAlign : SubtargetFeature<"strict-align",
171                                          "StrictAlign", "true",
172                                          "Disallow all unaligned memory "
173                                          "access">;
174
175foreach i = {1-7,9-15,18,20-28,30} in
176    def FeatureReserveX#i : SubtargetFeature<"reserve-x"#i, "ReserveXRegister["#i#"]", "true",
177                                             "Reserve X"#i#", making it unavailable "
178                                             "as a GPR">;
179
180foreach i = {8-15,18} in
181    def FeatureCallSavedX#i : SubtargetFeature<"call-saved-x"#i,
182         "CustomCallSavedXRegs["#i#"]", "true", "Make X"#i#" callee saved.">;
183
184def FeatureBalanceFPOps : SubtargetFeature<"balance-fp-ops", "BalanceFPOps",
185    "true",
186    "balance mix of odd and even D-registers for fp multiply(-accumulate) ops">;
187
188def FeaturePredictableSelectIsExpensive : SubtargetFeature<
189    "predictable-select-expensive", "PredictableSelectIsExpensive", "true",
190    "Prefer likely predicted branches over selects">;
191
192def FeatureCustomCheapAsMoveHandling : SubtargetFeature<"custom-cheap-as-move",
193    "CustomAsCheapAsMove", "true",
194    "Use custom handling of cheap instructions">;
195
196def FeatureExynosCheapAsMoveHandling : SubtargetFeature<"exynos-cheap-as-move",
197    "ExynosAsCheapAsMove", "true",
198    "Use Exynos specific handling of cheap instructions",
199    [FeatureCustomCheapAsMoveHandling]>;
200
201def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler",
202    "UsePostRAScheduler", "true", "Schedule again after register allocation">;
203
204def FeatureSlowMisaligned128Store : SubtargetFeature<"slow-misaligned-128store",
205    "Misaligned128StoreIsSlow", "true", "Misaligned 128 bit stores are slow">;
206
207def FeatureSlowPaired128 : SubtargetFeature<"slow-paired-128",
208    "Paired128IsSlow", "true", "Paired 128 bit loads and stores are slow">;
209
210def FeatureSlowSTRQro : SubtargetFeature<"slow-strqro-store", "STRQroIsSlow",
211    "true", "STR of Q register with register offset is slow">;
212
213def FeatureAlternateSExtLoadCVTF32Pattern : SubtargetFeature<
214    "alternate-sextload-cvt-f32-pattern", "UseAlternateSExtLoadCVTF32Pattern",
215    "true", "Use alternative pattern for sextload convert to f32">;
216
217def FeatureArithmeticBccFusion : SubtargetFeature<
218    "arith-bcc-fusion", "HasArithmeticBccFusion", "true",
219    "CPU fuses arithmetic+bcc operations">;
220
221def FeatureArithmeticCbzFusion : SubtargetFeature<
222    "arith-cbz-fusion", "HasArithmeticCbzFusion", "true",
223    "CPU fuses arithmetic + cbz/cbnz operations">;
224
225def FeatureCmpBccFusion : SubtargetFeature<
226    "cmp-bcc-fusion", "HasCmpBccFusion", "true",
227    "CPU fuses cmp+bcc operations">;
228
229def FeatureFuseAddress : SubtargetFeature<
230    "fuse-address", "HasFuseAddress", "true",
231    "CPU fuses address generation and memory operations">;
232
233def FeatureFuseAES : SubtargetFeature<
234    "fuse-aes", "HasFuseAES", "true",
235    "CPU fuses AES crypto operations">;
236
237def FeatureFuseArithmeticLogic : SubtargetFeature<
238    "fuse-arith-logic", "HasFuseArithmeticLogic", "true",
239    "CPU fuses arithmetic and logic operations">;
240
241def FeatureFuseCCSelect : SubtargetFeature<
242    "fuse-csel", "HasFuseCCSelect", "true",
243    "CPU fuses conditional select operations">;
244
245def FeatureFuseCryptoEOR : SubtargetFeature<
246    "fuse-crypto-eor", "HasFuseCryptoEOR", "true",
247    "CPU fuses AES/PMULL and EOR operations">;
248
249def FeatureFuseLiterals : SubtargetFeature<
250    "fuse-literals", "HasFuseLiterals", "true",
251    "CPU fuses literal generation operations">;
252
253def FeatureDisableLatencySchedHeuristic : SubtargetFeature<
254    "disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true",
255    "Disable latency scheduling heuristic">;
256
257def FeatureForce32BitJumpTables
258   : SubtargetFeature<"force-32bit-jump-tables", "Force32BitJumpTables", "true",
259                      "Force jump table entries to be 32-bits wide except at MinSize">;
260
261def FeatureRCPC : SubtargetFeature<"rcpc", "HasRCPC", "true",
262                                   "Enable support for RCPC extension">;
263
264def FeatureUseRSqrt : SubtargetFeature<
265    "use-reciprocal-square-root", "UseRSqrt", "true",
266    "Use the reciprocal square root approximation">;
267
268def FeatureDotProd : SubtargetFeature<
269    "dotprod", "HasDotProd", "true",
270    "Enable dot product support">;
271
272def FeaturePAuth : SubtargetFeature<
273    "pauth", "HasPAuth", "true",
274    "Enable v8.3-A Pointer Authentication extension">;
275
276def FeatureJS : SubtargetFeature<
277    "jsconv", "HasJS", "true",
278    "Enable v8.3-A JavaScript FP conversion instructions",
279    [FeatureFPARMv8]>;
280
281def FeatureCCIDX : SubtargetFeature<
282    "ccidx", "HasCCIDX", "true",
283    "Enable v8.3-A Extend of the CCSIDR number of sets">;
284
285def FeatureComplxNum : SubtargetFeature<
286    "complxnum", "HasComplxNum", "true",
287    "Enable v8.3-A Floating-point complex number support",
288    [FeatureNEON]>;
289
290def FeatureNV : SubtargetFeature<
291    "nv", "HasNV", "true",
292    "Enable v8.4-A Nested Virtualization Enchancement">;
293
294def FeatureMPAM : SubtargetFeature<
295    "mpam", "HasMPAM", "true",
296    "Enable v8.4-A Memory system Partitioning and Monitoring extension">;
297
298def FeatureDIT : SubtargetFeature<
299    "dit", "HasDIT", "true",
300    "Enable v8.4-A Data Independent Timing instructions">;
301
302def FeatureTRACEV8_4 : SubtargetFeature<
303    "tracev8.4", "HasTRACEV8_4", "true",
304    "Enable v8.4-A Trace extension">;
305
306def FeatureAM : SubtargetFeature<
307    "am", "HasAM", "true",
308    "Enable v8.4-A Activity Monitors extension">;
309
310def FeatureAMVS : SubtargetFeature<
311    "amvs", "HasAMVS", "true",
312    "Enable v8.6-A Activity Monitors Virtualization support",
313    [FeatureAM]>;
314
315def FeatureSEL2 : SubtargetFeature<
316    "sel2", "HasSEL2", "true",
317    "Enable v8.4-A Secure Exception Level 2 extension">;
318
319def FeatureTLB_RMI : SubtargetFeature<
320    "tlb-rmi", "HasTLB_RMI", "true",
321    "Enable v8.4-A TLB Range and Maintenance Instructions">;
322
323def FeatureFlagM : SubtargetFeature<
324    "flagm", "HasFlagM", "true",
325    "Enable v8.4-A Flag Manipulation Instructions">;
326
327// 8.4 RCPC enchancements: LDAPR & STLR instructions with Immediate Offset
328def FeatureRCPC_IMMO : SubtargetFeature<"rcpc-immo", "HasRCPC_IMMO", "true",
329    "Enable v8.4-A RCPC instructions with Immediate Offsets",
330    [FeatureRCPC]>;
331
332def FeatureNoNegativeImmediates : SubtargetFeature<"no-neg-immediates",
333                                        "NegativeImmediates", "false",
334                                        "Convert immediates and instructions "
335                                        "to their negated or complemented "
336                                        "equivalent when the immediate does "
337                                        "not fit in the encoding.">;
338
339def FeatureLSLFast : SubtargetFeature<
340    "lsl-fast", "HasLSLFast", "true",
341    "CPU has a fastpath logical shift of up to 3 places">;
342
343def FeatureAggressiveFMA :
344  SubtargetFeature<"aggressive-fma",
345                   "HasAggressiveFMA",
346                   "true",
347                   "Enable Aggressive FMA for floating-point.">;
348
349def FeatureAltFPCmp : SubtargetFeature<"altnzcv", "HasAlternativeNZCV", "true",
350  "Enable alternative NZCV format for floating point comparisons">;
351
352def FeatureFRInt3264 : SubtargetFeature<"fptoint", "HasFRInt3264", "true",
353  "Enable FRInt[32|64][Z|X] instructions that round a floating-point number to "
354  "an integer (in FP format) forcing it to fit into a 32- or 64-bit int" >;
355
356def FeatureSpecRestrict : SubtargetFeature<"specrestrict", "HasSpecRestrict",
357  "true", "Enable architectural speculation restriction" >;
358
359def FeatureSB : SubtargetFeature<"sb", "HasSB",
360  "true", "Enable v8.5 Speculation Barrier" >;
361
362def FeatureSSBS : SubtargetFeature<"ssbs", "HasSSBS",
363  "true", "Enable Speculative Store Bypass Safe bit" >;
364
365def FeaturePredRes : SubtargetFeature<"predres", "HasPredRes", "true",
366  "Enable v8.5a execution and data prediction invalidation instructions" >;
367
368def FeatureCacheDeepPersist : SubtargetFeature<"ccdp", "HasCCDP",
369    "true", "Enable v8.5 Cache Clean to Point of Deep Persistence" >;
370
371def FeatureBranchTargetId : SubtargetFeature<"bti", "HasBTI",
372    "true", "Enable Branch Target Identification" >;
373
374def FeatureRandGen : SubtargetFeature<"rand", "HasRandGen",
375    "true", "Enable Random Number generation instructions" >;
376
377def FeatureMTE : SubtargetFeature<"mte", "HasMTE",
378    "true", "Enable Memory Tagging Extension" >;
379
380def FeatureTRBE : SubtargetFeature<"trbe", "HasTRBE",
381    "true", "Enable Trace Buffer Extension">;
382
383def FeatureETE : SubtargetFeature<"ete", "HasETE",
384    "true", "Enable Embedded Trace Extension",
385    [FeatureTRBE]>;
386
387def FeatureTME : SubtargetFeature<"tme", "HasTME",
388    "true", "Enable Transactional Memory Extension" >;
389
390def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals",
391    "AllowTaggedGlobals",
392    "true", "Use an instruction sequence for taking the address of a global "
393    "that allows a memory tag in the upper address bits">;
394
395def FeatureBF16 : SubtargetFeature<"bf16", "HasBF16",
396    "true", "Enable BFloat16 Extension" >;
397
398def FeatureMatMulInt8 : SubtargetFeature<"i8mm", "HasMatMulInt8",
399    "true", "Enable Matrix Multiply Int8 Extension">;
400
401def FeatureMatMulFP32 : SubtargetFeature<"f32mm", "HasMatMulFP32",
402    "true", "Enable Matrix Multiply FP32 Extension", [FeatureSVE]>;
403
404def FeatureMatMulFP64 : SubtargetFeature<"f64mm", "HasMatMulFP64",
405    "true", "Enable Matrix Multiply FP64 Extension", [FeatureSVE]>;
406
407def FeatureXS : SubtargetFeature<"xs", "HasXS",
408    "true", "Enable Armv8.7-A limited-TLB-maintenance instruction">;
409
410def FeatureWFxT : SubtargetFeature<"wfxt", "HasWFxT",
411    "true", "Enable Armv8.7-A WFET and WFIT instruction">;
412
413def FeatureHCX : SubtargetFeature<
414    "hcx", "HasHCX", "true", "Enable Armv8.7-A HCRX_EL2 system register">;
415
416def FeatureLS64 : SubtargetFeature<"ls64", "HasLS64",
417    "true", "Enable Armv8.7-A LD64B/ST64B Accelerator Extension">;
418
419def FeatureHBC : SubtargetFeature<"hbc", "HasHBC",
420    "true", "Enable Armv8.8-A Hinted Conditional Branches Extension">;
421
422def FeatureMOPS : SubtargetFeature<"mops", "HasMOPS",
423    "true", "Enable Armv8.8-A memcpy and memset acceleration instructions">;
424
425def FeatureBRBE : SubtargetFeature<"brbe", "HasBRBE",
426    "true", "Enable Branch Record Buffer Extension">;
427
428def FeatureSPE_EEF : SubtargetFeature<"spe-eef", "HasSPE_EEF",
429    "true", "Enable extra register in the Statistical Profiling Extension">;
430
431def FeatureFineGrainedTraps : SubtargetFeature<"fgt", "HasFineGrainedTraps",
432    "true", "Enable fine grained virtualization traps extension">;
433
434def FeatureEnhancedCounterVirtualization :
435      SubtargetFeature<"ecv", "HasEnhancedCounterVirtualization",
436      "true", "Enable enhanced counter virtualization extension">;
437
438def FeatureRME : SubtargetFeature<"rme", "HasRME",
439    "true", "Enable Realm Management Extension">;
440
441// A subset of SVE(2) instructions are legal in Streaming SVE execution mode
442// defined by SME.
443def FeatureStreamingSVE : SubtargetFeature<"streaming-sve",
444                                           "HasStreamingSVE", "true",
445  "Enable subset of SVE(2) instructions for Streaming SVE execution mode">;
446def FeatureSME : SubtargetFeature<"sme", "HasSME", "true",
447  "Enable Scalable Matrix Extension (SME)", [FeatureStreamingSVE, FeatureBF16]>;
448
449def FeatureSMEF64 : SubtargetFeature<"sme-f64", "HasSMEF64", "true",
450  "Enable Scalable Matrix Extension (SME) F64F64 instructions", [FeatureSME]>;
451
452def FeatureSMEI64 : SubtargetFeature<"sme-i64", "HasSMEI64", "true",
453  "Enable Scalable Matrix Extension (SME) I16I64 instructions", [FeatureSME]>;
454
455def FeatureAppleA7SysReg  : SubtargetFeature<"apple-a7-sysreg", "HasAppleA7SysReg", "true",
456  "Apple A7 (the CPU formerly known as Cyclone)">;
457
458def FeatureEL2VMSA : SubtargetFeature<"el2vmsa", "HasEL2VMSA", "true",
459  "Enable Exception Level 2 Virtual Memory System Architecture">;
460
461def FeatureEL3 : SubtargetFeature<"el3", "HasEL3", "true",
462  "Enable Exception Level 3">;
463
464def FeatureFixCortexA53_835769 : SubtargetFeature<"fix-cortex-a53-835769",
465  "FixCortexA53_835769", "true", "Mitigate Cortex-A53 Erratum 835769">;
466
467def FeatureNoBTIAtReturnTwice : SubtargetFeature<"no-bti-at-return-twice",
468                                                 "NoBTIAtReturnTwice", "true",
469                                                 "Don't place a BTI instruction "
470                                                 "after a return-twice">;
471
472//===----------------------------------------------------------------------===//
473// Architectures.
474//
475def HasV8_0aOps : SubtargetFeature<"v8a", "HasV8_0aOps", "true",
476  "Support ARM v8.0a instructions", [FeatureEL2VMSA, FeatureEL3]>;
477
478def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
479  "Support ARM v8.1a instructions", [HasV8_0aOps, FeatureCRC, FeatureLSE,
480  FeatureRDM, FeaturePAN, FeatureLOR, FeatureVH]>;
481
482def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
483  "Support ARM v8.2a instructions", [HasV8_1aOps, FeaturePsUAO,
484  FeaturePAN_RWV, FeatureRAS, FeatureCCPP]>;
485
486def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true",
487  "Support ARM v8.3a instructions", [HasV8_2aOps, FeatureRCPC, FeaturePAuth,
488  FeatureJS, FeatureCCIDX, FeatureComplxNum]>;
489
490def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true",
491  "Support ARM v8.4a instructions", [HasV8_3aOps, FeatureDotProd,
492  FeatureNV, FeatureMPAM, FeatureDIT,
493  FeatureTRACEV8_4, FeatureAM, FeatureSEL2, FeatureTLB_RMI,
494  FeatureFlagM, FeatureRCPC_IMMO, FeatureLSE2]>;
495
496def HasV8_5aOps : SubtargetFeature<
497  "v8.5a", "HasV8_5aOps", "true", "Support ARM v8.5a instructions",
498  [HasV8_4aOps, FeatureAltFPCmp, FeatureFRInt3264, FeatureSpecRestrict,
499   FeatureSSBS, FeatureSB, FeaturePredRes, FeatureCacheDeepPersist,
500   FeatureBranchTargetId]>;
501
502def HasV8_6aOps : SubtargetFeature<
503  "v8.6a", "HasV8_6aOps", "true", "Support ARM v8.6a instructions",
504  [HasV8_5aOps, FeatureAMVS, FeatureBF16, FeatureFineGrainedTraps,
505   FeatureEnhancedCounterVirtualization, FeatureMatMulInt8]>;
506
507def HasV8_7aOps : SubtargetFeature<
508  "v8.7a", "HasV8_7aOps", "true", "Support ARM v8.7a instructions",
509  [HasV8_6aOps, FeatureXS, FeatureWFxT, FeatureHCX]>;
510
511def HasV8_8aOps : SubtargetFeature<
512  "v8.8a", "HasV8_8aOps", "true", "Support ARM v8.8a instructions",
513  [HasV8_7aOps, FeatureHBC, FeatureMOPS]>;
514
515def HasV9_0aOps : SubtargetFeature<
516  "v9a", "HasV9_0aOps", "true", "Support ARM v9a instructions",
517  [HasV8_5aOps, FeatureSVE2]>;
518
519def HasV9_1aOps : SubtargetFeature<
520  "v9.1a", "HasV9_1aOps", "true", "Support ARM v9.1a instructions",
521  [HasV8_6aOps, HasV9_0aOps]>;
522
523def HasV9_2aOps : SubtargetFeature<
524  "v9.2a", "HasV9_2aOps", "true", "Support ARM v9.2a instructions",
525  [HasV8_7aOps, HasV9_1aOps]>;
526
527def HasV9_3aOps : SubtargetFeature<
528  "v9.3a", "HasV9_3aOps", "true", "Support ARM v9.3a instructions",
529  [HasV8_8aOps, HasV9_2aOps]>;
530
531def HasV8_0rOps : SubtargetFeature<
532  "v8r", "HasV8_0rOps", "true", "Support ARM v8r instructions",
533  [//v8.1
534  FeatureCRC, FeaturePAN, FeatureRDM, FeatureLSE, FeatureCONTEXTIDREL2,
535  //v8.2
536  FeatureRAS, FeaturePsUAO, FeatureCCPP, FeaturePAN_RWV,
537  //v8.3
538  FeatureComplxNum, FeatureCCIDX, FeatureJS,
539  FeaturePAuth, FeatureRCPC,
540  //v8.4
541  FeatureDotProd, FeatureTRACEV8_4, FeatureTLB_RMI,
542  FeatureFlagM, FeatureDIT, FeatureSEL2, FeatureRCPC_IMMO]>;
543
544//===----------------------------------------------------------------------===//
545// Register File Description
546//===----------------------------------------------------------------------===//
547
548include "AArch64RegisterInfo.td"
549include "AArch64RegisterBanks.td"
550include "AArch64CallingConvention.td"
551
552//===----------------------------------------------------------------------===//
553// Instruction Descriptions
554//===----------------------------------------------------------------------===//
555
556include "AArch64Schedule.td"
557include "AArch64InstrInfo.td"
558include "AArch64SchedPredicates.td"
559include "AArch64SchedPredExynos.td"
560include "AArch64SchedPredAmpere.td"
561include "AArch64Combine.td"
562
563def AArch64InstrInfo : InstrInfo;
564
565//===----------------------------------------------------------------------===//
566// Named operands for MRS/MSR/TLBI/...
567//===----------------------------------------------------------------------===//
568
569include "AArch64SystemOperands.td"
570
571//===----------------------------------------------------------------------===//
572// Access to privileged registers
573//===----------------------------------------------------------------------===//
574
575foreach i = 1-3 in
576def FeatureUseEL#i#ForTP : SubtargetFeature<"tpidr-el"#i, "UseEL"#i#"ForTP",
577  "true", "Permit use of TPIDR_EL"#i#" for the TLS base">;
578
579//===----------------------------------------------------------------------===//
580// Control codegen mitigation against Straight Line Speculation vulnerability.
581//===----------------------------------------------------------------------===//
582
583def FeatureHardenSlsRetBr : SubtargetFeature<"harden-sls-retbr",
584  "HardenSlsRetBr", "true",
585  "Harden against straight line speculation across RET and BR instructions">;
586def FeatureHardenSlsBlr : SubtargetFeature<"harden-sls-blr",
587  "HardenSlsBlr", "true",
588  "Harden against straight line speculation across BLR instructions">;
589def FeatureHardenSlsNoComdat : SubtargetFeature<"harden-sls-nocomdat",
590  "HardenSlsNoComdat", "true",
591  "Generate thunk code for SLS mitigation in the normal text section">;
592
593//===----------------------------------------------------------------------===//
594// AArch64 Processors supported.
595//
596
597//===----------------------------------------------------------------------===//
598// Unsupported features to disable for scheduling models
599//===----------------------------------------------------------------------===//
600
601class AArch64Unsupported { list<Predicate> F; }
602
603def SVEUnsupported : AArch64Unsupported {
604  let F = [HasSVE, HasSVE2, HasSVE2AES, HasSVE2SM4, HasSVE2SHA3,
605           HasSVE2BitPerm, HasSVEorStreamingSVE, HasSVE2orStreamingSVE];
606}
607
608def PAUnsupported : AArch64Unsupported {
609  let F = [HasPAuth];
610}
611
612def SMEUnsupported : AArch64Unsupported {
613  let F = [HasSME, HasSMEF64, HasSMEI64];
614}
615
616include "AArch64SchedA53.td"
617include "AArch64SchedA55.td"
618include "AArch64SchedA57.td"
619include "AArch64SchedCyclone.td"
620include "AArch64SchedFalkor.td"
621include "AArch64SchedKryo.td"
622include "AArch64SchedExynosM3.td"
623include "AArch64SchedExynosM4.td"
624include "AArch64SchedExynosM5.td"
625include "AArch64SchedThunderX.td"
626include "AArch64SchedThunderX2T99.td"
627include "AArch64SchedA64FX.td"
628include "AArch64SchedThunderX3T110.td"
629include "AArch64SchedTSV110.td"
630include "AArch64SchedAmpere1.td"
631
632def TuneA35     : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35",
633                                "Cortex-A35 ARM processors">;
634
635def TuneA53     : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
636                                   "Cortex-A53 ARM processors", [
637                                   FeatureFuseAES,
638                                   FeatureBalanceFPOps,
639                                   FeatureCustomCheapAsMoveHandling,
640                                   FeaturePostRAScheduler]>;
641
642def TuneA55     : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55",
643                                   "Cortex-A55 ARM processors", [
644                                   FeatureFuseAES,
645                                   FeaturePostRAScheduler,
646                                   FeatureFuseAddress]>;
647
648def TuneA510    : SubtargetFeature<"a510", "ARMProcFamily", "CortexA510",
649                                   "Cortex-A510 ARM processors", [
650                                   FeatureFuseAES,
651                                   FeaturePostRAScheduler
652                                   ]>;
653
654def TuneA57     : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
655                                   "Cortex-A57 ARM processors", [
656                                   FeatureFuseAES,
657                                   FeatureBalanceFPOps,
658                                   FeatureCustomCheapAsMoveHandling,
659                                   FeatureFuseLiterals,
660                                   FeaturePostRAScheduler,
661                                   FeaturePredictableSelectIsExpensive]>;
662
663def TuneA65     : SubtargetFeature<"a65", "ARMProcFamily", "CortexA65",
664                                   "Cortex-A65 ARM processors", [
665                                   FeatureFuseAES,
666                                   FeatureFuseAddress,
667                                   FeatureFuseLiterals]>;
668
669def TuneA72     : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72",
670                                   "Cortex-A72 ARM processors", [
671                                   FeatureFuseAES,
672                                   FeatureFuseLiterals]>;
673
674def TuneA73     : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73",
675                                   "Cortex-A73 ARM processors", [
676                                   FeatureFuseAES]>;
677
678def TuneA75     : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75",
679                                   "Cortex-A75 ARM processors", [
680                                   FeatureFuseAES]>;
681
682def TuneA76     : SubtargetFeature<"a76", "ARMProcFamily", "CortexA76",
683                                   "Cortex-A76 ARM processors", [
684                                   FeatureFuseAES]>;
685
686def TuneA77     : SubtargetFeature<"a77", "ARMProcFamily", "CortexA77",
687                                   "Cortex-A77 ARM processors", [
688                                   FeatureCmpBccFusion,
689                                   FeatureFuseAES]>;
690
691def TuneA78 : SubtargetFeature<"a78", "ARMProcFamily", "CortexA78",
692                               "Cortex-A78 ARM processors", [
693                               FeatureCmpBccFusion,
694                               FeatureFuseAES,
695                               FeaturePostRAScheduler]>;
696
697def TuneA78C : SubtargetFeature<"a78c", "ARMProcFamily",
698                                "CortexA78C",
699                                "Cortex-A78C ARM processors", [
700                                FeatureCmpBccFusion,
701                                FeatureFuseAES,
702                                FeaturePostRAScheduler]>;
703
704def TuneA710    : SubtargetFeature<"a710", "ARMProcFamily", "CortexA710",
705                                   "Cortex-A710 ARM processors", [
706                                   FeatureFuseAES,
707                                   FeaturePostRAScheduler,
708                                   FeatureCmpBccFusion]>;
709
710def TuneR82 : SubtargetFeature<"cortex-r82", "ARMProcFamily",
711                               "CortexR82",
712                               "Cortex-R82 ARM processors", [
713                               FeaturePostRAScheduler]>;
714
715def TuneX1 : SubtargetFeature<"cortex-x1", "ARMProcFamily", "CortexX1",
716                                  "Cortex-X1 ARM processors", [
717                                  FeatureCmpBccFusion,
718                                  FeatureFuseAES,
719                                  FeaturePostRAScheduler]>;
720
721def TuneX2 : SubtargetFeature<"cortex-x2", "ARMProcFamily", "CortexX2",
722                                  "Cortex-X2 ARM processors", [
723                                  FeatureFuseAES,
724                                  FeaturePostRAScheduler,
725                                  FeatureCmpBccFusion]>;
726
727def TuneA64FX : SubtargetFeature<"a64fx", "ARMProcFamily", "A64FX",
728                                 "Fujitsu A64FX processors", [
729                                 FeaturePostRAScheduler,
730                                 FeatureAggressiveFMA,
731                                 FeatureArithmeticBccFusion,
732                                 FeaturePredictableSelectIsExpensive
733                                 ]>;
734
735def TuneCarmel : SubtargetFeature<"carmel", "ARMProcFamily", "Carmel",
736                                  "Nvidia Carmel processors">;
737
738// Note that cyclone does not fuse AES instructions, but newer apple chips do
739// perform the fusion and cyclone is used by default when targetting apple OSes.
740def TuneAppleA7  : SubtargetFeature<"apple-a7", "ARMProcFamily", "AppleA7",
741                                    "Apple A7 (the CPU formerly known as Cyclone)", [
742                                    FeatureAlternateSExtLoadCVTF32Pattern,
743                                    FeatureArithmeticBccFusion,
744                                    FeatureArithmeticCbzFusion,
745                                    FeatureDisableLatencySchedHeuristic,
746                                    FeatureFuseAES, FeatureFuseCryptoEOR,
747                                    FeatureZCRegMove,
748                                    FeatureZCZeroing,
749                                    FeatureZCZeroingFPWorkaround]
750                                    >;
751
752def TuneAppleA10 : SubtargetFeature<"apple-a10", "ARMProcFamily", "AppleA10",
753                                    "Apple A10", [
754                                    FeatureAlternateSExtLoadCVTF32Pattern,
755                                    FeatureArithmeticBccFusion,
756                                    FeatureArithmeticCbzFusion,
757                                    FeatureDisableLatencySchedHeuristic,
758                                    FeatureFuseAES,
759                                    FeatureFuseCryptoEOR,
760                                    FeatureZCRegMove,
761                                    FeatureZCZeroing]
762                                    >;
763
764def TuneAppleA11 : SubtargetFeature<"apple-a11", "ARMProcFamily", "AppleA11",
765                                    "Apple A11", [
766                                    FeatureAlternateSExtLoadCVTF32Pattern,
767                                    FeatureArithmeticBccFusion,
768                                    FeatureArithmeticCbzFusion,
769                                    FeatureDisableLatencySchedHeuristic,
770                                    FeatureFuseAES,
771                                    FeatureFuseCryptoEOR,
772                                    FeatureZCRegMove,
773                                    FeatureZCZeroing]
774                                    >;
775
776def TuneAppleA12 : SubtargetFeature<"apple-a12", "ARMProcFamily", "AppleA12",
777                                    "Apple A12", [
778                                    FeatureAlternateSExtLoadCVTF32Pattern,
779                                    FeatureArithmeticBccFusion,
780                                    FeatureArithmeticCbzFusion,
781                                    FeatureDisableLatencySchedHeuristic,
782                                    FeatureFuseAES,
783                                    FeatureFuseCryptoEOR,
784                                    FeatureZCRegMove,
785                                    FeatureZCZeroing]
786                                    >;
787
788def TuneAppleA13 : SubtargetFeature<"apple-a13", "ARMProcFamily", "AppleA13",
789                                    "Apple A13", [
790                                    FeatureAlternateSExtLoadCVTF32Pattern,
791                                    FeatureArithmeticBccFusion,
792                                    FeatureArithmeticCbzFusion,
793                                    FeatureDisableLatencySchedHeuristic,
794                                    FeatureFuseAES,
795                                    FeatureFuseCryptoEOR,
796                                    FeatureZCRegMove,
797                                    FeatureZCZeroing]
798                                    >;
799
800def TuneAppleA14 : SubtargetFeature<"apple-a14", "ARMProcFamily", "AppleA14",
801                                    "Apple A14", [
802                                    FeatureAggressiveFMA,
803                                    FeatureAlternateSExtLoadCVTF32Pattern,
804                                    FeatureArithmeticBccFusion,
805                                    FeatureArithmeticCbzFusion,
806                                    FeatureDisableLatencySchedHeuristic,
807                                    FeatureFuseAddress,
808                                    FeatureFuseAES,
809                                    FeatureFuseArithmeticLogic,
810                                    FeatureFuseCCSelect,
811                                    FeatureFuseCryptoEOR,
812                                    FeatureFuseLiterals,
813                                    FeatureZCRegMove,
814                                    FeatureZCZeroing]>;
815
816def TuneExynosM3 : SubtargetFeature<"exynosm3", "ARMProcFamily", "ExynosM3",
817                                    "Samsung Exynos-M3 processors",
818                                    [FeatureExynosCheapAsMoveHandling,
819                                     FeatureForce32BitJumpTables,
820                                     FeatureFuseAddress,
821                                     FeatureFuseAES,
822                                     FeatureFuseCCSelect,
823                                     FeatureFuseLiterals,
824                                     FeatureLSLFast,
825                                     FeaturePostRAScheduler,
826                                     FeaturePredictableSelectIsExpensive]>;
827
828def TuneExynosM4 : SubtargetFeature<"exynosm3", "ARMProcFamily", "ExynosM3",
829                                    "Samsung Exynos-M3 processors",
830                                    [FeatureArithmeticBccFusion,
831                                     FeatureArithmeticCbzFusion,
832                                     FeatureExynosCheapAsMoveHandling,
833                                     FeatureForce32BitJumpTables,
834                                     FeatureFuseAddress,
835                                     FeatureFuseAES,
836                                     FeatureFuseArithmeticLogic,
837                                     FeatureFuseCCSelect,
838                                     FeatureFuseLiterals,
839                                     FeatureLSLFast,
840                                     FeaturePostRAScheduler,
841                                     FeatureZCZeroing]>;
842
843def TuneKryo    : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo",
844                                   "Qualcomm Kryo processors", [
845                                   FeatureCustomCheapAsMoveHandling,
846                                   FeaturePostRAScheduler,
847                                   FeaturePredictableSelectIsExpensive,
848                                   FeatureZCZeroing,
849                                   FeatureLSLFast]
850                                   >;
851
852def TuneFalkor  : SubtargetFeature<"falkor", "ARMProcFamily", "Falkor",
853                                   "Qualcomm Falkor processors", [
854                                   FeatureCustomCheapAsMoveHandling,
855                                   FeaturePostRAScheduler,
856                                   FeaturePredictableSelectIsExpensive,
857                                   FeatureZCZeroing,
858                                   FeatureLSLFast,
859                                   FeatureSlowSTRQro
860                                   ]>;
861
862def TuneNeoverseE1 : SubtargetFeature<"neoversee1", "ARMProcFamily", "NeoverseE1",
863                                      "Neoverse E1 ARM processors", [
864                                      FeaturePostRAScheduler,
865                                      FeatureFuseAES
866                                      ]>;
867
868def TuneNeoverseN1 : SubtargetFeature<"neoversen1", "ARMProcFamily", "NeoverseN1",
869                                      "Neoverse N1 ARM processors", [
870                                      FeaturePostRAScheduler,
871                                      FeatureFuseAES
872                                      ]>;
873
874def TuneNeoverseN2 : SubtargetFeature<"neoversen2", "ARMProcFamily", "NeoverseN2",
875                                      "Neoverse N2 ARM processors", [
876                                      FeaturePostRAScheduler,
877                                      FeatureFuseAES
878                                      ]>;
879def TuneNeoverse512TVB : SubtargetFeature<"neoverse512tvb", "ARMProcFamily", "Neoverse512TVB",
880                                      "Neoverse 512-TVB ARM processors", [
881                                      FeaturePostRAScheduler,
882                                      FeatureFuseAES
883                                      ]>;
884
885def TuneNeoverseV1 : SubtargetFeature<"neoversev1", "ARMProcFamily", "NeoverseV1",
886                                      "Neoverse V1 ARM processors", [
887                                      FeatureFuseAES,
888                                      FeaturePostRAScheduler]>;
889
890def TuneSaphira  : SubtargetFeature<"saphira", "ARMProcFamily", "Saphira",
891                                   "Qualcomm Saphira processors", [
892                                   FeatureCustomCheapAsMoveHandling,
893                                   FeaturePostRAScheduler,
894                                   FeaturePredictableSelectIsExpensive,
895                                   FeatureZCZeroing,
896                                   FeatureLSLFast]>;
897
898def TuneThunderX2T99  : SubtargetFeature<"thunderx2t99", "ARMProcFamily", "ThunderX2T99",
899                                         "Cavium ThunderX2 processors", [
900                                          FeatureAggressiveFMA,
901                                          FeatureArithmeticBccFusion,
902                                          FeaturePostRAScheduler,
903                                          FeaturePredictableSelectIsExpensive]>;
904
905def TuneThunderX3T110  : SubtargetFeature<"thunderx3t110", "ARMProcFamily",
906                                          "ThunderX3T110",
907                                          "Marvell ThunderX3 processors", [
908                                           FeatureAggressiveFMA,
909                                           FeatureArithmeticBccFusion,
910                                           FeaturePostRAScheduler,
911                                           FeaturePredictableSelectIsExpensive,
912                                           FeatureBalanceFPOps,
913                                           FeatureStrictAlign]>;
914
915def TuneThunderX : SubtargetFeature<"thunderx", "ARMProcFamily", "ThunderX",
916                                    "Cavium ThunderX processors", [
917                                    FeaturePostRAScheduler,
918                                    FeaturePredictableSelectIsExpensive]>;
919
920def TuneThunderXT88 : SubtargetFeature<"thunderxt88", "ARMProcFamily",
921                                       "ThunderXT88",
922                                       "Cavium ThunderX processors", [
923                                       FeaturePostRAScheduler,
924                                       FeaturePredictableSelectIsExpensive]>;
925
926def TuneThunderXT81 : SubtargetFeature<"thunderxt81", "ARMProcFamily",
927                                       "ThunderXT81",
928                                       "Cavium ThunderX processors", [
929                                       FeaturePostRAScheduler,
930                                       FeaturePredictableSelectIsExpensive]>;
931
932def TuneThunderXT83 : SubtargetFeature<"thunderxt83", "ARMProcFamily",
933                                       "ThunderXT83",
934                                       "Cavium ThunderX processors", [
935                                       FeaturePostRAScheduler,
936                                       FeaturePredictableSelectIsExpensive]>;
937
938def TuneTSV110 : SubtargetFeature<"tsv110", "ARMProcFamily", "TSV110",
939                                  "HiSilicon TS-V110 processors", [
940                                  FeatureCustomCheapAsMoveHandling,
941                                  FeatureFuseAES,
942                                  FeaturePostRAScheduler]>;
943
944def TuneAmpere1 : SubtargetFeature<"ampere1", "ARMProcFamily", "Ampere1",
945                                   "Ampere Computing Ampere-1 processors", [
946                                   FeaturePostRAScheduler,
947                                   FeatureFuseAES,
948                                   FeatureLSLFast,
949                                   FeatureAggressiveFMA,
950                                   FeatureArithmeticBccFusion,
951                                   FeatureCmpBccFusion,
952                                   FeatureFuseAddress,
953                                   FeatureFuseLiterals]>;
954
955def ProcessorFeatures {
956  list<SubtargetFeature> A53  = [HasV8_0aOps, FeatureCRC, FeatureCrypto,
957                                 FeatureFPARMv8, FeatureNEON, FeaturePerfMon];
958  list<SubtargetFeature> A55  = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
959                                 FeatureNEON, FeatureFullFP16, FeatureDotProd,
960                                 FeatureRCPC, FeaturePerfMon];
961  list<SubtargetFeature> A510 = [HasV9_0aOps, FeatureNEON, FeaturePerfMon,
962                                 FeatureMatMulInt8, FeatureBF16, FeatureAM,
963                                 FeatureMTE, FeatureETE, FeatureSVE2BitPerm,
964                                 FeatureFP16FML];
965  list<SubtargetFeature> A65  = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
966                                 FeatureNEON, FeatureFullFP16, FeatureDotProd,
967                                 FeatureRCPC, FeatureSSBS, FeatureRAS];
968  list<SubtargetFeature> A76  = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
969                                 FeatureNEON, FeatureFullFP16, FeatureDotProd,
970                                 FeatureRCPC, FeatureSSBS];
971  list<SubtargetFeature> A77  = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
972                                 FeatureNEON, FeatureFullFP16, FeatureDotProd,
973                                 FeatureRCPC, FeatureSSBS];
974  list<SubtargetFeature> A78  = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
975                                 FeatureNEON, FeatureFullFP16, FeatureDotProd,
976                                 FeatureRCPC, FeaturePerfMon, FeatureSPE,
977                                 FeatureSSBS];
978  list<SubtargetFeature> A78C = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
979                                 FeatureNEON, FeatureFullFP16, FeatureDotProd,
980                                 FeatureFlagM, FeatureFP16FML, FeaturePAuth,
981                                 FeaturePerfMon, FeatureRCPC, FeatureSPE,
982                                 FeatureSSBS];
983  list<SubtargetFeature> A710 = [HasV9_0aOps, FeatureNEON, FeaturePerfMon,
984                                 FeatureETE, FeatureMTE, FeatureFP16FML,
985                                 FeatureSVE2BitPerm, FeatureBF16, FeatureMatMulInt8];
986  list<SubtargetFeature> R82  = [HasV8_0rOps, FeaturePerfMon, FeatureFullFP16,
987                                 FeatureFP16FML, FeatureSSBS, FeaturePredRes,
988                                 FeatureSB, FeatureSpecRestrict];
989  list<SubtargetFeature> X1   = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
990                                 FeatureNEON, FeatureRCPC, FeaturePerfMon,
991                                 FeatureSPE, FeatureFullFP16, FeatureDotProd,
992                                 FeatureSSBS];
993  list<SubtargetFeature> X1C  = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
994                                 FeatureNEON, FeatureRCPC, FeaturePerfMon,
995                                 FeatureSPE, FeatureFullFP16, FeatureDotProd,
996                                 FeaturePAuth, FeatureSSBS];
997  list<SubtargetFeature> X2   = [HasV9_0aOps, FeatureNEON, FeaturePerfMon,
998                                 FeatureMatMulInt8, FeatureBF16, FeatureAM,
999                                 FeatureMTE, FeatureETE, FeatureSVE2BitPerm,
1000                                 FeatureFP16FML];
1001  list<SubtargetFeature> A64FX    = [HasV8_2aOps, FeatureFPARMv8, FeatureNEON,
1002                                     FeatureSHA2, FeaturePerfMon, FeatureFullFP16,
1003                                     FeatureSVE, FeatureComplxNum];
1004  list<SubtargetFeature> Carmel   = [HasV8_2aOps, FeatureNEON, FeatureCrypto,
1005                                     FeatureFullFP16];
1006  list<SubtargetFeature> AppleA7  = [HasV8_0aOps, FeatureCrypto, FeatureFPARMv8,
1007                                     FeatureNEON,FeaturePerfMon, FeatureAppleA7SysReg];
1008  list<SubtargetFeature> AppleA10 = [HasV8_0aOps, FeatureCrypto, FeatureFPARMv8,
1009                                     FeatureNEON, FeaturePerfMon, FeatureCRC,
1010                                     FeatureRDM, FeaturePAN, FeatureLOR, FeatureVH];
1011  list<SubtargetFeature> AppleA11 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
1012                                     FeatureNEON, FeaturePerfMon, FeatureFullFP16];
1013  list<SubtargetFeature> AppleA12 = [HasV8_3aOps, FeatureCrypto, FeatureFPARMv8,
1014                                     FeatureNEON, FeaturePerfMon, FeatureFullFP16];
1015  list<SubtargetFeature> AppleA13 = [HasV8_4aOps, FeatureCrypto, FeatureFPARMv8,
1016                                     FeatureNEON, FeaturePerfMon, FeatureFullFP16,
1017                                     FeatureFP16FML, FeatureSHA3];
1018  list<SubtargetFeature> AppleA14 = [HasV8_4aOps, FeatureCrypto, FeatureFPARMv8,
1019                                     FeatureNEON, FeaturePerfMon, FeatureFRInt3264,
1020                                     FeatureSpecRestrict, FeatureSSBS, FeatureSB,
1021                                     FeaturePredRes, FeatureCacheDeepPersist,
1022                                     FeatureFullFP16, FeatureFP16FML, FeatureSHA3,
1023                                     FeatureAltFPCmp];
1024  list<SubtargetFeature> ExynosM3 = [HasV8_0aOps, FeatureCRC, FeatureCrypto,
1025                                     FeaturePerfMon];
1026  list<SubtargetFeature> ExynosM4 = [HasV8_2aOps, FeatureCrypto, FeatureDotProd,
1027                                     FeatureFullFP16, FeaturePerfMon];
1028  list<SubtargetFeature> Falkor   = [HasV8_0aOps, FeatureCRC, FeatureCrypto,
1029                                     FeatureFPARMv8, FeatureNEON, FeaturePerfMon,
1030                                     FeatureRDM];
1031  list<SubtargetFeature> NeoverseE1 = [HasV8_2aOps, FeatureCrypto, FeatureDotProd,
1032                                       FeatureFPARMv8, FeatureFullFP16, FeatureNEON,
1033                                       FeatureRCPC, FeatureSSBS];
1034  list<SubtargetFeature> NeoverseN1 = [HasV8_2aOps, FeatureCrypto, FeatureDotProd,
1035                                       FeatureFPARMv8, FeatureFullFP16, FeatureNEON,
1036                                       FeatureRCPC, FeatureSPE, FeatureSSBS];
1037  list<SubtargetFeature> NeoverseN2 = [HasV8_5aOps, FeatureBF16, FeatureETE,
1038                                       FeatureMatMulInt8, FeatureMTE, FeatureSVE2,
1039                                       FeatureSVE2BitPerm, FeatureTRBE, FeatureCrypto];
1040  list<SubtargetFeature> Neoverse512TVB = [HasV8_4aOps, FeatureBF16, FeatureCacheDeepPersist,
1041                                           FeatureCrypto, FeatureFPARMv8, FeatureFP16FML,
1042                                           FeatureFullFP16, FeatureMatMulInt8, FeatureNEON,
1043                                           FeaturePerfMon, FeatureRandGen, FeatureSPE,
1044                                           FeatureSSBS, FeatureSVE];
1045  list<SubtargetFeature> NeoverseV1 = [HasV8_4aOps, FeatureBF16, FeatureCacheDeepPersist,
1046                                       FeatureCrypto, FeatureFPARMv8, FeatureFP16FML,
1047                                       FeatureFullFP16, FeatureMatMulInt8, FeatureNEON,
1048                                       FeaturePerfMon, FeatureRandGen, FeatureSPE,
1049                                       FeatureSSBS, FeatureSVE];
1050  list<SubtargetFeature> Saphira    = [HasV8_4aOps, FeatureCrypto, FeatureFPARMv8,
1051                                       FeatureNEON, FeatureSPE, FeaturePerfMon];
1052  list<SubtargetFeature> ThunderX   = [HasV8_0aOps, FeatureCRC, FeatureCrypto,
1053                                       FeatureFPARMv8, FeaturePerfMon, FeatureNEON];
1054  list<SubtargetFeature> ThunderX2T99  = [HasV8_1aOps, FeatureCRC, FeatureCrypto,
1055                                          FeatureFPARMv8, FeatureNEON, FeatureLSE];
1056  list<SubtargetFeature> ThunderX3T110 = [HasV8_3aOps, FeatureCRC, FeatureCrypto,
1057                                          FeatureFPARMv8, FeatureNEON, FeatureLSE,
1058                                          FeaturePAuth, FeaturePerfMon];
1059  list<SubtargetFeature> TSV110 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
1060                                   FeatureNEON, FeaturePerfMon, FeatureSPE,
1061                                   FeatureFullFP16, FeatureFP16FML, FeatureDotProd];
1062  list<SubtargetFeature> Ampere1 = [HasV8_6aOps, FeatureNEON, FeaturePerfMon,
1063                                    FeatureMTE, FeatureSSBS];
1064
1065  // ETE and TRBE are future architecture extensions. We temporarily enable them
1066  // by default for users targeting generic AArch64. The extensions do not
1067  // affect code generated by the compiler and can be used only by explicitly
1068  // mentioning the new system register names in assembly.
1069  list<SubtargetFeature> Generic = [FeatureFPARMv8, FeatureNEON, FeaturePerfMon, FeatureETE];
1070}
1071
1072
1073def : ProcessorModel<"generic", CortexA55Model, ProcessorFeatures.Generic,
1074                     [FeatureFuseAES, FeaturePostRAScheduler]>;
1075def : ProcessorModel<"cortex-a35", CortexA53Model, ProcessorFeatures.A53,
1076                     [TuneA35]>;
1077def : ProcessorModel<"cortex-a34", CortexA53Model, ProcessorFeatures.A53,
1078                     [TuneA35]>;
1079def : ProcessorModel<"cortex-a53", CortexA53Model, ProcessorFeatures.A53,
1080                     [TuneA53]>;
1081def : ProcessorModel<"cortex-a55", CortexA55Model, ProcessorFeatures.A55,
1082                     [TuneA55]>;
1083def : ProcessorModel<"cortex-a510", CortexA55Model, ProcessorFeatures.A510,
1084                     [TuneA510]>;
1085def : ProcessorModel<"cortex-a57", CortexA57Model, ProcessorFeatures.A53,
1086                     [TuneA57]>;
1087def : ProcessorModel<"cortex-a65", CortexA53Model, ProcessorFeatures.A65,
1088                     [TuneA65]>;
1089def : ProcessorModel<"cortex-a65ae", CortexA53Model, ProcessorFeatures.A65,
1090                     [TuneA65]>;
1091def : ProcessorModel<"cortex-a72", CortexA57Model, ProcessorFeatures.A53,
1092                     [TuneA72]>;
1093def : ProcessorModel<"cortex-a73", CortexA57Model, ProcessorFeatures.A53,
1094                     [TuneA73]>;
1095def : ProcessorModel<"cortex-a75", CortexA57Model, ProcessorFeatures.A55,
1096                     [TuneA75]>;
1097def : ProcessorModel<"cortex-a76", CortexA57Model, ProcessorFeatures.A76,
1098                     [TuneA76]>;
1099def : ProcessorModel<"cortex-a76ae", CortexA57Model, ProcessorFeatures.A76,
1100                     [TuneA76]>;
1101def : ProcessorModel<"cortex-a77", CortexA57Model, ProcessorFeatures.A77,
1102                     [TuneA77]>;
1103def : ProcessorModel<"cortex-a78", CortexA57Model, ProcessorFeatures.A78,
1104                     [TuneA78]>;
1105def : ProcessorModel<"cortex-a78c", CortexA57Model, ProcessorFeatures.A78C,
1106                     [TuneA78C]>;
1107def : ProcessorModel<"cortex-a710", CortexA57Model, ProcessorFeatures.A710,
1108                     [TuneA710]>;
1109def : ProcessorModel<"cortex-r82", CortexA55Model, ProcessorFeatures.R82,
1110                     [TuneR82]>;
1111def : ProcessorModel<"cortex-x1", CortexA57Model, ProcessorFeatures.X1,
1112                     [TuneX1]>;
1113def : ProcessorModel<"cortex-x1c", CortexA57Model, ProcessorFeatures.X1C,
1114                     [TuneX1]>;
1115def : ProcessorModel<"cortex-x2", CortexA57Model, ProcessorFeatures.X2,
1116                     [TuneX2]>;
1117def : ProcessorModel<"neoverse-e1", CortexA53Model,
1118                     ProcessorFeatures.NeoverseE1, [TuneNeoverseE1]>;
1119def : ProcessorModel<"neoverse-n1", CortexA57Model,
1120                     ProcessorFeatures.NeoverseN1, [TuneNeoverseN1]>;
1121def : ProcessorModel<"neoverse-n2", CortexA57Model,
1122                     ProcessorFeatures.NeoverseN2, [TuneNeoverseN2]>;
1123def : ProcessorModel<"neoverse-512tvb", CortexA57Model,
1124                     ProcessorFeatures.Neoverse512TVB, [TuneNeoverse512TVB]>;
1125def : ProcessorModel<"neoverse-v1", CortexA57Model,
1126                     ProcessorFeatures.NeoverseV1, [TuneNeoverseV1]>;
1127def : ProcessorModel<"exynos-m3", ExynosM3Model, ProcessorFeatures.ExynosM3,
1128                     [TuneExynosM3]>;
1129def : ProcessorModel<"exynos-m4", ExynosM4Model, ProcessorFeatures.ExynosM4,
1130                     [TuneExynosM4]>;
1131def : ProcessorModel<"exynos-m5", ExynosM5Model, ProcessorFeatures.ExynosM4,
1132                     [TuneExynosM4]>;
1133def : ProcessorModel<"falkor", FalkorModel, ProcessorFeatures.Falkor,
1134                     [TuneFalkor]>;
1135def : ProcessorModel<"saphira", FalkorModel, ProcessorFeatures.Saphira,
1136                     [TuneSaphira]>;
1137def : ProcessorModel<"kryo", KryoModel, ProcessorFeatures.A53, [TuneKryo]>;
1138
1139// Cavium ThunderX/ThunderX T8X  Processors
1140def : ProcessorModel<"thunderx", ThunderXT8XModel,  ProcessorFeatures.ThunderX,
1141                     [TuneThunderX]>;
1142def : ProcessorModel<"thunderxt88", ThunderXT8XModel,
1143                     ProcessorFeatures.ThunderX, [TuneThunderXT88]>;
1144def : ProcessorModel<"thunderxt81", ThunderXT8XModel,
1145                     ProcessorFeatures.ThunderX, [TuneThunderXT81]>;
1146def : ProcessorModel<"thunderxt83", ThunderXT8XModel,
1147                     ProcessorFeatures.ThunderX, [TuneThunderXT83]>;
1148// Cavium ThunderX2T9X  Processors. Formerly Broadcom Vulcan.
1149def : ProcessorModel<"thunderx2t99", ThunderX2T99Model,
1150                     ProcessorFeatures.ThunderX2T99, [TuneThunderX2T99]>;
1151// Marvell ThunderX3T110 Processors.
1152def : ProcessorModel<"thunderx3t110", ThunderX3T110Model,
1153                     ProcessorFeatures.ThunderX3T110, [TuneThunderX3T110]>;
1154def : ProcessorModel<"tsv110", TSV110Model, ProcessorFeatures.TSV110,
1155                     [TuneTSV110]>;
1156
1157// Support cyclone as an alias for apple-a7 so we can still LTO old bitcode.
1158def : ProcessorModel<"cyclone", CycloneModel, ProcessorFeatures.AppleA7,
1159                     [TuneAppleA7]>;
1160
1161// iPhone and iPad CPUs
1162def : ProcessorModel<"apple-a7", CycloneModel, ProcessorFeatures.AppleA7,
1163                     [TuneAppleA7]>;
1164def : ProcessorModel<"apple-a8", CycloneModel, ProcessorFeatures.AppleA7,
1165                     [TuneAppleA7]>;
1166def : ProcessorModel<"apple-a9", CycloneModel, ProcessorFeatures.AppleA7,
1167                     [TuneAppleA7]>;
1168def : ProcessorModel<"apple-a10", CycloneModel, ProcessorFeatures.AppleA10,
1169                     [TuneAppleA10]>;
1170def : ProcessorModel<"apple-a11", CycloneModel, ProcessorFeatures.AppleA11,
1171                     [TuneAppleA11]>;
1172def : ProcessorModel<"apple-a12", CycloneModel, ProcessorFeatures.AppleA12,
1173                     [TuneAppleA12]>;
1174def : ProcessorModel<"apple-a13", CycloneModel, ProcessorFeatures.AppleA13,
1175                     [TuneAppleA13]>;
1176def : ProcessorModel<"apple-a14", CycloneModel, ProcessorFeatures.AppleA14,
1177                     [TuneAppleA14]>;
1178
1179// Mac CPUs
1180def : ProcessorModel<"apple-m1", CycloneModel, ProcessorFeatures.AppleA14,
1181                     [TuneAppleA14]>;
1182
1183// watch CPUs.
1184def : ProcessorModel<"apple-s4", CycloneModel, ProcessorFeatures.AppleA12,
1185                     [TuneAppleA12]>;
1186def : ProcessorModel<"apple-s5", CycloneModel, ProcessorFeatures.AppleA12,
1187                     [TuneAppleA12]>;
1188
1189// Alias for the latest Apple processor model supported by LLVM.
1190def : ProcessorModel<"apple-latest", CycloneModel, ProcessorFeatures.AppleA14,
1191                     [TuneAppleA14]>;
1192
1193// Fujitsu A64FX
1194def : ProcessorModel<"a64fx", A64FXModel, ProcessorFeatures.A64FX,
1195                     [TuneA64FX]>;
1196
1197// Nvidia Carmel
1198def : ProcessorModel<"carmel", NoSchedModel, ProcessorFeatures.Carmel,
1199                     [TuneCarmel]>;
1200
1201// Ampere Computing
1202def : ProcessorModel<"ampere1", Ampere1Model, ProcessorFeatures.Ampere1,
1203                     [TuneAmpere1]>;
1204
1205//===----------------------------------------------------------------------===//
1206// Assembly parser
1207//===----------------------------------------------------------------------===//
1208
1209def GenericAsmParserVariant : AsmParserVariant {
1210  int Variant = 0;
1211  string Name = "generic";
1212  string BreakCharacters = ".";
1213  string TokenizingCharacters = "[]*!/";
1214}
1215
1216def AppleAsmParserVariant : AsmParserVariant {
1217  int Variant = 1;
1218  string Name = "apple-neon";
1219  string BreakCharacters = ".";
1220  string TokenizingCharacters = "[]*!/";
1221}
1222
1223//===----------------------------------------------------------------------===//
1224// Assembly printer
1225//===----------------------------------------------------------------------===//
1226// AArch64 Uses the MC printer for asm output, so make sure the TableGen
1227// AsmWriter bits get associated with the correct class.
1228def GenericAsmWriter : AsmWriter {
1229  string AsmWriterClassName  = "InstPrinter";
1230  int PassSubtarget = 1;
1231  int Variant = 0;
1232  bit isMCAsmWriter = 1;
1233}
1234
1235def AppleAsmWriter : AsmWriter {
1236  let AsmWriterClassName = "AppleInstPrinter";
1237  int PassSubtarget = 1;
1238  int Variant = 1;
1239  int isMCAsmWriter = 1;
1240}
1241
1242//===----------------------------------------------------------------------===//
1243// Target Declaration
1244//===----------------------------------------------------------------------===//
1245
1246def AArch64 : Target {
1247  let InstructionSet = AArch64InstrInfo;
1248  let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant];
1249  let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter];
1250  let AllowRegisterRenaming = 1;
1251}
1252
1253//===----------------------------------------------------------------------===//
1254// Pfm Counters
1255//===----------------------------------------------------------------------===//
1256
1257include "AArch64PfmCounters.td"
1258