1//=- AArch64.td - Describe the AArch64 Target Machine --------*- tablegen -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9//
10//===----------------------------------------------------------------------===//
11
12//===----------------------------------------------------------------------===//
13// Target-independent interfaces which we are implementing.
14//===----------------------------------------------------------------------===//
15
16include "llvm/Target/Target.td"
17
18//===----------------------------------------------------------------------===//
19// AArch64 Subtarget features.
20//
21
22// Each SubtargetFeature which corresponds to an Arm Architecture feature should
23// be annotated with the respective FEAT_ feature name from the Architecture
24// Reference Manual. If a SubtargetFeature enables instructions from multiple
25// Arm Architecture Features, it should list all the relevant features. Not all
26// FEAT_ features have a corresponding SubtargetFeature.
27
28def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true",
29                                       "Enable ARMv8 FP (FEAT_FP)">;
30
31def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
32  "Enable Advanced SIMD instructions (FEAT_AdvSIMD)", [FeatureFPARMv8]>;
33
34def FeatureSM4 : SubtargetFeature<
35    "sm4", "HasSM4", "true",
36    "Enable SM3 and SM4 support (FEAT_SM4, FEAT_SM3)", [FeatureNEON]>;
37
38def FeatureSHA2 : SubtargetFeature<
39    "sha2", "HasSHA2", "true",
40    "Enable SHA1 and SHA256 support (FEAT_SHA1, FEAT_SHA256)", [FeatureNEON]>;
41
42def FeatureSHA3 : SubtargetFeature<
43    "sha3", "HasSHA3", "true",
44    "Enable SHA512 and SHA3 support (FEAT_SHA3, FEAT_SHA512)", [FeatureNEON, FeatureSHA2]>;
45
46def FeatureAES : SubtargetFeature<
47    "aes", "HasAES", "true",
48    "Enable AES support (FEAT_AES, FEAT_PMULL)", [FeatureNEON]>;
49
50// Crypto has been split up and any combination is now valid (see the
51// crypto definitions above). Also, crypto is now context sensitive:
52// it has a different meaning for e.g. Armv8.4 than it has for Armv8.2.
53// Therefore, we rely on Clang, the user interfacing tool, to pass on the
54// appropriate crypto options. But here in the backend, crypto has very little
55// meaning anymore. We kept the Crypto definition here for backward
56// compatibility, and now imply features SHA2 and AES, which was the
57// "traditional" meaning of Crypto.
58def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
59  "Enable cryptographic instructions", [FeatureNEON, FeatureSHA2, FeatureAES]>;
60
61def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
62  "Enable ARMv8 CRC-32 checksum instructions (FEAT_CRC32)">;
63
64def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true",
65  "Enable ARMv8 Reliability, Availability and Serviceability Extensions (FEAT_RAS, FEAT_RASv1p1)">;
66
67def FeatureRASv2 : SubtargetFeature<"rasv2", "HasRASv2", "true",
68  "Enable ARMv8.9-A Reliability, Availability and Serviceability Extensions (FEAT_RASv2)",
69  [FeatureRAS]>;
70
71def FeatureLSE : SubtargetFeature<"lse", "HasLSE", "true",
72  "Enable ARMv8.1 Large System Extension (LSE) atomic instructions (FEAT_LSE)">;
73
74def FeatureLSE2 : SubtargetFeature<"lse2", "HasLSE2", "true",
75  "Enable ARMv8.4 Large System Extension 2 (LSE2) atomicity rules (FEAT_LSE2)">;
76
77def FeatureOutlineAtomics : SubtargetFeature<"outline-atomics", "OutlineAtomics", "true",
78  "Enable out of line atomics to support LSE instructions">;
79
80def FeatureFMV : SubtargetFeature<"fmv", "HasFMV", "true",
81  "Enable Function Multi Versioning support.">;
82
83def FeatureRDM : SubtargetFeature<"rdm", "HasRDM", "true",
84  "Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions (FEAT_RDM)">;
85
86def FeaturePAN : SubtargetFeature<
87    "pan", "HasPAN", "true",
88    "Enables ARM v8.1 Privileged Access-Never extension (FEAT_PAN)">;
89
90def FeatureLOR : SubtargetFeature<
91    "lor", "HasLOR", "true",
92    "Enables ARM v8.1 Limited Ordering Regions extension (FEAT_LOR)">;
93
94def FeatureCONTEXTIDREL2 : SubtargetFeature<"CONTEXTIDREL2", "HasCONTEXTIDREL2",
95    "true", "Enable RW operand CONTEXTIDR_EL2" >;
96
97def FeatureVH : SubtargetFeature<"vh", "HasVH", "true",
98    "Enables ARM v8.1 Virtual Host extension (FEAT_VHE)", [FeatureCONTEXTIDREL2] >;
99
100// This SubtargetFeature is special. It controls only whether codegen will turn
101// `llvm.readcyclecounter()` into an access to a PMUv3 System Register. The
102// `FEAT_PMUv3*` system registers are always available for assembly/disassembly.
103def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
104  "Enable Code Generation for ARMv8 PMUv3 Performance Monitors extension (FEAT_PMUv3)">;
105
106def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
107  "Full FP16 (FEAT_FP16)", [FeatureFPARMv8]>;
108
109def FeatureFP16FML : SubtargetFeature<"fp16fml", "HasFP16FML", "true",
110  "Enable FP16 FML instructions (FEAT_FHM)", [FeatureFullFP16]>;
111
112def FeatureSPE : SubtargetFeature<"spe", "HasSPE", "true",
113  "Enable Statistical Profiling extension (FEAT_SPE)">;
114
115def FeaturePAN_RWV : SubtargetFeature<
116    "pan-rwv", "HasPAN_RWV", "true",
117    "Enable v8.2 PAN s1e1R and s1e1W Variants (FEAT_PAN2)",
118    [FeaturePAN]>;
119
120// UAO PState
121def FeaturePsUAO : SubtargetFeature< "uaops", "HasPsUAO", "true",
122    "Enable v8.2 UAO PState (FEAT_UAO)">;
123
124def FeatureCCPP : SubtargetFeature<"ccpp", "HasCCPP",
125    "true", "Enable v8.2 data Cache Clean to Point of Persistence (FEAT_DPB)" >;
126
127def FeatureSVE : SubtargetFeature<"sve", "HasSVE", "true",
128  "Enable Scalable Vector Extension (SVE) instructions (FEAT_SVE)", [FeatureFullFP16]>;
129
130// This flag is currently still labeled as Experimental, but when fully
131// implemented this should tell the compiler to use the zeroing pseudos to
132// benefit from the reverse instructions (e.g. SUB vs SUBR) if the inactive
133// lanes are known to be zero. The pseudos will then be expanded using the
134// MOVPRFX instruction to zero the inactive lanes. This feature should only be
135// enabled if MOVPRFX instructions are known to merge with the destructive
136// operations they prefix.
137//
138// This feature could similarly be extended to support cheap merging of _any_
139// value into the inactive lanes using the MOVPRFX instruction that uses
140// merging-predication.
141def FeatureExperimentalZeroingPseudos
142    : SubtargetFeature<"use-experimental-zeroing-pseudos",
143                       "UseExperimentalZeroingPseudos", "true",
144                       "Hint to the compiler that the MOVPRFX instruction is "
145                       "merged with destructive operations",
146                       []>;
147
148def FeatureUseScalarIncVL : SubtargetFeature<"use-scalar-inc-vl",
149  "UseScalarIncVL", "true", "Prefer inc/dec over add+cnt">;
150
151def FeatureNoSVEFPLD1R : SubtargetFeature<"no-sve-fp-ld1r",
152  "NoSVEFPLD1R", "true", "Avoid using LD1RX instructions for FP">;
153
154def FeatureSVE2 : SubtargetFeature<"sve2", "HasSVE2", "true",
155  "Enable Scalable Vector Extension 2 (SVE2) instructions (FEAT_SVE2)",
156  [FeatureSVE, FeatureUseScalarIncVL]>;
157
158def FeatureSVE2AES : SubtargetFeature<"sve2-aes", "HasSVE2AES", "true",
159  "Enable AES SVE2 instructions (FEAT_SVE_AES, FEAT_SVE_PMULL128)",
160  [FeatureSVE2, FeatureAES]>;
161
162def FeatureSVE2SM4 : SubtargetFeature<"sve2-sm4", "HasSVE2SM4", "true",
163  "Enable SM4 SVE2 instructions (FEAT_SVE_SM4)", [FeatureSVE2, FeatureSM4]>;
164
165def FeatureSVE2SHA3 : SubtargetFeature<"sve2-sha3", "HasSVE2SHA3", "true",
166  "Enable SHA3 SVE2 instructions (FEAT_SVE_SHA3)", [FeatureSVE2, FeatureSHA3]>;
167
168def FeatureSVE2BitPerm : SubtargetFeature<"sve2-bitperm", "HasSVE2BitPerm", "true",
169  "Enable bit permutation SVE2 instructions (FEAT_SVE_BitPerm)", [FeatureSVE2]>;
170
171def FeatureSVE2p1: SubtargetFeature<"sve2p1", "HasSVE2p1", "true",
172  "Enable Scalable Vector Extension 2.1 instructions", [FeatureSVE2]>;
173
174def FeatureB16B16 : SubtargetFeature<"b16b16", "HasB16B16", "true",
175  "Enable SVE2.1 or SME2.1 non-widening BFloat16 to BFloat16 instructions (FEAT_B16B16)", []>;
176
177def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
178                                        "Has zero-cycle register moves">;
179
180def FeatureZCZeroingGP : SubtargetFeature<"zcz-gp", "HasZeroCycleZeroingGP", "true",
181                                        "Has zero-cycle zeroing instructions for generic registers">;
182
183// It is generally beneficial to rewrite "fmov s0, wzr" to "movi d0, #0".
184// as movi is more efficient across all cores. Newer cores can eliminate
185// fmovs early and there is no difference with movi, but this not true for
186// all implementations.
187def FeatureNoZCZeroingFP : SubtargetFeature<"no-zcz-fp", "HasZeroCycleZeroingFP", "false",
188                                        "Has no zero-cycle zeroing instructions for FP registers">;
189
190def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
191                                        "Has zero-cycle zeroing instructions",
192                                        [FeatureZCZeroingGP]>;
193
194/// ... but the floating-point version doesn't quite work in rare cases on older
195/// CPUs.
196def FeatureZCZeroingFPWorkaround : SubtargetFeature<"zcz-fp-workaround",
197    "HasZeroCycleZeroingFPWorkaround", "true",
198    "The zero-cycle floating-point zeroing instruction has a bug">;
199
200def FeatureStrictAlign : SubtargetFeature<"strict-align",
201                                          "RequiresStrictAlign", "true",
202                                          "Disallow all unaligned memory "
203                                          "access">;
204
205foreach i = {1-7,9-15,18,20-28,30} in
206    def FeatureReserveX#i : SubtargetFeature<"reserve-x"#i, "ReserveXRegister["#i#"]", "true",
207                                             "Reserve X"#i#", making it unavailable "
208                                             "as a GPR">;
209
210foreach i = {8-15,18} in
211    def FeatureCallSavedX#i : SubtargetFeature<"call-saved-x"#i,
212         "CustomCallSavedXRegs["#i#"]", "true", "Make X"#i#" callee saved.">;
213
214def FeatureBalanceFPOps : SubtargetFeature<"balance-fp-ops", "BalanceFPOps",
215    "true",
216    "balance mix of odd and even D-registers for fp multiply(-accumulate) ops">;
217
218def FeaturePredictableSelectIsExpensive : SubtargetFeature<
219    "predictable-select-expensive", "PredictableSelectIsExpensive", "true",
220    "Prefer likely predicted branches over selects">;
221
222def FeatureEnableSelectOptimize : SubtargetFeature<
223    "enable-select-opt", "EnableSelectOptimize", "true",
224    "Enable the select optimize pass for select loop heuristics">;
225
226def FeatureCustomCheapAsMoveHandling : SubtargetFeature<"custom-cheap-as-move",
227    "HasCustomCheapAsMoveHandling", "true",
228    "Use custom handling of cheap instructions">;
229
230def FeatureExynosCheapAsMoveHandling : SubtargetFeature<"exynos-cheap-as-move",
231    "HasExynosCheapAsMoveHandling", "true",
232    "Use Exynos specific handling of cheap instructions",
233    [FeatureCustomCheapAsMoveHandling]>;
234
235def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler",
236    "UsePostRAScheduler", "true", "Schedule again after register allocation">;
237
238def FeatureSlowMisaligned128Store : SubtargetFeature<"slow-misaligned-128store",
239    "IsMisaligned128StoreSlow", "true", "Misaligned 128 bit stores are slow">;
240
241def FeatureSlowPaired128 : SubtargetFeature<"slow-paired-128",
242    "IsPaired128Slow", "true", "Paired 128 bit loads and stores are slow">;
243
244def FeatureAscendStoreAddress : SubtargetFeature<"ascend-store-address",
245    "IsStoreAddressAscend", "true",
246    "Schedule vector stores by ascending address">;
247
248def FeatureSlowSTRQro : SubtargetFeature<"slow-strqro-store", "IsSTRQroSlow",
249    "true", "STR of Q register with register offset is slow">;
250
251def FeatureAlternateSExtLoadCVTF32Pattern : SubtargetFeature<
252    "alternate-sextload-cvt-f32-pattern", "UseAlternateSExtLoadCVTF32Pattern",
253    "true", "Use alternative pattern for sextload convert to f32">;
254
255def FeatureArithmeticBccFusion : SubtargetFeature<
256    "arith-bcc-fusion", "HasArithmeticBccFusion", "true",
257    "CPU fuses arithmetic+bcc operations">;
258
259def FeatureArithmeticCbzFusion : SubtargetFeature<
260    "arith-cbz-fusion", "HasArithmeticCbzFusion", "true",
261    "CPU fuses arithmetic + cbz/cbnz operations">;
262
263def FeatureCmpBccFusion : SubtargetFeature<
264    "cmp-bcc-fusion", "HasCmpBccFusion", "true",
265    "CPU fuses cmp+bcc operations">;
266
267def FeatureFuseAddress : SubtargetFeature<
268    "fuse-address", "HasFuseAddress", "true",
269    "CPU fuses address generation and memory operations">;
270
271def FeatureFuseAES : SubtargetFeature<
272    "fuse-aes", "HasFuseAES", "true",
273    "CPU fuses AES crypto operations">;
274
275def FeatureFuseArithmeticLogic : SubtargetFeature<
276    "fuse-arith-logic", "HasFuseArithmeticLogic", "true",
277    "CPU fuses arithmetic and logic operations">;
278
279def FeatureFuseCCSelect : SubtargetFeature<
280    "fuse-csel", "HasFuseCCSelect", "true",
281    "CPU fuses conditional select operations">;
282
283def FeatureFuseCryptoEOR : SubtargetFeature<
284    "fuse-crypto-eor", "HasFuseCryptoEOR", "true",
285    "CPU fuses AES/PMULL and EOR operations">;
286
287def FeatureFuseAdrpAdd : SubtargetFeature<
288    "fuse-adrp-add", "HasFuseAdrpAdd", "true",
289    "CPU fuses adrp+add operations">;
290
291def FeatureFuseLiterals : SubtargetFeature<
292    "fuse-literals", "HasFuseLiterals", "true",
293    "CPU fuses literal generation operations">;
294
295def FeatureFuseAddSub2RegAndConstOne : SubtargetFeature<
296   "fuse-addsub-2reg-const1", "HasFuseAddSub2RegAndConstOne", "true",
297   "CPU fuses (a + b + 1) and (a - b - 1)">;
298
299def FeatureDisableLatencySchedHeuristic : SubtargetFeature<
300    "disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true",
301    "Disable latency scheduling heuristic">;
302
303def FeatureForce32BitJumpTables
304   : SubtargetFeature<"force-32bit-jump-tables", "Force32BitJumpTables", "true",
305                      "Force jump table entries to be 32-bits wide except at MinSize">;
306
307def FeatureRCPC : SubtargetFeature<"rcpc", "HasRCPC", "true",
308                                   "Enable support for RCPC extension (FEAT_LRCPC)">;
309
310def FeatureUseRSqrt : SubtargetFeature<
311    "use-reciprocal-square-root", "UseRSqrt", "true",
312    "Use the reciprocal square root approximation">;
313
314def FeatureDotProd : SubtargetFeature<
315    "dotprod", "HasDotProd", "true",
316    "Enable dot product support (FEAT_DotProd)">;
317
318def FeaturePAuth : SubtargetFeature<
319    "pauth", "HasPAuth", "true",
320    "Enable v8.3-A Pointer Authentication extension (FEAT_PAuth)">;
321
322def FeatureJS : SubtargetFeature<
323    "jsconv", "HasJS", "true",
324    "Enable v8.3-A JavaScript FP conversion instructions (FEAT_JSCVT)",
325    [FeatureFPARMv8]>;
326
327def FeatureCCIDX : SubtargetFeature<
328    "ccidx", "HasCCIDX", "true",
329    "Enable v8.3-A Extend of the CCSIDR number of sets (FEAT_CCIDX)">;
330
331def FeatureComplxNum : SubtargetFeature<
332    "complxnum", "HasComplxNum", "true",
333    "Enable v8.3-A Floating-point complex number support (FEAT_FCMA)",
334    [FeatureNEON]>;
335
336def FeatureNV : SubtargetFeature<
337    "nv", "HasNV", "true",
338    "Enable v8.4-A Nested Virtualization Enchancement (FEAT_NV, FEAT_NV2)">;
339
340def FeatureMPAM : SubtargetFeature<
341    "mpam", "HasMPAM", "true",
342    "Enable v8.4-A Memory system Partitioning and Monitoring extension (FEAT_MPAM)">;
343
344def FeatureDIT : SubtargetFeature<
345    "dit", "HasDIT", "true",
346    "Enable v8.4-A Data Independent Timing instructions (FEAT_DIT)">;
347
348def FeatureTRACEV8_4 : SubtargetFeature<
349    "tracev8.4", "HasTRACEV8_4", "true",
350    "Enable v8.4-A Trace extension (FEAT_TRF)">;
351
352def FeatureAM : SubtargetFeature<
353    "am", "HasAM", "true",
354    "Enable v8.4-A Activity Monitors extension (FEAT_AMUv1)">;
355
356def FeatureAMVS : SubtargetFeature<
357    "amvs", "HasAMVS", "true",
358    "Enable v8.6-A Activity Monitors Virtualization support (FEAT_AMUv1p1)",
359    [FeatureAM]>;
360
361def FeatureSEL2 : SubtargetFeature<
362    "sel2", "HasSEL2", "true",
363    "Enable v8.4-A Secure Exception Level 2 extension (FEAT_SEL2)">;
364
365def FeatureTLB_RMI : SubtargetFeature<
366    "tlb-rmi", "HasTLB_RMI", "true",
367    "Enable v8.4-A TLB Range and Maintenance Instructions (FEAT_TLBIOS, FEAT_TLBIRANGE)">;
368
369def FeatureFlagM : SubtargetFeature<
370    "flagm", "HasFlagM", "true",
371    "Enable v8.4-A Flag Manipulation Instructions (FEAT_FlagM)">;
372
373// 8.4 RCPC enchancements: LDAPR & STLR instructions with Immediate Offset
374def FeatureRCPC_IMMO : SubtargetFeature<"rcpc-immo", "HasRCPC_IMMO", "true",
375    "Enable v8.4-A RCPC instructions with Immediate Offsets (FEAT_LRCPC2)",
376    [FeatureRCPC]>;
377
378def FeatureNoNegativeImmediates : SubtargetFeature<"no-neg-immediates",
379                                        "NegativeImmediates", "false",
380                                        "Convert immediates and instructions "
381                                        "to their negated or complemented "
382                                        "equivalent when the immediate does "
383                                        "not fit in the encoding.">;
384
385def FeatureLSLFast : SubtargetFeature<
386    "lsl-fast", "HasLSLFast", "true",
387    "CPU has a fastpath logical shift of up to 3 places">;
388
389def FeatureAggressiveFMA :
390  SubtargetFeature<"aggressive-fma",
391                   "HasAggressiveFMA",
392                   "true",
393                   "Enable Aggressive FMA for floating-point.">;
394
395def FeatureAltFPCmp : SubtargetFeature<"altnzcv", "HasAlternativeNZCV", "true",
396  "Enable alternative NZCV format for floating point comparisons (FEAT_FlagM2)">;
397
398def FeatureFRInt3264 : SubtargetFeature<"fptoint", "HasFRInt3264", "true",
399  "Enable FRInt[32|64][Z|X] instructions that round a floating-point number to "
400  "an integer (in FP format) forcing it to fit into a 32- or 64-bit int (FEAT_FRINTTS)" >;
401
402def FeatureSpecRestrict : SubtargetFeature<"specrestrict", "HasSpecRestrict",
403  "true", "Enable architectural speculation restriction (FEAT_CSV2_2)">;
404
405def FeatureSB : SubtargetFeature<"sb", "HasSB",
406  "true", "Enable v8.5 Speculation Barrier (FEAT_SB)" >;
407
408def FeatureSSBS : SubtargetFeature<"ssbs", "HasSSBS",
409  "true", "Enable Speculative Store Bypass Safe bit (FEAT_SSBS, FEAT_SSBS2)" >;
410
411def FeaturePredRes : SubtargetFeature<"predres", "HasPredRes", "true",
412  "Enable v8.5a execution and data prediction invalidation instructions (FEAT_SPECRES)" >;
413
414def FeatureCacheDeepPersist : SubtargetFeature<"ccdp", "HasCCDP",
415    "true", "Enable v8.5 Cache Clean to Point of Deep Persistence (FEAT_DPB2)" >;
416
417def FeatureBranchTargetId : SubtargetFeature<"bti", "HasBTI",
418    "true", "Enable Branch Target Identification (FEAT_BTI)" >;
419
420def FeatureRandGen : SubtargetFeature<"rand", "HasRandGen",
421    "true", "Enable Random Number generation instructions (FEAT_RNG)" >;
422
423def FeatureMTE : SubtargetFeature<"mte", "HasMTE",
424    "true", "Enable Memory Tagging Extension (FEAT_MTE, FEAT_MTE2)" >;
425
426def FeatureTRBE : SubtargetFeature<"trbe", "HasTRBE",
427    "true", "Enable Trace Buffer Extension (FEAT_TRBE)">;
428
429def FeatureETE : SubtargetFeature<"ete", "HasETE",
430    "true", "Enable Embedded Trace Extension (FEAT_ETE)",
431    [FeatureTRBE]>;
432
433def FeatureTME : SubtargetFeature<"tme", "HasTME",
434    "true", "Enable Transactional Memory Extension (FEAT_TME)" >;
435
436def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals",
437    "AllowTaggedGlobals",
438    "true", "Use an instruction sequence for taking the address of a global "
439    "that allows a memory tag in the upper address bits">;
440
441def FeatureBF16 : SubtargetFeature<"bf16", "HasBF16",
442    "true", "Enable BFloat16 Extension (FEAT_BF16)" >;
443
444def FeatureMatMulInt8 : SubtargetFeature<"i8mm", "HasMatMulInt8",
445    "true", "Enable Matrix Multiply Int8 Extension (FEAT_I8MM)">;
446
447def FeatureMatMulFP32 : SubtargetFeature<"f32mm", "HasMatMulFP32",
448    "true", "Enable Matrix Multiply FP32 Extension (FEAT_F32MM)", [FeatureSVE]>;
449
450def FeatureMatMulFP64 : SubtargetFeature<"f64mm", "HasMatMulFP64",
451    "true", "Enable Matrix Multiply FP64 Extension (FEAT_F64MM)", [FeatureSVE]>;
452
453def FeatureXS : SubtargetFeature<"xs", "HasXS",
454    "true", "Enable Armv8.7-A limited-TLB-maintenance instruction (FEAT_XS)">;
455
456def FeatureWFxT : SubtargetFeature<"wfxt", "HasWFxT",
457    "true", "Enable Armv8.7-A WFET and WFIT instruction (FEAT_WFxT)">;
458
459def FeatureHCX : SubtargetFeature<
460    "hcx", "HasHCX", "true", "Enable Armv8.7-A HCRX_EL2 system register (FEAT_HCX)">;
461
462def FeatureLS64 : SubtargetFeature<"ls64", "HasLS64",
463    "true", "Enable Armv8.7-A LD64B/ST64B Accelerator Extension (FEAT_LS64, FEAT_LS64_V, FEAT_LS64_ACCDATA)">;
464
465def FeatureHBC : SubtargetFeature<"hbc", "HasHBC",
466    "true", "Enable Armv8.8-A Hinted Conditional Branches Extension (FEAT_HBC)">;
467
468def FeatureMOPS : SubtargetFeature<"mops", "HasMOPS",
469    "true", "Enable Armv8.8-A memcpy and memset acceleration instructions (FEAT_MOPS)">;
470
471def FeatureNMI : SubtargetFeature<"nmi", "HasNMI",
472    "true", "Enable Armv8.8-A Non-maskable Interrupts (FEAT_NMI, FEAT_GICv3_NMI)">;
473
474def FeatureBRBE : SubtargetFeature<"brbe", "HasBRBE",
475    "true", "Enable Branch Record Buffer Extension (FEAT_BRBE)">;
476
477def FeatureSPE_EEF : SubtargetFeature<"spe-eef", "HasSPE_EEF",
478    "true", "Enable extra register in the Statistical Profiling Extension (FEAT_SPEv1p2)">;
479
480def FeatureFineGrainedTraps : SubtargetFeature<"fgt", "HasFineGrainedTraps",
481    "true", "Enable fine grained virtualization traps extension (FEAT_FGT)">;
482
483def FeatureEnhancedCounterVirtualization :
484      SubtargetFeature<"ecv", "HasEnhancedCounterVirtualization",
485      "true", "Enable enhanced counter virtualization extension (FEAT_ECV)">;
486
487def FeatureRME : SubtargetFeature<"rme", "HasRME",
488    "true", "Enable Realm Management Extension (FEAT_RME)">;
489
490def FeatureSME : SubtargetFeature<"sme", "HasSME", "true",
491  "Enable Scalable Matrix Extension (SME) (FEAT_SME)", [FeatureBF16, FeatureUseScalarIncVL]>;
492
493def FeatureSMEF64F64 : SubtargetFeature<"sme-f64f64", "HasSMEF64F64", "true",
494  "Enable Scalable Matrix Extension (SME) F64F64 instructions (FEAT_SME_F64F64)", [FeatureSME]>;
495
496def FeatureSMEI16I64 : SubtargetFeature<"sme-i16i64", "HasSMEI16I64", "true",
497  "Enable Scalable Matrix Extension (SME) I16I64 instructions (FEAT_SME_I16I64)", [FeatureSME]>;
498
499def FeatureSMEF16F16 : SubtargetFeature<"sme-f16f16", "HasSMEF16F16", "true",
500  "Enable SME2.1 non-widening Float16 instructions (FEAT_SME_F16F16)", []>;
501
502def FeatureSME2 : SubtargetFeature<"sme2", "HasSME2", "true",
503  "Enable Scalable Matrix Extension 2 (SME2) instructions", [FeatureSME]>;
504
505def FeatureSME2p1 : SubtargetFeature<"sme2p1", "HasSME2p1", "true",
506  "Enable Scalable Matrix Extension 2.1 (FEAT_SME2p1) instructions", [FeatureSME2]>;
507
508def FeatureAppleA7SysReg  : SubtargetFeature<"apple-a7-sysreg", "HasAppleA7SysReg", "true",
509  "Apple A7 (the CPU formerly known as Cyclone)">;
510
511def FeatureEL2VMSA : SubtargetFeature<"el2vmsa", "HasEL2VMSA", "true",
512  "Enable Exception Level 2 Virtual Memory System Architecture">;
513
514def FeatureEL3 : SubtargetFeature<"el3", "HasEL3", "true",
515  "Enable Exception Level 3">;
516
517def FeatureCSSC : SubtargetFeature<"cssc", "HasCSSC", "true",
518  "Enable Common Short Sequence Compression (CSSC) instructions (FEAT_CSSC)">;
519
520def FeatureFixCortexA53_835769 : SubtargetFeature<"fix-cortex-a53-835769",
521  "FixCortexA53_835769", "true", "Mitigate Cortex-A53 Erratum 835769">;
522
523def FeatureNoBTIAtReturnTwice : SubtargetFeature<"no-bti-at-return-twice",
524                                                 "NoBTIAtReturnTwice", "true",
525                                                 "Don't place a BTI instruction "
526                                                 "after a return-twice">;
527
528def FeatureCHK : SubtargetFeature<"chk", "HasCHK",
529    "true", "Enable Armv8.0-A Check Feature Status Extension (FEAT_CHK)">;
530
531def FeatureGCS : SubtargetFeature<"gcs", "HasGCS",
532    "true", "Enable Armv9.4-A Guarded Call Stack Extension", [FeatureCHK]>;
533
534def FeatureCLRBHB : SubtargetFeature<"clrbhb", "HasCLRBHB",
535    "true", "Enable Clear BHB instruction (FEAT_CLRBHB)">;
536
537def FeaturePRFM_SLC : SubtargetFeature<"prfm-slc-target", "HasPRFM_SLC",
538    "true", "Enable SLC target for PRFM instruction">;
539
540def FeatureSPECRES2 : SubtargetFeature<"specres2", "HasSPECRES2",
541    "true", "Enable Speculation Restriction Instruction (FEAT_SPECRES2)",
542    [FeaturePredRes]>;
543
544def FeatureMEC : SubtargetFeature<"mec", "HasMEC",
545    "true", "Enable Memory Encryption Contexts Extension", [FeatureRME]>;
546
547def FeatureITE : SubtargetFeature<"ite", "HasITE",
548    "true", "Enable Armv9.4-A Instrumentation Extension FEAT_ITE", [FeatureETE,
549    FeatureTRBE]>;
550
551def FeatureRCPC3 : SubtargetFeature<"rcpc3", "HasRCPC3",
552    "true", "Enable Armv8.9-A RCPC instructions for A64 and Advanced SIMD and floating-point instruction set (FEAT_LRCPC3)",
553    [FeatureRCPC_IMMO]>;
554
555def FeatureTHE : SubtargetFeature<"the", "HasTHE",
556    "true", "Enable Armv8.9-A Translation Hardening Extension (FEAT_THE)">;
557
558def FeatureLSE128 : SubtargetFeature<"lse128", "HasLSE128",
559    "true", "Enable Armv9.4-A 128-bit Atomic Instructions (FEAT_LSE128)",
560    [FeatureLSE]>;
561
562// FEAT_D128, FEAT_LVA3, FEAT_SYSREG128, and FEAT_SYSINSTR128 are mutually implicit.
563// Therefore group them all under a single feature flag, d128:
564def FeatureD128 : SubtargetFeature<"d128", "HasD128",
565    "true", "Enable Armv9.4-A 128-bit Page Table Descriptors, System Registers "
566    "and Instructions (FEAT_D128, FEAT_LVA3, FEAT_SYSREG128, FEAT_SYSINSTR128)",
567    [FeatureLSE128]>;
568
569//===----------------------------------------------------------------------===//
570// Architectures.
571//
572def HasV8_0aOps : SubtargetFeature<"v8a", "HasV8_0aOps", "true",
573  "Support ARM v8.0a instructions", [FeatureEL2VMSA, FeatureEL3]>;
574
575def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
576  "Support ARM v8.1a instructions", [HasV8_0aOps, FeatureCRC, FeatureLSE,
577  FeatureRDM, FeaturePAN, FeatureLOR, FeatureVH]>;
578
579def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
580  "Support ARM v8.2a instructions", [HasV8_1aOps, FeaturePsUAO,
581  FeaturePAN_RWV, FeatureRAS, FeatureCCPP]>;
582
583def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true",
584  "Support ARM v8.3a instructions", [HasV8_2aOps, FeatureRCPC, FeaturePAuth,
585  FeatureJS, FeatureCCIDX, FeatureComplxNum]>;
586
587def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true",
588  "Support ARM v8.4a instructions", [HasV8_3aOps, FeatureDotProd,
589  FeatureNV, FeatureMPAM, FeatureDIT,
590  FeatureTRACEV8_4, FeatureAM, FeatureSEL2, FeatureTLB_RMI,
591  FeatureFlagM, FeatureRCPC_IMMO, FeatureLSE2]>;
592
593def HasV8_5aOps : SubtargetFeature<
594  "v8.5a", "HasV8_5aOps", "true", "Support ARM v8.5a instructions",
595  [HasV8_4aOps, FeatureAltFPCmp, FeatureFRInt3264, FeatureSpecRestrict,
596   FeatureSSBS, FeatureSB, FeaturePredRes, FeatureCacheDeepPersist,
597   FeatureBranchTargetId]>;
598
599def HasV8_6aOps : SubtargetFeature<
600  "v8.6a", "HasV8_6aOps", "true", "Support ARM v8.6a instructions",
601  [HasV8_5aOps, FeatureAMVS, FeatureBF16, FeatureFineGrainedTraps,
602   FeatureEnhancedCounterVirtualization, FeatureMatMulInt8]>;
603
604def HasV8_7aOps : SubtargetFeature<
605  "v8.7a", "HasV8_7aOps", "true", "Support ARM v8.7a instructions",
606  [HasV8_6aOps, FeatureXS, FeatureWFxT, FeatureHCX]>;
607
608def HasV8_8aOps : SubtargetFeature<
609  "v8.8a", "HasV8_8aOps", "true", "Support ARM v8.8a instructions",
610  [HasV8_7aOps, FeatureHBC, FeatureMOPS, FeatureNMI]>;
611
612def HasV8_9aOps : SubtargetFeature<
613  "v8.9a", "HasV8_9aOps", "true", "Support ARM v8.9a instructions",
614  [HasV8_8aOps, FeatureCLRBHB, FeaturePRFM_SLC, FeatureSPECRES2,
615   FeatureCSSC, FeatureRASv2, FeatureCHK]>;
616
617def HasV9_0aOps : SubtargetFeature<
618  "v9a", "HasV9_0aOps", "true", "Support ARM v9a instructions",
619  [HasV8_5aOps, FeatureMEC, FeatureSVE2]>;
620
621def HasV9_1aOps : SubtargetFeature<
622  "v9.1a", "HasV9_1aOps", "true", "Support ARM v9.1a instructions",
623  [HasV8_6aOps, HasV9_0aOps]>;
624
625def HasV9_2aOps : SubtargetFeature<
626  "v9.2a", "HasV9_2aOps", "true", "Support ARM v9.2a instructions",
627  [HasV8_7aOps, HasV9_1aOps]>;
628
629def HasV9_3aOps : SubtargetFeature<
630  "v9.3a", "HasV9_3aOps", "true", "Support ARM v9.3a instructions",
631  [HasV8_8aOps, HasV9_2aOps]>;
632
633def HasV9_4aOps : SubtargetFeature<
634  "v9.4a", "HasV9_4aOps", "true", "Support ARM v9.4a instructions",
635  [HasV8_9aOps, HasV9_3aOps]>;
636
637def HasV8_0rOps : SubtargetFeature<
638  "v8r", "HasV8_0rOps", "true", "Support ARM v8r instructions",
639  [//v8.1
640  FeatureCRC, FeaturePAN, FeatureRDM, FeatureLSE, FeatureCONTEXTIDREL2,
641  //v8.2
642  FeatureRAS, FeaturePsUAO, FeatureCCPP, FeaturePAN_RWV,
643  //v8.3
644  FeatureComplxNum, FeatureCCIDX, FeatureJS,
645  FeaturePAuth, FeatureRCPC,
646  //v8.4
647  FeatureDotProd, FeatureTRACEV8_4, FeatureTLB_RMI,
648  FeatureFlagM, FeatureDIT, FeatureSEL2, FeatureRCPC_IMMO,
649  // Not mandatory in v8.0-R, but included here on the grounds that it
650  // only enables names of system registers
651  FeatureSpecRestrict
652  ]>;
653
654// Only intended to be used by disassemblers.
655def FeatureAll
656    : SubtargetFeature<"all", "IsAll", "true", "Enable all instructions", []>;
657
658class AssemblerPredicateWithAll<dag cond, string name="">
659    : AssemblerPredicate<(any_of FeatureAll, cond), name>;
660
661//===----------------------------------------------------------------------===//
662// Register File Description
663//===----------------------------------------------------------------------===//
664
665include "AArch64RegisterInfo.td"
666include "AArch64RegisterBanks.td"
667include "AArch64CallingConvention.td"
668
669//===----------------------------------------------------------------------===//
670// Instruction Descriptions
671//===----------------------------------------------------------------------===//
672
673include "AArch64Schedule.td"
674include "AArch64InstrInfo.td"
675include "AArch64SchedPredicates.td"
676include "AArch64SchedPredExynos.td"
677include "AArch64SchedPredNeoverse.td"
678include "AArch64Combine.td"
679
680def AArch64InstrInfo : InstrInfo;
681
682//===----------------------------------------------------------------------===//
683// Named operands for MRS/MSR/TLBI/...
684//===----------------------------------------------------------------------===//
685
686include "AArch64SystemOperands.td"
687
688//===----------------------------------------------------------------------===//
689// Access to privileged registers
690//===----------------------------------------------------------------------===//
691
692foreach i = 1-3 in
693def FeatureUseEL#i#ForTP : SubtargetFeature<"tpidr-el"#i, "UseEL"#i#"ForTP",
694  "true", "Permit use of TPIDR_EL"#i#" for the TLS base">;
695def FeatureUseROEL0ForTP : SubtargetFeature<"tpidrro-el0", "UseROEL0ForTP",
696  "true", "Permit use of TPIDRRO_EL0 for the TLS base">;
697
698//===----------------------------------------------------------------------===//
699// Control codegen mitigation against Straight Line Speculation vulnerability.
700//===----------------------------------------------------------------------===//
701
702def FeatureHardenSlsRetBr : SubtargetFeature<"harden-sls-retbr",
703  "HardenSlsRetBr", "true",
704  "Harden against straight line speculation across RET and BR instructions">;
705def FeatureHardenSlsBlr : SubtargetFeature<"harden-sls-blr",
706  "HardenSlsBlr", "true",
707  "Harden against straight line speculation across BLR instructions">;
708def FeatureHardenSlsNoComdat : SubtargetFeature<"harden-sls-nocomdat",
709  "HardenSlsNoComdat", "true",
710  "Generate thunk code for SLS mitigation in the normal text section">;
711
712//===----------------------------------------------------------------------===//
713// AArch64 Processors supported.
714//
715
716//===----------------------------------------------------------------------===//
717// Unsupported features to disable for scheduling models
718//===----------------------------------------------------------------------===//
719
720class AArch64Unsupported { list<Predicate> F; }
721
722let F = [HasSVE2p1, HasSVE2p1_or_HasSME2, HasSVE2p1_or_HasSME2p1] in
723def SVE2p1Unsupported : AArch64Unsupported;
724
725def SVE2Unsupported : AArch64Unsupported {
726  let F = !listconcat([HasSVE2, HasSVE2orSME,
727                       HasSVE2AES, HasSVE2SHA3, HasSVE2SM4, HasSVE2BitPerm],
728                       SVE2p1Unsupported.F);
729}
730
731def SVEUnsupported : AArch64Unsupported {
732  let F = !listconcat([HasSVE, HasSVEorSME],
733                      SVE2Unsupported.F);
734}
735
736let F = [HasSME2p1, HasSVE2p1_or_HasSME2p1] in
737def SME2p1Unsupported : AArch64Unsupported;
738
739def SME2Unsupported : AArch64Unsupported {
740  let F = !listconcat([HasSME2, HasSVE2p1_or_HasSME2],
741                      SME2p1Unsupported.F);
742}
743
744def SMEUnsupported : AArch64Unsupported {
745  let F = !listconcat([HasSME, HasSMEI16I64, HasSMEF16F16, HasSMEF64F64],
746                      SME2Unsupported.F);
747}
748
749let F = [HasPAuth] in
750def PAUnsupported : AArch64Unsupported;
751
752include "AArch64SchedA53.td"
753include "AArch64SchedA55.td"
754include "AArch64SchedA510.td"
755include "AArch64SchedA57.td"
756include "AArch64SchedCyclone.td"
757include "AArch64SchedFalkor.td"
758include "AArch64SchedKryo.td"
759include "AArch64SchedExynosM3.td"
760include "AArch64SchedExynosM4.td"
761include "AArch64SchedExynosM5.td"
762include "AArch64SchedThunderX.td"
763include "AArch64SchedThunderX2T99.td"
764include "AArch64SchedA64FX.td"
765include "AArch64SchedThunderX3T110.td"
766include "AArch64SchedTSV110.td"
767include "AArch64SchedAmpere1.td"
768include "AArch64SchedNeoverseN1.td"
769include "AArch64SchedNeoverseN2.td"
770include "AArch64SchedNeoverseV1.td"
771include "AArch64SchedNeoverseV2.td"
772
773def TuneA35     : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35",
774                                "Cortex-A35 ARM processors">;
775
776def TuneA53     : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
777                                   "Cortex-A53 ARM processors", [
778                                   FeatureFuseAES,
779                                   FeatureFuseAdrpAdd,
780                                   FeatureBalanceFPOps,
781                                   FeatureCustomCheapAsMoveHandling,
782                                   FeaturePostRAScheduler]>;
783
784def TuneA55     : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55",
785                                   "Cortex-A55 ARM processors", [
786                                   FeatureFuseAES,
787                                   FeatureFuseAdrpAdd,
788                                   FeaturePostRAScheduler,
789                                   FeatureFuseAddress]>;
790
791def TuneA510    : SubtargetFeature<"a510", "ARMProcFamily", "CortexA510",
792                                   "Cortex-A510 ARM processors", [
793                                   FeatureFuseAES,
794                                   FeatureFuseAdrpAdd,
795                                   FeaturePostRAScheduler
796                                   ]>;
797
798def TuneA57     : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
799                                   "Cortex-A57 ARM processors", [
800                                   FeatureFuseAES,
801                                   FeatureBalanceFPOps,
802                                   FeatureCustomCheapAsMoveHandling,
803                                   FeatureFuseAdrpAdd,
804                                   FeatureFuseLiterals,
805                                   FeaturePostRAScheduler,
806                                   FeatureEnableSelectOptimize,
807                                   FeaturePredictableSelectIsExpensive]>;
808
809def TuneA65     : SubtargetFeature<"a65", "ARMProcFamily", "CortexA65",
810                                   "Cortex-A65 ARM processors", [
811                                   FeatureFuseAES,
812                                   FeatureFuseAddress,
813                                   FeatureFuseAdrpAdd,
814                                   FeatureFuseLiterals,
815                                   FeatureEnableSelectOptimize,
816                                   FeaturePredictableSelectIsExpensive]>;
817
818def TuneA72     : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72",
819                                   "Cortex-A72 ARM processors", [
820                                   FeatureFuseAES,
821                                   FeatureFuseAdrpAdd,
822                                   FeatureFuseLiterals,
823                                   FeatureEnableSelectOptimize,
824                                   FeaturePredictableSelectIsExpensive]>;
825
826def TuneA73     : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73",
827                                   "Cortex-A73 ARM processors", [
828                                   FeatureFuseAES,
829                                   FeatureFuseAdrpAdd,
830                                   FeatureEnableSelectOptimize,
831                                   FeaturePredictableSelectIsExpensive]>;
832
833def TuneA75     : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75",
834                                   "Cortex-A75 ARM processors", [
835                                   FeatureFuseAES,
836                                   FeatureFuseAdrpAdd,
837                                   FeatureEnableSelectOptimize,
838                                   FeaturePredictableSelectIsExpensive]>;
839
840def TuneA76     : SubtargetFeature<"a76", "ARMProcFamily", "CortexA76",
841                                   "Cortex-A76 ARM processors", [
842                                   FeatureFuseAES,
843                                   FeatureFuseAdrpAdd,
844                                   FeatureLSLFast,
845                                   FeatureEnableSelectOptimize,
846                                   FeaturePredictableSelectIsExpensive]>;
847
848def TuneA77     : SubtargetFeature<"a77", "ARMProcFamily", "CortexA77",
849                                   "Cortex-A77 ARM processors", [
850                                   FeatureCmpBccFusion,
851                                   FeatureFuseAES,
852                                   FeatureFuseAdrpAdd,
853                                   FeatureLSLFast,
854                                   FeatureEnableSelectOptimize,
855                                   FeaturePredictableSelectIsExpensive]>;
856
857def TuneA78 : SubtargetFeature<"a78", "ARMProcFamily", "CortexA78",
858                               "Cortex-A78 ARM processors", [
859                               FeatureCmpBccFusion,
860                               FeatureFuseAES,
861                               FeatureFuseAdrpAdd,
862                               FeatureLSLFast,
863                               FeaturePostRAScheduler,
864                               FeatureEnableSelectOptimize,
865                               FeaturePredictableSelectIsExpensive]>;
866
867def TuneA78C : SubtargetFeature<"a78c", "ARMProcFamily",
868                                "CortexA78C",
869                                "Cortex-A78C ARM processors", [
870                                FeatureCmpBccFusion,
871                                FeatureFuseAES,
872                                FeatureFuseAdrpAdd,
873                                FeatureLSLFast,
874                                FeaturePostRAScheduler,
875                                FeatureEnableSelectOptimize,
876                                FeaturePredictableSelectIsExpensive]>;
877
878def TuneA710    : SubtargetFeature<"a710", "ARMProcFamily", "CortexA710",
879                                   "Cortex-A710 ARM processors", [
880                                   FeatureCmpBccFusion,
881                                   FeatureFuseAES,
882                                   FeatureFuseAdrpAdd,
883                                   FeatureLSLFast,
884                                   FeaturePostRAScheduler,
885                                   FeatureEnableSelectOptimize,
886                                   FeaturePredictableSelectIsExpensive]>;
887
888def TuneA715 : SubtargetFeature<"a715", "ARMProcFamily", "CortexA715",
889                                 "Cortex-A715 ARM processors", [
890                                 FeatureFuseAES,
891                                 FeaturePostRAScheduler,
892                                 FeatureCmpBccFusion,
893                                 FeatureLSLFast,
894                                 FeatureFuseAdrpAdd,
895                                 FeatureEnableSelectOptimize,
896                                 FeaturePredictableSelectIsExpensive]>;
897
898def TuneR82 : SubtargetFeature<"cortex-r82", "ARMProcFamily",
899                               "CortexR82",
900                               "Cortex-R82 ARM processors", [
901                               FeaturePostRAScheduler]>;
902
903def TuneX1 : SubtargetFeature<"cortex-x1", "ARMProcFamily", "CortexX1",
904                                  "Cortex-X1 ARM processors", [
905                                  FeatureCmpBccFusion,
906                                  FeatureFuseAES,
907                                  FeatureFuseAdrpAdd,
908                                  FeatureLSLFast,
909                                  FeaturePostRAScheduler,
910                                  FeatureEnableSelectOptimize,
911                                  FeaturePredictableSelectIsExpensive]>;
912
913def TuneX2 : SubtargetFeature<"cortex-x2", "ARMProcFamily", "CortexX2",
914                                  "Cortex-X2 ARM processors", [
915                                  FeatureCmpBccFusion,
916                                  FeatureFuseAES,
917                                  FeatureFuseAdrpAdd,
918                                  FeatureLSLFast,
919                                  FeaturePostRAScheduler,
920                                  FeatureEnableSelectOptimize,
921                                  FeaturePredictableSelectIsExpensive]>;
922
923def TuneX3 : SubtargetFeature<"cortex-x3", "ARMProcFamily", "CortexX3",
924                              "Cortex-X3 ARM processors", [
925                               FeatureLSLFast,
926                               FeatureFuseAdrpAdd,
927                               FeatureFuseAES,
928                               FeaturePostRAScheduler,
929                               FeatureEnableSelectOptimize,
930                               FeaturePredictableSelectIsExpensive]>;
931
932def TuneA64FX : SubtargetFeature<"a64fx", "ARMProcFamily", "A64FX",
933                                 "Fujitsu A64FX processors", [
934                                 FeaturePostRAScheduler,
935                                 FeatureAggressiveFMA,
936                                 FeatureArithmeticBccFusion,
937                                 FeaturePredictableSelectIsExpensive
938                                 ]>;
939
940def TuneCarmel : SubtargetFeature<"carmel", "ARMProcFamily", "Carmel",
941                                  "Nvidia Carmel processors">;
942
943// Note that cyclone does not fuse AES instructions, but newer apple chips do
944// perform the fusion and cyclone is used by default when targetting apple OSes.
945def TuneAppleA7  : SubtargetFeature<"apple-a7", "ARMProcFamily", "AppleA7",
946                                    "Apple A7 (the CPU formerly known as Cyclone)", [
947                                    FeatureAlternateSExtLoadCVTF32Pattern,
948                                    FeatureArithmeticBccFusion,
949                                    FeatureArithmeticCbzFusion,
950                                    FeatureDisableLatencySchedHeuristic,
951                                    FeatureFuseAES, FeatureFuseCryptoEOR,
952                                    FeatureZCRegMove,
953                                    FeatureZCZeroing,
954                                    FeatureZCZeroingFPWorkaround]
955                                    >;
956
957def TuneAppleA10 : SubtargetFeature<"apple-a10", "ARMProcFamily", "AppleA10",
958                                    "Apple A10", [
959                                    FeatureAlternateSExtLoadCVTF32Pattern,
960                                    FeatureArithmeticBccFusion,
961                                    FeatureArithmeticCbzFusion,
962                                    FeatureDisableLatencySchedHeuristic,
963                                    FeatureFuseAES,
964                                    FeatureFuseCryptoEOR,
965                                    FeatureZCRegMove,
966                                    FeatureZCZeroing]
967                                    >;
968
969def TuneAppleA11 : SubtargetFeature<"apple-a11", "ARMProcFamily", "AppleA11",
970                                    "Apple A11", [
971                                    FeatureAlternateSExtLoadCVTF32Pattern,
972                                    FeatureArithmeticBccFusion,
973                                    FeatureArithmeticCbzFusion,
974                                    FeatureDisableLatencySchedHeuristic,
975                                    FeatureFuseAES,
976                                    FeatureFuseCryptoEOR,
977                                    FeatureZCRegMove,
978                                    FeatureZCZeroing]
979                                    >;
980
981def TuneAppleA12 : SubtargetFeature<"apple-a12", "ARMProcFamily", "AppleA12",
982                                    "Apple A12", [
983                                    FeatureAlternateSExtLoadCVTF32Pattern,
984                                    FeatureArithmeticBccFusion,
985                                    FeatureArithmeticCbzFusion,
986                                    FeatureDisableLatencySchedHeuristic,
987                                    FeatureFuseAES,
988                                    FeatureFuseCryptoEOR,
989                                    FeatureZCRegMove,
990                                    FeatureZCZeroing]
991                                    >;
992
993def TuneAppleA13 : SubtargetFeature<"apple-a13", "ARMProcFamily", "AppleA13",
994                                    "Apple A13", [
995                                    FeatureAlternateSExtLoadCVTF32Pattern,
996                                    FeatureArithmeticBccFusion,
997                                    FeatureArithmeticCbzFusion,
998                                    FeatureDisableLatencySchedHeuristic,
999                                    FeatureFuseAES,
1000                                    FeatureFuseCryptoEOR,
1001                                    FeatureZCRegMove,
1002                                    FeatureZCZeroing]
1003                                    >;
1004
1005def TuneAppleA14 : SubtargetFeature<"apple-a14", "ARMProcFamily", "AppleA14",
1006                                    "Apple A14", [
1007                                    FeatureAggressiveFMA,
1008                                    FeatureAlternateSExtLoadCVTF32Pattern,
1009                                    FeatureArithmeticBccFusion,
1010                                    FeatureArithmeticCbzFusion,
1011                                    FeatureDisableLatencySchedHeuristic,
1012                                    FeatureFuseAddress,
1013                                    FeatureFuseAES,
1014                                    FeatureFuseArithmeticLogic,
1015                                    FeatureFuseCCSelect,
1016                                    FeatureFuseCryptoEOR,
1017                                    FeatureFuseAdrpAdd,
1018                                    FeatureFuseLiterals,
1019                                    FeatureZCRegMove,
1020                                    FeatureZCZeroing]>;
1021
1022def TuneAppleA15 : SubtargetFeature<"apple-a15", "ARMProcFamily", "AppleA15",
1023                                    "Apple A15", [
1024                                    FeatureAlternateSExtLoadCVTF32Pattern,
1025                                    FeatureArithmeticBccFusion,
1026                                    FeatureArithmeticCbzFusion,
1027                                    FeatureDisableLatencySchedHeuristic,
1028                                    FeatureFuseAddress,
1029                                    FeatureFuseAES,
1030                                    FeatureFuseArithmeticLogic,
1031                                    FeatureFuseCCSelect,
1032                                    FeatureFuseCryptoEOR,
1033                                    FeatureFuseLiterals,
1034                                    FeatureZCRegMove,
1035                                    FeatureZCZeroing
1036                                    ]>;
1037
1038def TuneAppleA16 : SubtargetFeature<"apple-a16", "ARMProcFamily", "AppleA16",
1039                                    "Apple A16", [
1040                                    FeatureAlternateSExtLoadCVTF32Pattern,
1041                                    FeatureArithmeticBccFusion,
1042                                    FeatureArithmeticCbzFusion,
1043                                    FeatureDisableLatencySchedHeuristic,
1044                                    FeatureFuseAddress,
1045                                    FeatureFuseAES,
1046                                    FeatureFuseArithmeticLogic,
1047                                    FeatureFuseCCSelect,
1048                                    FeatureFuseCryptoEOR,
1049                                    FeatureFuseLiterals,
1050                                    FeatureZCRegMove,
1051                                    FeatureZCZeroing
1052                                    ]>;
1053
1054def TuneExynosM3 : SubtargetFeature<"exynosm3", "ARMProcFamily", "ExynosM3",
1055                                    "Samsung Exynos-M3 processors",
1056                                    [FeatureExynosCheapAsMoveHandling,
1057                                     FeatureForce32BitJumpTables,
1058                                     FeatureFuseAddress,
1059                                     FeatureFuseAES,
1060                                     FeatureFuseCCSelect,
1061                                     FeatureFuseAdrpAdd,
1062                                     FeatureFuseLiterals,
1063                                     FeatureLSLFast,
1064                                     FeaturePostRAScheduler,
1065                                     FeaturePredictableSelectIsExpensive]>;
1066
1067// Re-uses some scheduling and tunings from the ExynosM3 proc family.
1068def TuneExynosM4 : SubtargetFeature<"exynosm4", "ARMProcFamily", "ExynosM3",
1069                                    "Samsung Exynos-M4 processors",
1070                                    [FeatureArithmeticBccFusion,
1071                                     FeatureArithmeticCbzFusion,
1072                                     FeatureExynosCheapAsMoveHandling,
1073                                     FeatureForce32BitJumpTables,
1074                                     FeatureFuseAddress,
1075                                     FeatureFuseAES,
1076                                     FeatureFuseArithmeticLogic,
1077                                     FeatureFuseCCSelect,
1078                                     FeatureFuseAdrpAdd,
1079                                     FeatureFuseLiterals,
1080                                     FeatureLSLFast,
1081                                     FeaturePostRAScheduler,
1082                                     FeatureZCZeroing]>;
1083
1084def TuneKryo    : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo",
1085                                   "Qualcomm Kryo processors", [
1086                                   FeatureCustomCheapAsMoveHandling,
1087                                   FeaturePostRAScheduler,
1088                                   FeaturePredictableSelectIsExpensive,
1089                                   FeatureZCZeroing,
1090                                   FeatureLSLFast]
1091                                   >;
1092
1093def TuneFalkor  : SubtargetFeature<"falkor", "ARMProcFamily", "Falkor",
1094                                   "Qualcomm Falkor processors", [
1095                                   FeatureCustomCheapAsMoveHandling,
1096                                   FeaturePostRAScheduler,
1097                                   FeaturePredictableSelectIsExpensive,
1098                                   FeatureZCZeroing,
1099                                   FeatureLSLFast,
1100                                   FeatureSlowSTRQro
1101                                   ]>;
1102
1103def TuneNeoverseE1 : SubtargetFeature<"neoversee1", "ARMProcFamily", "NeoverseE1",
1104                                      "Neoverse E1 ARM processors", [
1105                                      FeatureFuseAES,
1106                                      FeatureFuseAdrpAdd,
1107                                      FeaturePostRAScheduler]>;
1108
1109def TuneNeoverseN1 : SubtargetFeature<"neoversen1", "ARMProcFamily", "NeoverseN1",
1110                                      "Neoverse N1 ARM processors", [
1111                                      FeatureFuseAES,
1112                                      FeatureFuseAdrpAdd,
1113                                      FeatureLSLFast,
1114                                      FeaturePostRAScheduler,
1115                                      FeatureEnableSelectOptimize,
1116                                      FeaturePredictableSelectIsExpensive]>;
1117
1118def TuneNeoverseN2 : SubtargetFeature<"neoversen2", "ARMProcFamily", "NeoverseN2",
1119                                      "Neoverse N2 ARM processors", [
1120                                      FeatureFuseAES,
1121                                      FeatureFuseAdrpAdd,
1122                                      FeatureLSLFast,
1123                                      FeaturePostRAScheduler,
1124                                      FeatureEnableSelectOptimize,
1125                                      FeaturePredictableSelectIsExpensive]>;
1126
1127def TuneNeoverse512TVB : SubtargetFeature<"neoverse512tvb", "ARMProcFamily", "Neoverse512TVB",
1128                                      "Neoverse 512-TVB ARM processors", [
1129                                      FeatureFuseAES,
1130                                      FeatureFuseAdrpAdd,
1131                                      FeatureLSLFast,
1132                                      FeaturePostRAScheduler,
1133                                      FeatureEnableSelectOptimize,
1134                                      FeaturePredictableSelectIsExpensive]>;
1135
1136def TuneNeoverseV1 : SubtargetFeature<"neoversev1", "ARMProcFamily", "NeoverseV1",
1137                                      "Neoverse V1 ARM processors", [
1138                                      FeatureFuseAES,
1139                                      FeatureFuseAdrpAdd,
1140                                      FeatureLSLFast,
1141                                      FeaturePostRAScheduler,
1142                                      FeatureEnableSelectOptimize,
1143                                      FeaturePredictableSelectIsExpensive,
1144                                      FeatureNoSVEFPLD1R]>;
1145
1146def TuneNeoverseV2 : SubtargetFeature<"neoversev2", "ARMProcFamily", "NeoverseV2",
1147                                      "Neoverse V2 ARM processors", [
1148                                      FeatureFuseAES,
1149                                      FeatureLSLFast,
1150                                      FeaturePostRAScheduler,
1151                                      FeatureEnableSelectOptimize,
1152                                      FeaturePredictableSelectIsExpensive]>;
1153
1154def TuneSaphira  : SubtargetFeature<"saphira", "ARMProcFamily", "Saphira",
1155                                   "Qualcomm Saphira processors", [
1156                                   FeatureCustomCheapAsMoveHandling,
1157                                   FeaturePostRAScheduler,
1158                                   FeaturePredictableSelectIsExpensive,
1159                                   FeatureZCZeroing,
1160                                   FeatureLSLFast]>;
1161
1162def TuneThunderX2T99  : SubtargetFeature<"thunderx2t99", "ARMProcFamily", "ThunderX2T99",
1163                                         "Cavium ThunderX2 processors", [
1164                                          FeatureAggressiveFMA,
1165                                          FeatureArithmeticBccFusion,
1166                                          FeaturePostRAScheduler,
1167                                          FeaturePredictableSelectIsExpensive]>;
1168
1169def TuneThunderX3T110  : SubtargetFeature<"thunderx3t110", "ARMProcFamily",
1170                                          "ThunderX3T110",
1171                                          "Marvell ThunderX3 processors", [
1172                                           FeatureAggressiveFMA,
1173                                           FeatureArithmeticBccFusion,
1174                                           FeaturePostRAScheduler,
1175                                           FeaturePredictableSelectIsExpensive,
1176                                           FeatureBalanceFPOps,
1177                                           FeatureStrictAlign]>;
1178
1179def TuneThunderX : SubtargetFeature<"thunderx", "ARMProcFamily", "ThunderX",
1180                                    "Cavium ThunderX processors", [
1181                                    FeaturePostRAScheduler,
1182                                    FeaturePredictableSelectIsExpensive]>;
1183
1184def TuneThunderXT88 : SubtargetFeature<"thunderxt88", "ARMProcFamily",
1185                                       "ThunderXT88",
1186                                       "Cavium ThunderX processors", [
1187                                       FeaturePostRAScheduler,
1188                                       FeaturePredictableSelectIsExpensive]>;
1189
1190def TuneThunderXT81 : SubtargetFeature<"thunderxt81", "ARMProcFamily",
1191                                       "ThunderXT81",
1192                                       "Cavium ThunderX processors", [
1193                                       FeaturePostRAScheduler,
1194                                       FeaturePredictableSelectIsExpensive]>;
1195
1196def TuneThunderXT83 : SubtargetFeature<"thunderxt83", "ARMProcFamily",
1197                                       "ThunderXT83",
1198                                       "Cavium ThunderX processors", [
1199                                       FeaturePostRAScheduler,
1200                                       FeaturePredictableSelectIsExpensive]>;
1201
1202def TuneTSV110 : SubtargetFeature<"tsv110", "ARMProcFamily", "TSV110",
1203                                  "HiSilicon TS-V110 processors", [
1204                                  FeatureCustomCheapAsMoveHandling,
1205                                  FeatureFuseAES,
1206                                  FeaturePostRAScheduler]>;
1207
1208def TuneAmpere1 : SubtargetFeature<"ampere1", "ARMProcFamily", "Ampere1",
1209                                   "Ampere Computing Ampere-1 processors", [
1210                                   FeaturePostRAScheduler,
1211                                   FeatureFuseAES,
1212                                   FeatureLSLFast,
1213                                   FeatureAggressiveFMA,
1214                                   FeatureArithmeticBccFusion,
1215                                   FeatureCmpBccFusion,
1216                                   FeatureFuseAddress,
1217                                   FeatureFuseLiterals]>;
1218
1219def TuneAmpere1A : SubtargetFeature<"ampere1a", "ARMProcFamily", "Ampere1A",
1220                                    "Ampere Computing Ampere-1A processors", [
1221                                    FeaturePostRAScheduler,
1222                                    FeatureFuseAES,
1223                                    FeatureLSLFast,
1224                                    FeatureAggressiveFMA,
1225                                    FeatureArithmeticBccFusion,
1226                                    FeatureCmpBccFusion,
1227                                    FeatureFuseAddress,
1228                                    FeatureFuseLiterals,
1229                                    FeatureFuseLiterals]>;
1230
1231def ProcessorFeatures {
1232  list<SubtargetFeature> A53  = [HasV8_0aOps, FeatureCRC, FeatureCrypto,
1233                                 FeatureFPARMv8, FeatureNEON, FeaturePerfMon];
1234  list<SubtargetFeature> A55  = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
1235                                 FeatureNEON, FeatureFullFP16, FeatureDotProd,
1236                                 FeatureRCPC, FeaturePerfMon];
1237  list<SubtargetFeature> A510 = [HasV9_0aOps, FeatureNEON, FeaturePerfMon,
1238                                 FeatureMatMulInt8, FeatureBF16, FeatureAM,
1239                                 FeatureMTE, FeatureETE, FeatureSVE2BitPerm,
1240                                 FeatureFP16FML];
1241  list<SubtargetFeature> A65  = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
1242                                 FeatureNEON, FeatureFullFP16, FeatureDotProd,
1243                                 FeatureRCPC, FeatureSSBS, FeatureRAS,
1244                                 FeaturePerfMon];
1245  list<SubtargetFeature> A76  = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
1246                                 FeatureNEON, FeatureFullFP16, FeatureDotProd,
1247                                 FeatureRCPC, FeatureSSBS, FeaturePerfMon];
1248  list<SubtargetFeature> A77  = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
1249                                 FeatureNEON, FeatureFullFP16, FeatureDotProd,
1250                                 FeatureRCPC, FeaturePerfMon, FeatureSSBS];
1251  list<SubtargetFeature> A78  = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
1252                                 FeatureNEON, FeatureFullFP16, FeatureDotProd,
1253                                 FeatureRCPC, FeaturePerfMon, FeatureSPE,
1254                                 FeatureSSBS];
1255  list<SubtargetFeature> A78C = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
1256                                 FeatureNEON, FeatureFullFP16, FeatureDotProd,
1257                                 FeatureFlagM, FeatureFP16FML, FeaturePAuth,
1258                                 FeaturePerfMon, FeatureRCPC, FeatureSPE,
1259                                 FeatureSSBS];
1260  list<SubtargetFeature> A710 = [HasV9_0aOps, FeatureNEON, FeaturePerfMon,
1261                                 FeatureETE, FeatureMTE, FeatureFP16FML,
1262                                 FeatureSVE2BitPerm, FeatureBF16, FeatureMatMulInt8];
1263  list<SubtargetFeature> A715 = [HasV9_0aOps, FeatureNEON, FeatureMTE,
1264                                 FeatureFP16FML, FeatureSVE, FeatureTRBE,
1265                                 FeatureSVE2BitPerm, FeatureBF16, FeatureETE,
1266                                 FeaturePerfMon, FeatureMatMulInt8, FeatureSPE];
1267  list<SubtargetFeature> R82  = [HasV8_0rOps, FeaturePerfMon, FeatureFullFP16,
1268                                 FeatureFP16FML, FeatureSSBS, FeaturePredRes,
1269                                 FeatureSB];
1270  list<SubtargetFeature> X1   = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
1271                                 FeatureNEON, FeatureRCPC, FeaturePerfMon,
1272                                 FeatureSPE, FeatureFullFP16, FeatureDotProd,
1273                                 FeatureSSBS];
1274  list<SubtargetFeature> X1C  = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
1275                                 FeatureNEON, FeatureRCPC_IMMO, FeaturePerfMon,
1276                                 FeatureSPE, FeatureFullFP16, FeatureDotProd,
1277                                 FeaturePAuth, FeatureSSBS, FeatureFlagM,
1278                                 FeatureLSE2];
1279  list<SubtargetFeature> X2   = [HasV9_0aOps, FeatureNEON, FeaturePerfMon,
1280                                 FeatureMatMulInt8, FeatureBF16, FeatureAM,
1281                                 FeatureMTE, FeatureETE, FeatureSVE2BitPerm,
1282                                 FeatureFP16FML];
1283  list<SubtargetFeature> X3 =   [HasV9_0aOps, FeatureSVE, FeatureNEON,
1284                                 FeaturePerfMon, FeatureETE, FeatureTRBE,
1285                                 FeatureSPE, FeatureBF16, FeatureMatMulInt8,
1286                                 FeatureMTE, FeatureSVE2BitPerm, FeatureFullFP16,
1287                                 FeatureFP16FML];
1288  list<SubtargetFeature> A64FX    = [HasV8_2aOps, FeatureFPARMv8, FeatureNEON,
1289                                     FeatureSHA2, FeaturePerfMon, FeatureFullFP16,
1290                                     FeatureSVE, FeatureComplxNum];
1291  list<SubtargetFeature> Carmel   = [HasV8_2aOps, FeatureNEON, FeatureCrypto,
1292                                     FeatureFullFP16];
1293  list<SubtargetFeature> AppleA7  = [HasV8_0aOps, FeatureCrypto, FeatureFPARMv8,
1294                                     FeatureNEON,FeaturePerfMon, FeatureAppleA7SysReg];
1295  list<SubtargetFeature> AppleA10 = [HasV8_0aOps, FeatureCrypto, FeatureFPARMv8,
1296                                     FeatureNEON, FeaturePerfMon, FeatureCRC,
1297                                     FeatureRDM, FeaturePAN, FeatureLOR, FeatureVH];
1298  list<SubtargetFeature> AppleA11 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
1299                                     FeatureNEON, FeaturePerfMon, FeatureFullFP16];
1300  list<SubtargetFeature> AppleA12 = [HasV8_3aOps, FeatureCrypto, FeatureFPARMv8,
1301                                     FeatureNEON, FeaturePerfMon, FeatureFullFP16];
1302  list<SubtargetFeature> AppleA13 = [HasV8_4aOps, FeatureCrypto, FeatureFPARMv8,
1303                                     FeatureNEON, FeaturePerfMon, FeatureFullFP16,
1304                                     FeatureFP16FML, FeatureSHA3];
1305  list<SubtargetFeature> AppleA14 = [HasV8_4aOps, FeatureCrypto, FeatureFPARMv8,
1306                                     FeatureNEON, FeaturePerfMon, FeatureFRInt3264,
1307                                     FeatureSpecRestrict, FeatureSSBS, FeatureSB,
1308                                     FeaturePredRes, FeatureCacheDeepPersist,
1309                                     FeatureFullFP16, FeatureFP16FML, FeatureSHA3,
1310                                     FeatureAltFPCmp];
1311  list<SubtargetFeature> AppleA15 = [HasV8_6aOps, FeatureCrypto, FeatureFPARMv8,
1312                                     FeatureNEON, FeaturePerfMon, FeatureSHA3,
1313                                     FeatureFullFP16, FeatureFP16FML];
1314  list<SubtargetFeature> AppleA16 = [HasV8_6aOps, FeatureCrypto, FeatureFPARMv8,
1315                                     FeatureNEON, FeaturePerfMon, FeatureSHA3,
1316                                     FeatureFullFP16, FeatureFP16FML,
1317                                     FeatureHCX];
1318  list<SubtargetFeature> ExynosM3 = [HasV8_0aOps, FeatureCRC, FeatureCrypto,
1319                                     FeaturePerfMon];
1320  list<SubtargetFeature> ExynosM4 = [HasV8_2aOps, FeatureCrypto, FeatureDotProd,
1321                                     FeatureFullFP16, FeaturePerfMon];
1322  list<SubtargetFeature> Falkor   = [HasV8_0aOps, FeatureCRC, FeatureCrypto,
1323                                     FeatureFPARMv8, FeatureNEON, FeaturePerfMon,
1324                                     FeatureRDM];
1325  list<SubtargetFeature> NeoverseE1 = [HasV8_2aOps, FeatureCrypto, FeatureDotProd,
1326                                       FeatureFPARMv8, FeatureFullFP16, FeatureNEON,
1327                                       FeatureRCPC, FeatureSSBS, FeaturePerfMon];
1328  list<SubtargetFeature> NeoverseN1 = [HasV8_2aOps, FeatureCrypto, FeatureDotProd,
1329                                       FeatureFPARMv8, FeatureFullFP16, FeatureNEON,
1330                                       FeatureRCPC, FeatureSPE, FeatureSSBS,
1331                                       FeaturePerfMon];
1332  list<SubtargetFeature> NeoverseN2 = [HasV8_5aOps, FeatureBF16, FeatureETE,
1333                                       FeatureMatMulInt8, FeatureMTE, FeatureSVE2,
1334                                       FeatureSVE2BitPerm, FeatureTRBE, FeatureCrypto,
1335                                       FeaturePerfMon];
1336  list<SubtargetFeature> Neoverse512TVB = [HasV8_4aOps, FeatureBF16, FeatureCacheDeepPersist,
1337                                           FeatureCrypto, FeatureFPARMv8, FeatureFP16FML,
1338                                           FeatureFullFP16, FeatureMatMulInt8, FeatureNEON,
1339                                           FeaturePerfMon, FeatureRandGen, FeatureSPE,
1340                                           FeatureSSBS, FeatureSVE];
1341  list<SubtargetFeature> NeoverseV1 = [HasV8_4aOps, FeatureBF16, FeatureCacheDeepPersist,
1342                                       FeatureCrypto, FeatureFPARMv8, FeatureFP16FML,
1343                                       FeatureFullFP16, FeatureMatMulInt8, FeatureNEON,
1344                                       FeaturePerfMon, FeatureRandGen, FeatureSPE,
1345                                       FeatureSSBS, FeatureSVE];
1346  list<SubtargetFeature> NeoverseV2 = [HasV9_0aOps, FeatureBF16, FeatureSPE,
1347                                       FeaturePerfMon, FeatureETE, FeatureMatMulInt8,
1348                                       FeatureNEON, FeatureSVE2BitPerm, FeatureFP16FML,
1349                                       FeatureMTE, FeatureRandGen];
1350  list<SubtargetFeature> Saphira    = [HasV8_4aOps, FeatureCrypto, FeatureFPARMv8,
1351                                       FeatureNEON, FeatureSPE, FeaturePerfMon];
1352  list<SubtargetFeature> ThunderX   = [HasV8_0aOps, FeatureCRC, FeatureCrypto,
1353                                       FeatureFPARMv8, FeaturePerfMon, FeatureNEON];
1354  list<SubtargetFeature> ThunderX2T99  = [HasV8_1aOps, FeatureCRC, FeatureCrypto,
1355                                          FeatureFPARMv8, FeatureNEON, FeatureLSE];
1356  list<SubtargetFeature> ThunderX3T110 = [HasV8_3aOps, FeatureCRC, FeatureCrypto,
1357                                          FeatureFPARMv8, FeatureNEON, FeatureLSE,
1358                                          FeaturePAuth, FeaturePerfMon];
1359  list<SubtargetFeature> TSV110 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
1360                                   FeatureNEON, FeaturePerfMon, FeatureSPE,
1361                                   FeatureFullFP16, FeatureFP16FML, FeatureDotProd];
1362  list<SubtargetFeature> Ampere1 = [HasV8_6aOps, FeatureNEON, FeaturePerfMon,
1363                                    FeatureSSBS, FeatureRandGen, FeatureSB,
1364                                    FeatureSHA2, FeatureSHA3, FeatureAES];
1365  list<SubtargetFeature> Ampere1A = [HasV8_6aOps, FeatureNEON, FeaturePerfMon,
1366                                     FeatureMTE, FeatureSSBS, FeatureRandGen,
1367                                     FeatureSB, FeatureSM4, FeatureSHA2,
1368                                     FeatureSHA3, FeatureAES];
1369
1370  // ETE and TRBE are future architecture extensions. We temporarily enable them
1371  // by default for users targeting generic AArch64. The extensions do not
1372  // affect code generated by the compiler and can be used only by explicitly
1373  // mentioning the new system register names in assembly.
1374  list<SubtargetFeature> Generic = [FeatureFPARMv8, FeatureNEON, FeatureETE];
1375}
1376
1377// FeatureFuseAdrpAdd is enabled under Generic to allow linker merging
1378// optimizations.
1379def : ProcessorModel<"generic", CortexA55Model, ProcessorFeatures.Generic,
1380                     [FeatureFuseAES, FeatureFuseAdrpAdd, FeaturePostRAScheduler,
1381                      FeatureEnableSelectOptimize]>;
1382def : ProcessorModel<"cortex-a35", CortexA53Model, ProcessorFeatures.A53,
1383                     [TuneA35]>;
1384def : ProcessorModel<"cortex-a34", CortexA53Model, ProcessorFeatures.A53,
1385                     [TuneA35]>;
1386def : ProcessorModel<"cortex-a53", CortexA53Model, ProcessorFeatures.A53,
1387                     [TuneA53]>;
1388def : ProcessorModel<"cortex-a55", CortexA55Model, ProcessorFeatures.A55,
1389                     [TuneA55]>;
1390def : ProcessorModel<"cortex-a510", CortexA510Model, ProcessorFeatures.A510,
1391                     [TuneA510]>;
1392def : ProcessorModel<"cortex-a57", CortexA57Model, ProcessorFeatures.A53,
1393                     [TuneA57]>;
1394def : ProcessorModel<"cortex-a65", CortexA53Model, ProcessorFeatures.A65,
1395                     [TuneA65]>;
1396def : ProcessorModel<"cortex-a65ae", CortexA53Model, ProcessorFeatures.A65,
1397                     [TuneA65]>;
1398def : ProcessorModel<"cortex-a72", CortexA57Model, ProcessorFeatures.A53,
1399                     [TuneA72]>;
1400def : ProcessorModel<"cortex-a73", CortexA57Model, ProcessorFeatures.A53,
1401                     [TuneA73]>;
1402def : ProcessorModel<"cortex-a75", CortexA57Model, ProcessorFeatures.A55,
1403                     [TuneA75]>;
1404def : ProcessorModel<"cortex-a76", CortexA57Model, ProcessorFeatures.A76,
1405                     [TuneA76]>;
1406def : ProcessorModel<"cortex-a76ae", CortexA57Model, ProcessorFeatures.A76,
1407                     [TuneA76]>;
1408def : ProcessorModel<"cortex-a77", CortexA57Model, ProcessorFeatures.A77,
1409                     [TuneA77]>;
1410def : ProcessorModel<"cortex-a78", CortexA57Model, ProcessorFeatures.A78,
1411                     [TuneA78]>;
1412def : ProcessorModel<"cortex-a78c", CortexA57Model, ProcessorFeatures.A78C,
1413                     [TuneA78C]>;
1414def : ProcessorModel<"cortex-a710", NeoverseN2Model, ProcessorFeatures.A710,
1415                     [TuneA710]>;
1416def : ProcessorModel<"cortex-a715", NeoverseN2Model, ProcessorFeatures.A715,
1417                     [TuneA715]>;
1418def : ProcessorModel<"cortex-r82", CortexA55Model, ProcessorFeatures.R82,
1419                     [TuneR82]>;
1420def : ProcessorModel<"cortex-x1", CortexA57Model, ProcessorFeatures.X1,
1421                     [TuneX1]>;
1422def : ProcessorModel<"cortex-x1c", CortexA57Model, ProcessorFeatures.X1C,
1423                     [TuneX1]>;
1424def : ProcessorModel<"cortex-x2", NeoverseN2Model, ProcessorFeatures.X2,
1425                     [TuneX2]>;
1426def : ProcessorModel<"cortex-x3", NeoverseN2Model, ProcessorFeatures.X3,
1427                     [TuneX3]>;
1428def : ProcessorModel<"neoverse-e1", CortexA53Model,
1429                     ProcessorFeatures.NeoverseE1, [TuneNeoverseE1]>;
1430def : ProcessorModel<"neoverse-n1", NeoverseN1Model,
1431                     ProcessorFeatures.NeoverseN1, [TuneNeoverseN1]>;
1432def : ProcessorModel<"neoverse-n2", NeoverseN2Model,
1433                     ProcessorFeatures.NeoverseN2, [TuneNeoverseN2]>;
1434def : ProcessorModel<"neoverse-512tvb", NeoverseV1Model,
1435                     ProcessorFeatures.Neoverse512TVB, [TuneNeoverse512TVB]>;
1436def : ProcessorModel<"neoverse-v1", NeoverseV1Model,
1437                     ProcessorFeatures.NeoverseV1, [TuneNeoverseV1]>;
1438def : ProcessorModel<"neoverse-v2", NeoverseV2Model,
1439                     ProcessorFeatures.NeoverseV2, [TuneNeoverseV2]>;
1440def : ProcessorModel<"exynos-m3", ExynosM3Model, ProcessorFeatures.ExynosM3,
1441                     [TuneExynosM3]>;
1442def : ProcessorModel<"exynos-m4", ExynosM4Model, ProcessorFeatures.ExynosM4,
1443                     [TuneExynosM4]>;
1444def : ProcessorModel<"exynos-m5", ExynosM5Model, ProcessorFeatures.ExynosM4,
1445                     [TuneExynosM4]>;
1446def : ProcessorModel<"falkor", FalkorModel, ProcessorFeatures.Falkor,
1447                     [TuneFalkor]>;
1448def : ProcessorModel<"saphira", FalkorModel, ProcessorFeatures.Saphira,
1449                     [TuneSaphira]>;
1450def : ProcessorModel<"kryo", KryoModel, ProcessorFeatures.A53, [TuneKryo]>;
1451
1452// Cavium ThunderX/ThunderX T8X  Processors
1453def : ProcessorModel<"thunderx", ThunderXT8XModel,  ProcessorFeatures.ThunderX,
1454                     [TuneThunderX]>;
1455def : ProcessorModel<"thunderxt88", ThunderXT8XModel,
1456                     ProcessorFeatures.ThunderX, [TuneThunderXT88]>;
1457def : ProcessorModel<"thunderxt81", ThunderXT8XModel,
1458                     ProcessorFeatures.ThunderX, [TuneThunderXT81]>;
1459def : ProcessorModel<"thunderxt83", ThunderXT8XModel,
1460                     ProcessorFeatures.ThunderX, [TuneThunderXT83]>;
1461// Cavium ThunderX2T9X  Processors. Formerly Broadcom Vulcan.
1462def : ProcessorModel<"thunderx2t99", ThunderX2T99Model,
1463                     ProcessorFeatures.ThunderX2T99, [TuneThunderX2T99]>;
1464// Marvell ThunderX3T110 Processors.
1465def : ProcessorModel<"thunderx3t110", ThunderX3T110Model,
1466                     ProcessorFeatures.ThunderX3T110, [TuneThunderX3T110]>;
1467def : ProcessorModel<"tsv110", TSV110Model, ProcessorFeatures.TSV110,
1468                     [TuneTSV110]>;
1469
1470// Support cyclone as an alias for apple-a7 so we can still LTO old bitcode.
1471def : ProcessorModel<"cyclone", CycloneModel, ProcessorFeatures.AppleA7,
1472                     [TuneAppleA7]>;
1473
1474// iPhone and iPad CPUs
1475def : ProcessorModel<"apple-a7", CycloneModel, ProcessorFeatures.AppleA7,
1476                     [TuneAppleA7]>;
1477def : ProcessorModel<"apple-a8", CycloneModel, ProcessorFeatures.AppleA7,
1478                     [TuneAppleA7]>;
1479def : ProcessorModel<"apple-a9", CycloneModel, ProcessorFeatures.AppleA7,
1480                     [TuneAppleA7]>;
1481def : ProcessorModel<"apple-a10", CycloneModel, ProcessorFeatures.AppleA10,
1482                     [TuneAppleA10]>;
1483def : ProcessorModel<"apple-a11", CycloneModel, ProcessorFeatures.AppleA11,
1484                     [TuneAppleA11]>;
1485def : ProcessorModel<"apple-a12", CycloneModel, ProcessorFeatures.AppleA12,
1486                     [TuneAppleA12]>;
1487def : ProcessorModel<"apple-a13", CycloneModel, ProcessorFeatures.AppleA13,
1488                     [TuneAppleA13]>;
1489def : ProcessorModel<"apple-a14", CycloneModel, ProcessorFeatures.AppleA14,
1490                     [TuneAppleA14]>;
1491def : ProcessorModel<"apple-a15", CycloneModel, ProcessorFeatures.AppleA15,
1492                     [TuneAppleA15]>;
1493def : ProcessorModel<"apple-a16", CycloneModel, ProcessorFeatures.AppleA16,
1494                     [TuneAppleA16]>;
1495
1496// Mac CPUs
1497def : ProcessorModel<"apple-m1", CycloneModel, ProcessorFeatures.AppleA14,
1498                     [TuneAppleA14]>;
1499def : ProcessorModel<"apple-m2", CycloneModel, ProcessorFeatures.AppleA15,
1500                     [TuneAppleA15]>;
1501
1502// watch CPUs.
1503def : ProcessorModel<"apple-s4", CycloneModel, ProcessorFeatures.AppleA12,
1504                     [TuneAppleA12]>;
1505def : ProcessorModel<"apple-s5", CycloneModel, ProcessorFeatures.AppleA12,
1506                     [TuneAppleA12]>;
1507
1508// Alias for the latest Apple processor model supported by LLVM.
1509def : ProcessorModel<"apple-latest", CycloneModel, ProcessorFeatures.AppleA16,
1510                     [TuneAppleA16]>;
1511
1512// Fujitsu A64FX
1513def : ProcessorModel<"a64fx", A64FXModel, ProcessorFeatures.A64FX,
1514                     [TuneA64FX]>;
1515
1516// Nvidia Carmel
1517def : ProcessorModel<"carmel", NoSchedModel, ProcessorFeatures.Carmel,
1518                     [TuneCarmel]>;
1519
1520// Ampere Computing
1521def : ProcessorModel<"ampere1", Ampere1Model, ProcessorFeatures.Ampere1,
1522                     [TuneAmpere1]>;
1523
1524def : ProcessorModel<"ampere1a", Ampere1Model, ProcessorFeatures.Ampere1A,
1525                     [TuneAmpere1A]>;
1526
1527//===----------------------------------------------------------------------===//
1528// Assembly parser
1529//===----------------------------------------------------------------------===//
1530
1531def GenericAsmParserVariant : AsmParserVariant {
1532  int Variant = 0;
1533  string Name = "generic";
1534  string BreakCharacters = ".";
1535  string TokenizingCharacters = "[]*!/";
1536}
1537
1538def AppleAsmParserVariant : AsmParserVariant {
1539  int Variant = 1;
1540  string Name = "apple-neon";
1541  string BreakCharacters = ".";
1542  string TokenizingCharacters = "[]*!/";
1543}
1544
1545//===----------------------------------------------------------------------===//
1546// Assembly printer
1547//===----------------------------------------------------------------------===//
1548// AArch64 Uses the MC printer for asm output, so make sure the TableGen
1549// AsmWriter bits get associated with the correct class.
1550def GenericAsmWriter : AsmWriter {
1551  string AsmWriterClassName  = "InstPrinter";
1552  int PassSubtarget = 1;
1553  int Variant = 0;
1554  bit isMCAsmWriter = 1;
1555}
1556
1557def AppleAsmWriter : AsmWriter {
1558  let AsmWriterClassName = "AppleInstPrinter";
1559  int PassSubtarget = 1;
1560  int Variant = 1;
1561  int isMCAsmWriter = 1;
1562}
1563
1564//===----------------------------------------------------------------------===//
1565// Target Declaration
1566//===----------------------------------------------------------------------===//
1567
1568def AArch64 : Target {
1569  let InstructionSet = AArch64InstrInfo;
1570  let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant];
1571  let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter];
1572  let AllowRegisterRenaming = 1;
1573}
1574
1575//===----------------------------------------------------------------------===//
1576// Pfm Counters
1577//===----------------------------------------------------------------------===//
1578
1579include "AArch64PfmCounters.td"
1580