1//=- AArch64InstrInfo.td - Describe the AArch64 Instructions -*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// AArch64 Instruction definitions. 10// 11//===----------------------------------------------------------------------===// 12 13//===----------------------------------------------------------------------===// 14// ARM Instruction Predicate Definitions. 15// 16def HasV8_1a : Predicate<"Subtarget->hasV8_1aOps()">, 17 AssemblerPredicate<(all_of HasV8_1aOps), "armv8.1a">; 18def HasV8_2a : Predicate<"Subtarget->hasV8_2aOps()">, 19 AssemblerPredicate<(all_of HasV8_2aOps), "armv8.2a">; 20def HasV8_3a : Predicate<"Subtarget->hasV8_3aOps()">, 21 AssemblerPredicate<(all_of HasV8_3aOps), "armv8.3a">; 22def HasV8_4a : Predicate<"Subtarget->hasV8_4aOps()">, 23 AssemblerPredicate<(all_of HasV8_4aOps), "armv8.4a">; 24def HasV8_5a : Predicate<"Subtarget->hasV8_5aOps()">, 25 AssemblerPredicate<(all_of HasV8_5aOps), "armv8.5a">; 26def HasV8_6a : Predicate<"Subtarget->hasV8_6aOps()">, 27 AssemblerPredicate<(all_of HasV8_6aOps), "armv8.6a">; 28def HasV8_7a : Predicate<"Subtarget->hasV8_7aOps()">, 29 AssemblerPredicate<(all_of HasV8_7aOps), "armv8.7a">; 30def HasVH : Predicate<"Subtarget->hasVH()">, 31 AssemblerPredicate<(all_of FeatureVH), "vh">; 32 33def HasLOR : Predicate<"Subtarget->hasLOR()">, 34 AssemblerPredicate<(all_of FeatureLOR), "lor">; 35 36def HasPAuth : Predicate<"Subtarget->hasPAuth()">, 37 AssemblerPredicate<(all_of FeaturePAuth), "pauth">; 38 39def HasJS : Predicate<"Subtarget->hasJS()">, 40 AssemblerPredicate<(all_of FeatureJS), "jsconv">; 41 42def HasCCIDX : Predicate<"Subtarget->hasCCIDX()">, 43 AssemblerPredicate<(all_of FeatureCCIDX), "ccidx">; 44 45def HasComplxNum : Predicate<"Subtarget->hasComplxNum()">, 46 AssemblerPredicate<(all_of FeatureComplxNum), "complxnum">; 47 48def HasNV : Predicate<"Subtarget->hasNV()">, 49 AssemblerPredicate<(all_of FeatureNV), "nv">; 50 51def HasMPAM : Predicate<"Subtarget->hasMPAM()">, 52 AssemblerPredicate<(all_of FeatureMPAM), "mpam">; 53 54def HasDIT : Predicate<"Subtarget->hasDIT()">, 55 AssemblerPredicate<(all_of FeatureDIT), "dit">; 56 57def HasTRACEV8_4 : Predicate<"Subtarget->hasTRACEV8_4()">, 58 AssemblerPredicate<(all_of FeatureTRACEV8_4), "tracev8.4">; 59 60def HasAM : Predicate<"Subtarget->hasAM()">, 61 AssemblerPredicate<(all_of FeatureAM), "am">; 62 63def HasSEL2 : Predicate<"Subtarget->hasSEL2()">, 64 AssemblerPredicate<(all_of FeatureSEL2), "sel2">; 65 66def HasPMU : Predicate<"Subtarget->hasPMU()">, 67 AssemblerPredicate<(all_of FeaturePMU), "pmu">; 68 69def HasTLB_RMI : Predicate<"Subtarget->hasTLB_RMI()">, 70 AssemblerPredicate<(all_of FeatureTLB_RMI), "tlb-rmi">; 71 72def HasFlagM : Predicate<"Subtarget->hasFlagM()">, 73 AssemblerPredicate<(all_of FeatureFlagM), "flagm">; 74 75def HasRCPC_IMMO : Predicate<"Subtarget->hasRCPCImm()">, 76 AssemblerPredicate<(all_of FeatureRCPC_IMMO), "rcpc-immo">; 77 78def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">, 79 AssemblerPredicate<(all_of FeatureFPARMv8), "fp-armv8">; 80def HasNEON : Predicate<"Subtarget->hasNEON()">, 81 AssemblerPredicate<(all_of FeatureNEON), "neon">; 82def HasCrypto : Predicate<"Subtarget->hasCrypto()">, 83 AssemblerPredicate<(all_of FeatureCrypto), "crypto">; 84def HasSM4 : Predicate<"Subtarget->hasSM4()">, 85 AssemblerPredicate<(all_of FeatureSM4), "sm4">; 86def HasSHA3 : Predicate<"Subtarget->hasSHA3()">, 87 AssemblerPredicate<(all_of FeatureSHA3), "sha3">; 88def HasSHA2 : Predicate<"Subtarget->hasSHA2()">, 89 AssemblerPredicate<(all_of FeatureSHA2), "sha2">; 90def HasAES : Predicate<"Subtarget->hasAES()">, 91 AssemblerPredicate<(all_of FeatureAES), "aes">; 92def HasDotProd : Predicate<"Subtarget->hasDotProd()">, 93 AssemblerPredicate<(all_of FeatureDotProd), "dotprod">; 94def HasCRC : Predicate<"Subtarget->hasCRC()">, 95 AssemblerPredicate<(all_of FeatureCRC), "crc">; 96def HasLSE : Predicate<"Subtarget->hasLSE()">, 97 AssemblerPredicate<(all_of FeatureLSE), "lse">; 98def HasNoLSE : Predicate<"!Subtarget->hasLSE()">; 99def HasRAS : Predicate<"Subtarget->hasRAS()">, 100 AssemblerPredicate<(all_of FeatureRAS), "ras">; 101def HasRDM : Predicate<"Subtarget->hasRDM()">, 102 AssemblerPredicate<(all_of FeatureRDM), "rdm">; 103def HasPerfMon : Predicate<"Subtarget->hasPerfMon()">; 104def HasFullFP16 : Predicate<"Subtarget->hasFullFP16()">, 105 AssemblerPredicate<(all_of FeatureFullFP16), "fullfp16">; 106def HasFP16FML : Predicate<"Subtarget->hasFP16FML()">, 107 AssemblerPredicate<(all_of FeatureFP16FML), "fp16fml">; 108def HasSPE : Predicate<"Subtarget->hasSPE()">, 109 AssemblerPredicate<(all_of FeatureSPE), "spe">; 110def HasFuseAES : Predicate<"Subtarget->hasFuseAES()">, 111 AssemblerPredicate<(all_of FeatureFuseAES), 112 "fuse-aes">; 113def HasSVE : Predicate<"Subtarget->hasSVE()">, 114 AssemblerPredicate<(all_of FeatureSVE), "sve">; 115def HasSVE2 : Predicate<"Subtarget->hasSVE2()">, 116 AssemblerPredicate<(all_of FeatureSVE2), "sve2">; 117def HasSVE2AES : Predicate<"Subtarget->hasSVE2AES()">, 118 AssemblerPredicate<(all_of FeatureSVE2AES), "sve2-aes">; 119def HasSVE2SM4 : Predicate<"Subtarget->hasSVE2SM4()">, 120 AssemblerPredicate<(all_of FeatureSVE2SM4), "sve2-sm4">; 121def HasSVE2SHA3 : Predicate<"Subtarget->hasSVE2SHA3()">, 122 AssemblerPredicate<(all_of FeatureSVE2SHA3), "sve2-sha3">; 123def HasSVE2BitPerm : Predicate<"Subtarget->hasSVE2BitPerm()">, 124 AssemblerPredicate<(all_of FeatureSVE2BitPerm), "sve2-bitperm">; 125def HasSME : Predicate<"Subtarget->hasSME()">, 126 AssemblerPredicate<(all_of FeatureSME), "sme">; 127def HasSMEF64 : Predicate<"Subtarget->hasSMEF64()">, 128 AssemblerPredicate<(all_of FeatureSMEF64), "sme-f64">; 129def HasSMEI64 : Predicate<"Subtarget->hasSMEI64()">, 130 AssemblerPredicate<(all_of FeatureSMEI64), "sme-i64">; 131def HasRCPC : Predicate<"Subtarget->hasRCPC()">, 132 AssemblerPredicate<(all_of FeatureRCPC), "rcpc">; 133def HasAltNZCV : Predicate<"Subtarget->hasAlternativeNZCV()">, 134 AssemblerPredicate<(all_of FeatureAltFPCmp), "altnzcv">; 135def HasFRInt3264 : Predicate<"Subtarget->hasFRInt3264()">, 136 AssemblerPredicate<(all_of FeatureFRInt3264), "frint3264">; 137def HasSB : Predicate<"Subtarget->hasSB()">, 138 AssemblerPredicate<(all_of FeatureSB), "sb">; 139def HasPredRes : Predicate<"Subtarget->hasPredRes()">, 140 AssemblerPredicate<(all_of FeaturePredRes), "predres">; 141def HasCCDP : Predicate<"Subtarget->hasCCDP()">, 142 AssemblerPredicate<(all_of FeatureCacheDeepPersist), "ccdp">; 143def HasBTI : Predicate<"Subtarget->hasBTI()">, 144 AssemblerPredicate<(all_of FeatureBranchTargetId), "bti">; 145def HasMTE : Predicate<"Subtarget->hasMTE()">, 146 AssemblerPredicate<(all_of FeatureMTE), "mte">; 147def HasTME : Predicate<"Subtarget->hasTME()">, 148 AssemblerPredicate<(all_of FeatureTME), "tme">; 149def HasETE : Predicate<"Subtarget->hasETE()">, 150 AssemblerPredicate<(all_of FeatureETE), "ete">; 151def HasTRBE : Predicate<"Subtarget->hasTRBE()">, 152 AssemblerPredicate<(all_of FeatureTRBE), "trbe">; 153def HasBF16 : Predicate<"Subtarget->hasBF16()">, 154 AssemblerPredicate<(all_of FeatureBF16), "bf16">; 155def HasMatMulInt8 : Predicate<"Subtarget->hasMatMulInt8()">, 156 AssemblerPredicate<(all_of FeatureMatMulInt8), "i8mm">; 157def HasMatMulFP32 : Predicate<"Subtarget->hasMatMulFP32()">, 158 AssemblerPredicate<(all_of FeatureMatMulFP32), "f32mm">; 159def HasMatMulFP64 : Predicate<"Subtarget->hasMatMulFP64()">, 160 AssemblerPredicate<(all_of FeatureMatMulFP64), "f64mm">; 161def HasXS : Predicate<"Subtarget->hasXS()">, 162 AssemblerPredicate<(all_of FeatureXS), "xs">; 163def HasWFxT : Predicate<"Subtarget->hasWFxT()">, 164 AssemblerPredicate<(all_of FeatureWFxT), "wfxt">; 165def HasLS64 : Predicate<"Subtarget->hasLS64()">, 166 AssemblerPredicate<(all_of FeatureLS64), "ls64">; 167def HasBRBE : Predicate<"Subtarget->hasBRBE()">, 168 AssemblerPredicate<(all_of FeatureBRBE), "brbe">; 169def HasSPE_EEF : Predicate<"Subtarget->hasSPE_EEF()">, 170 AssemblerPredicate<(all_of FeatureSPE_EEF), "spe-eef">; 171def IsLE : Predicate<"Subtarget->isLittleEndian()">; 172def IsBE : Predicate<"!Subtarget->isLittleEndian()">; 173def IsWindows : Predicate<"Subtarget->isTargetWindows()">; 174def UseExperimentalZeroingPseudos 175 : Predicate<"Subtarget->useExperimentalZeroingPseudos()">; 176def UseAlternateSExtLoadCVTF32 177 : Predicate<"Subtarget->useAlternateSExtLoadCVTF32Pattern()">; 178 179def UseNegativeImmediates 180 : Predicate<"false">, AssemblerPredicate<(all_of (not FeatureNoNegativeImmediates)), 181 "NegativeImmediates">; 182 183def AArch64LocalRecover : SDNode<"ISD::LOCAL_RECOVER", 184 SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, 185 SDTCisInt<1>]>>; 186 187 188//===----------------------------------------------------------------------===// 189// AArch64-specific DAG Nodes. 190// 191 192// SDTBinaryArithWithFlagsOut - RES1, FLAGS = op LHS, RHS 193def SDTBinaryArithWithFlagsOut : SDTypeProfile<2, 2, 194 [SDTCisSameAs<0, 2>, 195 SDTCisSameAs<0, 3>, 196 SDTCisInt<0>, SDTCisVT<1, i32>]>; 197 198// SDTBinaryArithWithFlagsIn - RES1, FLAGS = op LHS, RHS, FLAGS 199def SDTBinaryArithWithFlagsIn : SDTypeProfile<1, 3, 200 [SDTCisSameAs<0, 1>, 201 SDTCisSameAs<0, 2>, 202 SDTCisInt<0>, 203 SDTCisVT<3, i32>]>; 204 205// SDTBinaryArithWithFlagsInOut - RES1, FLAGS = op LHS, RHS, FLAGS 206def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3, 207 [SDTCisSameAs<0, 2>, 208 SDTCisSameAs<0, 3>, 209 SDTCisInt<0>, 210 SDTCisVT<1, i32>, 211 SDTCisVT<4, i32>]>; 212 213def SDT_AArch64Brcond : SDTypeProfile<0, 3, 214 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>, 215 SDTCisVT<2, i32>]>; 216def SDT_AArch64cbz : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisVT<1, OtherVT>]>; 217def SDT_AArch64tbz : SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisInt<1>, 218 SDTCisVT<2, OtherVT>]>; 219 220 221def SDT_AArch64CSel : SDTypeProfile<1, 4, 222 [SDTCisSameAs<0, 1>, 223 SDTCisSameAs<0, 2>, 224 SDTCisInt<3>, 225 SDTCisVT<4, i32>]>; 226def SDT_AArch64CCMP : SDTypeProfile<1, 5, 227 [SDTCisVT<0, i32>, 228 SDTCisInt<1>, 229 SDTCisSameAs<1, 2>, 230 SDTCisInt<3>, 231 SDTCisInt<4>, 232 SDTCisVT<5, i32>]>; 233def SDT_AArch64FCCMP : SDTypeProfile<1, 5, 234 [SDTCisVT<0, i32>, 235 SDTCisFP<1>, 236 SDTCisSameAs<1, 2>, 237 SDTCisInt<3>, 238 SDTCisInt<4>, 239 SDTCisVT<5, i32>]>; 240def SDT_AArch64FCmp : SDTypeProfile<0, 2, 241 [SDTCisFP<0>, 242 SDTCisSameAs<0, 1>]>; 243def SDT_AArch64Dup : SDTypeProfile<1, 1, [SDTCisVec<0>]>; 244def SDT_AArch64DupLane : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<2>]>; 245def SDT_AArch64Insr : SDTypeProfile<1, 2, [SDTCisVec<0>]>; 246def SDT_AArch64Zip : SDTypeProfile<1, 2, [SDTCisVec<0>, 247 SDTCisSameAs<0, 1>, 248 SDTCisSameAs<0, 2>]>; 249def SDT_AArch64MOVIedit : SDTypeProfile<1, 1, [SDTCisInt<1>]>; 250def SDT_AArch64MOVIshift : SDTypeProfile<1, 2, [SDTCisInt<1>, SDTCisInt<2>]>; 251def SDT_AArch64vecimm : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>, 252 SDTCisInt<2>, SDTCisInt<3>]>; 253def SDT_AArch64UnaryVec: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>; 254def SDT_AArch64ExtVec: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>, 255 SDTCisSameAs<0,2>, SDTCisInt<3>]>; 256def SDT_AArch64vshift : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>, SDTCisInt<2>]>; 257def SDT_AArch64Dot: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>, 258 SDTCisVec<2>, SDTCisSameAs<2,3>]>; 259 260def SDT_AArch64vshiftinsert : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisInt<3>, 261 SDTCisSameAs<0,1>, 262 SDTCisSameAs<0,2>]>; 263 264def SDT_AArch64unvec : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>; 265def SDT_AArch64fcmpz : SDTypeProfile<1, 1, []>; 266def SDT_AArch64fcmp : SDTypeProfile<1, 2, [SDTCisSameAs<1,2>]>; 267def SDT_AArch64binvec : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, 268 SDTCisSameAs<0,2>]>; 269def SDT_AArch64trivec : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>, 270 SDTCisSameAs<0,2>, 271 SDTCisSameAs<0,3>]>; 272def SDT_AArch64TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>]>; 273def SDT_AArch64PREFETCH : SDTypeProfile<0, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<1>]>; 274 275def SDT_AArch64ITOF : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>; 276 277def SDT_AArch64TLSDescCall : SDTypeProfile<0, -2, [SDTCisPtrTy<0>, 278 SDTCisPtrTy<1>]>; 279 280def SDT_AArch64uaddlp : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>]>; 281 282def SDT_AArch64ldp : SDTypeProfile<2, 1, [SDTCisVT<0, i64>, SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>; 283def SDT_AArch64stp : SDTypeProfile<0, 3, [SDTCisVT<0, i64>, SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>; 284def SDT_AArch64stnp : SDTypeProfile<0, 3, [SDTCisVT<0, v4i32>, SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>; 285 286// Generates the general dynamic sequences, i.e. 287// adrp x0, :tlsdesc:var 288// ldr x1, [x0, #:tlsdesc_lo12:var] 289// add x0, x0, #:tlsdesc_lo12:var 290// .tlsdesccall var 291// blr x1 292 293// (the TPIDR_EL0 offset is put directly in X0, hence no "result" here) 294// number of operands (the variable) 295def SDT_AArch64TLSDescCallSeq : SDTypeProfile<0,1, 296 [SDTCisPtrTy<0>]>; 297 298def SDT_AArch64WrapperLarge : SDTypeProfile<1, 4, 299 [SDTCisVT<0, i64>, SDTCisVT<1, i32>, 300 SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>, 301 SDTCisSameAs<1, 4>]>; 302 303def SDT_AArch64TBL : SDTypeProfile<1, 2, [ 304 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisInt<2> 305]>; 306 307// non-extending masked load fragment. 308def nonext_masked_load : 309 PatFrag<(ops node:$ptr, node:$pred, node:$def), 310 (masked_ld node:$ptr, undef, node:$pred, node:$def), [{ 311 return cast<MaskedLoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD && 312 cast<MaskedLoadSDNode>(N)->isUnindexed() && 313 !cast<MaskedLoadSDNode>(N)->isNonTemporal(); 314}]>; 315// sign extending masked load fragments. 316def asext_masked_load : 317 PatFrag<(ops node:$ptr, node:$pred, node:$def), 318 (masked_ld node:$ptr, undef, node:$pred, node:$def),[{ 319 return (cast<MaskedLoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD || 320 cast<MaskedLoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD) && 321 cast<MaskedLoadSDNode>(N)->isUnindexed(); 322}]>; 323def asext_masked_load_i8 : 324 PatFrag<(ops node:$ptr, node:$pred, node:$def), 325 (asext_masked_load node:$ptr, node:$pred, node:$def), [{ 326 return cast<MaskedLoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8; 327}]>; 328def asext_masked_load_i16 : 329 PatFrag<(ops node:$ptr, node:$pred, node:$def), 330 (asext_masked_load node:$ptr, node:$pred, node:$def), [{ 331 return cast<MaskedLoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16; 332}]>; 333def asext_masked_load_i32 : 334 PatFrag<(ops node:$ptr, node:$pred, node:$def), 335 (asext_masked_load node:$ptr, node:$pred, node:$def), [{ 336 return cast<MaskedLoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32; 337}]>; 338// zero extending masked load fragments. 339def zext_masked_load : 340 PatFrag<(ops node:$ptr, node:$pred, node:$def), 341 (masked_ld node:$ptr, undef, node:$pred, node:$def), [{ 342 return cast<MaskedLoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD && 343 cast<MaskedLoadSDNode>(N)->isUnindexed(); 344}]>; 345def zext_masked_load_i8 : 346 PatFrag<(ops node:$ptr, node:$pred, node:$def), 347 (zext_masked_load node:$ptr, node:$pred, node:$def), [{ 348 return cast<MaskedLoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8; 349}]>; 350def zext_masked_load_i16 : 351 PatFrag<(ops node:$ptr, node:$pred, node:$def), 352 (zext_masked_load node:$ptr, node:$pred, node:$def), [{ 353 return cast<MaskedLoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16; 354}]>; 355def zext_masked_load_i32 : 356 PatFrag<(ops node:$ptr, node:$pred, node:$def), 357 (zext_masked_load node:$ptr, node:$pred, node:$def), [{ 358 return cast<MaskedLoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32; 359}]>; 360 361def non_temporal_load : 362 PatFrag<(ops node:$ptr, node:$pred, node:$def), 363 (masked_ld node:$ptr, undef, node:$pred, node:$def), [{ 364 return cast<MaskedLoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD && 365 cast<MaskedLoadSDNode>(N)->isUnindexed() && 366 cast<MaskedLoadSDNode>(N)->isNonTemporal(); 367}]>; 368 369// non-truncating masked store fragment. 370def nontrunc_masked_store : 371 PatFrag<(ops node:$val, node:$ptr, node:$pred), 372 (masked_st node:$val, node:$ptr, undef, node:$pred), [{ 373 return !cast<MaskedStoreSDNode>(N)->isTruncatingStore() && 374 cast<MaskedStoreSDNode>(N)->isUnindexed() && 375 !cast<MaskedStoreSDNode>(N)->isNonTemporal(); 376}]>; 377// truncating masked store fragments. 378def trunc_masked_store : 379 PatFrag<(ops node:$val, node:$ptr, node:$pred), 380 (masked_st node:$val, node:$ptr, undef, node:$pred), [{ 381 return cast<MaskedStoreSDNode>(N)->isTruncatingStore() && 382 cast<MaskedStoreSDNode>(N)->isUnindexed(); 383}]>; 384def trunc_masked_store_i8 : 385 PatFrag<(ops node:$val, node:$ptr, node:$pred), 386 (trunc_masked_store node:$val, node:$ptr, node:$pred), [{ 387 return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8; 388}]>; 389def trunc_masked_store_i16 : 390 PatFrag<(ops node:$val, node:$ptr, node:$pred), 391 (trunc_masked_store node:$val, node:$ptr, node:$pred), [{ 392 return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16; 393}]>; 394def trunc_masked_store_i32 : 395 PatFrag<(ops node:$val, node:$ptr, node:$pred), 396 (trunc_masked_store node:$val, node:$ptr, node:$pred), [{ 397 return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32; 398}]>; 399 400def non_temporal_store : 401 PatFrag<(ops node:$val, node:$ptr, node:$pred), 402 (masked_st node:$val, node:$ptr, undef, node:$pred), [{ 403 return !cast<MaskedStoreSDNode>(N)->isTruncatingStore() && 404 cast<MaskedStoreSDNode>(N)->isUnindexed() && 405 cast<MaskedStoreSDNode>(N)->isNonTemporal(); 406}]>; 407 408// Node definitions. 409def AArch64adrp : SDNode<"AArch64ISD::ADRP", SDTIntUnaryOp, []>; 410def AArch64adr : SDNode<"AArch64ISD::ADR", SDTIntUnaryOp, []>; 411def AArch64addlow : SDNode<"AArch64ISD::ADDlow", SDTIntBinOp, []>; 412def AArch64LOADgot : SDNode<"AArch64ISD::LOADgot", SDTIntUnaryOp>; 413def AArch64callseq_start : SDNode<"ISD::CALLSEQ_START", 414 SDCallSeqStart<[ SDTCisVT<0, i32>, 415 SDTCisVT<1, i32> ]>, 416 [SDNPHasChain, SDNPOutGlue]>; 417def AArch64callseq_end : SDNode<"ISD::CALLSEQ_END", 418 SDCallSeqEnd<[ SDTCisVT<0, i32>, 419 SDTCisVT<1, i32> ]>, 420 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 421def AArch64call : SDNode<"AArch64ISD::CALL", 422 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>, 423 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 424 SDNPVariadic]>; 425 426def AArch64call_rvmarker: SDNode<"AArch64ISD::CALL_RVMARKER", 427 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>, 428 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 429 SDNPVariadic]>; 430 431def AArch64brcond : SDNode<"AArch64ISD::BRCOND", SDT_AArch64Brcond, 432 [SDNPHasChain]>; 433def AArch64cbz : SDNode<"AArch64ISD::CBZ", SDT_AArch64cbz, 434 [SDNPHasChain]>; 435def AArch64cbnz : SDNode<"AArch64ISD::CBNZ", SDT_AArch64cbz, 436 [SDNPHasChain]>; 437def AArch64tbz : SDNode<"AArch64ISD::TBZ", SDT_AArch64tbz, 438 [SDNPHasChain]>; 439def AArch64tbnz : SDNode<"AArch64ISD::TBNZ", SDT_AArch64tbz, 440 [SDNPHasChain]>; 441 442 443def AArch64csel : SDNode<"AArch64ISD::CSEL", SDT_AArch64CSel>; 444def AArch64csinv : SDNode<"AArch64ISD::CSINV", SDT_AArch64CSel>; 445def AArch64csneg : SDNode<"AArch64ISD::CSNEG", SDT_AArch64CSel>; 446def AArch64csinc : SDNode<"AArch64ISD::CSINC", SDT_AArch64CSel>; 447def AArch64retflag : SDNode<"AArch64ISD::RET_FLAG", SDTNone, 448 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 449def AArch64adc : SDNode<"AArch64ISD::ADC", SDTBinaryArithWithFlagsIn >; 450def AArch64sbc : SDNode<"AArch64ISD::SBC", SDTBinaryArithWithFlagsIn>; 451def AArch64add_flag : SDNode<"AArch64ISD::ADDS", SDTBinaryArithWithFlagsOut, 452 [SDNPCommutative]>; 453def AArch64sub_flag : SDNode<"AArch64ISD::SUBS", SDTBinaryArithWithFlagsOut>; 454def AArch64and_flag : SDNode<"AArch64ISD::ANDS", SDTBinaryArithWithFlagsOut, 455 [SDNPCommutative]>; 456def AArch64adc_flag : SDNode<"AArch64ISD::ADCS", SDTBinaryArithWithFlagsInOut>; 457def AArch64sbc_flag : SDNode<"AArch64ISD::SBCS", SDTBinaryArithWithFlagsInOut>; 458 459def AArch64ccmp : SDNode<"AArch64ISD::CCMP", SDT_AArch64CCMP>; 460def AArch64ccmn : SDNode<"AArch64ISD::CCMN", SDT_AArch64CCMP>; 461def AArch64fccmp : SDNode<"AArch64ISD::FCCMP", SDT_AArch64FCCMP>; 462 463def AArch64threadpointer : SDNode<"AArch64ISD::THREAD_POINTER", SDTPtrLeaf>; 464 465def AArch64fcmp : SDNode<"AArch64ISD::FCMP", SDT_AArch64FCmp>; 466def AArch64strict_fcmp : SDNode<"AArch64ISD::STRICT_FCMP", SDT_AArch64FCmp, 467 [SDNPHasChain]>; 468def AArch64strict_fcmpe : SDNode<"AArch64ISD::STRICT_FCMPE", SDT_AArch64FCmp, 469 [SDNPHasChain]>; 470def AArch64any_fcmp : PatFrags<(ops node:$lhs, node:$rhs), 471 [(AArch64strict_fcmp node:$lhs, node:$rhs), 472 (AArch64fcmp node:$lhs, node:$rhs)]>; 473 474def AArch64dup : SDNode<"AArch64ISD::DUP", SDT_AArch64Dup>; 475def AArch64duplane8 : SDNode<"AArch64ISD::DUPLANE8", SDT_AArch64DupLane>; 476def AArch64duplane16 : SDNode<"AArch64ISD::DUPLANE16", SDT_AArch64DupLane>; 477def AArch64duplane32 : SDNode<"AArch64ISD::DUPLANE32", SDT_AArch64DupLane>; 478def AArch64duplane64 : SDNode<"AArch64ISD::DUPLANE64", SDT_AArch64DupLane>; 479 480def AArch64insr : SDNode<"AArch64ISD::INSR", SDT_AArch64Insr>; 481 482def AArch64zip1 : SDNode<"AArch64ISD::ZIP1", SDT_AArch64Zip>; 483def AArch64zip2 : SDNode<"AArch64ISD::ZIP2", SDT_AArch64Zip>; 484def AArch64uzp1 : SDNode<"AArch64ISD::UZP1", SDT_AArch64Zip>; 485def AArch64uzp2 : SDNode<"AArch64ISD::UZP2", SDT_AArch64Zip>; 486def AArch64trn1 : SDNode<"AArch64ISD::TRN1", SDT_AArch64Zip>; 487def AArch64trn2 : SDNode<"AArch64ISD::TRN2", SDT_AArch64Zip>; 488 489def AArch64movi_edit : SDNode<"AArch64ISD::MOVIedit", SDT_AArch64MOVIedit>; 490def AArch64movi_shift : SDNode<"AArch64ISD::MOVIshift", SDT_AArch64MOVIshift>; 491def AArch64movi_msl : SDNode<"AArch64ISD::MOVImsl", SDT_AArch64MOVIshift>; 492def AArch64mvni_shift : SDNode<"AArch64ISD::MVNIshift", SDT_AArch64MOVIshift>; 493def AArch64mvni_msl : SDNode<"AArch64ISD::MVNImsl", SDT_AArch64MOVIshift>; 494def AArch64movi : SDNode<"AArch64ISD::MOVI", SDT_AArch64MOVIedit>; 495def AArch64fmov : SDNode<"AArch64ISD::FMOV", SDT_AArch64MOVIedit>; 496 497def AArch64rev16 : SDNode<"AArch64ISD::REV16", SDT_AArch64UnaryVec>; 498def AArch64rev32 : SDNode<"AArch64ISD::REV32", SDT_AArch64UnaryVec>; 499def AArch64rev64 : SDNode<"AArch64ISD::REV64", SDT_AArch64UnaryVec>; 500def AArch64ext : SDNode<"AArch64ISD::EXT", SDT_AArch64ExtVec>; 501 502def AArch64vashr : SDNode<"AArch64ISD::VASHR", SDT_AArch64vshift>; 503def AArch64vlshr : SDNode<"AArch64ISD::VLSHR", SDT_AArch64vshift>; 504def AArch64vshl : SDNode<"AArch64ISD::VSHL", SDT_AArch64vshift>; 505def AArch64sqshli : SDNode<"AArch64ISD::SQSHL_I", SDT_AArch64vshift>; 506def AArch64uqshli : SDNode<"AArch64ISD::UQSHL_I", SDT_AArch64vshift>; 507def AArch64sqshlui : SDNode<"AArch64ISD::SQSHLU_I", SDT_AArch64vshift>; 508def AArch64srshri : SDNode<"AArch64ISD::SRSHR_I", SDT_AArch64vshift>; 509def AArch64urshri : SDNode<"AArch64ISD::URSHR_I", SDT_AArch64vshift>; 510def AArch64vsli : SDNode<"AArch64ISD::VSLI", SDT_AArch64vshiftinsert>; 511def AArch64vsri : SDNode<"AArch64ISD::VSRI", SDT_AArch64vshiftinsert>; 512 513def AArch64bit: SDNode<"AArch64ISD::BIT", SDT_AArch64trivec>; 514def AArch64bsp: SDNode<"AArch64ISD::BSP", SDT_AArch64trivec>; 515 516def AArch64cmeq: SDNode<"AArch64ISD::CMEQ", SDT_AArch64binvec>; 517def AArch64cmge: SDNode<"AArch64ISD::CMGE", SDT_AArch64binvec>; 518def AArch64cmgt: SDNode<"AArch64ISD::CMGT", SDT_AArch64binvec>; 519def AArch64cmhi: SDNode<"AArch64ISD::CMHI", SDT_AArch64binvec>; 520def AArch64cmhs: SDNode<"AArch64ISD::CMHS", SDT_AArch64binvec>; 521 522def AArch64fcmeq: SDNode<"AArch64ISD::FCMEQ", SDT_AArch64fcmp>; 523def AArch64fcmge: SDNode<"AArch64ISD::FCMGE", SDT_AArch64fcmp>; 524def AArch64fcmgt: SDNode<"AArch64ISD::FCMGT", SDT_AArch64fcmp>; 525 526def AArch64cmeqz: SDNode<"AArch64ISD::CMEQz", SDT_AArch64unvec>; 527def AArch64cmgez: SDNode<"AArch64ISD::CMGEz", SDT_AArch64unvec>; 528def AArch64cmgtz: SDNode<"AArch64ISD::CMGTz", SDT_AArch64unvec>; 529def AArch64cmlez: SDNode<"AArch64ISD::CMLEz", SDT_AArch64unvec>; 530def AArch64cmltz: SDNode<"AArch64ISD::CMLTz", SDT_AArch64unvec>; 531def AArch64cmtst : PatFrag<(ops node:$LHS, node:$RHS), 532 (vnot (AArch64cmeqz (and node:$LHS, node:$RHS)))>; 533 534def AArch64fcmeqz: SDNode<"AArch64ISD::FCMEQz", SDT_AArch64fcmpz>; 535def AArch64fcmgez: SDNode<"AArch64ISD::FCMGEz", SDT_AArch64fcmpz>; 536def AArch64fcmgtz: SDNode<"AArch64ISD::FCMGTz", SDT_AArch64fcmpz>; 537def AArch64fcmlez: SDNode<"AArch64ISD::FCMLEz", SDT_AArch64fcmpz>; 538def AArch64fcmltz: SDNode<"AArch64ISD::FCMLTz", SDT_AArch64fcmpz>; 539 540def AArch64bici: SDNode<"AArch64ISD::BICi", SDT_AArch64vecimm>; 541def AArch64orri: SDNode<"AArch64ISD::ORRi", SDT_AArch64vecimm>; 542 543def AArch64tcret: SDNode<"AArch64ISD::TC_RETURN", SDT_AArch64TCRET, 544 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 545 546def AArch64Prefetch : SDNode<"AArch64ISD::PREFETCH", SDT_AArch64PREFETCH, 547 [SDNPHasChain, SDNPSideEffect]>; 548 549def AArch64sitof: SDNode<"AArch64ISD::SITOF", SDT_AArch64ITOF>; 550def AArch64uitof: SDNode<"AArch64ISD::UITOF", SDT_AArch64ITOF>; 551 552def AArch64tlsdesc_callseq : SDNode<"AArch64ISD::TLSDESC_CALLSEQ", 553 SDT_AArch64TLSDescCallSeq, 554 [SDNPInGlue, SDNPOutGlue, SDNPHasChain, 555 SDNPVariadic]>; 556 557 558def AArch64WrapperLarge : SDNode<"AArch64ISD::WrapperLarge", 559 SDT_AArch64WrapperLarge>; 560 561def AArch64NvCast : SDNode<"AArch64ISD::NVCAST", SDTUnaryOp>; 562 563def SDT_AArch64mull : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>, 564 SDTCisSameAs<1, 2>]>; 565def AArch64smull : SDNode<"AArch64ISD::SMULL", SDT_AArch64mull>; 566def AArch64umull : SDNode<"AArch64ISD::UMULL", SDT_AArch64mull>; 567 568def AArch64frecpe : SDNode<"AArch64ISD::FRECPE", SDTFPUnaryOp>; 569def AArch64frecps : SDNode<"AArch64ISD::FRECPS", SDTFPBinOp>; 570def AArch64frsqrte : SDNode<"AArch64ISD::FRSQRTE", SDTFPUnaryOp>; 571def AArch64frsqrts : SDNode<"AArch64ISD::FRSQRTS", SDTFPBinOp>; 572 573def AArch64sdot : SDNode<"AArch64ISD::SDOT", SDT_AArch64Dot>; 574def AArch64udot : SDNode<"AArch64ISD::UDOT", SDT_AArch64Dot>; 575 576def AArch64saddv : SDNode<"AArch64ISD::SADDV", SDT_AArch64UnaryVec>; 577def AArch64uaddv : SDNode<"AArch64ISD::UADDV", SDT_AArch64UnaryVec>; 578def AArch64sminv : SDNode<"AArch64ISD::SMINV", SDT_AArch64UnaryVec>; 579def AArch64uminv : SDNode<"AArch64ISD::UMINV", SDT_AArch64UnaryVec>; 580def AArch64smaxv : SDNode<"AArch64ISD::SMAXV", SDT_AArch64UnaryVec>; 581def AArch64umaxv : SDNode<"AArch64ISD::UMAXV", SDT_AArch64UnaryVec>; 582 583def AArch64srhadd : SDNode<"AArch64ISD::SRHADD", SDT_AArch64binvec>; 584def AArch64urhadd : SDNode<"AArch64ISD::URHADD", SDT_AArch64binvec>; 585def AArch64shadd : SDNode<"AArch64ISD::SHADD", SDT_AArch64binvec>; 586def AArch64uhadd : SDNode<"AArch64ISD::UHADD", SDT_AArch64binvec>; 587 588def AArch64uabd : PatFrags<(ops node:$lhs, node:$rhs), 589 [(abdu node:$lhs, node:$rhs), 590 (int_aarch64_neon_uabd node:$lhs, node:$rhs)]>; 591def AArch64sabd : PatFrags<(ops node:$lhs, node:$rhs), 592 [(abds node:$lhs, node:$rhs), 593 (int_aarch64_neon_sabd node:$lhs, node:$rhs)]>; 594 595def AArch64uaddlp_n : SDNode<"AArch64ISD::UADDLP", SDT_AArch64uaddlp>; 596def AArch64uaddlp : PatFrags<(ops node:$src), 597 [(AArch64uaddlp_n node:$src), 598 (int_aarch64_neon_uaddlp node:$src)]>; 599 600def SDT_AArch64SETTAG : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>; 601def AArch64stg : SDNode<"AArch64ISD::STG", SDT_AArch64SETTAG, [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 602def AArch64stzg : SDNode<"AArch64ISD::STZG", SDT_AArch64SETTAG, [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 603def AArch64st2g : SDNode<"AArch64ISD::ST2G", SDT_AArch64SETTAG, [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 604def AArch64stz2g : SDNode<"AArch64ISD::STZ2G", SDT_AArch64SETTAG, [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 605 606def SDT_AArch64unpk : SDTypeProfile<1, 1, [ 607 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0> 608]>; 609def AArch64sunpkhi : SDNode<"AArch64ISD::SUNPKHI", SDT_AArch64unpk>; 610def AArch64sunpklo : SDNode<"AArch64ISD::SUNPKLO", SDT_AArch64unpk>; 611def AArch64uunpkhi : SDNode<"AArch64ISD::UUNPKHI", SDT_AArch64unpk>; 612def AArch64uunpklo : SDNode<"AArch64ISD::UUNPKLO", SDT_AArch64unpk>; 613 614def AArch64ldp : SDNode<"AArch64ISD::LDP", SDT_AArch64ldp, [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 615def AArch64stp : SDNode<"AArch64ISD::STP", SDT_AArch64stp, [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 616def AArch64stnp : SDNode<"AArch64ISD::STNP", SDT_AArch64stnp, [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 617 618def AArch64tbl : SDNode<"AArch64ISD::TBL", SDT_AArch64TBL>; 619def AArch64mrs : SDNode<"AArch64ISD::MRS", 620 SDTypeProfile<1, 1, [SDTCisVT<0, i64>, SDTCisVT<1, i32>]>, 621 [SDNPHasChain, SDNPOutGlue]>; 622//===----------------------------------------------------------------------===// 623 624//===----------------------------------------------------------------------===// 625 626// AArch64 Instruction Predicate Definitions. 627// We could compute these on a per-module basis but doing so requires accessing 628// the Function object through the <Target>Subtarget and objections were raised 629// to that (see post-commit review comments for r301750). 630let RecomputePerFunction = 1 in { 631 def ForCodeSize : Predicate<"shouldOptForSize(MF)">; 632 def NotForCodeSize : Predicate<"!shouldOptForSize(MF)">; 633 // Avoid generating STRQro if it is slow, unless we're optimizing for code size. 634 def UseSTRQro : Predicate<"!Subtarget->isSTRQroSlow() || shouldOptForSize(MF)">; 635 636 def UseBTI : Predicate<[{ MF->getInfo<AArch64FunctionInfo>()->branchTargetEnforcement() }]>; 637 def NotUseBTI : Predicate<[{ !MF->getInfo<AArch64FunctionInfo>()->branchTargetEnforcement() }]>; 638 639 def SLSBLRMitigation : Predicate<[{ MF->getSubtarget<AArch64Subtarget>().hardenSlsBlr() }]>; 640 def NoSLSBLRMitigation : Predicate<[{ !MF->getSubtarget<AArch64Subtarget>().hardenSlsBlr() }]>; 641 // Toggles patterns which aren't beneficial in GlobalISel when we aren't 642 // optimizing. This allows us to selectively use patterns without impacting 643 // SelectionDAG's behaviour. 644 // FIXME: One day there will probably be a nicer way to check for this, but 645 // today is not that day. 646 def OptimizedGISelOrOtherSelector : Predicate<"!MF->getFunction().hasOptNone() || MF->getProperties().hasProperty(MachineFunctionProperties::Property::FailedISel) || !MF->getProperties().hasProperty(MachineFunctionProperties::Property::Legalized)">; 647} 648 649include "AArch64InstrFormats.td" 650include "SVEInstrFormats.td" 651include "SMEInstrFormats.td" 652 653//===----------------------------------------------------------------------===// 654 655//===----------------------------------------------------------------------===// 656// Miscellaneous instructions. 657//===----------------------------------------------------------------------===// 658 659let Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1 in { 660// We set Sched to empty list because we expect these instructions to simply get 661// removed in most cases. 662def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 663 [(AArch64callseq_start timm:$amt1, timm:$amt2)]>, 664 Sched<[]>; 665def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 666 [(AArch64callseq_end timm:$amt1, timm:$amt2)]>, 667 Sched<[]>; 668} // Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1 669 670let isReMaterializable = 1, isCodeGenOnly = 1 in { 671// FIXME: The following pseudo instructions are only needed because remat 672// cannot handle multiple instructions. When that changes, they can be 673// removed, along with the AArch64Wrapper node. 674 675let AddedComplexity = 10 in 676def LOADgot : Pseudo<(outs GPR64:$dst), (ins i64imm:$addr), 677 [(set GPR64:$dst, (AArch64LOADgot tglobaladdr:$addr))]>, 678 Sched<[WriteLDAdr]>; 679 680// The MOVaddr instruction should match only when the add is not folded 681// into a load or store address. 682def MOVaddr 683 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low), 684 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tglobaladdr:$hi), 685 tglobaladdr:$low))]>, 686 Sched<[WriteAdrAdr]>; 687def MOVaddrJT 688 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low), 689 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tjumptable:$hi), 690 tjumptable:$low))]>, 691 Sched<[WriteAdrAdr]>; 692def MOVaddrCP 693 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low), 694 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tconstpool:$hi), 695 tconstpool:$low))]>, 696 Sched<[WriteAdrAdr]>; 697def MOVaddrBA 698 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low), 699 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tblockaddress:$hi), 700 tblockaddress:$low))]>, 701 Sched<[WriteAdrAdr]>; 702def MOVaddrTLS 703 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low), 704 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tglobaltlsaddr:$hi), 705 tglobaltlsaddr:$low))]>, 706 Sched<[WriteAdrAdr]>; 707def MOVaddrEXT 708 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low), 709 [(set GPR64:$dst, (AArch64addlow (AArch64adrp texternalsym:$hi), 710 texternalsym:$low))]>, 711 Sched<[WriteAdrAdr]>; 712// Normally AArch64addlow either gets folded into a following ldr/str, 713// or together with an adrp into MOVaddr above. For cases with TLS, it 714// might appear without either of them, so allow lowering it into a plain 715// add. 716def ADDlowTLS 717 : Pseudo<(outs GPR64:$dst), (ins GPR64:$src, i64imm:$low), 718 [(set GPR64:$dst, (AArch64addlow GPR64:$src, 719 tglobaltlsaddr:$low))]>, 720 Sched<[WriteAdr]>; 721 722} // isReMaterializable, isCodeGenOnly 723 724def : Pat<(AArch64LOADgot tglobaltlsaddr:$addr), 725 (LOADgot tglobaltlsaddr:$addr)>; 726 727def : Pat<(AArch64LOADgot texternalsym:$addr), 728 (LOADgot texternalsym:$addr)>; 729 730def : Pat<(AArch64LOADgot tconstpool:$addr), 731 (LOADgot tconstpool:$addr)>; 732 733// 32-bit jump table destination is actually only 2 instructions since we can 734// use the table itself as a PC-relative base. But optimization occurs after 735// branch relaxation so be pessimistic. 736let Size = 12, Constraints = "@earlyclobber $dst,@earlyclobber $scratch", 737 isNotDuplicable = 1 in { 738def JumpTableDest32 : Pseudo<(outs GPR64:$dst, GPR64sp:$scratch), 739 (ins GPR64:$table, GPR64:$entry, i32imm:$jti), []>, 740 Sched<[]>; 741def JumpTableDest16 : Pseudo<(outs GPR64:$dst, GPR64sp:$scratch), 742 (ins GPR64:$table, GPR64:$entry, i32imm:$jti), []>, 743 Sched<[]>; 744def JumpTableDest8 : Pseudo<(outs GPR64:$dst, GPR64sp:$scratch), 745 (ins GPR64:$table, GPR64:$entry, i32imm:$jti), []>, 746 Sched<[]>; 747} 748 749// Space-consuming pseudo to aid testing of placement and reachability 750// algorithms. Immediate operand is the number of bytes this "instruction" 751// occupies; register operands can be used to enforce dependency and constrain 752// the scheduler. 753let hasSideEffects = 1, mayLoad = 1, mayStore = 1 in 754def SPACE : Pseudo<(outs GPR64:$Rd), (ins i32imm:$size, GPR64:$Rn), 755 [(set GPR64:$Rd, (int_aarch64_space imm:$size, GPR64:$Rn))]>, 756 Sched<[]>; 757 758let hasSideEffects = 1, isCodeGenOnly = 1 in { 759 def SpeculationSafeValueX 760 : Pseudo<(outs GPR64:$dst), (ins GPR64:$src), []>, Sched<[]>; 761 def SpeculationSafeValueW 762 : Pseudo<(outs GPR32:$dst), (ins GPR32:$src), []>, Sched<[]>; 763} 764 765// SpeculationBarrierEndBB must only be used after an unconditional control 766// flow, i.e. after a terminator for which isBarrier is True. 767let hasSideEffects = 1, isCodeGenOnly = 1, isTerminator = 1, isBarrier = 1 in { 768 def SpeculationBarrierISBDSBEndBB 769 : Pseudo<(outs), (ins), []>, Sched<[]>; 770 def SpeculationBarrierSBEndBB 771 : Pseudo<(outs), (ins), []>, Sched<[]>; 772} 773 774//===----------------------------------------------------------------------===// 775// System instructions. 776//===----------------------------------------------------------------------===// 777 778def HINT : HintI<"hint">; 779def : InstAlias<"nop", (HINT 0b000)>; 780def : InstAlias<"yield",(HINT 0b001)>; 781def : InstAlias<"wfe", (HINT 0b010)>; 782def : InstAlias<"wfi", (HINT 0b011)>; 783def : InstAlias<"sev", (HINT 0b100)>; 784def : InstAlias<"sevl", (HINT 0b101)>; 785def : InstAlias<"dgh", (HINT 0b110)>; 786def : InstAlias<"esb", (HINT 0b10000)>, Requires<[HasRAS]>; 787def : InstAlias<"csdb", (HINT 20)>; 788// In order to be able to write readable assembly, LLVM should accept assembly 789// inputs that use Branch Target Indentification mnemonics, even with BTI disabled. 790// However, in order to be compatible with other assemblers (e.g. GAS), LLVM 791// should not emit these mnemonics unless BTI is enabled. 792def : InstAlias<"bti", (HINT 32), 0>; 793def : InstAlias<"bti $op", (HINT btihint_op:$op), 0>; 794def : InstAlias<"bti", (HINT 32)>, Requires<[HasBTI]>; 795def : InstAlias<"bti $op", (HINT btihint_op:$op)>, Requires<[HasBTI]>; 796 797// v8.2a Statistical Profiling extension 798def : InstAlias<"psb $op", (HINT psbhint_op:$op)>, Requires<[HasSPE]>; 799 800// As far as LLVM is concerned this writes to the system's exclusive monitors. 801let mayLoad = 1, mayStore = 1 in 802def CLREX : CRmSystemI<imm0_15, 0b010, "clrex">; 803 804// NOTE: ideally, this would have mayStore = 0, mayLoad = 0, but we cannot 805// model patterns with sufficiently fine granularity. 806let mayLoad = ?, mayStore = ? in { 807def DMB : CRmSystemI<barrier_op, 0b101, "dmb", 808 [(int_aarch64_dmb (i32 imm32_0_15:$CRm))]>; 809 810def DSB : CRmSystemI<barrier_op, 0b100, "dsb", 811 [(int_aarch64_dsb (i32 imm32_0_15:$CRm))]>; 812 813def ISB : CRmSystemI<barrier_op, 0b110, "isb", 814 [(int_aarch64_isb (i32 imm32_0_15:$CRm))]>; 815 816def TSB : CRmSystemI<barrier_op, 0b010, "tsb", []> { 817 let CRm = 0b0010; 818 let Inst{12} = 0; 819 let Predicates = [HasTRACEV8_4]; 820} 821 822def DSBnXS : CRmSystemI<barrier_nxs_op, 0b001, "dsb"> { 823 let CRm{1-0} = 0b11; 824 let Inst{9-8} = 0b10; 825 let Predicates = [HasXS]; 826} 827 828let Predicates = [HasWFxT] in { 829def WFET : RegInputSystemI<0b0000, 0b000, "wfet">; 830def WFIT : RegInputSystemI<0b0000, 0b001, "wfit">; 831} 832 833// Branch Record Buffer two-word mnemonic instructions 834class BRBEI<bits<3> op2, string keyword> 835 : SimpleSystemI<0, (ins), "brb", keyword>, Sched<[WriteSys]> { 836 let Inst{31-8} = 0b110101010000100101110010; 837 let Inst{7-5} = op2; 838 let Predicates = [HasBRBE]; 839} 840def BRB_IALL: BRBEI<0b100, "\tiall">; 841def BRB_INJ: BRBEI<0b101, "\tinj">; 842 843} 844 845// Allow uppercase and lowercase keyword arguments for BRB IALL and BRB INJ 846def : TokenAlias<"INJ", "inj">; 847def : TokenAlias<"IALL", "iall">; 848 849// ARMv8.2-A Dot Product 850let Predicates = [HasDotProd] in { 851defm SDOT : SIMDThreeSameVectorDot<0, 0, "sdot", AArch64sdot>; 852defm UDOT : SIMDThreeSameVectorDot<1, 0, "udot", AArch64udot>; 853defm SDOTlane : SIMDThreeSameVectorDotIndex<0, 0, 0b10, "sdot", AArch64sdot>; 854defm UDOTlane : SIMDThreeSameVectorDotIndex<1, 0, 0b10, "udot", AArch64udot>; 855} 856 857// ARMv8.6-A BFloat 858let Predicates = [HasBF16] in { 859defm BFDOT : SIMDThreeSameVectorBFDot<1, "bfdot">; 860defm BF16DOTlane : SIMDThreeSameVectorBF16DotI<0, "bfdot">; 861def BFMMLA : SIMDThreeSameVectorBF16MatrixMul<"bfmmla">; 862def BFMLALB : SIMDBF16MLAL<0, "bfmlalb", int_aarch64_neon_bfmlalb>; 863def BFMLALT : SIMDBF16MLAL<1, "bfmlalt", int_aarch64_neon_bfmlalt>; 864def BFMLALBIdx : SIMDBF16MLALIndex<0, "bfmlalb", int_aarch64_neon_bfmlalb>; 865def BFMLALTIdx : SIMDBF16MLALIndex<1, "bfmlalt", int_aarch64_neon_bfmlalt>; 866def BFCVTN : SIMD_BFCVTN; 867def BFCVTN2 : SIMD_BFCVTN2; 868def BFCVT : BF16ToSinglePrecision<"bfcvt">; 869 870// Vector-scalar BFDOT: 871// The second source operand of the 64-bit variant of BF16DOTlane is a 128-bit 872// register (the instruction uses a single 32-bit lane from it), so the pattern 873// is a bit tricky. 874def : Pat<(v2f32 (int_aarch64_neon_bfdot 875 (v2f32 V64:$Rd), (v4bf16 V64:$Rn), 876 (v4bf16 (bitconvert 877 (v2i32 (AArch64duplane32 878 (v4i32 (bitconvert 879 (v8bf16 (insert_subvector undef, 880 (v4bf16 V64:$Rm), 881 (i64 0))))), 882 VectorIndexS:$idx)))))), 883 (BF16DOTlanev4bf16 (v2f32 V64:$Rd), (v4bf16 V64:$Rn), 884 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), 885 VectorIndexS:$idx)>; 886} 887 888// ARMv8.6A AArch64 matrix multiplication 889let Predicates = [HasMatMulInt8] in { 890def SMMLA : SIMDThreeSameVectorMatMul<0, 0, "smmla", int_aarch64_neon_smmla>; 891def UMMLA : SIMDThreeSameVectorMatMul<0, 1, "ummla", int_aarch64_neon_ummla>; 892def USMMLA : SIMDThreeSameVectorMatMul<1, 0, "usmmla", int_aarch64_neon_usmmla>; 893defm USDOT : SIMDThreeSameVectorDot<0, 1, "usdot", int_aarch64_neon_usdot>; 894defm USDOTlane : SIMDThreeSameVectorDotIndex<0, 1, 0b10, "usdot", int_aarch64_neon_usdot>; 895 896// sudot lane has a pattern where usdot is expected (there is no sudot). 897// The second operand is used in the dup operation to repeat the indexed 898// element. 899class BaseSIMDSUDOTIndex<bit Q, string dst_kind, string lhs_kind, 900 string rhs_kind, RegisterOperand RegType, 901 ValueType AccumType, ValueType InputType> 902 : BaseSIMDThreeSameVectorDotIndex<Q, 0, 1, 0b00, "sudot", dst_kind, 903 lhs_kind, rhs_kind, RegType, AccumType, 904 InputType, null_frag> { 905 let Pattern = [(set (AccumType RegType:$dst), 906 (AccumType (int_aarch64_neon_usdot (AccumType RegType:$Rd), 907 (InputType (bitconvert (AccumType 908 (AArch64duplane32 (v4i32 V128:$Rm), 909 VectorIndexS:$idx)))), 910 (InputType RegType:$Rn))))]; 911} 912 913multiclass SIMDSUDOTIndex { 914 def v8i8 : BaseSIMDSUDOTIndex<0, ".2s", ".8b", ".4b", V64, v2i32, v8i8>; 915 def v16i8 : BaseSIMDSUDOTIndex<1, ".4s", ".16b", ".4b", V128, v4i32, v16i8>; 916} 917 918defm SUDOTlane : SIMDSUDOTIndex; 919 920} 921 922// ARMv8.2-A FP16 Fused Multiply-Add Long 923let Predicates = [HasNEON, HasFP16FML] in { 924defm FMLAL : SIMDThreeSameVectorFML<0, 1, 0b001, "fmlal", int_aarch64_neon_fmlal>; 925defm FMLSL : SIMDThreeSameVectorFML<0, 1, 0b101, "fmlsl", int_aarch64_neon_fmlsl>; 926defm FMLAL2 : SIMDThreeSameVectorFML<1, 0, 0b001, "fmlal2", int_aarch64_neon_fmlal2>; 927defm FMLSL2 : SIMDThreeSameVectorFML<1, 0, 0b101, "fmlsl2", int_aarch64_neon_fmlsl2>; 928defm FMLALlane : SIMDThreeSameVectorFMLIndex<0, 0b0000, "fmlal", int_aarch64_neon_fmlal>; 929defm FMLSLlane : SIMDThreeSameVectorFMLIndex<0, 0b0100, "fmlsl", int_aarch64_neon_fmlsl>; 930defm FMLAL2lane : SIMDThreeSameVectorFMLIndex<1, 0b1000, "fmlal2", int_aarch64_neon_fmlal2>; 931defm FMLSL2lane : SIMDThreeSameVectorFMLIndex<1, 0b1100, "fmlsl2", int_aarch64_neon_fmlsl2>; 932} 933 934// Armv8.2-A Crypto extensions 935let Predicates = [HasSHA3] in { 936def SHA512H : CryptoRRRTied<0b0, 0b00, "sha512h">; 937def SHA512H2 : CryptoRRRTied<0b0, 0b01, "sha512h2">; 938def SHA512SU0 : CryptoRRTied_2D<0b0, 0b00, "sha512su0">; 939def SHA512SU1 : CryptoRRRTied_2D<0b0, 0b10, "sha512su1">; 940def RAX1 : CryptoRRR_2D<0b0,0b11, "rax1">; 941def EOR3 : CryptoRRRR_16B<0b00, "eor3">; 942def BCAX : CryptoRRRR_16B<0b01, "bcax">; 943def XAR : CryptoRRRi6<"xar">; 944 945class SHA3_pattern<Instruction INST, Intrinsic OpNode, ValueType VecTy> 946 : Pat<(VecTy (OpNode (VecTy V128:$Vd), (VecTy V128:$Vn), (VecTy V128:$Vm))), 947 (INST (VecTy V128:$Vd), (VecTy V128:$Vn), (VecTy V128:$Vm))>; 948 949def : Pat<(v2i64 (int_aarch64_crypto_sha512su0 (v2i64 V128:$Vn), (v2i64 V128:$Vm))), 950 (SHA512SU0 (v2i64 V128:$Vn), (v2i64 V128:$Vm))>; 951 952def : SHA3_pattern<SHA512H, int_aarch64_crypto_sha512h, v2i64>; 953def : SHA3_pattern<SHA512H2, int_aarch64_crypto_sha512h2, v2i64>; 954def : SHA3_pattern<SHA512SU1, int_aarch64_crypto_sha512su1, v2i64>; 955 956def : SHA3_pattern<EOR3, int_aarch64_crypto_eor3u, v16i8>; 957def : SHA3_pattern<EOR3, int_aarch64_crypto_eor3u, v8i16>; 958def : SHA3_pattern<EOR3, int_aarch64_crypto_eor3u, v4i32>; 959def : SHA3_pattern<EOR3, int_aarch64_crypto_eor3u, v2i64>; 960 961def : SHA3_pattern<BCAX, int_aarch64_crypto_bcaxu, v16i8>; 962def : SHA3_pattern<BCAX, int_aarch64_crypto_bcaxu, v8i16>; 963def : SHA3_pattern<BCAX, int_aarch64_crypto_bcaxu, v4i32>; 964def : SHA3_pattern<BCAX, int_aarch64_crypto_bcaxu, v2i64>; 965 966def : SHA3_pattern<EOR3, int_aarch64_crypto_eor3s, v16i8>; 967def : SHA3_pattern<EOR3, int_aarch64_crypto_eor3s, v8i16>; 968def : SHA3_pattern<EOR3, int_aarch64_crypto_eor3s, v4i32>; 969def : SHA3_pattern<EOR3, int_aarch64_crypto_eor3s, v2i64>; 970 971def : SHA3_pattern<BCAX, int_aarch64_crypto_bcaxs, v16i8>; 972def : SHA3_pattern<BCAX, int_aarch64_crypto_bcaxs, v8i16>; 973def : SHA3_pattern<BCAX, int_aarch64_crypto_bcaxs, v4i32>; 974def : SHA3_pattern<BCAX, int_aarch64_crypto_bcaxs, v2i64>; 975 976def : Pat<(v2i64 (int_aarch64_crypto_rax1 (v2i64 V128:$Vn), (v2i64 V128:$Vm))), 977 (RAX1 (v2i64 V128:$Vn), (v2i64 V128:$Vm))>; 978 979def : Pat<(v2i64 (int_aarch64_crypto_xar (v2i64 V128:$Vn), (v2i64 V128:$Vm), (i64 timm0_63:$imm))), 980 (XAR (v2i64 V128:$Vn), (v2i64 V128:$Vm), (timm0_63:$imm))>; 981 982 983} // HasSHA3 984 985let Predicates = [HasSM4] in { 986def SM3TT1A : CryptoRRRi2Tied<0b0, 0b00, "sm3tt1a">; 987def SM3TT1B : CryptoRRRi2Tied<0b0, 0b01, "sm3tt1b">; 988def SM3TT2A : CryptoRRRi2Tied<0b0, 0b10, "sm3tt2a">; 989def SM3TT2B : CryptoRRRi2Tied<0b0, 0b11, "sm3tt2b">; 990def SM3SS1 : CryptoRRRR_4S<0b10, "sm3ss1">; 991def SM3PARTW1 : CryptoRRRTied_4S<0b1, 0b00, "sm3partw1">; 992def SM3PARTW2 : CryptoRRRTied_4S<0b1, 0b01, "sm3partw2">; 993def SM4ENCKEY : CryptoRRR_4S<0b1, 0b10, "sm4ekey">; 994def SM4E : CryptoRRTied_4S<0b0, 0b01, "sm4e">; 995 996def : Pat<(v4i32 (int_aarch64_crypto_sm3ss1 (v4i32 V128:$Vn), (v4i32 V128:$Vm), (v4i32 V128:$Va))), 997 (SM3SS1 (v4i32 V128:$Vn), (v4i32 V128:$Vm), (v4i32 V128:$Va))>; 998 999class SM3PARTW_pattern<Instruction INST, Intrinsic OpNode> 1000 : Pat<(v4i32 (OpNode (v4i32 V128:$Vd), (v4i32 V128:$Vn), (v4i32 V128:$Vm))), 1001 (INST (v4i32 V128:$Vd), (v4i32 V128:$Vn), (v4i32 V128:$Vm))>; 1002 1003class SM3TT_pattern<Instruction INST, Intrinsic OpNode> 1004 : Pat<(v4i32 (OpNode (v4i32 V128:$Vd), (v4i32 V128:$Vn), (v4i32 V128:$Vm), (i64 VectorIndexS_timm:$imm) )), 1005 (INST (v4i32 V128:$Vd), (v4i32 V128:$Vn), (v4i32 V128:$Vm), (VectorIndexS_timm:$imm))>; 1006 1007class SM4_pattern<Instruction INST, Intrinsic OpNode> 1008 : Pat<(v4i32 (OpNode (v4i32 V128:$Vn), (v4i32 V128:$Vm))), 1009 (INST (v4i32 V128:$Vn), (v4i32 V128:$Vm))>; 1010 1011def : SM3PARTW_pattern<SM3PARTW1, int_aarch64_crypto_sm3partw1>; 1012def : SM3PARTW_pattern<SM3PARTW2, int_aarch64_crypto_sm3partw2>; 1013 1014def : SM3TT_pattern<SM3TT1A, int_aarch64_crypto_sm3tt1a>; 1015def : SM3TT_pattern<SM3TT1B, int_aarch64_crypto_sm3tt1b>; 1016def : SM3TT_pattern<SM3TT2A, int_aarch64_crypto_sm3tt2a>; 1017def : SM3TT_pattern<SM3TT2B, int_aarch64_crypto_sm3tt2b>; 1018 1019def : SM4_pattern<SM4ENCKEY, int_aarch64_crypto_sm4ekey>; 1020def : SM4_pattern<SM4E, int_aarch64_crypto_sm4e>; 1021} // HasSM4 1022 1023let Predicates = [HasRCPC] in { 1024 // v8.3 Release Consistent Processor Consistent support, optional in v8.2. 1025 def LDAPRB : RCPCLoad<0b00, "ldaprb", GPR32>; 1026 def LDAPRH : RCPCLoad<0b01, "ldaprh", GPR32>; 1027 def LDAPRW : RCPCLoad<0b10, "ldapr", GPR32>; 1028 def LDAPRX : RCPCLoad<0b11, "ldapr", GPR64>; 1029} 1030 1031// v8.3a complex add and multiply-accumulate. No predicate here, that is done 1032// inside the multiclass as the FP16 versions need different predicates. 1033defm FCMLA : SIMDThreeSameVectorTiedComplexHSD<1, 0b110, complexrotateop, 1034 "fcmla", null_frag>; 1035defm FCADD : SIMDThreeSameVectorComplexHSD<1, 0b111, complexrotateopodd, 1036 "fcadd", null_frag>; 1037defm FCMLA : SIMDIndexedTiedComplexHSD<1, 0, 1, complexrotateop, "fcmla", 1038 null_frag>; 1039 1040let Predicates = [HasComplxNum, HasNEON, HasFullFP16] in { 1041 def : Pat<(v4f16 (int_aarch64_neon_vcadd_rot90 (v4f16 V64:$Rn), (v4f16 V64:$Rm))), 1042 (FCADDv4f16 (v4f16 V64:$Rn), (v4f16 V64:$Rm), (i32 0))>; 1043 def : Pat<(v4f16 (int_aarch64_neon_vcadd_rot270 (v4f16 V64:$Rn), (v4f16 V64:$Rm))), 1044 (FCADDv4f16 (v4f16 V64:$Rn), (v4f16 V64:$Rm), (i32 1))>; 1045 def : Pat<(v8f16 (int_aarch64_neon_vcadd_rot90 (v8f16 V128:$Rn), (v8f16 V128:$Rm))), 1046 (FCADDv8f16 (v8f16 V128:$Rn), (v8f16 V128:$Rm), (i32 0))>; 1047 def : Pat<(v8f16 (int_aarch64_neon_vcadd_rot270 (v8f16 V128:$Rn), (v8f16 V128:$Rm))), 1048 (FCADDv8f16 (v8f16 V128:$Rn), (v8f16 V128:$Rm), (i32 1))>; 1049} 1050 1051let Predicates = [HasComplxNum, HasNEON] in { 1052 def : Pat<(v2f32 (int_aarch64_neon_vcadd_rot90 (v2f32 V64:$Rn), (v2f32 V64:$Rm))), 1053 (FCADDv2f32 (v2f32 V64:$Rn), (v2f32 V64:$Rm), (i32 0))>; 1054 def : Pat<(v2f32 (int_aarch64_neon_vcadd_rot270 (v2f32 V64:$Rn), (v2f32 V64:$Rm))), 1055 (FCADDv2f32 (v2f32 V64:$Rn), (v2f32 V64:$Rm), (i32 1))>; 1056 foreach Ty = [v4f32, v2f64] in { 1057 def : Pat<(Ty (int_aarch64_neon_vcadd_rot90 (Ty V128:$Rn), (Ty V128:$Rm))), 1058 (!cast<Instruction>("FCADD"#Ty) (Ty V128:$Rn), (Ty V128:$Rm), (i32 0))>; 1059 def : Pat<(Ty (int_aarch64_neon_vcadd_rot270 (Ty V128:$Rn), (Ty V128:$Rm))), 1060 (!cast<Instruction>("FCADD"#Ty) (Ty V128:$Rn), (Ty V128:$Rm), (i32 1))>; 1061 } 1062} 1063 1064multiclass FCMLA_PATS<ValueType ty, DAGOperand Reg> { 1065 def : Pat<(ty (int_aarch64_neon_vcmla_rot0 (ty Reg:$Rd), (ty Reg:$Rn), (ty Reg:$Rm))), 1066 (!cast<Instruction>("FCMLA" # ty) $Rd, $Rn, $Rm, 0)>; 1067 def : Pat<(ty (int_aarch64_neon_vcmla_rot90 (ty Reg:$Rd), (ty Reg:$Rn), (ty Reg:$Rm))), 1068 (!cast<Instruction>("FCMLA" # ty) $Rd, $Rn, $Rm, 1)>; 1069 def : Pat<(ty (int_aarch64_neon_vcmla_rot180 (ty Reg:$Rd), (ty Reg:$Rn), (ty Reg:$Rm))), 1070 (!cast<Instruction>("FCMLA" # ty) $Rd, $Rn, $Rm, 2)>; 1071 def : Pat<(ty (int_aarch64_neon_vcmla_rot270 (ty Reg:$Rd), (ty Reg:$Rn), (ty Reg:$Rm))), 1072 (!cast<Instruction>("FCMLA" # ty) $Rd, $Rn, $Rm, 3)>; 1073} 1074 1075multiclass FCMLA_LANE_PATS<ValueType ty, DAGOperand Reg, dag RHSDup> { 1076 def : Pat<(ty (int_aarch64_neon_vcmla_rot0 (ty Reg:$Rd), (ty Reg:$Rn), RHSDup)), 1077 (!cast<Instruction>("FCMLA" # ty # "_indexed") $Rd, $Rn, $Rm, VectorIndexS:$idx, 0)>; 1078 def : Pat<(ty (int_aarch64_neon_vcmla_rot90 (ty Reg:$Rd), (ty Reg:$Rn), RHSDup)), 1079 (!cast<Instruction>("FCMLA" # ty # "_indexed") $Rd, $Rn, $Rm, VectorIndexS:$idx, 1)>; 1080 def : Pat<(ty (int_aarch64_neon_vcmla_rot180 (ty Reg:$Rd), (ty Reg:$Rn), RHSDup)), 1081 (!cast<Instruction>("FCMLA" # ty # "_indexed") $Rd, $Rn, $Rm, VectorIndexS:$idx, 2)>; 1082 def : Pat<(ty (int_aarch64_neon_vcmla_rot270 (ty Reg:$Rd), (ty Reg:$Rn), RHSDup)), 1083 (!cast<Instruction>("FCMLA" # ty # "_indexed") $Rd, $Rn, $Rm, VectorIndexS:$idx, 3)>; 1084} 1085 1086 1087let Predicates = [HasComplxNum, HasNEON, HasFullFP16] in { 1088 defm : FCMLA_PATS<v4f16, V64>; 1089 defm : FCMLA_PATS<v8f16, V128>; 1090 1091 defm : FCMLA_LANE_PATS<v4f16, V64, 1092 (v4f16 (bitconvert (v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexD:$idx))))>; 1093 defm : FCMLA_LANE_PATS<v8f16, V128, 1094 (v8f16 (bitconvert (v4i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))>; 1095} 1096let Predicates = [HasComplxNum, HasNEON] in { 1097 defm : FCMLA_PATS<v2f32, V64>; 1098 defm : FCMLA_PATS<v4f32, V128>; 1099 defm : FCMLA_PATS<v2f64, V128>; 1100 1101 defm : FCMLA_LANE_PATS<v4f32, V128, 1102 (v4f32 (bitconvert (v2i64 (AArch64duplane64 (v2i64 V128:$Rm), VectorIndexD:$idx))))>; 1103} 1104 1105// v8.3a Pointer Authentication 1106// These instructions inhabit part of the hint space and so can be used for 1107// armv8 targets. Keeping the old HINT mnemonic when compiling without PA is 1108// important for compatibility with other assemblers (e.g. GAS) when building 1109// software compatible with both CPUs that do or don't implement PA. 1110let Uses = [LR], Defs = [LR] in { 1111 def PACIAZ : SystemNoOperands<0b000, "hint\t#24">; 1112 def PACIBZ : SystemNoOperands<0b010, "hint\t#26">; 1113 let isAuthenticated = 1 in { 1114 def AUTIAZ : SystemNoOperands<0b100, "hint\t#28">; 1115 def AUTIBZ : SystemNoOperands<0b110, "hint\t#30">; 1116 } 1117} 1118let Uses = [LR, SP], Defs = [LR] in { 1119 def PACIASP : SystemNoOperands<0b001, "hint\t#25">; 1120 def PACIBSP : SystemNoOperands<0b011, "hint\t#27">; 1121 let isAuthenticated = 1 in { 1122 def AUTIASP : SystemNoOperands<0b101, "hint\t#29">; 1123 def AUTIBSP : SystemNoOperands<0b111, "hint\t#31">; 1124 } 1125} 1126let Uses = [X16, X17], Defs = [X17], CRm = 0b0001 in { 1127 def PACIA1716 : SystemNoOperands<0b000, "hint\t#8">; 1128 def PACIB1716 : SystemNoOperands<0b010, "hint\t#10">; 1129 let isAuthenticated = 1 in { 1130 def AUTIA1716 : SystemNoOperands<0b100, "hint\t#12">; 1131 def AUTIB1716 : SystemNoOperands<0b110, "hint\t#14">; 1132 } 1133} 1134 1135let Uses = [LR], Defs = [LR], CRm = 0b0000 in { 1136 def XPACLRI : SystemNoOperands<0b111, "hint\t#7">; 1137} 1138 1139// In order to be able to write readable assembly, LLVM should accept assembly 1140// inputs that use pointer authentication mnemonics, even with PA disabled. 1141// However, in order to be compatible with other assemblers (e.g. GAS), LLVM 1142// should not emit these mnemonics unless PA is enabled. 1143def : InstAlias<"paciaz", (PACIAZ), 0>; 1144def : InstAlias<"pacibz", (PACIBZ), 0>; 1145def : InstAlias<"autiaz", (AUTIAZ), 0>; 1146def : InstAlias<"autibz", (AUTIBZ), 0>; 1147def : InstAlias<"paciasp", (PACIASP), 0>; 1148def : InstAlias<"pacibsp", (PACIBSP), 0>; 1149def : InstAlias<"autiasp", (AUTIASP), 0>; 1150def : InstAlias<"autibsp", (AUTIBSP), 0>; 1151def : InstAlias<"pacia1716", (PACIA1716), 0>; 1152def : InstAlias<"pacib1716", (PACIB1716), 0>; 1153def : InstAlias<"autia1716", (AUTIA1716), 0>; 1154def : InstAlias<"autib1716", (AUTIB1716), 0>; 1155def : InstAlias<"xpaclri", (XPACLRI), 0>; 1156 1157// These pointer authentication instructions require armv8.3a 1158let Predicates = [HasPAuth] in { 1159 1160 // When PA is enabled, a better mnemonic should be emitted. 1161 def : InstAlias<"paciaz", (PACIAZ), 1>; 1162 def : InstAlias<"pacibz", (PACIBZ), 1>; 1163 def : InstAlias<"autiaz", (AUTIAZ), 1>; 1164 def : InstAlias<"autibz", (AUTIBZ), 1>; 1165 def : InstAlias<"paciasp", (PACIASP), 1>; 1166 def : InstAlias<"pacibsp", (PACIBSP), 1>; 1167 def : InstAlias<"autiasp", (AUTIASP), 1>; 1168 def : InstAlias<"autibsp", (AUTIBSP), 1>; 1169 def : InstAlias<"pacia1716", (PACIA1716), 1>; 1170 def : InstAlias<"pacib1716", (PACIB1716), 1>; 1171 def : InstAlias<"autia1716", (AUTIA1716), 1>; 1172 def : InstAlias<"autib1716", (AUTIB1716), 1>; 1173 def : InstAlias<"xpaclri", (XPACLRI), 1>; 1174 1175 multiclass SignAuth<bits<3> prefix, bits<3> prefix_z, string asm> { 1176 def IA : SignAuthOneData<prefix, 0b00, !strconcat(asm, "ia")>; 1177 def IB : SignAuthOneData<prefix, 0b01, !strconcat(asm, "ib")>; 1178 def DA : SignAuthOneData<prefix, 0b10, !strconcat(asm, "da")>; 1179 def DB : SignAuthOneData<prefix, 0b11, !strconcat(asm, "db")>; 1180 def IZA : SignAuthZero<prefix_z, 0b00, !strconcat(asm, "iza")>; 1181 def DZA : SignAuthZero<prefix_z, 0b10, !strconcat(asm, "dza")>; 1182 def IZB : SignAuthZero<prefix_z, 0b01, !strconcat(asm, "izb")>; 1183 def DZB : SignAuthZero<prefix_z, 0b11, !strconcat(asm, "dzb")>; 1184 } 1185 1186 defm PAC : SignAuth<0b000, 0b010, "pac">; 1187 defm AUT : SignAuth<0b001, 0b011, "aut">; 1188 1189 def XPACI : ClearAuth<0, "xpaci">; 1190 def XPACD : ClearAuth<1, "xpacd">; 1191 def PACGA : SignAuthTwoOperand<0b1100, "pacga", null_frag>; 1192 1193 // Combined Instructions 1194 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 1195 def BRAA : AuthBranchTwoOperands<0, 0, "braa">; 1196 def BRAB : AuthBranchTwoOperands<0, 1, "brab">; 1197 } 1198 let isCall = 1, Defs = [LR], Uses = [SP] in { 1199 def BLRAA : AuthBranchTwoOperands<1, 0, "blraa">; 1200 def BLRAB : AuthBranchTwoOperands<1, 1, "blrab">; 1201 } 1202 1203 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 1204 def BRAAZ : AuthOneOperand<0b000, 0, "braaz">; 1205 def BRABZ : AuthOneOperand<0b000, 1, "brabz">; 1206 } 1207 let isCall = 1, Defs = [LR], Uses = [SP] in { 1208 def BLRAAZ : AuthOneOperand<0b001, 0, "blraaz">; 1209 def BLRABZ : AuthOneOperand<0b001, 1, "blrabz">; 1210 } 1211 1212 let isReturn = 1, isTerminator = 1, isBarrier = 1 in { 1213 def RETAA : AuthReturn<0b010, 0, "retaa">; 1214 def RETAB : AuthReturn<0b010, 1, "retab">; 1215 def ERETAA : AuthReturn<0b100, 0, "eretaa">; 1216 def ERETAB : AuthReturn<0b100, 1, "eretab">; 1217 } 1218 1219 defm LDRAA : AuthLoad<0, "ldraa", simm10Scaled>; 1220 defm LDRAB : AuthLoad<1, "ldrab", simm10Scaled>; 1221 1222} 1223 1224// v8.3a floating point conversion for javascript 1225let Predicates = [HasJS, HasFPARMv8], Defs = [NZCV] in 1226def FJCVTZS : BaseFPToIntegerUnscaled<0b01, 0b11, 0b110, FPR64, GPR32, 1227 "fjcvtzs", 1228 [(set GPR32:$Rd, 1229 (int_aarch64_fjcvtzs FPR64:$Rn))]> { 1230 let Inst{31} = 0; 1231} // HasJS, HasFPARMv8 1232 1233// v8.4 Flag manipulation instructions 1234let Predicates = [HasFlagM], Defs = [NZCV], Uses = [NZCV] in { 1235def CFINV : SimpleSystemI<0, (ins), "cfinv", "">, Sched<[WriteSys]> { 1236 let Inst{20-5} = 0b0000001000000000; 1237} 1238def SETF8 : BaseFlagManipulation<0, 0, (ins GPR32:$Rn), "setf8", "{\t$Rn}">; 1239def SETF16 : BaseFlagManipulation<0, 1, (ins GPR32:$Rn), "setf16", "{\t$Rn}">; 1240def RMIF : FlagRotate<(ins GPR64:$Rn, uimm6:$imm, imm0_15:$mask), "rmif", 1241 "{\t$Rn, $imm, $mask}">; 1242} // HasFlagM 1243 1244// v8.5 flag manipulation instructions 1245let Predicates = [HasAltNZCV], Uses = [NZCV], Defs = [NZCV] in { 1246 1247def XAFLAG : PstateWriteSimple<(ins), "xaflag", "">, Sched<[WriteSys]> { 1248 let Inst{18-16} = 0b000; 1249 let Inst{11-8} = 0b0000; 1250 let Unpredictable{11-8} = 0b1111; 1251 let Inst{7-5} = 0b001; 1252} 1253 1254def AXFLAG : PstateWriteSimple<(ins), "axflag", "">, Sched<[WriteSys]> { 1255 let Inst{18-16} = 0b000; 1256 let Inst{11-8} = 0b0000; 1257 let Unpredictable{11-8} = 0b1111; 1258 let Inst{7-5} = 0b010; 1259} 1260} // HasAltNZCV 1261 1262 1263// Armv8.5-A speculation barrier 1264def SB : SimpleSystemI<0, (ins), "sb", "">, Sched<[]> { 1265 let Inst{20-5} = 0b0001100110000111; 1266 let Unpredictable{11-8} = 0b1111; 1267 let Predicates = [HasSB]; 1268 let hasSideEffects = 1; 1269} 1270 1271def : InstAlias<"clrex", (CLREX 0xf)>; 1272def : InstAlias<"isb", (ISB 0xf)>; 1273def : InstAlias<"ssbb", (DSB 0)>; 1274def : InstAlias<"pssbb", (DSB 4)>; 1275 1276def MRS : MRSI; 1277def MSR : MSRI; 1278def MSRpstateImm1 : MSRpstateImm0_1; 1279def MSRpstateImm4 : MSRpstateImm0_15; 1280 1281def : Pat<(AArch64mrs imm:$id), 1282 (MRS imm:$id)>; 1283 1284// The thread pointer (on Linux, at least, where this has been implemented) is 1285// TPIDR_EL0. 1286def MOVbaseTLS : Pseudo<(outs GPR64:$dst), (ins), 1287 [(set GPR64:$dst, AArch64threadpointer)]>, Sched<[WriteSys]>; 1288 1289let Uses = [ X9 ], Defs = [ X16, X17, LR, NZCV ] in { 1290def HWASAN_CHECK_MEMACCESS : Pseudo< 1291 (outs), (ins GPR64noip:$ptr, i32imm:$accessinfo), 1292 [(int_hwasan_check_memaccess X9, GPR64noip:$ptr, (i32 timm:$accessinfo))]>, 1293 Sched<[]>; 1294} 1295 1296let Uses = [ X20 ], Defs = [ X16, X17, LR, NZCV ] in { 1297def HWASAN_CHECK_MEMACCESS_SHORTGRANULES : Pseudo< 1298 (outs), (ins GPR64noip:$ptr, i32imm:$accessinfo), 1299 [(int_hwasan_check_memaccess_shortgranules X20, GPR64noip:$ptr, (i32 timm:$accessinfo))]>, 1300 Sched<[]>; 1301} 1302 1303// The cycle counter PMC register is PMCCNTR_EL0. 1304let Predicates = [HasPerfMon] in 1305def : Pat<(readcyclecounter), (MRS 0xdce8)>; 1306 1307// FPCR register 1308def : Pat<(i64 (int_aarch64_get_fpcr)), (MRS 0xda20)>; 1309def : Pat<(int_aarch64_set_fpcr i64:$val), (MSR 0xda20, GPR64:$val)>; 1310 1311// Generic system instructions 1312def SYSxt : SystemXtI<0, "sys">; 1313def SYSLxt : SystemLXtI<1, "sysl">; 1314 1315def : InstAlias<"sys $op1, $Cn, $Cm, $op2", 1316 (SYSxt imm0_7:$op1, sys_cr_op:$Cn, 1317 sys_cr_op:$Cm, imm0_7:$op2, XZR)>; 1318 1319 1320let Predicates = [HasTME] in { 1321 1322def TSTART : TMSystemI<0b0000, "tstart", 1323 [(set GPR64:$Rt, (int_aarch64_tstart))]>; 1324 1325def TCOMMIT : TMSystemINoOperand<0b0000, "tcommit", [(int_aarch64_tcommit)]>; 1326 1327def TCANCEL : TMSystemException<0b011, "tcancel", 1328 [(int_aarch64_tcancel i64_imm0_65535:$imm)]>; 1329 1330def TTEST : TMSystemI<0b0001, "ttest", [(set GPR64:$Rt, (int_aarch64_ttest))]> { 1331 let mayLoad = 0; 1332 let mayStore = 0; 1333} 1334} // HasTME 1335 1336//===----------------------------------------------------------------------===// 1337// Move immediate instructions. 1338//===----------------------------------------------------------------------===// 1339 1340defm MOVK : InsertImmediate<0b11, "movk">; 1341defm MOVN : MoveImmediate<0b00, "movn">; 1342 1343let PostEncoderMethod = "fixMOVZ" in 1344defm MOVZ : MoveImmediate<0b10, "movz">; 1345 1346// First group of aliases covers an implicit "lsl #0". 1347def : InstAlias<"movk $dst, $imm", (MOVKWi GPR32:$dst, i32_imm0_65535:$imm, 0), 0>; 1348def : InstAlias<"movk $dst, $imm", (MOVKXi GPR64:$dst, i32_imm0_65535:$imm, 0), 0>; 1349def : InstAlias<"movn $dst, $imm", (MOVNWi GPR32:$dst, i32_imm0_65535:$imm, 0)>; 1350def : InstAlias<"movn $dst, $imm", (MOVNXi GPR64:$dst, i32_imm0_65535:$imm, 0)>; 1351def : InstAlias<"movz $dst, $imm", (MOVZWi GPR32:$dst, i32_imm0_65535:$imm, 0)>; 1352def : InstAlias<"movz $dst, $imm", (MOVZXi GPR64:$dst, i32_imm0_65535:$imm, 0)>; 1353 1354// Next, we have various ELF relocations with the ":XYZ_g0:sym" syntax. 1355def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movw_symbol_g3:$sym, 48)>; 1356def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movw_symbol_g2:$sym, 32)>; 1357def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movw_symbol_g1:$sym, 16)>; 1358def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movw_symbol_g0:$sym, 0)>; 1359 1360def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movw_symbol_g3:$sym, 48)>; 1361def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movw_symbol_g2:$sym, 32)>; 1362def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movw_symbol_g1:$sym, 16)>; 1363def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movw_symbol_g0:$sym, 0)>; 1364 1365def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movw_symbol_g3:$sym, 48), 0>; 1366def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movw_symbol_g2:$sym, 32), 0>; 1367def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movw_symbol_g1:$sym, 16), 0>; 1368def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movw_symbol_g0:$sym, 0), 0>; 1369 1370def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movw_symbol_g1:$sym, 16)>; 1371def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movw_symbol_g0:$sym, 0)>; 1372 1373def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movw_symbol_g1:$sym, 16)>; 1374def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movw_symbol_g0:$sym, 0)>; 1375 1376def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movw_symbol_g1:$sym, 16), 0>; 1377def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movw_symbol_g0:$sym, 0), 0>; 1378 1379// Final group of aliases covers true "mov $Rd, $imm" cases. 1380multiclass movw_mov_alias<string basename,Instruction INST, RegisterClass GPR, 1381 int width, int shift> { 1382 def _asmoperand : AsmOperandClass { 1383 let Name = basename # width # "_lsl" # shift # "MovAlias"; 1384 let PredicateMethod = "is" # basename # "MovAlias<" # width # ", " 1385 # shift # ">"; 1386 let RenderMethod = "add" # basename # "MovAliasOperands<" # shift # ">"; 1387 } 1388 1389 def _movimm : Operand<i32> { 1390 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_asmoperand"); 1391 } 1392 1393 def : InstAlias<"mov $Rd, $imm", 1394 (INST GPR:$Rd, !cast<Operand>(NAME # "_movimm"):$imm, shift)>; 1395} 1396 1397defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 0>; 1398defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 16>; 1399 1400defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 0>; 1401defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 16>; 1402defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 32>; 1403defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 48>; 1404 1405defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 0>; 1406defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 16>; 1407 1408defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 0>; 1409defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 16>; 1410defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 32>; 1411defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 48>; 1412 1413let isReMaterializable = 1, isCodeGenOnly = 1, isMoveImm = 1, 1414 isAsCheapAsAMove = 1 in { 1415// FIXME: The following pseudo instructions are only needed because remat 1416// cannot handle multiple instructions. When that changes, we can select 1417// directly to the real instructions and get rid of these pseudos. 1418 1419def MOVi32imm 1420 : Pseudo<(outs GPR32:$dst), (ins i32imm:$src), 1421 [(set GPR32:$dst, imm:$src)]>, 1422 Sched<[WriteImm]>; 1423def MOVi64imm 1424 : Pseudo<(outs GPR64:$dst), (ins i64imm:$src), 1425 [(set GPR64:$dst, imm:$src)]>, 1426 Sched<[WriteImm]>; 1427} // isReMaterializable, isCodeGenOnly 1428 1429// If possible, we want to use MOVi32imm even for 64-bit moves. This gives the 1430// eventual expansion code fewer bits to worry about getting right. Marshalling 1431// the types is a little tricky though: 1432def i64imm_32bit : ImmLeaf<i64, [{ 1433 return (Imm & 0xffffffffULL) == static_cast<uint64_t>(Imm); 1434}]>; 1435 1436def s64imm_32bit : ImmLeaf<i64, [{ 1437 int64_t Imm64 = static_cast<int64_t>(Imm); 1438 return Imm64 >= std::numeric_limits<int32_t>::min() && 1439 Imm64 <= std::numeric_limits<int32_t>::max(); 1440}]>; 1441 1442def trunc_imm : SDNodeXForm<imm, [{ 1443 return CurDAG->getTargetConstant(N->getZExtValue(), SDLoc(N), MVT::i32); 1444}]>; 1445 1446def gi_trunc_imm : GICustomOperandRenderer<"renderTruncImm">, 1447 GISDNodeXFormEquiv<trunc_imm>; 1448 1449let Predicates = [OptimizedGISelOrOtherSelector] in { 1450// The SUBREG_TO_REG isn't eliminated at -O0, which can result in pointless 1451// copies. 1452def : Pat<(i64 i64imm_32bit:$src), 1453 (SUBREG_TO_REG (i64 0), (MOVi32imm (trunc_imm imm:$src)), sub_32)>; 1454} 1455 1456// Materialize FP constants via MOVi32imm/MOVi64imm (MachO large code model). 1457def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{ 1458return CurDAG->getTargetConstant( 1459 N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i32); 1460}]>; 1461 1462def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{ 1463return CurDAG->getTargetConstant( 1464 N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i64); 1465}]>; 1466 1467 1468def : Pat<(f32 fpimm:$in), 1469 (COPY_TO_REGCLASS (MOVi32imm (bitcast_fpimm_to_i32 f32:$in)), FPR32)>; 1470def : Pat<(f64 fpimm:$in), 1471 (COPY_TO_REGCLASS (MOVi64imm (bitcast_fpimm_to_i64 f64:$in)), FPR64)>; 1472 1473 1474// Deal with the various forms of (ELF) large addressing with MOVZ/MOVK 1475// sequences. 1476def : Pat<(AArch64WrapperLarge tglobaladdr:$g3, tglobaladdr:$g2, 1477 tglobaladdr:$g1, tglobaladdr:$g0), 1478 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tglobaladdr:$g0, 0), 1479 tglobaladdr:$g1, 16), 1480 tglobaladdr:$g2, 32), 1481 tglobaladdr:$g3, 48)>; 1482 1483def : Pat<(AArch64WrapperLarge tblockaddress:$g3, tblockaddress:$g2, 1484 tblockaddress:$g1, tblockaddress:$g0), 1485 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tblockaddress:$g0, 0), 1486 tblockaddress:$g1, 16), 1487 tblockaddress:$g2, 32), 1488 tblockaddress:$g3, 48)>; 1489 1490def : Pat<(AArch64WrapperLarge tconstpool:$g3, tconstpool:$g2, 1491 tconstpool:$g1, tconstpool:$g0), 1492 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tconstpool:$g0, 0), 1493 tconstpool:$g1, 16), 1494 tconstpool:$g2, 32), 1495 tconstpool:$g3, 48)>; 1496 1497def : Pat<(AArch64WrapperLarge tjumptable:$g3, tjumptable:$g2, 1498 tjumptable:$g1, tjumptable:$g0), 1499 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tjumptable:$g0, 0), 1500 tjumptable:$g1, 16), 1501 tjumptable:$g2, 32), 1502 tjumptable:$g3, 48)>; 1503 1504 1505//===----------------------------------------------------------------------===// 1506// Arithmetic instructions. 1507//===----------------------------------------------------------------------===// 1508 1509// Add/subtract with carry. 1510defm ADC : AddSubCarry<0, "adc", "adcs", AArch64adc, AArch64adc_flag>; 1511defm SBC : AddSubCarry<1, "sbc", "sbcs", AArch64sbc, AArch64sbc_flag>; 1512 1513def : InstAlias<"ngc $dst, $src", (SBCWr GPR32:$dst, WZR, GPR32:$src)>; 1514def : InstAlias<"ngc $dst, $src", (SBCXr GPR64:$dst, XZR, GPR64:$src)>; 1515def : InstAlias<"ngcs $dst, $src", (SBCSWr GPR32:$dst, WZR, GPR32:$src)>; 1516def : InstAlias<"ngcs $dst, $src", (SBCSXr GPR64:$dst, XZR, GPR64:$src)>; 1517 1518// Add/subtract 1519defm ADD : AddSub<0, "add", "sub", add>; 1520defm SUB : AddSub<1, "sub", "add">; 1521 1522def : InstAlias<"mov $dst, $src", 1523 (ADDWri GPR32sponly:$dst, GPR32sp:$src, 0, 0)>; 1524def : InstAlias<"mov $dst, $src", 1525 (ADDWri GPR32sp:$dst, GPR32sponly:$src, 0, 0)>; 1526def : InstAlias<"mov $dst, $src", 1527 (ADDXri GPR64sponly:$dst, GPR64sp:$src, 0, 0)>; 1528def : InstAlias<"mov $dst, $src", 1529 (ADDXri GPR64sp:$dst, GPR64sponly:$src, 0, 0)>; 1530 1531defm ADDS : AddSubS<0, "adds", AArch64add_flag, "cmn", "subs", "cmp">; 1532defm SUBS : AddSubS<1, "subs", AArch64sub_flag, "cmp", "adds", "cmn">; 1533 1534// Use SUBS instead of SUB to enable CSE between SUBS and SUB. 1535def : Pat<(sub GPR32sp:$Rn, addsub_shifted_imm32:$imm), 1536 (SUBSWri GPR32sp:$Rn, addsub_shifted_imm32:$imm)>; 1537def : Pat<(sub GPR64sp:$Rn, addsub_shifted_imm64:$imm), 1538 (SUBSXri GPR64sp:$Rn, addsub_shifted_imm64:$imm)>; 1539def : Pat<(sub GPR32:$Rn, GPR32:$Rm), 1540 (SUBSWrr GPR32:$Rn, GPR32:$Rm)>; 1541def : Pat<(sub GPR64:$Rn, GPR64:$Rm), 1542 (SUBSXrr GPR64:$Rn, GPR64:$Rm)>; 1543def : Pat<(sub GPR32:$Rn, arith_shifted_reg32:$Rm), 1544 (SUBSWrs GPR32:$Rn, arith_shifted_reg32:$Rm)>; 1545def : Pat<(sub GPR64:$Rn, arith_shifted_reg64:$Rm), 1546 (SUBSXrs GPR64:$Rn, arith_shifted_reg64:$Rm)>; 1547let AddedComplexity = 1 in { 1548def : Pat<(sub GPR32sp:$R2, arith_extended_reg32_i32:$R3), 1549 (SUBSWrx GPR32sp:$R2, arith_extended_reg32_i32:$R3)>; 1550def : Pat<(sub GPR64sp:$R2, arith_extended_reg32to64_i64:$R3), 1551 (SUBSXrx GPR64sp:$R2, arith_extended_reg32to64_i64:$R3)>; 1552} 1553 1554// Because of the immediate format for add/sub-imm instructions, the 1555// expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1). 1556// These patterns capture that transformation. 1557let AddedComplexity = 1 in { 1558def : Pat<(add GPR32:$Rn, neg_addsub_shifted_imm32:$imm), 1559 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>; 1560def : Pat<(add GPR64:$Rn, neg_addsub_shifted_imm64:$imm), 1561 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>; 1562def : Pat<(sub GPR32:$Rn, neg_addsub_shifted_imm32:$imm), 1563 (ADDWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>; 1564def : Pat<(sub GPR64:$Rn, neg_addsub_shifted_imm64:$imm), 1565 (ADDXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>; 1566} 1567 1568// Because of the immediate format for add/sub-imm instructions, the 1569// expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1). 1570// These patterns capture that transformation. 1571let AddedComplexity = 1 in { 1572def : Pat<(AArch64add_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm), 1573 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>; 1574def : Pat<(AArch64add_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm), 1575 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>; 1576def : Pat<(AArch64sub_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm), 1577 (ADDSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>; 1578def : Pat<(AArch64sub_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm), 1579 (ADDSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>; 1580} 1581 1582def : InstAlias<"neg $dst, $src", (SUBWrs GPR32:$dst, WZR, GPR32:$src, 0), 3>; 1583def : InstAlias<"neg $dst, $src", (SUBXrs GPR64:$dst, XZR, GPR64:$src, 0), 3>; 1584def : InstAlias<"neg $dst, $src$shift", 1585 (SUBWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift), 2>; 1586def : InstAlias<"neg $dst, $src$shift", 1587 (SUBXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift), 2>; 1588 1589def : InstAlias<"negs $dst, $src", (SUBSWrs GPR32:$dst, WZR, GPR32:$src, 0), 3>; 1590def : InstAlias<"negs $dst, $src", (SUBSXrs GPR64:$dst, XZR, GPR64:$src, 0), 3>; 1591def : InstAlias<"negs $dst, $src$shift", 1592 (SUBSWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift), 2>; 1593def : InstAlias<"negs $dst, $src$shift", 1594 (SUBSXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift), 2>; 1595 1596 1597// Unsigned/Signed divide 1598defm UDIV : Div<0, "udiv", udiv>; 1599defm SDIV : Div<1, "sdiv", sdiv>; 1600 1601def : Pat<(int_aarch64_udiv GPR32:$Rn, GPR32:$Rm), (UDIVWr GPR32:$Rn, GPR32:$Rm)>; 1602def : Pat<(int_aarch64_udiv GPR64:$Rn, GPR64:$Rm), (UDIVXr GPR64:$Rn, GPR64:$Rm)>; 1603def : Pat<(int_aarch64_sdiv GPR32:$Rn, GPR32:$Rm), (SDIVWr GPR32:$Rn, GPR32:$Rm)>; 1604def : Pat<(int_aarch64_sdiv GPR64:$Rn, GPR64:$Rm), (SDIVXr GPR64:$Rn, GPR64:$Rm)>; 1605 1606// Variable shift 1607defm ASRV : Shift<0b10, "asr", sra>; 1608defm LSLV : Shift<0b00, "lsl", shl>; 1609defm LSRV : Shift<0b01, "lsr", srl>; 1610defm RORV : Shift<0b11, "ror", rotr>; 1611 1612def : ShiftAlias<"asrv", ASRVWr, GPR32>; 1613def : ShiftAlias<"asrv", ASRVXr, GPR64>; 1614def : ShiftAlias<"lslv", LSLVWr, GPR32>; 1615def : ShiftAlias<"lslv", LSLVXr, GPR64>; 1616def : ShiftAlias<"lsrv", LSRVWr, GPR32>; 1617def : ShiftAlias<"lsrv", LSRVXr, GPR64>; 1618def : ShiftAlias<"rorv", RORVWr, GPR32>; 1619def : ShiftAlias<"rorv", RORVXr, GPR64>; 1620 1621// Multiply-add 1622let AddedComplexity = 5 in { 1623defm MADD : MulAccum<0, "madd", add>; 1624defm MSUB : MulAccum<1, "msub", sub>; 1625 1626def : Pat<(i32 (mul GPR32:$Rn, GPR32:$Rm)), 1627 (MADDWrrr GPR32:$Rn, GPR32:$Rm, WZR)>; 1628def : Pat<(i64 (mul GPR64:$Rn, GPR64:$Rm)), 1629 (MADDXrrr GPR64:$Rn, GPR64:$Rm, XZR)>; 1630 1631def : Pat<(i32 (ineg (mul GPR32:$Rn, GPR32:$Rm))), 1632 (MSUBWrrr GPR32:$Rn, GPR32:$Rm, WZR)>; 1633def : Pat<(i64 (ineg (mul GPR64:$Rn, GPR64:$Rm))), 1634 (MSUBXrrr GPR64:$Rn, GPR64:$Rm, XZR)>; 1635def : Pat<(i32 (mul (ineg GPR32:$Rn), GPR32:$Rm)), 1636 (MSUBWrrr GPR32:$Rn, GPR32:$Rm, WZR)>; 1637def : Pat<(i64 (mul (ineg GPR64:$Rn), GPR64:$Rm)), 1638 (MSUBXrrr GPR64:$Rn, GPR64:$Rm, XZR)>; 1639} // AddedComplexity = 5 1640 1641let AddedComplexity = 5 in { 1642def SMADDLrrr : WideMulAccum<0, 0b001, "smaddl", add, sext>; 1643def SMSUBLrrr : WideMulAccum<1, 0b001, "smsubl", sub, sext>; 1644def UMADDLrrr : WideMulAccum<0, 0b101, "umaddl", add, zext>; 1645def UMSUBLrrr : WideMulAccum<1, 0b101, "umsubl", sub, zext>; 1646 1647def : Pat<(i64 (mul (sext_inreg GPR64:$Rn, i32), (sext_inreg GPR64:$Rm, i32))), 1648 (SMADDLrrr (EXTRACT_SUBREG $Rn, sub_32), (EXTRACT_SUBREG $Rm, sub_32), XZR)>; 1649def : Pat<(i64 (mul (sext_inreg GPR64:$Rn, i32), (sext GPR32:$Rm))), 1650 (SMADDLrrr (EXTRACT_SUBREG $Rn, sub_32), $Rm, XZR)>; 1651def : Pat<(i64 (mul (sext GPR32:$Rn), (sext GPR32:$Rm))), 1652 (SMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>; 1653def : Pat<(i64 (mul (and GPR64:$Rn, 0xFFFFFFFF), (and GPR64:$Rm, 0xFFFFFFFF))), 1654 (UMADDLrrr (EXTRACT_SUBREG $Rn, sub_32), (EXTRACT_SUBREG $Rm, sub_32), XZR)>; 1655def : Pat<(i64 (mul (and GPR64:$Rn, 0xFFFFFFFF), (zext GPR32:$Rm))), 1656 (UMADDLrrr (EXTRACT_SUBREG $Rn, sub_32), $Rm, XZR)>; 1657def : Pat<(i64 (mul (zext GPR32:$Rn), (zext GPR32:$Rm))), 1658 (UMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>; 1659 1660def : Pat<(i64 (ineg (mul (sext GPR32:$Rn), (sext GPR32:$Rm)))), 1661 (SMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>; 1662def : Pat<(i64 (ineg (mul (zext GPR32:$Rn), (zext GPR32:$Rm)))), 1663 (UMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>; 1664 1665def : Pat<(i64 (mul (sext GPR32:$Rn), (s64imm_32bit:$C))), 1666 (SMADDLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), XZR)>; 1667def : Pat<(i64 (mul (zext GPR32:$Rn), (i64imm_32bit:$C))), 1668 (UMADDLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), XZR)>; 1669def : Pat<(i64 (mul (sext_inreg GPR64:$Rn, i32), (s64imm_32bit:$C))), 1670 (SMADDLrrr (i32 (EXTRACT_SUBREG GPR64:$Rn, sub_32)), 1671 (MOVi32imm (trunc_imm imm:$C)), XZR)>; 1672 1673def : Pat<(i64 (ineg (mul (sext GPR32:$Rn), (s64imm_32bit:$C)))), 1674 (SMSUBLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), XZR)>; 1675def : Pat<(i64 (ineg (mul (zext GPR32:$Rn), (i64imm_32bit:$C)))), 1676 (UMSUBLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), XZR)>; 1677def : Pat<(i64 (ineg (mul (sext_inreg GPR64:$Rn, i32), (s64imm_32bit:$C)))), 1678 (SMSUBLrrr (i32 (EXTRACT_SUBREG GPR64:$Rn, sub_32)), 1679 (MOVi32imm (trunc_imm imm:$C)), XZR)>; 1680 1681def : Pat<(i64 (add (mul (sext GPR32:$Rn), (s64imm_32bit:$C)), GPR64:$Ra)), 1682 (SMADDLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), GPR64:$Ra)>; 1683def : Pat<(i64 (add (mul (zext GPR32:$Rn), (i64imm_32bit:$C)), GPR64:$Ra)), 1684 (UMADDLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), GPR64:$Ra)>; 1685def : Pat<(i64 (add (mul (sext_inreg GPR64:$Rn, i32), (s64imm_32bit:$C)), 1686 GPR64:$Ra)), 1687 (SMADDLrrr (i32 (EXTRACT_SUBREG GPR64:$Rn, sub_32)), 1688 (MOVi32imm (trunc_imm imm:$C)), GPR64:$Ra)>; 1689 1690def : Pat<(i64 (sub GPR64:$Ra, (mul (sext GPR32:$Rn), (s64imm_32bit:$C)))), 1691 (SMSUBLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), GPR64:$Ra)>; 1692def : Pat<(i64 (sub GPR64:$Ra, (mul (zext GPR32:$Rn), (i64imm_32bit:$C)))), 1693 (UMSUBLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), GPR64:$Ra)>; 1694def : Pat<(i64 (sub GPR64:$Ra, (mul (sext_inreg GPR64:$Rn, i32), 1695 (s64imm_32bit:$C)))), 1696 (SMSUBLrrr (i32 (EXTRACT_SUBREG GPR64:$Rn, sub_32)), 1697 (MOVi32imm (trunc_imm imm:$C)), GPR64:$Ra)>; 1698} // AddedComplexity = 5 1699 1700def : MulAccumWAlias<"mul", MADDWrrr>; 1701def : MulAccumXAlias<"mul", MADDXrrr>; 1702def : MulAccumWAlias<"mneg", MSUBWrrr>; 1703def : MulAccumXAlias<"mneg", MSUBXrrr>; 1704def : WideMulAccumAlias<"smull", SMADDLrrr>; 1705def : WideMulAccumAlias<"smnegl", SMSUBLrrr>; 1706def : WideMulAccumAlias<"umull", UMADDLrrr>; 1707def : WideMulAccumAlias<"umnegl", UMSUBLrrr>; 1708 1709// Multiply-high 1710def SMULHrr : MulHi<0b010, "smulh", mulhs>; 1711def UMULHrr : MulHi<0b110, "umulh", mulhu>; 1712 1713// CRC32 1714def CRC32Brr : BaseCRC32<0, 0b00, 0, GPR32, int_aarch64_crc32b, "crc32b">; 1715def CRC32Hrr : BaseCRC32<0, 0b01, 0, GPR32, int_aarch64_crc32h, "crc32h">; 1716def CRC32Wrr : BaseCRC32<0, 0b10, 0, GPR32, int_aarch64_crc32w, "crc32w">; 1717def CRC32Xrr : BaseCRC32<1, 0b11, 0, GPR64, int_aarch64_crc32x, "crc32x">; 1718 1719def CRC32CBrr : BaseCRC32<0, 0b00, 1, GPR32, int_aarch64_crc32cb, "crc32cb">; 1720def CRC32CHrr : BaseCRC32<0, 0b01, 1, GPR32, int_aarch64_crc32ch, "crc32ch">; 1721def CRC32CWrr : BaseCRC32<0, 0b10, 1, GPR32, int_aarch64_crc32cw, "crc32cw">; 1722def CRC32CXrr : BaseCRC32<1, 0b11, 1, GPR64, int_aarch64_crc32cx, "crc32cx">; 1723 1724// v8.1 atomic CAS 1725defm CAS : CompareAndSwap<0, 0, "">; 1726defm CASA : CompareAndSwap<1, 0, "a">; 1727defm CASL : CompareAndSwap<0, 1, "l">; 1728defm CASAL : CompareAndSwap<1, 1, "al">; 1729 1730// v8.1 atomic CASP 1731defm CASP : CompareAndSwapPair<0, 0, "">; 1732defm CASPA : CompareAndSwapPair<1, 0, "a">; 1733defm CASPL : CompareAndSwapPair<0, 1, "l">; 1734defm CASPAL : CompareAndSwapPair<1, 1, "al">; 1735 1736// v8.1 atomic SWP 1737defm SWP : Swap<0, 0, "">; 1738defm SWPA : Swap<1, 0, "a">; 1739defm SWPL : Swap<0, 1, "l">; 1740defm SWPAL : Swap<1, 1, "al">; 1741 1742// v8.1 atomic LD<OP>(register). Performs load and then ST<OP>(register) 1743defm LDADD : LDOPregister<0b000, "add", 0, 0, "">; 1744defm LDADDA : LDOPregister<0b000, "add", 1, 0, "a">; 1745defm LDADDL : LDOPregister<0b000, "add", 0, 1, "l">; 1746defm LDADDAL : LDOPregister<0b000, "add", 1, 1, "al">; 1747 1748defm LDCLR : LDOPregister<0b001, "clr", 0, 0, "">; 1749defm LDCLRA : LDOPregister<0b001, "clr", 1, 0, "a">; 1750defm LDCLRL : LDOPregister<0b001, "clr", 0, 1, "l">; 1751defm LDCLRAL : LDOPregister<0b001, "clr", 1, 1, "al">; 1752 1753defm LDEOR : LDOPregister<0b010, "eor", 0, 0, "">; 1754defm LDEORA : LDOPregister<0b010, "eor", 1, 0, "a">; 1755defm LDEORL : LDOPregister<0b010, "eor", 0, 1, "l">; 1756defm LDEORAL : LDOPregister<0b010, "eor", 1, 1, "al">; 1757 1758defm LDSET : LDOPregister<0b011, "set", 0, 0, "">; 1759defm LDSETA : LDOPregister<0b011, "set", 1, 0, "a">; 1760defm LDSETL : LDOPregister<0b011, "set", 0, 1, "l">; 1761defm LDSETAL : LDOPregister<0b011, "set", 1, 1, "al">; 1762 1763defm LDSMAX : LDOPregister<0b100, "smax", 0, 0, "">; 1764defm LDSMAXA : LDOPregister<0b100, "smax", 1, 0, "a">; 1765defm LDSMAXL : LDOPregister<0b100, "smax", 0, 1, "l">; 1766defm LDSMAXAL : LDOPregister<0b100, "smax", 1, 1, "al">; 1767 1768defm LDSMIN : LDOPregister<0b101, "smin", 0, 0, "">; 1769defm LDSMINA : LDOPregister<0b101, "smin", 1, 0, "a">; 1770defm LDSMINL : LDOPregister<0b101, "smin", 0, 1, "l">; 1771defm LDSMINAL : LDOPregister<0b101, "smin", 1, 1, "al">; 1772 1773defm LDUMAX : LDOPregister<0b110, "umax", 0, 0, "">; 1774defm LDUMAXA : LDOPregister<0b110, "umax", 1, 0, "a">; 1775defm LDUMAXL : LDOPregister<0b110, "umax", 0, 1, "l">; 1776defm LDUMAXAL : LDOPregister<0b110, "umax", 1, 1, "al">; 1777 1778defm LDUMIN : LDOPregister<0b111, "umin", 0, 0, "">; 1779defm LDUMINA : LDOPregister<0b111, "umin", 1, 0, "a">; 1780defm LDUMINL : LDOPregister<0b111, "umin", 0, 1, "l">; 1781defm LDUMINAL : LDOPregister<0b111, "umin", 1, 1, "al">; 1782 1783// v8.1 atomic ST<OP>(register) as aliases to "LD<OP>(register) when Rt=xZR" 1784defm : STOPregister<"stadd","LDADD">; // STADDx 1785defm : STOPregister<"stclr","LDCLR">; // STCLRx 1786defm : STOPregister<"steor","LDEOR">; // STEORx 1787defm : STOPregister<"stset","LDSET">; // STSETx 1788defm : STOPregister<"stsmax","LDSMAX">;// STSMAXx 1789defm : STOPregister<"stsmin","LDSMIN">;// STSMINx 1790defm : STOPregister<"stumax","LDUMAX">;// STUMAXx 1791defm : STOPregister<"stumin","LDUMIN">;// STUMINx 1792 1793// v8.5 Memory Tagging Extension 1794let Predicates = [HasMTE] in { 1795 1796def IRG : BaseTwoOperand<0b0100, GPR64sp, "irg", int_aarch64_irg, GPR64sp, GPR64>, 1797 Sched<[]>{ 1798 let Inst{31} = 1; 1799} 1800def GMI : BaseTwoOperand<0b0101, GPR64, "gmi", int_aarch64_gmi, GPR64sp>, Sched<[]>{ 1801 let Inst{31} = 1; 1802 let isNotDuplicable = 1; 1803} 1804def ADDG : AddSubG<0, "addg", null_frag>; 1805def SUBG : AddSubG<1, "subg", null_frag>; 1806 1807def : InstAlias<"irg $dst, $src", (IRG GPR64sp:$dst, GPR64sp:$src, XZR), 1>; 1808 1809def SUBP : SUBP<0, "subp", int_aarch64_subp>, Sched<[]>; 1810def SUBPS : SUBP<1, "subps", null_frag>, Sched<[]>{ 1811 let Defs = [NZCV]; 1812} 1813 1814def : InstAlias<"cmpp $lhs, $rhs", (SUBPS XZR, GPR64sp:$lhs, GPR64sp:$rhs), 0>; 1815 1816def LDG : MemTagLoad<"ldg", "\t$Rt, [$Rn, $offset]">; 1817 1818def : Pat<(int_aarch64_addg (am_indexedu6s128 GPR64sp:$Rn, uimm6s16:$imm6), imm0_15:$imm4), 1819 (ADDG GPR64sp:$Rn, imm0_63:$imm6, imm0_15:$imm4)>; 1820def : Pat<(int_aarch64_ldg GPR64:$Rt, (am_indexeds9s128 GPR64sp:$Rn, simm9s16:$offset)), 1821 (LDG GPR64:$Rt, GPR64sp:$Rn, simm9s16:$offset)>; 1822 1823def : InstAlias<"ldg $Rt, [$Rn]", (LDG GPR64:$Rt, GPR64sp:$Rn, 0), 1>; 1824 1825def LDGM : MemTagVector<1, "ldgm", "\t$Rt, [$Rn]", 1826 (outs GPR64:$Rt), (ins GPR64sp:$Rn)>; 1827def STGM : MemTagVector<0, "stgm", "\t$Rt, [$Rn]", 1828 (outs), (ins GPR64:$Rt, GPR64sp:$Rn)>; 1829def STZGM : MemTagVector<0, "stzgm", "\t$Rt, [$Rn]", 1830 (outs), (ins GPR64:$Rt, GPR64sp:$Rn)> { 1831 let Inst{23} = 0; 1832} 1833 1834defm STG : MemTagStore<0b00, "stg">; 1835defm STZG : MemTagStore<0b01, "stzg">; 1836defm ST2G : MemTagStore<0b10, "st2g">; 1837defm STZ2G : MemTagStore<0b11, "stz2g">; 1838 1839def : Pat<(AArch64stg GPR64sp:$Rn, (am_indexeds9s128 GPR64sp:$Rm, simm9s16:$imm)), 1840 (STGOffset $Rn, $Rm, $imm)>; 1841def : Pat<(AArch64stzg GPR64sp:$Rn, (am_indexeds9s128 GPR64sp:$Rm, simm9s16:$imm)), 1842 (STZGOffset $Rn, $Rm, $imm)>; 1843def : Pat<(AArch64st2g GPR64sp:$Rn, (am_indexeds9s128 GPR64sp:$Rm, simm9s16:$imm)), 1844 (ST2GOffset $Rn, $Rm, $imm)>; 1845def : Pat<(AArch64stz2g GPR64sp:$Rn, (am_indexeds9s128 GPR64sp:$Rm, simm9s16:$imm)), 1846 (STZ2GOffset $Rn, $Rm, $imm)>; 1847 1848defm STGP : StorePairOffset <0b01, 0, GPR64z, simm7s16, "stgp">; 1849def STGPpre : StorePairPreIdx <0b01, 0, GPR64z, simm7s16, "stgp">; 1850def STGPpost : StorePairPostIdx<0b01, 0, GPR64z, simm7s16, "stgp">; 1851 1852def : Pat<(int_aarch64_stg GPR64:$Rt, (am_indexeds9s128 GPR64sp:$Rn, simm9s16:$offset)), 1853 (STGOffset GPR64:$Rt, GPR64sp:$Rn, simm9s16:$offset)>; 1854 1855def : Pat<(int_aarch64_stgp (am_indexed7s128 GPR64sp:$Rn, simm7s16:$imm), GPR64:$Rt, GPR64:$Rt2), 1856 (STGPi $Rt, $Rt2, $Rn, $imm)>; 1857 1858def IRGstack 1859 : Pseudo<(outs GPR64sp:$Rd), (ins GPR64sp:$Rsp, GPR64:$Rm), []>, 1860 Sched<[]>; 1861def TAGPstack 1862 : Pseudo<(outs GPR64sp:$Rd), (ins GPR64sp:$Rn, uimm6s16:$imm6, GPR64sp:$Rm, imm0_15:$imm4), []>, 1863 Sched<[]>; 1864 1865// Explicit SP in the first operand prevents ShrinkWrap optimization 1866// from leaving this instruction out of the stack frame. When IRGstack 1867// is transformed into IRG, this operand is replaced with the actual 1868// register / expression for the tagged base pointer of the current function. 1869def : Pat<(int_aarch64_irg_sp i64:$Rm), (IRGstack SP, i64:$Rm)>; 1870 1871// Large STG to be expanded into a loop. $sz is the size, $Rn is start address. 1872// $Rn_wback is one past the end of the range. $Rm is the loop counter. 1873let isCodeGenOnly=1, mayStore=1 in { 1874def STGloop_wback 1875 : Pseudo<(outs GPR64common:$Rm, GPR64sp:$Rn_wback), (ins i64imm:$sz, GPR64sp:$Rn), 1876 [], "$Rn = $Rn_wback,@earlyclobber $Rn_wback,@earlyclobber $Rm" >, 1877 Sched<[WriteAdr, WriteST]>; 1878 1879def STZGloop_wback 1880 : Pseudo<(outs GPR64common:$Rm, GPR64sp:$Rn_wback), (ins i64imm:$sz, GPR64sp:$Rn), 1881 [], "$Rn = $Rn_wback,@earlyclobber $Rn_wback,@earlyclobber $Rm" >, 1882 Sched<[WriteAdr, WriteST]>; 1883 1884// A variant of the above where $Rn2 is an independent register not tied to the input register $Rn. 1885// Their purpose is to use a FrameIndex operand as $Rn (which of course can not be written back). 1886def STGloop 1887 : Pseudo<(outs GPR64common:$Rm, GPR64sp:$Rn2), (ins i64imm:$sz, GPR64sp:$Rn), 1888 [], "@earlyclobber $Rn2,@earlyclobber $Rm" >, 1889 Sched<[WriteAdr, WriteST]>; 1890 1891def STZGloop 1892 : Pseudo<(outs GPR64common:$Rm, GPR64sp:$Rn2), (ins i64imm:$sz, GPR64sp:$Rn), 1893 [], "@earlyclobber $Rn2,@earlyclobber $Rm" >, 1894 Sched<[WriteAdr, WriteST]>; 1895} 1896 1897} // Predicates = [HasMTE] 1898 1899//===----------------------------------------------------------------------===// 1900// Logical instructions. 1901//===----------------------------------------------------------------------===// 1902 1903// (immediate) 1904defm ANDS : LogicalImmS<0b11, "ands", AArch64and_flag, "bics">; 1905defm AND : LogicalImm<0b00, "and", and, "bic">; 1906defm EOR : LogicalImm<0b10, "eor", xor, "eon">; 1907defm ORR : LogicalImm<0b01, "orr", or, "orn">; 1908 1909// FIXME: these aliases *are* canonical sometimes (when movz can't be 1910// used). Actually, it seems to be working right now, but putting logical_immXX 1911// here is a bit dodgy on the AsmParser side too. 1912def : InstAlias<"mov $dst, $imm", (ORRWri GPR32sp:$dst, WZR, 1913 logical_imm32:$imm), 0>; 1914def : InstAlias<"mov $dst, $imm", (ORRXri GPR64sp:$dst, XZR, 1915 logical_imm64:$imm), 0>; 1916 1917 1918// (register) 1919defm ANDS : LogicalRegS<0b11, 0, "ands", AArch64and_flag>; 1920defm BICS : LogicalRegS<0b11, 1, "bics", 1921 BinOpFrag<(AArch64and_flag node:$LHS, (not node:$RHS))>>; 1922defm AND : LogicalReg<0b00, 0, "and", and>; 1923defm BIC : LogicalReg<0b00, 1, "bic", 1924 BinOpFrag<(and node:$LHS, (not node:$RHS))>>; 1925defm EON : LogicalReg<0b10, 1, "eon", 1926 BinOpFrag<(not (xor node:$LHS, node:$RHS))>>; 1927defm EOR : LogicalReg<0b10, 0, "eor", xor>; 1928defm ORN : LogicalReg<0b01, 1, "orn", 1929 BinOpFrag<(or node:$LHS, (not node:$RHS))>>; 1930defm ORR : LogicalReg<0b01, 0, "orr", or>; 1931 1932def : InstAlias<"mov $dst, $src", (ORRWrs GPR32:$dst, WZR, GPR32:$src, 0), 2>; 1933def : InstAlias<"mov $dst, $src", (ORRXrs GPR64:$dst, XZR, GPR64:$src, 0), 2>; 1934 1935def : InstAlias<"mvn $Wd, $Wm", (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, 0), 3>; 1936def : InstAlias<"mvn $Xd, $Xm", (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, 0), 3>; 1937 1938def : InstAlias<"mvn $Wd, $Wm$sh", 1939 (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, logical_shift32:$sh), 2>; 1940def : InstAlias<"mvn $Xd, $Xm$sh", 1941 (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, logical_shift64:$sh), 2>; 1942 1943def : InstAlias<"tst $src1, $src2", 1944 (ANDSWri WZR, GPR32:$src1, logical_imm32:$src2), 2>; 1945def : InstAlias<"tst $src1, $src2", 1946 (ANDSXri XZR, GPR64:$src1, logical_imm64:$src2), 2>; 1947 1948def : InstAlias<"tst $src1, $src2", 1949 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, 0), 3>; 1950def : InstAlias<"tst $src1, $src2", 1951 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, 0), 3>; 1952 1953def : InstAlias<"tst $src1, $src2$sh", 1954 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, logical_shift32:$sh), 2>; 1955def : InstAlias<"tst $src1, $src2$sh", 1956 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, logical_shift64:$sh), 2>; 1957 1958 1959def : Pat<(not GPR32:$Wm), (ORNWrr WZR, GPR32:$Wm)>; 1960def : Pat<(not GPR64:$Xm), (ORNXrr XZR, GPR64:$Xm)>; 1961 1962 1963//===----------------------------------------------------------------------===// 1964// One operand data processing instructions. 1965//===----------------------------------------------------------------------===// 1966 1967defm CLS : OneOperandData<0b101, "cls">; 1968defm CLZ : OneOperandData<0b100, "clz", ctlz>; 1969defm RBIT : OneOperandData<0b000, "rbit", bitreverse>; 1970 1971def REV16Wr : OneWRegData<0b001, "rev16", 1972 UnOpFrag<(rotr (bswap node:$LHS), (i64 16))>>; 1973def REV16Xr : OneXRegData<0b001, "rev16", null_frag>; 1974 1975def : Pat<(cttz GPR32:$Rn), 1976 (CLZWr (RBITWr GPR32:$Rn))>; 1977def : Pat<(cttz GPR64:$Rn), 1978 (CLZXr (RBITXr GPR64:$Rn))>; 1979def : Pat<(ctlz (or (shl (xor (sra GPR32:$Rn, (i64 31)), GPR32:$Rn), (i64 1)), 1980 (i32 1))), 1981 (CLSWr GPR32:$Rn)>; 1982def : Pat<(ctlz (or (shl (xor (sra GPR64:$Rn, (i64 63)), GPR64:$Rn), (i64 1)), 1983 (i64 1))), 1984 (CLSXr GPR64:$Rn)>; 1985def : Pat<(int_aarch64_cls GPR32:$Rn), (CLSWr GPR32:$Rn)>; 1986def : Pat<(int_aarch64_cls64 GPR64:$Rm), (EXTRACT_SUBREG (CLSXr GPR64:$Rm), sub_32)>; 1987 1988// Unlike the other one operand instructions, the instructions with the "rev" 1989// mnemonic do *not* just different in the size bit, but actually use different 1990// opcode bits for the different sizes. 1991def REVWr : OneWRegData<0b010, "rev", bswap>; 1992def REVXr : OneXRegData<0b011, "rev", bswap>; 1993def REV32Xr : OneXRegData<0b010, "rev32", 1994 UnOpFrag<(rotr (bswap node:$LHS), (i64 32))>>; 1995 1996def : InstAlias<"rev64 $Rd, $Rn", (REVXr GPR64:$Rd, GPR64:$Rn), 0>; 1997 1998// The bswap commutes with the rotr so we want a pattern for both possible 1999// orders. 2000def : Pat<(bswap (rotr GPR32:$Rn, (i64 16))), (REV16Wr GPR32:$Rn)>; 2001def : Pat<(bswap (rotr GPR64:$Rn, (i64 32))), (REV32Xr GPR64:$Rn)>; 2002 2003//===----------------------------------------------------------------------===// 2004// Bitfield immediate extraction instruction. 2005//===----------------------------------------------------------------------===// 2006let hasSideEffects = 0 in 2007defm EXTR : ExtractImm<"extr">; 2008def : InstAlias<"ror $dst, $src, $shift", 2009 (EXTRWrri GPR32:$dst, GPR32:$src, GPR32:$src, imm0_31:$shift)>; 2010def : InstAlias<"ror $dst, $src, $shift", 2011 (EXTRXrri GPR64:$dst, GPR64:$src, GPR64:$src, imm0_63:$shift)>; 2012 2013def : Pat<(rotr GPR32:$Rn, (i64 imm0_31:$imm)), 2014 (EXTRWrri GPR32:$Rn, GPR32:$Rn, imm0_31:$imm)>; 2015def : Pat<(rotr GPR64:$Rn, (i64 imm0_63:$imm)), 2016 (EXTRXrri GPR64:$Rn, GPR64:$Rn, imm0_63:$imm)>; 2017 2018//===----------------------------------------------------------------------===// 2019// Other bitfield immediate instructions. 2020//===----------------------------------------------------------------------===// 2021let hasSideEffects = 0 in { 2022defm BFM : BitfieldImmWith2RegArgs<0b01, "bfm">; 2023defm SBFM : BitfieldImm<0b00, "sbfm">; 2024defm UBFM : BitfieldImm<0b10, "ubfm">; 2025} 2026 2027def i32shift_a : Operand<i64>, SDNodeXForm<imm, [{ 2028 uint64_t enc = (32 - N->getZExtValue()) & 0x1f; 2029 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64); 2030}]>; 2031 2032def i32shift_b : Operand<i64>, SDNodeXForm<imm, [{ 2033 uint64_t enc = 31 - N->getZExtValue(); 2034 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64); 2035}]>; 2036 2037// min(7, 31 - shift_amt) 2038def i32shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{ 2039 uint64_t enc = 31 - N->getZExtValue(); 2040 enc = enc > 7 ? 7 : enc; 2041 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64); 2042}]>; 2043 2044// min(15, 31 - shift_amt) 2045def i32shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{ 2046 uint64_t enc = 31 - N->getZExtValue(); 2047 enc = enc > 15 ? 15 : enc; 2048 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64); 2049}]>; 2050 2051def i64shift_a : Operand<i64>, SDNodeXForm<imm, [{ 2052 uint64_t enc = (64 - N->getZExtValue()) & 0x3f; 2053 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64); 2054}]>; 2055 2056def i64shift_b : Operand<i64>, SDNodeXForm<imm, [{ 2057 uint64_t enc = 63 - N->getZExtValue(); 2058 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64); 2059}]>; 2060 2061// min(7, 63 - shift_amt) 2062def i64shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{ 2063 uint64_t enc = 63 - N->getZExtValue(); 2064 enc = enc > 7 ? 7 : enc; 2065 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64); 2066}]>; 2067 2068// min(15, 63 - shift_amt) 2069def i64shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{ 2070 uint64_t enc = 63 - N->getZExtValue(); 2071 enc = enc > 15 ? 15 : enc; 2072 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64); 2073}]>; 2074 2075// min(31, 63 - shift_amt) 2076def i64shift_sext_i32 : Operand<i64>, SDNodeXForm<imm, [{ 2077 uint64_t enc = 63 - N->getZExtValue(); 2078 enc = enc > 31 ? 31 : enc; 2079 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64); 2080}]>; 2081 2082def : Pat<(shl GPR32:$Rn, (i64 imm0_31:$imm)), 2083 (UBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)), 2084 (i64 (i32shift_b imm0_31:$imm)))>; 2085def : Pat<(shl GPR64:$Rn, (i64 imm0_63:$imm)), 2086 (UBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)), 2087 (i64 (i64shift_b imm0_63:$imm)))>; 2088 2089let AddedComplexity = 10 in { 2090def : Pat<(sra GPR32:$Rn, (i64 imm0_31:$imm)), 2091 (SBFMWri GPR32:$Rn, imm0_31:$imm, 31)>; 2092def : Pat<(sra GPR64:$Rn, (i64 imm0_63:$imm)), 2093 (SBFMXri GPR64:$Rn, imm0_63:$imm, 63)>; 2094} 2095 2096def : InstAlias<"asr $dst, $src, $shift", 2097 (SBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>; 2098def : InstAlias<"asr $dst, $src, $shift", 2099 (SBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>; 2100def : InstAlias<"sxtb $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 7)>; 2101def : InstAlias<"sxtb $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 7)>; 2102def : InstAlias<"sxth $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 15)>; 2103def : InstAlias<"sxth $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 15)>; 2104def : InstAlias<"sxtw $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 31)>; 2105 2106def : Pat<(srl GPR32:$Rn, (i64 imm0_31:$imm)), 2107 (UBFMWri GPR32:$Rn, imm0_31:$imm, 31)>; 2108def : Pat<(srl GPR64:$Rn, (i64 imm0_63:$imm)), 2109 (UBFMXri GPR64:$Rn, imm0_63:$imm, 63)>; 2110 2111def : InstAlias<"lsr $dst, $src, $shift", 2112 (UBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>; 2113def : InstAlias<"lsr $dst, $src, $shift", 2114 (UBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>; 2115def : InstAlias<"uxtb $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 7)>; 2116def : InstAlias<"uxtb $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 7)>; 2117def : InstAlias<"uxth $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 15)>; 2118def : InstAlias<"uxth $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 15)>; 2119def : InstAlias<"uxtw $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 31)>; 2120 2121//===----------------------------------------------------------------------===// 2122// Conditional comparison instructions. 2123//===----------------------------------------------------------------------===// 2124defm CCMN : CondComparison<0, "ccmn", AArch64ccmn>; 2125defm CCMP : CondComparison<1, "ccmp", AArch64ccmp>; 2126 2127//===----------------------------------------------------------------------===// 2128// Conditional select instructions. 2129//===----------------------------------------------------------------------===// 2130defm CSEL : CondSelect<0, 0b00, "csel">; 2131 2132def inc : PatFrag<(ops node:$in), (add node:$in, 1)>; 2133defm CSINC : CondSelectOp<0, 0b01, "csinc", inc>; 2134defm CSINV : CondSelectOp<1, 0b00, "csinv", not>; 2135defm CSNEG : CondSelectOp<1, 0b01, "csneg", ineg>; 2136 2137def : Pat<(AArch64csinv GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV), 2138 (CSINVWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>; 2139def : Pat<(AArch64csinv GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV), 2140 (CSINVXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>; 2141def : Pat<(AArch64csneg GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV), 2142 (CSNEGWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>; 2143def : Pat<(AArch64csneg GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV), 2144 (CSNEGXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>; 2145def : Pat<(AArch64csinc GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV), 2146 (CSINCWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>; 2147def : Pat<(AArch64csinc GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV), 2148 (CSINCXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>; 2149 2150def : Pat<(AArch64csel (i32 0), (i32 1), (i32 imm:$cc), NZCV), 2151 (CSINCWr WZR, WZR, (i32 imm:$cc))>; 2152def : Pat<(AArch64csel (i64 0), (i64 1), (i32 imm:$cc), NZCV), 2153 (CSINCXr XZR, XZR, (i32 imm:$cc))>; 2154def : Pat<(AArch64csel GPR32:$tval, (i32 1), (i32 imm:$cc), NZCV), 2155 (CSINCWr GPR32:$tval, WZR, (i32 imm:$cc))>; 2156def : Pat<(AArch64csel GPR64:$tval, (i64 1), (i32 imm:$cc), NZCV), 2157 (CSINCXr GPR64:$tval, XZR, (i32 imm:$cc))>; 2158def : Pat<(AArch64csel (i32 1), GPR32:$fval, (i32 imm:$cc), NZCV), 2159 (CSINCWr GPR32:$fval, WZR, (i32 (inv_cond_XFORM imm:$cc)))>; 2160def : Pat<(AArch64csel (i64 1), GPR64:$fval, (i32 imm:$cc), NZCV), 2161 (CSINCXr GPR64:$fval, XZR, (i32 (inv_cond_XFORM imm:$cc)))>; 2162def : Pat<(AArch64csel (i32 0), (i32 -1), (i32 imm:$cc), NZCV), 2163 (CSINVWr WZR, WZR, (i32 imm:$cc))>; 2164def : Pat<(AArch64csel (i64 0), (i64 -1), (i32 imm:$cc), NZCV), 2165 (CSINVXr XZR, XZR, (i32 imm:$cc))>; 2166def : Pat<(AArch64csel GPR32:$tval, (i32 -1), (i32 imm:$cc), NZCV), 2167 (CSINVWr GPR32:$tval, WZR, (i32 imm:$cc))>; 2168def : Pat<(AArch64csel GPR64:$tval, (i64 -1), (i32 imm:$cc), NZCV), 2169 (CSINVXr GPR64:$tval, XZR, (i32 imm:$cc))>; 2170def : Pat<(AArch64csel (i32 -1), GPR32:$fval, (i32 imm:$cc), NZCV), 2171 (CSINVWr GPR32:$fval, WZR, (i32 (inv_cond_XFORM imm:$cc)))>; 2172def : Pat<(AArch64csel (i64 -1), GPR64:$fval, (i32 imm:$cc), NZCV), 2173 (CSINVXr GPR64:$fval, XZR, (i32 (inv_cond_XFORM imm:$cc)))>; 2174 2175def : Pat<(add GPR32:$val, (AArch64csel (i32 0), (i32 1), (i32 imm:$cc), NZCV)), 2176 (CSINCWr GPR32:$val, GPR32:$val, (i32 imm:$cc))>; 2177def : Pat<(add GPR64:$val, (zext (AArch64csel (i32 0), (i32 1), (i32 imm:$cc), NZCV))), 2178 (CSINCXr GPR64:$val, GPR64:$val, (i32 imm:$cc))>; 2179 2180// The inverse of the condition code from the alias instruction is what is used 2181// in the aliased instruction. The parser all ready inverts the condition code 2182// for these aliases. 2183def : InstAlias<"cset $dst, $cc", 2184 (CSINCWr GPR32:$dst, WZR, WZR, inv_ccode:$cc)>; 2185def : InstAlias<"cset $dst, $cc", 2186 (CSINCXr GPR64:$dst, XZR, XZR, inv_ccode:$cc)>; 2187 2188def : InstAlias<"csetm $dst, $cc", 2189 (CSINVWr GPR32:$dst, WZR, WZR, inv_ccode:$cc)>; 2190def : InstAlias<"csetm $dst, $cc", 2191 (CSINVXr GPR64:$dst, XZR, XZR, inv_ccode:$cc)>; 2192 2193def : InstAlias<"cinc $dst, $src, $cc", 2194 (CSINCWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>; 2195def : InstAlias<"cinc $dst, $src, $cc", 2196 (CSINCXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>; 2197 2198def : InstAlias<"cinv $dst, $src, $cc", 2199 (CSINVWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>; 2200def : InstAlias<"cinv $dst, $src, $cc", 2201 (CSINVXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>; 2202 2203def : InstAlias<"cneg $dst, $src, $cc", 2204 (CSNEGWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>; 2205def : InstAlias<"cneg $dst, $src, $cc", 2206 (CSNEGXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>; 2207 2208//===----------------------------------------------------------------------===// 2209// PC-relative instructions. 2210//===----------------------------------------------------------------------===// 2211let isReMaterializable = 1 in { 2212let hasSideEffects = 0, mayStore = 0, mayLoad = 0 in { 2213def ADR : ADRI<0, "adr", adrlabel, 2214 [(set GPR64:$Xd, (AArch64adr tglobaladdr:$label))]>; 2215} // hasSideEffects = 0 2216 2217def ADRP : ADRI<1, "adrp", adrplabel, 2218 [(set GPR64:$Xd, (AArch64adrp tglobaladdr:$label))]>; 2219} // isReMaterializable = 1 2220 2221// page address of a constant pool entry, block address 2222def : Pat<(AArch64adr tconstpool:$cp), (ADR tconstpool:$cp)>; 2223def : Pat<(AArch64adr tblockaddress:$cp), (ADR tblockaddress:$cp)>; 2224def : Pat<(AArch64adr texternalsym:$sym), (ADR texternalsym:$sym)>; 2225def : Pat<(AArch64adr tjumptable:$sym), (ADR tjumptable:$sym)>; 2226def : Pat<(AArch64adrp tconstpool:$cp), (ADRP tconstpool:$cp)>; 2227def : Pat<(AArch64adrp tblockaddress:$cp), (ADRP tblockaddress:$cp)>; 2228def : Pat<(AArch64adrp texternalsym:$sym), (ADRP texternalsym:$sym)>; 2229 2230//===----------------------------------------------------------------------===// 2231// Unconditional branch (register) instructions. 2232//===----------------------------------------------------------------------===// 2233 2234let isReturn = 1, isTerminator = 1, isBarrier = 1 in { 2235def RET : BranchReg<0b0010, "ret", []>; 2236def DRPS : SpecialReturn<0b0101, "drps">; 2237def ERET : SpecialReturn<0b0100, "eret">; 2238} // isReturn = 1, isTerminator = 1, isBarrier = 1 2239 2240// Default to the LR register. 2241def : InstAlias<"ret", (RET LR)>; 2242 2243let isCall = 1, Defs = [LR], Uses = [SP] in { 2244 def BLR : BranchReg<0b0001, "blr", []>; 2245 def BLRNoIP : Pseudo<(outs), (ins GPR64noip:$Rn), []>, 2246 Sched<[WriteBrReg]>, 2247 PseudoInstExpansion<(BLR GPR64:$Rn)>; 2248 def BLR_RVMARKER : Pseudo<(outs), (ins variable_ops), []>, 2249 Sched<[WriteBrReg]>; 2250} // isCall 2251 2252def : Pat<(AArch64call GPR64:$Rn), 2253 (BLR GPR64:$Rn)>, 2254 Requires<[NoSLSBLRMitigation]>; 2255def : Pat<(AArch64call GPR64noip:$Rn), 2256 (BLRNoIP GPR64noip:$Rn)>, 2257 Requires<[SLSBLRMitigation]>; 2258 2259def : Pat<(AArch64call_rvmarker GPR64:$Rn), 2260 (BLR_RVMARKER GPR64:$Rn)>, 2261 Requires<[NoSLSBLRMitigation]>; 2262 2263let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 2264def BR : BranchReg<0b0000, "br", [(brind GPR64:$Rn)]>; 2265} // isBranch, isTerminator, isBarrier, isIndirectBranch 2266 2267// Create a separate pseudo-instruction for codegen to use so that we don't 2268// flag lr as used in every function. It'll be restored before the RET by the 2269// epilogue if it's legitimately used. 2270def RET_ReallyLR : Pseudo<(outs), (ins), [(AArch64retflag)]>, 2271 Sched<[WriteBrReg]> { 2272 let isTerminator = 1; 2273 let isBarrier = 1; 2274 let isReturn = 1; 2275} 2276 2277// This is a directive-like pseudo-instruction. The purpose is to insert an 2278// R_AARCH64_TLSDESC_CALL relocation at the offset of the following instruction 2279// (which in the usual case is a BLR). 2280let hasSideEffects = 1 in 2281def TLSDESCCALL : Pseudo<(outs), (ins i64imm:$sym), []>, Sched<[]> { 2282 let AsmString = ".tlsdesccall $sym"; 2283} 2284 2285// Pseudo instruction to tell the streamer to emit a 'B' character into the 2286// augmentation string. 2287def EMITBKEY : Pseudo<(outs), (ins), []>, Sched<[]> {} 2288 2289// FIXME: maybe the scratch register used shouldn't be fixed to X1? 2290// FIXME: can "hasSideEffects be dropped? 2291let isCall = 1, Defs = [LR, X0, X1], hasSideEffects = 1, 2292 isCodeGenOnly = 1 in 2293def TLSDESC_CALLSEQ 2294 : Pseudo<(outs), (ins i64imm:$sym), 2295 [(AArch64tlsdesc_callseq tglobaltlsaddr:$sym)]>, 2296 Sched<[WriteI, WriteLD, WriteI, WriteBrReg]>; 2297def : Pat<(AArch64tlsdesc_callseq texternalsym:$sym), 2298 (TLSDESC_CALLSEQ texternalsym:$sym)>; 2299 2300//===----------------------------------------------------------------------===// 2301// Conditional branch (immediate) instruction. 2302//===----------------------------------------------------------------------===// 2303def Bcc : BranchCond; 2304 2305//===----------------------------------------------------------------------===// 2306// Compare-and-branch instructions. 2307//===----------------------------------------------------------------------===// 2308defm CBZ : CmpBranch<0, "cbz", AArch64cbz>; 2309defm CBNZ : CmpBranch<1, "cbnz", AArch64cbnz>; 2310 2311//===----------------------------------------------------------------------===// 2312// Test-bit-and-branch instructions. 2313//===----------------------------------------------------------------------===// 2314defm TBZ : TestBranch<0, "tbz", AArch64tbz>; 2315defm TBNZ : TestBranch<1, "tbnz", AArch64tbnz>; 2316 2317//===----------------------------------------------------------------------===// 2318// Unconditional branch (immediate) instructions. 2319//===----------------------------------------------------------------------===// 2320let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 2321def B : BranchImm<0, "b", [(br bb:$addr)]>; 2322} // isBranch, isTerminator, isBarrier 2323 2324let isCall = 1, Defs = [LR], Uses = [SP] in { 2325def BL : CallImm<1, "bl", [(AArch64call tglobaladdr:$addr)]>; 2326} // isCall 2327def : Pat<(AArch64call texternalsym:$func), (BL texternalsym:$func)>; 2328 2329//===----------------------------------------------------------------------===// 2330// Exception generation instructions. 2331//===----------------------------------------------------------------------===// 2332let isTrap = 1 in { 2333def BRK : ExceptionGeneration<0b001, 0b00, "brk">; 2334} 2335def DCPS1 : ExceptionGeneration<0b101, 0b01, "dcps1">; 2336def DCPS2 : ExceptionGeneration<0b101, 0b10, "dcps2">; 2337def DCPS3 : ExceptionGeneration<0b101, 0b11, "dcps3">; 2338def HLT : ExceptionGeneration<0b010, 0b00, "hlt">; 2339def HVC : ExceptionGeneration<0b000, 0b10, "hvc">; 2340def SMC : ExceptionGeneration<0b000, 0b11, "smc">; 2341def SVC : ExceptionGeneration<0b000, 0b01, "svc">; 2342 2343// DCPSn defaults to an immediate operand of zero if unspecified. 2344def : InstAlias<"dcps1", (DCPS1 0)>; 2345def : InstAlias<"dcps2", (DCPS2 0)>; 2346def : InstAlias<"dcps3", (DCPS3 0)>; 2347 2348def UDF : UDFType<0, "udf">; 2349 2350//===----------------------------------------------------------------------===// 2351// Load instructions. 2352//===----------------------------------------------------------------------===// 2353 2354// Pair (indexed, offset) 2355defm LDPW : LoadPairOffset<0b00, 0, GPR32z, simm7s4, "ldp">; 2356defm LDPX : LoadPairOffset<0b10, 0, GPR64z, simm7s8, "ldp">; 2357defm LDPS : LoadPairOffset<0b00, 1, FPR32Op, simm7s4, "ldp">; 2358defm LDPD : LoadPairOffset<0b01, 1, FPR64Op, simm7s8, "ldp">; 2359defm LDPQ : LoadPairOffset<0b10, 1, FPR128Op, simm7s16, "ldp">; 2360 2361defm LDPSW : LoadPairOffset<0b01, 0, GPR64z, simm7s4, "ldpsw">; 2362 2363// Pair (pre-indexed) 2364def LDPWpre : LoadPairPreIdx<0b00, 0, GPR32z, simm7s4, "ldp">; 2365def LDPXpre : LoadPairPreIdx<0b10, 0, GPR64z, simm7s8, "ldp">; 2366def LDPSpre : LoadPairPreIdx<0b00, 1, FPR32Op, simm7s4, "ldp">; 2367def LDPDpre : LoadPairPreIdx<0b01, 1, FPR64Op, simm7s8, "ldp">; 2368def LDPQpre : LoadPairPreIdx<0b10, 1, FPR128Op, simm7s16, "ldp">; 2369 2370def LDPSWpre : LoadPairPreIdx<0b01, 0, GPR64z, simm7s4, "ldpsw">; 2371 2372// Pair (post-indexed) 2373def LDPWpost : LoadPairPostIdx<0b00, 0, GPR32z, simm7s4, "ldp">; 2374def LDPXpost : LoadPairPostIdx<0b10, 0, GPR64z, simm7s8, "ldp">; 2375def LDPSpost : LoadPairPostIdx<0b00, 1, FPR32Op, simm7s4, "ldp">; 2376def LDPDpost : LoadPairPostIdx<0b01, 1, FPR64Op, simm7s8, "ldp">; 2377def LDPQpost : LoadPairPostIdx<0b10, 1, FPR128Op, simm7s16, "ldp">; 2378 2379def LDPSWpost : LoadPairPostIdx<0b01, 0, GPR64z, simm7s4, "ldpsw">; 2380 2381 2382// Pair (no allocate) 2383defm LDNPW : LoadPairNoAlloc<0b00, 0, GPR32z, simm7s4, "ldnp">; 2384defm LDNPX : LoadPairNoAlloc<0b10, 0, GPR64z, simm7s8, "ldnp">; 2385defm LDNPS : LoadPairNoAlloc<0b00, 1, FPR32Op, simm7s4, "ldnp">; 2386defm LDNPD : LoadPairNoAlloc<0b01, 1, FPR64Op, simm7s8, "ldnp">; 2387defm LDNPQ : LoadPairNoAlloc<0b10, 1, FPR128Op, simm7s16, "ldnp">; 2388 2389def : Pat<(AArch64ldp (am_indexed7s64 GPR64sp:$Rn, simm7s8:$offset)), 2390 (LDPXi GPR64sp:$Rn, simm7s8:$offset)>; 2391 2392//--- 2393// (register offset) 2394//--- 2395 2396// Integer 2397defm LDRBB : Load8RO<0b00, 0, 0b01, GPR32, "ldrb", i32, zextloadi8>; 2398defm LDRHH : Load16RO<0b01, 0, 0b01, GPR32, "ldrh", i32, zextloadi16>; 2399defm LDRW : Load32RO<0b10, 0, 0b01, GPR32, "ldr", i32, load>; 2400defm LDRX : Load64RO<0b11, 0, 0b01, GPR64, "ldr", i64, load>; 2401 2402// Floating-point 2403defm LDRB : Load8RO<0b00, 1, 0b01, FPR8Op, "ldr", untyped, load>; 2404defm LDRH : Load16RO<0b01, 1, 0b01, FPR16Op, "ldr", f16, load>; 2405defm LDRS : Load32RO<0b10, 1, 0b01, FPR32Op, "ldr", f32, load>; 2406defm LDRD : Load64RO<0b11, 1, 0b01, FPR64Op, "ldr", f64, load>; 2407defm LDRQ : Load128RO<0b00, 1, 0b11, FPR128Op, "ldr", f128, load>; 2408 2409// Load sign-extended half-word 2410defm LDRSHW : Load16RO<0b01, 0, 0b11, GPR32, "ldrsh", i32, sextloadi16>; 2411defm LDRSHX : Load16RO<0b01, 0, 0b10, GPR64, "ldrsh", i64, sextloadi16>; 2412 2413// Load sign-extended byte 2414defm LDRSBW : Load8RO<0b00, 0, 0b11, GPR32, "ldrsb", i32, sextloadi8>; 2415defm LDRSBX : Load8RO<0b00, 0, 0b10, GPR64, "ldrsb", i64, sextloadi8>; 2416 2417// Load sign-extended word 2418defm LDRSW : Load32RO<0b10, 0, 0b10, GPR64, "ldrsw", i64, sextloadi32>; 2419 2420// Pre-fetch. 2421defm PRFM : PrefetchRO<0b11, 0, 0b10, "prfm">; 2422 2423// For regular load, we do not have any alignment requirement. 2424// Thus, it is safe to directly map the vector loads with interesting 2425// addressing modes. 2426// FIXME: We could do the same for bitconvert to floating point vectors. 2427multiclass ScalToVecROLoadPat<ROAddrMode ro, SDPatternOperator loadop, 2428 ValueType ScalTy, ValueType VecTy, 2429 Instruction LOADW, Instruction LOADX, 2430 SubRegIndex sub> { 2431 def : Pat<(VecTy (scalar_to_vector (ScalTy 2432 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$offset))))), 2433 (INSERT_SUBREG (VecTy (IMPLICIT_DEF)), 2434 (LOADW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$offset), 2435 sub)>; 2436 2437 def : Pat<(VecTy (scalar_to_vector (ScalTy 2438 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$offset))))), 2439 (INSERT_SUBREG (VecTy (IMPLICIT_DEF)), 2440 (LOADX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$offset), 2441 sub)>; 2442} 2443 2444let AddedComplexity = 10 in { 2445defm : ScalToVecROLoadPat<ro8, extloadi8, i32, v8i8, LDRBroW, LDRBroX, bsub>; 2446defm : ScalToVecROLoadPat<ro8, extloadi8, i32, v16i8, LDRBroW, LDRBroX, bsub>; 2447 2448defm : ScalToVecROLoadPat<ro16, extloadi16, i32, v4i16, LDRHroW, LDRHroX, hsub>; 2449defm : ScalToVecROLoadPat<ro16, extloadi16, i32, v8i16, LDRHroW, LDRHroX, hsub>; 2450 2451defm : ScalToVecROLoadPat<ro16, load, i32, v4f16, LDRHroW, LDRHroX, hsub>; 2452defm : ScalToVecROLoadPat<ro16, load, i32, v8f16, LDRHroW, LDRHroX, hsub>; 2453 2454defm : ScalToVecROLoadPat<ro32, load, i32, v2i32, LDRSroW, LDRSroX, ssub>; 2455defm : ScalToVecROLoadPat<ro32, load, i32, v4i32, LDRSroW, LDRSroX, ssub>; 2456 2457defm : ScalToVecROLoadPat<ro32, load, f32, v2f32, LDRSroW, LDRSroX, ssub>; 2458defm : ScalToVecROLoadPat<ro32, load, f32, v4f32, LDRSroW, LDRSroX, ssub>; 2459 2460defm : ScalToVecROLoadPat<ro64, load, i64, v2i64, LDRDroW, LDRDroX, dsub>; 2461 2462defm : ScalToVecROLoadPat<ro64, load, f64, v2f64, LDRDroW, LDRDroX, dsub>; 2463 2464 2465def : Pat <(v1i64 (scalar_to_vector (i64 2466 (load (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm, 2467 ro_Wextend64:$extend))))), 2468 (LDRDroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend)>; 2469 2470def : Pat <(v1i64 (scalar_to_vector (i64 2471 (load (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm, 2472 ro_Xextend64:$extend))))), 2473 (LDRDroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend)>; 2474} 2475 2476// Match all load 64 bits width whose type is compatible with FPR64 2477multiclass VecROLoadPat<ROAddrMode ro, ValueType VecTy, 2478 Instruction LOADW, Instruction LOADX> { 2479 2480 def : Pat<(VecTy (load (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))), 2481 (LOADW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>; 2482 2483 def : Pat<(VecTy (load (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))), 2484 (LOADX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>; 2485} 2486 2487let AddedComplexity = 10 in { 2488let Predicates = [IsLE] in { 2489 // We must do vector loads with LD1 in big-endian. 2490 defm : VecROLoadPat<ro64, v2i32, LDRDroW, LDRDroX>; 2491 defm : VecROLoadPat<ro64, v2f32, LDRDroW, LDRDroX>; 2492 defm : VecROLoadPat<ro64, v8i8, LDRDroW, LDRDroX>; 2493 defm : VecROLoadPat<ro64, v4i16, LDRDroW, LDRDroX>; 2494 defm : VecROLoadPat<ro64, v4f16, LDRDroW, LDRDroX>; 2495 defm : VecROLoadPat<ro64, v4bf16, LDRDroW, LDRDroX>; 2496} 2497 2498defm : VecROLoadPat<ro64, v1i64, LDRDroW, LDRDroX>; 2499defm : VecROLoadPat<ro64, v1f64, LDRDroW, LDRDroX>; 2500 2501// Match all load 128 bits width whose type is compatible with FPR128 2502let Predicates = [IsLE] in { 2503 // We must do vector loads with LD1 in big-endian. 2504 defm : VecROLoadPat<ro128, v2i64, LDRQroW, LDRQroX>; 2505 defm : VecROLoadPat<ro128, v2f64, LDRQroW, LDRQroX>; 2506 defm : VecROLoadPat<ro128, v4i32, LDRQroW, LDRQroX>; 2507 defm : VecROLoadPat<ro128, v4f32, LDRQroW, LDRQroX>; 2508 defm : VecROLoadPat<ro128, v8i16, LDRQroW, LDRQroX>; 2509 defm : VecROLoadPat<ro128, v8f16, LDRQroW, LDRQroX>; 2510 defm : VecROLoadPat<ro128, v8bf16, LDRQroW, LDRQroX>; 2511 defm : VecROLoadPat<ro128, v16i8, LDRQroW, LDRQroX>; 2512} 2513} // AddedComplexity = 10 2514 2515// zextload -> i64 2516multiclass ExtLoadTo64ROPat<ROAddrMode ro, SDPatternOperator loadop, 2517 Instruction INSTW, Instruction INSTX> { 2518 def : Pat<(i64 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))), 2519 (SUBREG_TO_REG (i64 0), 2520 (INSTW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend), 2521 sub_32)>; 2522 2523 def : Pat<(i64 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))), 2524 (SUBREG_TO_REG (i64 0), 2525 (INSTX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend), 2526 sub_32)>; 2527} 2528 2529let AddedComplexity = 10 in { 2530 defm : ExtLoadTo64ROPat<ro8, zextloadi8, LDRBBroW, LDRBBroX>; 2531 defm : ExtLoadTo64ROPat<ro16, zextloadi16, LDRHHroW, LDRHHroX>; 2532 defm : ExtLoadTo64ROPat<ro32, zextloadi32, LDRWroW, LDRWroX>; 2533 2534 // zextloadi1 -> zextloadi8 2535 defm : ExtLoadTo64ROPat<ro8, zextloadi1, LDRBBroW, LDRBBroX>; 2536 2537 // extload -> zextload 2538 defm : ExtLoadTo64ROPat<ro8, extloadi8, LDRBBroW, LDRBBroX>; 2539 defm : ExtLoadTo64ROPat<ro16, extloadi16, LDRHHroW, LDRHHroX>; 2540 defm : ExtLoadTo64ROPat<ro32, extloadi32, LDRWroW, LDRWroX>; 2541 2542 // extloadi1 -> zextloadi8 2543 defm : ExtLoadTo64ROPat<ro8, extloadi1, LDRBBroW, LDRBBroX>; 2544} 2545 2546 2547// zextload -> i64 2548multiclass ExtLoadTo32ROPat<ROAddrMode ro, SDPatternOperator loadop, 2549 Instruction INSTW, Instruction INSTX> { 2550 def : Pat<(i32 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))), 2551 (INSTW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>; 2552 2553 def : Pat<(i32 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))), 2554 (INSTX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>; 2555 2556} 2557 2558let AddedComplexity = 10 in { 2559 // extload -> zextload 2560 defm : ExtLoadTo32ROPat<ro8, extloadi8, LDRBBroW, LDRBBroX>; 2561 defm : ExtLoadTo32ROPat<ro16, extloadi16, LDRHHroW, LDRHHroX>; 2562 defm : ExtLoadTo32ROPat<ro32, extloadi32, LDRWroW, LDRWroX>; 2563 2564 // zextloadi1 -> zextloadi8 2565 defm : ExtLoadTo32ROPat<ro8, zextloadi1, LDRBBroW, LDRBBroX>; 2566} 2567 2568//--- 2569// (unsigned immediate) 2570//--- 2571defm LDRX : LoadUI<0b11, 0, 0b01, GPR64z, uimm12s8, "ldr", 2572 [(set GPR64z:$Rt, 2573 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)))]>; 2574defm LDRW : LoadUI<0b10, 0, 0b01, GPR32z, uimm12s4, "ldr", 2575 [(set GPR32z:$Rt, 2576 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)))]>; 2577defm LDRB : LoadUI<0b00, 1, 0b01, FPR8Op, uimm12s1, "ldr", 2578 [(set FPR8Op:$Rt, 2579 (load (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset)))]>; 2580defm LDRH : LoadUI<0b01, 1, 0b01, FPR16Op, uimm12s2, "ldr", 2581 [(set (f16 FPR16Op:$Rt), 2582 (load (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)))]>; 2583defm LDRS : LoadUI<0b10, 1, 0b01, FPR32Op, uimm12s4, "ldr", 2584 [(set (f32 FPR32Op:$Rt), 2585 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)))]>; 2586defm LDRD : LoadUI<0b11, 1, 0b01, FPR64Op, uimm12s8, "ldr", 2587 [(set (f64 FPR64Op:$Rt), 2588 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)))]>; 2589defm LDRQ : LoadUI<0b00, 1, 0b11, FPR128Op, uimm12s16, "ldr", 2590 [(set (f128 FPR128Op:$Rt), 2591 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)))]>; 2592 2593// bf16 load pattern 2594def : Pat <(bf16 (load (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))), 2595 (LDRHui GPR64sp:$Rn, uimm12s2:$offset)>; 2596 2597// For regular load, we do not have any alignment requirement. 2598// Thus, it is safe to directly map the vector loads with interesting 2599// addressing modes. 2600// FIXME: We could do the same for bitconvert to floating point vectors. 2601def : Pat <(v8i8 (scalar_to_vector (i32 2602 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))), 2603 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)), 2604 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub)>; 2605def : Pat <(v16i8 (scalar_to_vector (i32 2606 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))), 2607 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 2608 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub)>; 2609def : Pat <(v4i16 (scalar_to_vector (i32 2610 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))), 2611 (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)), 2612 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>; 2613def : Pat <(v8i16 (scalar_to_vector (i32 2614 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))), 2615 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), 2616 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>; 2617def : Pat <(v2i32 (scalar_to_vector (i32 2618 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))), 2619 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)), 2620 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub)>; 2621def : Pat <(v4i32 (scalar_to_vector (i32 2622 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))), 2623 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), 2624 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub)>; 2625def : Pat <(v1i64 (scalar_to_vector (i64 2626 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))))), 2627 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>; 2628def : Pat <(v2i64 (scalar_to_vector (i64 2629 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))))), 2630 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), 2631 (LDRDui GPR64sp:$Rn, uimm12s8:$offset), dsub)>; 2632 2633// Match all load 64 bits width whose type is compatible with FPR64 2634let Predicates = [IsLE] in { 2635 // We must use LD1 to perform vector loads in big-endian. 2636 def : Pat<(v2f32 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))), 2637 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>; 2638 def : Pat<(v8i8 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))), 2639 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>; 2640 def : Pat<(v4i16 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))), 2641 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>; 2642 def : Pat<(v2i32 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))), 2643 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>; 2644 def : Pat<(v4f16 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))), 2645 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>; 2646 def : Pat<(v4bf16 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))), 2647 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>; 2648} 2649def : Pat<(v1f64 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))), 2650 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>; 2651def : Pat<(v1i64 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))), 2652 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>; 2653 2654// Match all load 128 bits width whose type is compatible with FPR128 2655let Predicates = [IsLE] in { 2656 // We must use LD1 to perform vector loads in big-endian. 2657 def : Pat<(v4f32 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))), 2658 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>; 2659 def : Pat<(v2f64 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))), 2660 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>; 2661 def : Pat<(v16i8 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))), 2662 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>; 2663 def : Pat<(v8i16 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))), 2664 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>; 2665 def : Pat<(v4i32 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))), 2666 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>; 2667 def : Pat<(v2i64 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))), 2668 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>; 2669 def : Pat<(v8f16 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))), 2670 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>; 2671 def : Pat<(v8bf16 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))), 2672 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>; 2673} 2674def : Pat<(f128 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))), 2675 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>; 2676 2677defm LDRHH : LoadUI<0b01, 0, 0b01, GPR32, uimm12s2, "ldrh", 2678 [(set GPR32:$Rt, 2679 (zextloadi16 (am_indexed16 GPR64sp:$Rn, 2680 uimm12s2:$offset)))]>; 2681defm LDRBB : LoadUI<0b00, 0, 0b01, GPR32, uimm12s1, "ldrb", 2682 [(set GPR32:$Rt, 2683 (zextloadi8 (am_indexed8 GPR64sp:$Rn, 2684 uimm12s1:$offset)))]>; 2685// zextload -> i64 2686def : Pat<(i64 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))), 2687 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>; 2688def : Pat<(i64 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))), 2689 (SUBREG_TO_REG (i64 0), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>; 2690 2691// zextloadi1 -> zextloadi8 2692def : Pat<(i32 (zextloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))), 2693 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>; 2694def : Pat<(i64 (zextloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))), 2695 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>; 2696 2697// extload -> zextload 2698def : Pat<(i32 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))), 2699 (LDRHHui GPR64sp:$Rn, uimm12s2:$offset)>; 2700def : Pat<(i32 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))), 2701 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>; 2702def : Pat<(i32 (extloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))), 2703 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>; 2704def : Pat<(i64 (extloadi32 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))), 2705 (SUBREG_TO_REG (i64 0), (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>; 2706def : Pat<(i64 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))), 2707 (SUBREG_TO_REG (i64 0), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>; 2708def : Pat<(i64 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))), 2709 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>; 2710def : Pat<(i64 (extloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))), 2711 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>; 2712 2713// load sign-extended half-word 2714defm LDRSHW : LoadUI<0b01, 0, 0b11, GPR32, uimm12s2, "ldrsh", 2715 [(set GPR32:$Rt, 2716 (sextloadi16 (am_indexed16 GPR64sp:$Rn, 2717 uimm12s2:$offset)))]>; 2718defm LDRSHX : LoadUI<0b01, 0, 0b10, GPR64, uimm12s2, "ldrsh", 2719 [(set GPR64:$Rt, 2720 (sextloadi16 (am_indexed16 GPR64sp:$Rn, 2721 uimm12s2:$offset)))]>; 2722 2723// load sign-extended byte 2724defm LDRSBW : LoadUI<0b00, 0, 0b11, GPR32, uimm12s1, "ldrsb", 2725 [(set GPR32:$Rt, 2726 (sextloadi8 (am_indexed8 GPR64sp:$Rn, 2727 uimm12s1:$offset)))]>; 2728defm LDRSBX : LoadUI<0b00, 0, 0b10, GPR64, uimm12s1, "ldrsb", 2729 [(set GPR64:$Rt, 2730 (sextloadi8 (am_indexed8 GPR64sp:$Rn, 2731 uimm12s1:$offset)))]>; 2732 2733// load sign-extended word 2734defm LDRSW : LoadUI<0b10, 0, 0b10, GPR64, uimm12s4, "ldrsw", 2735 [(set GPR64:$Rt, 2736 (sextloadi32 (am_indexed32 GPR64sp:$Rn, 2737 uimm12s4:$offset)))]>; 2738 2739// load zero-extended word 2740def : Pat<(i64 (zextloadi32 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))), 2741 (SUBREG_TO_REG (i64 0), (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>; 2742 2743// Pre-fetch. 2744def PRFMui : PrefetchUI<0b11, 0, 0b10, "prfm", 2745 [(AArch64Prefetch imm:$Rt, 2746 (am_indexed64 GPR64sp:$Rn, 2747 uimm12s8:$offset))]>; 2748 2749def : InstAlias<"prfm $Rt, [$Rn]", (PRFMui prfop:$Rt, GPR64sp:$Rn, 0)>; 2750 2751//--- 2752// (literal) 2753 2754def alignedglobal : PatLeaf<(iPTR iPTR:$label), [{ 2755 if (auto *G = dyn_cast<GlobalAddressSDNode>(N)) { 2756 const DataLayout &DL = MF->getDataLayout(); 2757 Align Align = G->getGlobal()->getPointerAlignment(DL); 2758 return Align >= 4 && G->getOffset() % 4 == 0; 2759 } 2760 if (auto *C = dyn_cast<ConstantPoolSDNode>(N)) 2761 return C->getAlign() >= 4 && C->getOffset() % 4 == 0; 2762 return false; 2763}]>; 2764 2765def LDRWl : LoadLiteral<0b00, 0, GPR32z, "ldr", 2766 [(set GPR32z:$Rt, (load (AArch64adr alignedglobal:$label)))]>; 2767def LDRXl : LoadLiteral<0b01, 0, GPR64z, "ldr", 2768 [(set GPR64z:$Rt, (load (AArch64adr alignedglobal:$label)))]>; 2769def LDRSl : LoadLiteral<0b00, 1, FPR32Op, "ldr", 2770 [(set (f32 FPR32Op:$Rt), (load (AArch64adr alignedglobal:$label)))]>; 2771def LDRDl : LoadLiteral<0b01, 1, FPR64Op, "ldr", 2772 [(set (f64 FPR64Op:$Rt), (load (AArch64adr alignedglobal:$label)))]>; 2773def LDRQl : LoadLiteral<0b10, 1, FPR128Op, "ldr", 2774 [(set (f128 FPR128Op:$Rt), (load (AArch64adr alignedglobal:$label)))]>; 2775 2776// load sign-extended word 2777def LDRSWl : LoadLiteral<0b10, 0, GPR64z, "ldrsw", 2778 [(set GPR64z:$Rt, (sextloadi32 (AArch64adr alignedglobal:$label)))]>; 2779 2780let AddedComplexity = 20 in { 2781def : Pat<(i64 (zextloadi32 (AArch64adr alignedglobal:$label))), 2782 (SUBREG_TO_REG (i64 0), (LDRWl $label), sub_32)>; 2783} 2784 2785// prefetch 2786def PRFMl : PrefetchLiteral<0b11, 0, "prfm", []>; 2787// [(AArch64Prefetch imm:$Rt, tglobaladdr:$label)]>; 2788 2789//--- 2790// (unscaled immediate) 2791defm LDURX : LoadUnscaled<0b11, 0, 0b01, GPR64z, "ldur", 2792 [(set GPR64z:$Rt, 2793 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset)))]>; 2794defm LDURW : LoadUnscaled<0b10, 0, 0b01, GPR32z, "ldur", 2795 [(set GPR32z:$Rt, 2796 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>; 2797defm LDURB : LoadUnscaled<0b00, 1, 0b01, FPR8Op, "ldur", 2798 [(set FPR8Op:$Rt, 2799 (load (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>; 2800defm LDURH : LoadUnscaled<0b01, 1, 0b01, FPR16Op, "ldur", 2801 [(set (f16 FPR16Op:$Rt), 2802 (load (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>; 2803defm LDURS : LoadUnscaled<0b10, 1, 0b01, FPR32Op, "ldur", 2804 [(set (f32 FPR32Op:$Rt), 2805 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>; 2806defm LDURD : LoadUnscaled<0b11, 1, 0b01, FPR64Op, "ldur", 2807 [(set (f64 FPR64Op:$Rt), 2808 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset)))]>; 2809defm LDURQ : LoadUnscaled<0b00, 1, 0b11, FPR128Op, "ldur", 2810 [(set (f128 FPR128Op:$Rt), 2811 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset)))]>; 2812 2813defm LDURHH 2814 : LoadUnscaled<0b01, 0, 0b01, GPR32, "ldurh", 2815 [(set GPR32:$Rt, 2816 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>; 2817defm LDURBB 2818 : LoadUnscaled<0b00, 0, 0b01, GPR32, "ldurb", 2819 [(set GPR32:$Rt, 2820 (zextloadi8 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>; 2821 2822// Match all load 64 bits width whose type is compatible with FPR64 2823let Predicates = [IsLE] in { 2824 def : Pat<(v2f32 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))), 2825 (LDURDi GPR64sp:$Rn, simm9:$offset)>; 2826 def : Pat<(v2i32 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))), 2827 (LDURDi GPR64sp:$Rn, simm9:$offset)>; 2828 def : Pat<(v4i16 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))), 2829 (LDURDi GPR64sp:$Rn, simm9:$offset)>; 2830 def : Pat<(v8i8 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))), 2831 (LDURDi GPR64sp:$Rn, simm9:$offset)>; 2832 def : Pat<(v4f16 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))), 2833 (LDURDi GPR64sp:$Rn, simm9:$offset)>; 2834} 2835def : Pat<(v1f64 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))), 2836 (LDURDi GPR64sp:$Rn, simm9:$offset)>; 2837def : Pat<(v1i64 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))), 2838 (LDURDi GPR64sp:$Rn, simm9:$offset)>; 2839 2840// Match all load 128 bits width whose type is compatible with FPR128 2841let Predicates = [IsLE] in { 2842 def : Pat<(v2f64 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))), 2843 (LDURQi GPR64sp:$Rn, simm9:$offset)>; 2844 def : Pat<(v2i64 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))), 2845 (LDURQi GPR64sp:$Rn, simm9:$offset)>; 2846 def : Pat<(v4f32 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))), 2847 (LDURQi GPR64sp:$Rn, simm9:$offset)>; 2848 def : Pat<(v4i32 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))), 2849 (LDURQi GPR64sp:$Rn, simm9:$offset)>; 2850 def : Pat<(v8i16 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))), 2851 (LDURQi GPR64sp:$Rn, simm9:$offset)>; 2852 def : Pat<(v16i8 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))), 2853 (LDURQi GPR64sp:$Rn, simm9:$offset)>; 2854 def : Pat<(v8f16 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))), 2855 (LDURQi GPR64sp:$Rn, simm9:$offset)>; 2856} 2857 2858// anyext -> zext 2859def : Pat<(i32 (extloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))), 2860 (LDURHHi GPR64sp:$Rn, simm9:$offset)>; 2861def : Pat<(i32 (extloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))), 2862 (LDURBBi GPR64sp:$Rn, simm9:$offset)>; 2863def : Pat<(i32 (extloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))), 2864 (LDURBBi GPR64sp:$Rn, simm9:$offset)>; 2865def : Pat<(i64 (extloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))), 2866 (SUBREG_TO_REG (i64 0), (LDURWi GPR64sp:$Rn, simm9:$offset), sub_32)>; 2867def : Pat<(i64 (extloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))), 2868 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>; 2869def : Pat<(i64 (extloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))), 2870 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>; 2871def : Pat<(i64 (extloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))), 2872 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>; 2873// unscaled zext 2874def : Pat<(i32 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))), 2875 (LDURHHi GPR64sp:$Rn, simm9:$offset)>; 2876def : Pat<(i32 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))), 2877 (LDURBBi GPR64sp:$Rn, simm9:$offset)>; 2878def : Pat<(i32 (zextloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))), 2879 (LDURBBi GPR64sp:$Rn, simm9:$offset)>; 2880def : Pat<(i64 (zextloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))), 2881 (SUBREG_TO_REG (i64 0), (LDURWi GPR64sp:$Rn, simm9:$offset), sub_32)>; 2882def : Pat<(i64 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))), 2883 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>; 2884def : Pat<(i64 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))), 2885 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>; 2886def : Pat<(i64 (zextloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))), 2887 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>; 2888 2889 2890//--- 2891// LDR mnemonics fall back to LDUR for negative or unaligned offsets. 2892 2893// Define new assembler match classes as we want to only match these when 2894// the don't otherwise match the scaled addressing mode for LDR/STR. Don't 2895// associate a DiagnosticType either, as we want the diagnostic for the 2896// canonical form (the scaled operand) to take precedence. 2897class SImm9OffsetOperand<int Width> : AsmOperandClass { 2898 let Name = "SImm9OffsetFB" # Width; 2899 let PredicateMethod = "isSImm9OffsetFB<" # Width # ">"; 2900 let RenderMethod = "addImmOperands"; 2901} 2902 2903def SImm9OffsetFB8Operand : SImm9OffsetOperand<8>; 2904def SImm9OffsetFB16Operand : SImm9OffsetOperand<16>; 2905def SImm9OffsetFB32Operand : SImm9OffsetOperand<32>; 2906def SImm9OffsetFB64Operand : SImm9OffsetOperand<64>; 2907def SImm9OffsetFB128Operand : SImm9OffsetOperand<128>; 2908 2909def simm9_offset_fb8 : Operand<i64> { 2910 let ParserMatchClass = SImm9OffsetFB8Operand; 2911} 2912def simm9_offset_fb16 : Operand<i64> { 2913 let ParserMatchClass = SImm9OffsetFB16Operand; 2914} 2915def simm9_offset_fb32 : Operand<i64> { 2916 let ParserMatchClass = SImm9OffsetFB32Operand; 2917} 2918def simm9_offset_fb64 : Operand<i64> { 2919 let ParserMatchClass = SImm9OffsetFB64Operand; 2920} 2921def simm9_offset_fb128 : Operand<i64> { 2922 let ParserMatchClass = SImm9OffsetFB128Operand; 2923} 2924 2925def : InstAlias<"ldr $Rt, [$Rn, $offset]", 2926 (LDURXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>; 2927def : InstAlias<"ldr $Rt, [$Rn, $offset]", 2928 (LDURWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>; 2929def : InstAlias<"ldr $Rt, [$Rn, $offset]", 2930 (LDURBi FPR8Op:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>; 2931def : InstAlias<"ldr $Rt, [$Rn, $offset]", 2932 (LDURHi FPR16Op:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>; 2933def : InstAlias<"ldr $Rt, [$Rn, $offset]", 2934 (LDURSi FPR32Op:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>; 2935def : InstAlias<"ldr $Rt, [$Rn, $offset]", 2936 (LDURDi FPR64Op:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>; 2937def : InstAlias<"ldr $Rt, [$Rn, $offset]", 2938 (LDURQi FPR128Op:$Rt, GPR64sp:$Rn, simm9_offset_fb128:$offset), 0>; 2939 2940// zextload -> i64 2941def : Pat<(i64 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))), 2942 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>; 2943def : Pat<(i64 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))), 2944 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>; 2945 2946// load sign-extended half-word 2947defm LDURSHW 2948 : LoadUnscaled<0b01, 0, 0b11, GPR32, "ldursh", 2949 [(set GPR32:$Rt, 2950 (sextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>; 2951defm LDURSHX 2952 : LoadUnscaled<0b01, 0, 0b10, GPR64, "ldursh", 2953 [(set GPR64:$Rt, 2954 (sextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>; 2955 2956// load sign-extended byte 2957defm LDURSBW 2958 : LoadUnscaled<0b00, 0, 0b11, GPR32, "ldursb", 2959 [(set GPR32:$Rt, 2960 (sextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>; 2961defm LDURSBX 2962 : LoadUnscaled<0b00, 0, 0b10, GPR64, "ldursb", 2963 [(set GPR64:$Rt, 2964 (sextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>; 2965 2966// load sign-extended word 2967defm LDURSW 2968 : LoadUnscaled<0b10, 0, 0b10, GPR64, "ldursw", 2969 [(set GPR64:$Rt, 2970 (sextloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>; 2971 2972// zero and sign extending aliases from generic LDR* mnemonics to LDUR*. 2973def : InstAlias<"ldrb $Rt, [$Rn, $offset]", 2974 (LDURBBi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>; 2975def : InstAlias<"ldrh $Rt, [$Rn, $offset]", 2976 (LDURHHi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>; 2977def : InstAlias<"ldrsb $Rt, [$Rn, $offset]", 2978 (LDURSBWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>; 2979def : InstAlias<"ldrsb $Rt, [$Rn, $offset]", 2980 (LDURSBXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>; 2981def : InstAlias<"ldrsh $Rt, [$Rn, $offset]", 2982 (LDURSHWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>; 2983def : InstAlias<"ldrsh $Rt, [$Rn, $offset]", 2984 (LDURSHXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>; 2985def : InstAlias<"ldrsw $Rt, [$Rn, $offset]", 2986 (LDURSWi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>; 2987 2988// Pre-fetch. 2989defm PRFUM : PrefetchUnscaled<0b11, 0, 0b10, "prfum", 2990 [(AArch64Prefetch imm:$Rt, 2991 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>; 2992 2993//--- 2994// (unscaled immediate, unprivileged) 2995defm LDTRX : LoadUnprivileged<0b11, 0, 0b01, GPR64, "ldtr">; 2996defm LDTRW : LoadUnprivileged<0b10, 0, 0b01, GPR32, "ldtr">; 2997 2998defm LDTRH : LoadUnprivileged<0b01, 0, 0b01, GPR32, "ldtrh">; 2999defm LDTRB : LoadUnprivileged<0b00, 0, 0b01, GPR32, "ldtrb">; 3000 3001// load sign-extended half-word 3002defm LDTRSHW : LoadUnprivileged<0b01, 0, 0b11, GPR32, "ldtrsh">; 3003defm LDTRSHX : LoadUnprivileged<0b01, 0, 0b10, GPR64, "ldtrsh">; 3004 3005// load sign-extended byte 3006defm LDTRSBW : LoadUnprivileged<0b00, 0, 0b11, GPR32, "ldtrsb">; 3007defm LDTRSBX : LoadUnprivileged<0b00, 0, 0b10, GPR64, "ldtrsb">; 3008 3009// load sign-extended word 3010defm LDTRSW : LoadUnprivileged<0b10, 0, 0b10, GPR64, "ldtrsw">; 3011 3012//--- 3013// (immediate pre-indexed) 3014def LDRWpre : LoadPreIdx<0b10, 0, 0b01, GPR32z, "ldr">; 3015def LDRXpre : LoadPreIdx<0b11, 0, 0b01, GPR64z, "ldr">; 3016def LDRBpre : LoadPreIdx<0b00, 1, 0b01, FPR8Op, "ldr">; 3017def LDRHpre : LoadPreIdx<0b01, 1, 0b01, FPR16Op, "ldr">; 3018def LDRSpre : LoadPreIdx<0b10, 1, 0b01, FPR32Op, "ldr">; 3019def LDRDpre : LoadPreIdx<0b11, 1, 0b01, FPR64Op, "ldr">; 3020def LDRQpre : LoadPreIdx<0b00, 1, 0b11, FPR128Op, "ldr">; 3021 3022// load sign-extended half-word 3023def LDRSHWpre : LoadPreIdx<0b01, 0, 0b11, GPR32z, "ldrsh">; 3024def LDRSHXpre : LoadPreIdx<0b01, 0, 0b10, GPR64z, "ldrsh">; 3025 3026// load sign-extended byte 3027def LDRSBWpre : LoadPreIdx<0b00, 0, 0b11, GPR32z, "ldrsb">; 3028def LDRSBXpre : LoadPreIdx<0b00, 0, 0b10, GPR64z, "ldrsb">; 3029 3030// load zero-extended byte 3031def LDRBBpre : LoadPreIdx<0b00, 0, 0b01, GPR32z, "ldrb">; 3032def LDRHHpre : LoadPreIdx<0b01, 0, 0b01, GPR32z, "ldrh">; 3033 3034// load sign-extended word 3035def LDRSWpre : LoadPreIdx<0b10, 0, 0b10, GPR64z, "ldrsw">; 3036 3037//--- 3038// (immediate post-indexed) 3039def LDRWpost : LoadPostIdx<0b10, 0, 0b01, GPR32z, "ldr">; 3040def LDRXpost : LoadPostIdx<0b11, 0, 0b01, GPR64z, "ldr">; 3041def LDRBpost : LoadPostIdx<0b00, 1, 0b01, FPR8Op, "ldr">; 3042def LDRHpost : LoadPostIdx<0b01, 1, 0b01, FPR16Op, "ldr">; 3043def LDRSpost : LoadPostIdx<0b10, 1, 0b01, FPR32Op, "ldr">; 3044def LDRDpost : LoadPostIdx<0b11, 1, 0b01, FPR64Op, "ldr">; 3045def LDRQpost : LoadPostIdx<0b00, 1, 0b11, FPR128Op, "ldr">; 3046 3047// load sign-extended half-word 3048def LDRSHWpost : LoadPostIdx<0b01, 0, 0b11, GPR32z, "ldrsh">; 3049def LDRSHXpost : LoadPostIdx<0b01, 0, 0b10, GPR64z, "ldrsh">; 3050 3051// load sign-extended byte 3052def LDRSBWpost : LoadPostIdx<0b00, 0, 0b11, GPR32z, "ldrsb">; 3053def LDRSBXpost : LoadPostIdx<0b00, 0, 0b10, GPR64z, "ldrsb">; 3054 3055// load zero-extended byte 3056def LDRBBpost : LoadPostIdx<0b00, 0, 0b01, GPR32z, "ldrb">; 3057def LDRHHpost : LoadPostIdx<0b01, 0, 0b01, GPR32z, "ldrh">; 3058 3059// load sign-extended word 3060def LDRSWpost : LoadPostIdx<0b10, 0, 0b10, GPR64z, "ldrsw">; 3061 3062//===----------------------------------------------------------------------===// 3063// Store instructions. 3064//===----------------------------------------------------------------------===// 3065 3066// Pair (indexed, offset) 3067// FIXME: Use dedicated range-checked addressing mode operand here. 3068defm STPW : StorePairOffset<0b00, 0, GPR32z, simm7s4, "stp">; 3069defm STPX : StorePairOffset<0b10, 0, GPR64z, simm7s8, "stp">; 3070defm STPS : StorePairOffset<0b00, 1, FPR32Op, simm7s4, "stp">; 3071defm STPD : StorePairOffset<0b01, 1, FPR64Op, simm7s8, "stp">; 3072defm STPQ : StorePairOffset<0b10, 1, FPR128Op, simm7s16, "stp">; 3073 3074// Pair (pre-indexed) 3075def STPWpre : StorePairPreIdx<0b00, 0, GPR32z, simm7s4, "stp">; 3076def STPXpre : StorePairPreIdx<0b10, 0, GPR64z, simm7s8, "stp">; 3077def STPSpre : StorePairPreIdx<0b00, 1, FPR32Op, simm7s4, "stp">; 3078def STPDpre : StorePairPreIdx<0b01, 1, FPR64Op, simm7s8, "stp">; 3079def STPQpre : StorePairPreIdx<0b10, 1, FPR128Op, simm7s16, "stp">; 3080 3081// Pair (pre-indexed) 3082def STPWpost : StorePairPostIdx<0b00, 0, GPR32z, simm7s4, "stp">; 3083def STPXpost : StorePairPostIdx<0b10, 0, GPR64z, simm7s8, "stp">; 3084def STPSpost : StorePairPostIdx<0b00, 1, FPR32Op, simm7s4, "stp">; 3085def STPDpost : StorePairPostIdx<0b01, 1, FPR64Op, simm7s8, "stp">; 3086def STPQpost : StorePairPostIdx<0b10, 1, FPR128Op, simm7s16, "stp">; 3087 3088// Pair (no allocate) 3089defm STNPW : StorePairNoAlloc<0b00, 0, GPR32z, simm7s4, "stnp">; 3090defm STNPX : StorePairNoAlloc<0b10, 0, GPR64z, simm7s8, "stnp">; 3091defm STNPS : StorePairNoAlloc<0b00, 1, FPR32Op, simm7s4, "stnp">; 3092defm STNPD : StorePairNoAlloc<0b01, 1, FPR64Op, simm7s8, "stnp">; 3093defm STNPQ : StorePairNoAlloc<0b10, 1, FPR128Op, simm7s16, "stnp">; 3094 3095def : Pat<(AArch64stp GPR64z:$Rt, GPR64z:$Rt2, (am_indexed7s64 GPR64sp:$Rn, simm7s8:$offset)), 3096 (STPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, simm7s8:$offset)>; 3097 3098def : Pat<(AArch64stnp FPR128:$Rt, FPR128:$Rt2, (am_indexed7s128 GPR64sp:$Rn, simm7s16:$offset)), 3099 (STNPQi FPR128:$Rt, FPR128:$Rt2, GPR64sp:$Rn, simm7s16:$offset)>; 3100 3101 3102//--- 3103// (Register offset) 3104 3105// Integer 3106defm STRBB : Store8RO< 0b00, 0, 0b00, GPR32, "strb", i32, truncstorei8>; 3107defm STRHH : Store16RO<0b01, 0, 0b00, GPR32, "strh", i32, truncstorei16>; 3108defm STRW : Store32RO<0b10, 0, 0b00, GPR32, "str", i32, store>; 3109defm STRX : Store64RO<0b11, 0, 0b00, GPR64, "str", i64, store>; 3110 3111 3112// Floating-point 3113defm STRB : Store8RO< 0b00, 1, 0b00, FPR8Op, "str", untyped, store>; 3114defm STRH : Store16RO<0b01, 1, 0b00, FPR16Op, "str", f16, store>; 3115defm STRS : Store32RO<0b10, 1, 0b00, FPR32Op, "str", f32, store>; 3116defm STRD : Store64RO<0b11, 1, 0b00, FPR64Op, "str", f64, store>; 3117defm STRQ : Store128RO<0b00, 1, 0b10, FPR128Op, "str", f128, store>; 3118 3119let Predicates = [UseSTRQro], AddedComplexity = 10 in { 3120 def : Pat<(store (f128 FPR128:$Rt), 3121 (ro_Windexed128 GPR64sp:$Rn, GPR32:$Rm, 3122 ro_Wextend128:$extend)), 3123 (STRQroW FPR128:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend128:$extend)>; 3124 def : Pat<(store (f128 FPR128:$Rt), 3125 (ro_Xindexed128 GPR64sp:$Rn, GPR64:$Rm, 3126 ro_Xextend128:$extend)), 3127 (STRQroX FPR128:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Wextend128:$extend)>; 3128} 3129 3130multiclass TruncStoreFrom64ROPat<ROAddrMode ro, SDPatternOperator storeop, 3131 Instruction STRW, Instruction STRX> { 3132 3133 def : Pat<(storeop GPR64:$Rt, 3134 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)), 3135 (STRW (EXTRACT_SUBREG GPR64:$Rt, sub_32), 3136 GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>; 3137 3138 def : Pat<(storeop GPR64:$Rt, 3139 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)), 3140 (STRX (EXTRACT_SUBREG GPR64:$Rt, sub_32), 3141 GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>; 3142} 3143 3144let AddedComplexity = 10 in { 3145 // truncstore i64 3146 defm : TruncStoreFrom64ROPat<ro8, truncstorei8, STRBBroW, STRBBroX>; 3147 defm : TruncStoreFrom64ROPat<ro16, truncstorei16, STRHHroW, STRHHroX>; 3148 defm : TruncStoreFrom64ROPat<ro32, truncstorei32, STRWroW, STRWroX>; 3149} 3150 3151multiclass VecROStorePat<ROAddrMode ro, ValueType VecTy, RegisterClass FPR, 3152 Instruction STRW, Instruction STRX> { 3153 def : Pat<(store (VecTy FPR:$Rt), 3154 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)), 3155 (STRW FPR:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>; 3156 3157 def : Pat<(store (VecTy FPR:$Rt), 3158 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)), 3159 (STRX FPR:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>; 3160} 3161 3162let AddedComplexity = 10 in { 3163// Match all store 64 bits width whose type is compatible with FPR64 3164let Predicates = [IsLE] in { 3165 // We must use ST1 to store vectors in big-endian. 3166 defm : VecROStorePat<ro64, v2i32, FPR64, STRDroW, STRDroX>; 3167 defm : VecROStorePat<ro64, v2f32, FPR64, STRDroW, STRDroX>; 3168 defm : VecROStorePat<ro64, v4i16, FPR64, STRDroW, STRDroX>; 3169 defm : VecROStorePat<ro64, v8i8, FPR64, STRDroW, STRDroX>; 3170 defm : VecROStorePat<ro64, v4f16, FPR64, STRDroW, STRDroX>; 3171 defm : VecROStorePat<ro64, v4bf16, FPR64, STRDroW, STRDroX>; 3172} 3173 3174defm : VecROStorePat<ro64, v1i64, FPR64, STRDroW, STRDroX>; 3175defm : VecROStorePat<ro64, v1f64, FPR64, STRDroW, STRDroX>; 3176 3177// Match all store 128 bits width whose type is compatible with FPR128 3178let Predicates = [IsLE, UseSTRQro] in { 3179 // We must use ST1 to store vectors in big-endian. 3180 defm : VecROStorePat<ro128, v2i64, FPR128, STRQroW, STRQroX>; 3181 defm : VecROStorePat<ro128, v2f64, FPR128, STRQroW, STRQroX>; 3182 defm : VecROStorePat<ro128, v4i32, FPR128, STRQroW, STRQroX>; 3183 defm : VecROStorePat<ro128, v4f32, FPR128, STRQroW, STRQroX>; 3184 defm : VecROStorePat<ro128, v8i16, FPR128, STRQroW, STRQroX>; 3185 defm : VecROStorePat<ro128, v16i8, FPR128, STRQroW, STRQroX>; 3186 defm : VecROStorePat<ro128, v8f16, FPR128, STRQroW, STRQroX>; 3187 defm : VecROStorePat<ro128, v8bf16, FPR128, STRQroW, STRQroX>; 3188} 3189} // AddedComplexity = 10 3190 3191// Match stores from lane 0 to the appropriate subreg's store. 3192multiclass VecROStoreLane0Pat<ROAddrMode ro, SDPatternOperator storeop, 3193 ValueType VecTy, ValueType STy, 3194 SubRegIndex SubRegIdx, 3195 Instruction STRW, Instruction STRX> { 3196 3197 def : Pat<(storeop (STy (vector_extract (VecTy VecListOne128:$Vt), 0)), 3198 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)), 3199 (STRW (EXTRACT_SUBREG VecListOne128:$Vt, SubRegIdx), 3200 GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>; 3201 3202 def : Pat<(storeop (STy (vector_extract (VecTy VecListOne128:$Vt), 0)), 3203 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)), 3204 (STRX (EXTRACT_SUBREG VecListOne128:$Vt, SubRegIdx), 3205 GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>; 3206} 3207 3208let AddedComplexity = 19 in { 3209 defm : VecROStoreLane0Pat<ro16, truncstorei16, v8i16, i32, hsub, STRHroW, STRHroX>; 3210 defm : VecROStoreLane0Pat<ro16, store, v8f16, f16, hsub, STRHroW, STRHroX>; 3211 defm : VecROStoreLane0Pat<ro32, store, v4i32, i32, ssub, STRSroW, STRSroX>; 3212 defm : VecROStoreLane0Pat<ro32, store, v4f32, f32, ssub, STRSroW, STRSroX>; 3213 defm : VecROStoreLane0Pat<ro64, store, v2i64, i64, dsub, STRDroW, STRDroX>; 3214 defm : VecROStoreLane0Pat<ro64, store, v2f64, f64, dsub, STRDroW, STRDroX>; 3215} 3216 3217//--- 3218// (unsigned immediate) 3219defm STRX : StoreUIz<0b11, 0, 0b00, GPR64z, uimm12s8, "str", 3220 [(store GPR64z:$Rt, 3221 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))]>; 3222defm STRW : StoreUIz<0b10, 0, 0b00, GPR32z, uimm12s4, "str", 3223 [(store GPR32z:$Rt, 3224 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))]>; 3225defm STRB : StoreUI<0b00, 1, 0b00, FPR8Op, uimm12s1, "str", 3226 [(store FPR8Op:$Rt, 3227 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))]>; 3228defm STRH : StoreUI<0b01, 1, 0b00, FPR16Op, uimm12s2, "str", 3229 [(store (f16 FPR16Op:$Rt), 3230 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))]>; 3231defm STRS : StoreUI<0b10, 1, 0b00, FPR32Op, uimm12s4, "str", 3232 [(store (f32 FPR32Op:$Rt), 3233 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))]>; 3234defm STRD : StoreUI<0b11, 1, 0b00, FPR64Op, uimm12s8, "str", 3235 [(store (f64 FPR64Op:$Rt), 3236 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))]>; 3237defm STRQ : StoreUI<0b00, 1, 0b10, FPR128Op, uimm12s16, "str", []>; 3238 3239defm STRHH : StoreUIz<0b01, 0, 0b00, GPR32z, uimm12s2, "strh", 3240 [(truncstorei16 GPR32z:$Rt, 3241 (am_indexed16 GPR64sp:$Rn, 3242 uimm12s2:$offset))]>; 3243defm STRBB : StoreUIz<0b00, 0, 0b00, GPR32z, uimm12s1, "strb", 3244 [(truncstorei8 GPR32z:$Rt, 3245 (am_indexed8 GPR64sp:$Rn, 3246 uimm12s1:$offset))]>; 3247 3248// bf16 store pattern 3249def : Pat<(store (bf16 FPR16Op:$Rt), 3250 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)), 3251 (STRHui FPR16:$Rt, GPR64sp:$Rn, uimm12s2:$offset)>; 3252 3253let AddedComplexity = 10 in { 3254 3255// Match all store 64 bits width whose type is compatible with FPR64 3256def : Pat<(store (v1i64 FPR64:$Rt), 3257 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)), 3258 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>; 3259def : Pat<(store (v1f64 FPR64:$Rt), 3260 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)), 3261 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>; 3262 3263let Predicates = [IsLE] in { 3264 // We must use ST1 to store vectors in big-endian. 3265 def : Pat<(store (v2f32 FPR64:$Rt), 3266 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)), 3267 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>; 3268 def : Pat<(store (v8i8 FPR64:$Rt), 3269 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)), 3270 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>; 3271 def : Pat<(store (v4i16 FPR64:$Rt), 3272 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)), 3273 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>; 3274 def : Pat<(store (v2i32 FPR64:$Rt), 3275 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)), 3276 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>; 3277 def : Pat<(store (v4f16 FPR64:$Rt), 3278 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)), 3279 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>; 3280 def : Pat<(store (v4bf16 FPR64:$Rt), 3281 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)), 3282 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>; 3283} 3284 3285// Match all store 128 bits width whose type is compatible with FPR128 3286def : Pat<(store (f128 FPR128:$Rt), 3287 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)), 3288 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>; 3289 3290let Predicates = [IsLE] in { 3291 // We must use ST1 to store vectors in big-endian. 3292 def : Pat<(store (v4f32 FPR128:$Rt), 3293 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)), 3294 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>; 3295 def : Pat<(store (v2f64 FPR128:$Rt), 3296 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)), 3297 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>; 3298 def : Pat<(store (v16i8 FPR128:$Rt), 3299 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)), 3300 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>; 3301 def : Pat<(store (v8i16 FPR128:$Rt), 3302 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)), 3303 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>; 3304 def : Pat<(store (v4i32 FPR128:$Rt), 3305 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)), 3306 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>; 3307 def : Pat<(store (v2i64 FPR128:$Rt), 3308 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)), 3309 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>; 3310 def : Pat<(store (v8f16 FPR128:$Rt), 3311 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)), 3312 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>; 3313 def : Pat<(store (v8bf16 FPR128:$Rt), 3314 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)), 3315 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>; 3316} 3317 3318// truncstore i64 3319def : Pat<(truncstorei32 GPR64:$Rt, 3320 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)), 3321 (STRWui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s4:$offset)>; 3322def : Pat<(truncstorei16 GPR64:$Rt, 3323 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)), 3324 (STRHHui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s2:$offset)>; 3325def : Pat<(truncstorei8 GPR64:$Rt, (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset)), 3326 (STRBBui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s1:$offset)>; 3327 3328} // AddedComplexity = 10 3329 3330// Match stores from lane 0 to the appropriate subreg's store. 3331multiclass VecStoreLane0Pat<ComplexPattern UIAddrMode, SDPatternOperator storeop, 3332 ValueType VTy, ValueType STy, 3333 SubRegIndex SubRegIdx, Operand IndexType, 3334 Instruction STR> { 3335 def : Pat<(storeop (STy (vector_extract (VTy VecListOne128:$Vt), 0)), 3336 (UIAddrMode GPR64sp:$Rn, IndexType:$offset)), 3337 (STR (EXTRACT_SUBREG VecListOne128:$Vt, SubRegIdx), 3338 GPR64sp:$Rn, IndexType:$offset)>; 3339} 3340 3341let AddedComplexity = 19 in { 3342 defm : VecStoreLane0Pat<am_indexed16, truncstorei16, v8i16, i32, hsub, uimm12s2, STRHui>; 3343 defm : VecStoreLane0Pat<am_indexed16, store, v8f16, f16, hsub, uimm12s2, STRHui>; 3344 defm : VecStoreLane0Pat<am_indexed32, store, v4i32, i32, ssub, uimm12s4, STRSui>; 3345 defm : VecStoreLane0Pat<am_indexed32, store, v4f32, f32, ssub, uimm12s4, STRSui>; 3346 defm : VecStoreLane0Pat<am_indexed64, store, v2i64, i64, dsub, uimm12s8, STRDui>; 3347 defm : VecStoreLane0Pat<am_indexed64, store, v2f64, f64, dsub, uimm12s8, STRDui>; 3348} 3349 3350//--- 3351// (unscaled immediate) 3352defm STURX : StoreUnscaled<0b11, 0, 0b00, GPR64z, "stur", 3353 [(store GPR64z:$Rt, 3354 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>; 3355defm STURW : StoreUnscaled<0b10, 0, 0b00, GPR32z, "stur", 3356 [(store GPR32z:$Rt, 3357 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))]>; 3358defm STURB : StoreUnscaled<0b00, 1, 0b00, FPR8Op, "stur", 3359 [(store FPR8Op:$Rt, 3360 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>; 3361defm STURH : StoreUnscaled<0b01, 1, 0b00, FPR16Op, "stur", 3362 [(store (f16 FPR16Op:$Rt), 3363 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))]>; 3364defm STURS : StoreUnscaled<0b10, 1, 0b00, FPR32Op, "stur", 3365 [(store (f32 FPR32Op:$Rt), 3366 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))]>; 3367defm STURD : StoreUnscaled<0b11, 1, 0b00, FPR64Op, "stur", 3368 [(store (f64 FPR64Op:$Rt), 3369 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>; 3370defm STURQ : StoreUnscaled<0b00, 1, 0b10, FPR128Op, "stur", 3371 [(store (f128 FPR128Op:$Rt), 3372 (am_unscaled128 GPR64sp:$Rn, simm9:$offset))]>; 3373defm STURHH : StoreUnscaled<0b01, 0, 0b00, GPR32z, "sturh", 3374 [(truncstorei16 GPR32z:$Rt, 3375 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))]>; 3376defm STURBB : StoreUnscaled<0b00, 0, 0b00, GPR32z, "sturb", 3377 [(truncstorei8 GPR32z:$Rt, 3378 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>; 3379 3380// Armv8.4 Weaker Release Consistency enhancements 3381// LDAPR & STLR with Immediate Offset instructions 3382let Predicates = [HasRCPC_IMMO] in { 3383defm STLURB : BaseStoreUnscaleV84<"stlurb", 0b00, 0b00, GPR32>; 3384defm STLURH : BaseStoreUnscaleV84<"stlurh", 0b01, 0b00, GPR32>; 3385defm STLURW : BaseStoreUnscaleV84<"stlur", 0b10, 0b00, GPR32>; 3386defm STLURX : BaseStoreUnscaleV84<"stlur", 0b11, 0b00, GPR64>; 3387defm LDAPURB : BaseLoadUnscaleV84<"ldapurb", 0b00, 0b01, GPR32>; 3388defm LDAPURSBW : BaseLoadUnscaleV84<"ldapursb", 0b00, 0b11, GPR32>; 3389defm LDAPURSBX : BaseLoadUnscaleV84<"ldapursb", 0b00, 0b10, GPR64>; 3390defm LDAPURH : BaseLoadUnscaleV84<"ldapurh", 0b01, 0b01, GPR32>; 3391defm LDAPURSHW : BaseLoadUnscaleV84<"ldapursh", 0b01, 0b11, GPR32>; 3392defm LDAPURSHX : BaseLoadUnscaleV84<"ldapursh", 0b01, 0b10, GPR64>; 3393defm LDAPUR : BaseLoadUnscaleV84<"ldapur", 0b10, 0b01, GPR32>; 3394defm LDAPURSW : BaseLoadUnscaleV84<"ldapursw", 0b10, 0b10, GPR64>; 3395defm LDAPURX : BaseLoadUnscaleV84<"ldapur", 0b11, 0b01, GPR64>; 3396} 3397 3398// Match all store 64 bits width whose type is compatible with FPR64 3399def : Pat<(store (v1f64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)), 3400 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>; 3401def : Pat<(store (v1i64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)), 3402 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>; 3403 3404let AddedComplexity = 10 in { 3405 3406let Predicates = [IsLE] in { 3407 // We must use ST1 to store vectors in big-endian. 3408 def : Pat<(store (v2f32 FPR64:$Rt), 3409 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)), 3410 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>; 3411 def : Pat<(store (v8i8 FPR64:$Rt), 3412 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)), 3413 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>; 3414 def : Pat<(store (v4i16 FPR64:$Rt), 3415 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)), 3416 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>; 3417 def : Pat<(store (v2i32 FPR64:$Rt), 3418 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)), 3419 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>; 3420 def : Pat<(store (v4f16 FPR64:$Rt), 3421 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)), 3422 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>; 3423 def : Pat<(store (v4bf16 FPR64:$Rt), 3424 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)), 3425 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>; 3426} 3427 3428// Match all store 128 bits width whose type is compatible with FPR128 3429def : Pat<(store (f128 FPR128:$Rt), (am_unscaled128 GPR64sp:$Rn, simm9:$offset)), 3430 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>; 3431 3432let Predicates = [IsLE] in { 3433 // We must use ST1 to store vectors in big-endian. 3434 def : Pat<(store (v4f32 FPR128:$Rt), 3435 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)), 3436 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>; 3437 def : Pat<(store (v2f64 FPR128:$Rt), 3438 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)), 3439 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>; 3440 def : Pat<(store (v16i8 FPR128:$Rt), 3441 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)), 3442 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>; 3443 def : Pat<(store (v8i16 FPR128:$Rt), 3444 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)), 3445 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>; 3446 def : Pat<(store (v4i32 FPR128:$Rt), 3447 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)), 3448 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>; 3449 def : Pat<(store (v2i64 FPR128:$Rt), 3450 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)), 3451 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>; 3452 def : Pat<(store (v2f64 FPR128:$Rt), 3453 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)), 3454 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>; 3455 def : Pat<(store (v8f16 FPR128:$Rt), 3456 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)), 3457 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>; 3458 def : Pat<(store (v8bf16 FPR128:$Rt), 3459 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)), 3460 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>; 3461} 3462 3463} // AddedComplexity = 10 3464 3465// unscaled i64 truncating stores 3466def : Pat<(truncstorei32 GPR64:$Rt, (am_unscaled32 GPR64sp:$Rn, simm9:$offset)), 3467 (STURWi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>; 3468def : Pat<(truncstorei16 GPR64:$Rt, (am_unscaled16 GPR64sp:$Rn, simm9:$offset)), 3469 (STURHHi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>; 3470def : Pat<(truncstorei8 GPR64:$Rt, (am_unscaled8 GPR64sp:$Rn, simm9:$offset)), 3471 (STURBBi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>; 3472 3473// Match stores from lane 0 to the appropriate subreg's store. 3474multiclass VecStoreULane0Pat<SDPatternOperator StoreOp, 3475 ValueType VTy, ValueType STy, 3476 SubRegIndex SubRegIdx, Instruction STR> { 3477 defm : VecStoreLane0Pat<am_unscaled128, StoreOp, VTy, STy, SubRegIdx, simm9, STR>; 3478} 3479 3480let AddedComplexity = 19 in { 3481 defm : VecStoreULane0Pat<truncstorei16, v8i16, i32, hsub, STURHi>; 3482 defm : VecStoreULane0Pat<store, v8f16, f16, hsub, STURHi>; 3483 defm : VecStoreULane0Pat<store, v4i32, i32, ssub, STURSi>; 3484 defm : VecStoreULane0Pat<store, v4f32, f32, ssub, STURSi>; 3485 defm : VecStoreULane0Pat<store, v2i64, i64, dsub, STURDi>; 3486 defm : VecStoreULane0Pat<store, v2f64, f64, dsub, STURDi>; 3487} 3488 3489//--- 3490// STR mnemonics fall back to STUR for negative or unaligned offsets. 3491def : InstAlias<"str $Rt, [$Rn, $offset]", 3492 (STURXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>; 3493def : InstAlias<"str $Rt, [$Rn, $offset]", 3494 (STURWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>; 3495def : InstAlias<"str $Rt, [$Rn, $offset]", 3496 (STURBi FPR8Op:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>; 3497def : InstAlias<"str $Rt, [$Rn, $offset]", 3498 (STURHi FPR16Op:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>; 3499def : InstAlias<"str $Rt, [$Rn, $offset]", 3500 (STURSi FPR32Op:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>; 3501def : InstAlias<"str $Rt, [$Rn, $offset]", 3502 (STURDi FPR64Op:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>; 3503def : InstAlias<"str $Rt, [$Rn, $offset]", 3504 (STURQi FPR128Op:$Rt, GPR64sp:$Rn, simm9_offset_fb128:$offset), 0>; 3505 3506def : InstAlias<"strb $Rt, [$Rn, $offset]", 3507 (STURBBi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>; 3508def : InstAlias<"strh $Rt, [$Rn, $offset]", 3509 (STURHHi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>; 3510 3511//--- 3512// (unscaled immediate, unprivileged) 3513defm STTRW : StoreUnprivileged<0b10, 0, 0b00, GPR32, "sttr">; 3514defm STTRX : StoreUnprivileged<0b11, 0, 0b00, GPR64, "sttr">; 3515 3516defm STTRH : StoreUnprivileged<0b01, 0, 0b00, GPR32, "sttrh">; 3517defm STTRB : StoreUnprivileged<0b00, 0, 0b00, GPR32, "sttrb">; 3518 3519//--- 3520// (immediate pre-indexed) 3521def STRWpre : StorePreIdx<0b10, 0, 0b00, GPR32z, "str", pre_store, i32>; 3522def STRXpre : StorePreIdx<0b11, 0, 0b00, GPR64z, "str", pre_store, i64>; 3523def STRBpre : StorePreIdx<0b00, 1, 0b00, FPR8Op, "str", pre_store, untyped>; 3524def STRHpre : StorePreIdx<0b01, 1, 0b00, FPR16Op, "str", pre_store, f16>; 3525def STRSpre : StorePreIdx<0b10, 1, 0b00, FPR32Op, "str", pre_store, f32>; 3526def STRDpre : StorePreIdx<0b11, 1, 0b00, FPR64Op, "str", pre_store, f64>; 3527def STRQpre : StorePreIdx<0b00, 1, 0b10, FPR128Op, "str", pre_store, f128>; 3528 3529def STRBBpre : StorePreIdx<0b00, 0, 0b00, GPR32z, "strb", pre_truncsti8, i32>; 3530def STRHHpre : StorePreIdx<0b01, 0, 0b00, GPR32z, "strh", pre_truncsti16, i32>; 3531 3532// truncstore i64 3533def : Pat<(pre_truncsti32 GPR64:$Rt, GPR64sp:$addr, simm9:$off), 3534 (STRWpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr, 3535 simm9:$off)>; 3536def : Pat<(pre_truncsti16 GPR64:$Rt, GPR64sp:$addr, simm9:$off), 3537 (STRHHpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr, 3538 simm9:$off)>; 3539def : Pat<(pre_truncsti8 GPR64:$Rt, GPR64sp:$addr, simm9:$off), 3540 (STRBBpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr, 3541 simm9:$off)>; 3542 3543def : Pat<(pre_store (v8i8 FPR64:$Rt), GPR64sp:$addr, simm9:$off), 3544 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>; 3545def : Pat<(pre_store (v4i16 FPR64:$Rt), GPR64sp:$addr, simm9:$off), 3546 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>; 3547def : Pat<(pre_store (v2i32 FPR64:$Rt), GPR64sp:$addr, simm9:$off), 3548 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>; 3549def : Pat<(pre_store (v2f32 FPR64:$Rt), GPR64sp:$addr, simm9:$off), 3550 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>; 3551def : Pat<(pre_store (v1i64 FPR64:$Rt), GPR64sp:$addr, simm9:$off), 3552 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>; 3553def : Pat<(pre_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off), 3554 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>; 3555def : Pat<(pre_store (v4f16 FPR64:$Rt), GPR64sp:$addr, simm9:$off), 3556 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>; 3557 3558def : Pat<(pre_store (v16i8 FPR128:$Rt), GPR64sp:$addr, simm9:$off), 3559 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>; 3560def : Pat<(pre_store (v8i16 FPR128:$Rt), GPR64sp:$addr, simm9:$off), 3561 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>; 3562def : Pat<(pre_store (v4i32 FPR128:$Rt), GPR64sp:$addr, simm9:$off), 3563 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>; 3564def : Pat<(pre_store (v4f32 FPR128:$Rt), GPR64sp:$addr, simm9:$off), 3565 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>; 3566def : Pat<(pre_store (v2i64 FPR128:$Rt), GPR64sp:$addr, simm9:$off), 3567 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>; 3568def : Pat<(pre_store (v2f64 FPR128:$Rt), GPR64sp:$addr, simm9:$off), 3569 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>; 3570def : Pat<(pre_store (v8f16 FPR128:$Rt), GPR64sp:$addr, simm9:$off), 3571 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>; 3572 3573//--- 3574// (immediate post-indexed) 3575def STRWpost : StorePostIdx<0b10, 0, 0b00, GPR32z, "str", post_store, i32>; 3576def STRXpost : StorePostIdx<0b11, 0, 0b00, GPR64z, "str", post_store, i64>; 3577def STRBpost : StorePostIdx<0b00, 1, 0b00, FPR8Op, "str", post_store, untyped>; 3578def STRHpost : StorePostIdx<0b01, 1, 0b00, FPR16Op, "str", post_store, f16>; 3579def STRSpost : StorePostIdx<0b10, 1, 0b00, FPR32Op, "str", post_store, f32>; 3580def STRDpost : StorePostIdx<0b11, 1, 0b00, FPR64Op, "str", post_store, f64>; 3581def STRQpost : StorePostIdx<0b00, 1, 0b10, FPR128Op, "str", post_store, f128>; 3582 3583def STRBBpost : StorePostIdx<0b00, 0, 0b00, GPR32z, "strb", post_truncsti8, i32>; 3584def STRHHpost : StorePostIdx<0b01, 0, 0b00, GPR32z, "strh", post_truncsti16, i32>; 3585 3586// truncstore i64 3587def : Pat<(post_truncsti32 GPR64:$Rt, GPR64sp:$addr, simm9:$off), 3588 (STRWpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr, 3589 simm9:$off)>; 3590def : Pat<(post_truncsti16 GPR64:$Rt, GPR64sp:$addr, simm9:$off), 3591 (STRHHpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr, 3592 simm9:$off)>; 3593def : Pat<(post_truncsti8 GPR64:$Rt, GPR64sp:$addr, simm9:$off), 3594 (STRBBpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr, 3595 simm9:$off)>; 3596 3597def : Pat<(post_store (bf16 FPR16:$Rt), GPR64sp:$addr, simm9:$off), 3598 (STRHpost FPR16:$Rt, GPR64sp:$addr, simm9:$off)>; 3599 3600def : Pat<(post_store (v8i8 FPR64:$Rt), GPR64sp:$addr, simm9:$off), 3601 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>; 3602def : Pat<(post_store (v4i16 FPR64:$Rt), GPR64sp:$addr, simm9:$off), 3603 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>; 3604def : Pat<(post_store (v2i32 FPR64:$Rt), GPR64sp:$addr, simm9:$off), 3605 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>; 3606def : Pat<(post_store (v2f32 FPR64:$Rt), GPR64sp:$addr, simm9:$off), 3607 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>; 3608def : Pat<(post_store (v1i64 FPR64:$Rt), GPR64sp:$addr, simm9:$off), 3609 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>; 3610def : Pat<(post_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off), 3611 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>; 3612def : Pat<(post_store (v4f16 FPR64:$Rt), GPR64sp:$addr, simm9:$off), 3613 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>; 3614def : Pat<(post_store (v4bf16 FPR64:$Rt), GPR64sp:$addr, simm9:$off), 3615 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>; 3616 3617def : Pat<(post_store (v16i8 FPR128:$Rt), GPR64sp:$addr, simm9:$off), 3618 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>; 3619def : Pat<(post_store (v8i16 FPR128:$Rt), GPR64sp:$addr, simm9:$off), 3620 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>; 3621def : Pat<(post_store (v4i32 FPR128:$Rt), GPR64sp:$addr, simm9:$off), 3622 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>; 3623def : Pat<(post_store (v4f32 FPR128:$Rt), GPR64sp:$addr, simm9:$off), 3624 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>; 3625def : Pat<(post_store (v2i64 FPR128:$Rt), GPR64sp:$addr, simm9:$off), 3626 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>; 3627def : Pat<(post_store (v2f64 FPR128:$Rt), GPR64sp:$addr, simm9:$off), 3628 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>; 3629def : Pat<(post_store (v8f16 FPR128:$Rt), GPR64sp:$addr, simm9:$off), 3630 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>; 3631def : Pat<(post_store (v8bf16 FPR128:$Rt), GPR64sp:$addr, simm9:$off), 3632 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>; 3633 3634//===----------------------------------------------------------------------===// 3635// Load/store exclusive instructions. 3636//===----------------------------------------------------------------------===// 3637 3638def LDARW : LoadAcquire <0b10, 1, 1, 0, 1, GPR32, "ldar">; 3639def LDARX : LoadAcquire <0b11, 1, 1, 0, 1, GPR64, "ldar">; 3640def LDARB : LoadAcquire <0b00, 1, 1, 0, 1, GPR32, "ldarb">; 3641def LDARH : LoadAcquire <0b01, 1, 1, 0, 1, GPR32, "ldarh">; 3642 3643def LDAXRW : LoadExclusive <0b10, 0, 1, 0, 1, GPR32, "ldaxr">; 3644def LDAXRX : LoadExclusive <0b11, 0, 1, 0, 1, GPR64, "ldaxr">; 3645def LDAXRB : LoadExclusive <0b00, 0, 1, 0, 1, GPR32, "ldaxrb">; 3646def LDAXRH : LoadExclusive <0b01, 0, 1, 0, 1, GPR32, "ldaxrh">; 3647 3648def LDXRW : LoadExclusive <0b10, 0, 1, 0, 0, GPR32, "ldxr">; 3649def LDXRX : LoadExclusive <0b11, 0, 1, 0, 0, GPR64, "ldxr">; 3650def LDXRB : LoadExclusive <0b00, 0, 1, 0, 0, GPR32, "ldxrb">; 3651def LDXRH : LoadExclusive <0b01, 0, 1, 0, 0, GPR32, "ldxrh">; 3652 3653def STLRW : StoreRelease <0b10, 1, 0, 0, 1, GPR32, "stlr">; 3654def STLRX : StoreRelease <0b11, 1, 0, 0, 1, GPR64, "stlr">; 3655def STLRB : StoreRelease <0b00, 1, 0, 0, 1, GPR32, "stlrb">; 3656def STLRH : StoreRelease <0b01, 1, 0, 0, 1, GPR32, "stlrh">; 3657 3658def STLXRW : StoreExclusive<0b10, 0, 0, 0, 1, GPR32, "stlxr">; 3659def STLXRX : StoreExclusive<0b11, 0, 0, 0, 1, GPR64, "stlxr">; 3660def STLXRB : StoreExclusive<0b00, 0, 0, 0, 1, GPR32, "stlxrb">; 3661def STLXRH : StoreExclusive<0b01, 0, 0, 0, 1, GPR32, "stlxrh">; 3662 3663def STXRW : StoreExclusive<0b10, 0, 0, 0, 0, GPR32, "stxr">; 3664def STXRX : StoreExclusive<0b11, 0, 0, 0, 0, GPR64, "stxr">; 3665def STXRB : StoreExclusive<0b00, 0, 0, 0, 0, GPR32, "stxrb">; 3666def STXRH : StoreExclusive<0b01, 0, 0, 0, 0, GPR32, "stxrh">; 3667 3668def LDAXPW : LoadExclusivePair<0b10, 0, 1, 1, 1, GPR32, "ldaxp">; 3669def LDAXPX : LoadExclusivePair<0b11, 0, 1, 1, 1, GPR64, "ldaxp">; 3670 3671def LDXPW : LoadExclusivePair<0b10, 0, 1, 1, 0, GPR32, "ldxp">; 3672def LDXPX : LoadExclusivePair<0b11, 0, 1, 1, 0, GPR64, "ldxp">; 3673 3674def STLXPW : StoreExclusivePair<0b10, 0, 0, 1, 1, GPR32, "stlxp">; 3675def STLXPX : StoreExclusivePair<0b11, 0, 0, 1, 1, GPR64, "stlxp">; 3676 3677def STXPW : StoreExclusivePair<0b10, 0, 0, 1, 0, GPR32, "stxp">; 3678def STXPX : StoreExclusivePair<0b11, 0, 0, 1, 0, GPR64, "stxp">; 3679 3680let Predicates = [HasLOR] in { 3681 // v8.1a "Limited Order Region" extension load-acquire instructions 3682 def LDLARW : LoadAcquire <0b10, 1, 1, 0, 0, GPR32, "ldlar">; 3683 def LDLARX : LoadAcquire <0b11, 1, 1, 0, 0, GPR64, "ldlar">; 3684 def LDLARB : LoadAcquire <0b00, 1, 1, 0, 0, GPR32, "ldlarb">; 3685 def LDLARH : LoadAcquire <0b01, 1, 1, 0, 0, GPR32, "ldlarh">; 3686 3687 // v8.1a "Limited Order Region" extension store-release instructions 3688 def STLLRW : StoreRelease <0b10, 1, 0, 0, 0, GPR32, "stllr">; 3689 def STLLRX : StoreRelease <0b11, 1, 0, 0, 0, GPR64, "stllr">; 3690 def STLLRB : StoreRelease <0b00, 1, 0, 0, 0, GPR32, "stllrb">; 3691 def STLLRH : StoreRelease <0b01, 1, 0, 0, 0, GPR32, "stllrh">; 3692} 3693 3694//===----------------------------------------------------------------------===// 3695// Scaled floating point to integer conversion instructions. 3696//===----------------------------------------------------------------------===// 3697 3698defm FCVTAS : FPToIntegerUnscaled<0b00, 0b100, "fcvtas", int_aarch64_neon_fcvtas>; 3699defm FCVTAU : FPToIntegerUnscaled<0b00, 0b101, "fcvtau", int_aarch64_neon_fcvtau>; 3700defm FCVTMS : FPToIntegerUnscaled<0b10, 0b000, "fcvtms", int_aarch64_neon_fcvtms>; 3701defm FCVTMU : FPToIntegerUnscaled<0b10, 0b001, "fcvtmu", int_aarch64_neon_fcvtmu>; 3702defm FCVTNS : FPToIntegerUnscaled<0b00, 0b000, "fcvtns", int_aarch64_neon_fcvtns>; 3703defm FCVTNU : FPToIntegerUnscaled<0b00, 0b001, "fcvtnu", int_aarch64_neon_fcvtnu>; 3704defm FCVTPS : FPToIntegerUnscaled<0b01, 0b000, "fcvtps", int_aarch64_neon_fcvtps>; 3705defm FCVTPU : FPToIntegerUnscaled<0b01, 0b001, "fcvtpu", int_aarch64_neon_fcvtpu>; 3706defm FCVTZS : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", any_fp_to_sint>; 3707defm FCVTZU : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", any_fp_to_uint>; 3708defm FCVTZS : FPToIntegerScaled<0b11, 0b000, "fcvtzs", any_fp_to_sint>; 3709defm FCVTZU : FPToIntegerScaled<0b11, 0b001, "fcvtzu", any_fp_to_uint>; 3710 3711// AArch64's FCVT instructions saturate when out of range. 3712multiclass FPToIntegerSatPats<SDNode to_int_sat, string INST> { 3713 def : Pat<(i32 (to_int_sat f16:$Rn, i32)), 3714 (!cast<Instruction>(INST # UWHr) f16:$Rn)>; 3715 def : Pat<(i32 (to_int_sat f32:$Rn, i32)), 3716 (!cast<Instruction>(INST # UWSr) f32:$Rn)>; 3717 def : Pat<(i32 (to_int_sat f64:$Rn, i32)), 3718 (!cast<Instruction>(INST # UWDr) f64:$Rn)>; 3719 def : Pat<(i64 (to_int_sat f16:$Rn, i64)), 3720 (!cast<Instruction>(INST # UXHr) f16:$Rn)>; 3721 def : Pat<(i64 (to_int_sat f32:$Rn, i64)), 3722 (!cast<Instruction>(INST # UXSr) f32:$Rn)>; 3723 def : Pat<(i64 (to_int_sat f64:$Rn, i64)), 3724 (!cast<Instruction>(INST # UXDr) f64:$Rn)>; 3725} 3726 3727defm : FPToIntegerSatPats<fp_to_sint_sat, "FCVTZS">; 3728defm : FPToIntegerSatPats<fp_to_uint_sat, "FCVTZU">; 3729 3730multiclass FPToIntegerIntPats<Intrinsic round, string INST> { 3731 def : Pat<(i32 (round f16:$Rn)), (!cast<Instruction>(INST # UWHr) $Rn)>; 3732 def : Pat<(i64 (round f16:$Rn)), (!cast<Instruction>(INST # UXHr) $Rn)>; 3733 def : Pat<(i32 (round f32:$Rn)), (!cast<Instruction>(INST # UWSr) $Rn)>; 3734 def : Pat<(i64 (round f32:$Rn)), (!cast<Instruction>(INST # UXSr) $Rn)>; 3735 def : Pat<(i32 (round f64:$Rn)), (!cast<Instruction>(INST # UWDr) $Rn)>; 3736 def : Pat<(i64 (round f64:$Rn)), (!cast<Instruction>(INST # UXDr) $Rn)>; 3737 3738 def : Pat<(i32 (round (fmul f16:$Rn, fixedpoint_f16_i32:$scale))), 3739 (!cast<Instruction>(INST # SWHri) $Rn, $scale)>; 3740 def : Pat<(i64 (round (fmul f16:$Rn, fixedpoint_f16_i64:$scale))), 3741 (!cast<Instruction>(INST # SXHri) $Rn, $scale)>; 3742 def : Pat<(i32 (round (fmul f32:$Rn, fixedpoint_f32_i32:$scale))), 3743 (!cast<Instruction>(INST # SWSri) $Rn, $scale)>; 3744 def : Pat<(i64 (round (fmul f32:$Rn, fixedpoint_f32_i64:$scale))), 3745 (!cast<Instruction>(INST # SXSri) $Rn, $scale)>; 3746 def : Pat<(i32 (round (fmul f64:$Rn, fixedpoint_f64_i32:$scale))), 3747 (!cast<Instruction>(INST # SWDri) $Rn, $scale)>; 3748 def : Pat<(i64 (round (fmul f64:$Rn, fixedpoint_f64_i64:$scale))), 3749 (!cast<Instruction>(INST # SXDri) $Rn, $scale)>; 3750} 3751 3752defm : FPToIntegerIntPats<int_aarch64_neon_fcvtzs, "FCVTZS">; 3753defm : FPToIntegerIntPats<int_aarch64_neon_fcvtzu, "FCVTZU">; 3754 3755multiclass FPToIntegerPats<SDNode to_int, SDNode to_int_sat, SDNode round, string INST> { 3756 def : Pat<(i32 (to_int (round f32:$Rn))), 3757 (!cast<Instruction>(INST # UWSr) f32:$Rn)>; 3758 def : Pat<(i64 (to_int (round f32:$Rn))), 3759 (!cast<Instruction>(INST # UXSr) f32:$Rn)>; 3760 def : Pat<(i32 (to_int (round f64:$Rn))), 3761 (!cast<Instruction>(INST # UWDr) f64:$Rn)>; 3762 def : Pat<(i64 (to_int (round f64:$Rn))), 3763 (!cast<Instruction>(INST # UXDr) f64:$Rn)>; 3764 3765 // These instructions saturate like fp_to_[su]int_sat. 3766 def : Pat<(i32 (to_int_sat (round f16:$Rn), i32)), 3767 (!cast<Instruction>(INST # UWHr) f16:$Rn)>; 3768 def : Pat<(i64 (to_int_sat (round f16:$Rn), i64)), 3769 (!cast<Instruction>(INST # UXHr) f16:$Rn)>; 3770 def : Pat<(i32 (to_int_sat (round f32:$Rn), i32)), 3771 (!cast<Instruction>(INST # UWSr) f32:$Rn)>; 3772 def : Pat<(i64 (to_int_sat (round f32:$Rn), i64)), 3773 (!cast<Instruction>(INST # UXSr) f32:$Rn)>; 3774 def : Pat<(i32 (to_int_sat (round f64:$Rn), i32)), 3775 (!cast<Instruction>(INST # UWDr) f64:$Rn)>; 3776 def : Pat<(i64 (to_int_sat (round f64:$Rn), i64)), 3777 (!cast<Instruction>(INST # UXDr) f64:$Rn)>; 3778} 3779 3780defm : FPToIntegerPats<fp_to_sint, fp_to_sint_sat, fceil, "FCVTPS">; 3781defm : FPToIntegerPats<fp_to_uint, fp_to_uint_sat, fceil, "FCVTPU">; 3782defm : FPToIntegerPats<fp_to_sint, fp_to_sint_sat, ffloor, "FCVTMS">; 3783defm : FPToIntegerPats<fp_to_uint, fp_to_uint_sat, ffloor, "FCVTMU">; 3784defm : FPToIntegerPats<fp_to_sint, fp_to_sint_sat, ftrunc, "FCVTZS">; 3785defm : FPToIntegerPats<fp_to_uint, fp_to_uint_sat, ftrunc, "FCVTZU">; 3786defm : FPToIntegerPats<fp_to_sint, fp_to_sint_sat, fround, "FCVTAS">; 3787defm : FPToIntegerPats<fp_to_uint, fp_to_uint_sat, fround, "FCVTAU">; 3788 3789 3790 3791let Predicates = [HasFullFP16] in { 3792 def : Pat<(i32 (lround f16:$Rn)), 3793 (!cast<Instruction>(FCVTASUWHr) f16:$Rn)>; 3794 def : Pat<(i64 (lround f16:$Rn)), 3795 (!cast<Instruction>(FCVTASUXHr) f16:$Rn)>; 3796 def : Pat<(i64 (llround f16:$Rn)), 3797 (!cast<Instruction>(FCVTASUXHr) f16:$Rn)>; 3798} 3799def : Pat<(i32 (lround f32:$Rn)), 3800 (!cast<Instruction>(FCVTASUWSr) f32:$Rn)>; 3801def : Pat<(i32 (lround f64:$Rn)), 3802 (!cast<Instruction>(FCVTASUWDr) f64:$Rn)>; 3803def : Pat<(i64 (lround f32:$Rn)), 3804 (!cast<Instruction>(FCVTASUXSr) f32:$Rn)>; 3805def : Pat<(i64 (lround f64:$Rn)), 3806 (!cast<Instruction>(FCVTASUXDr) f64:$Rn)>; 3807def : Pat<(i64 (llround f32:$Rn)), 3808 (!cast<Instruction>(FCVTASUXSr) f32:$Rn)>; 3809def : Pat<(i64 (llround f64:$Rn)), 3810 (!cast<Instruction>(FCVTASUXDr) f64:$Rn)>; 3811 3812//===----------------------------------------------------------------------===// 3813// Scaled integer to floating point conversion instructions. 3814//===----------------------------------------------------------------------===// 3815 3816defm SCVTF : IntegerToFP<0, "scvtf", any_sint_to_fp>; 3817defm UCVTF : IntegerToFP<1, "ucvtf", any_uint_to_fp>; 3818 3819//===----------------------------------------------------------------------===// 3820// Unscaled integer to floating point conversion instruction. 3821//===----------------------------------------------------------------------===// 3822 3823defm FMOV : UnscaledConversion<"fmov">; 3824 3825// Add pseudo ops for FMOV 0 so we can mark them as isReMaterializable 3826let isReMaterializable = 1, isCodeGenOnly = 1, isAsCheapAsAMove = 1 in { 3827def FMOVH0 : Pseudo<(outs FPR16:$Rd), (ins), [(set f16:$Rd, (fpimm0))]>, 3828 Sched<[WriteF]>, Requires<[HasFullFP16]>; 3829def FMOVS0 : Pseudo<(outs FPR32:$Rd), (ins), [(set f32:$Rd, (fpimm0))]>, 3830 Sched<[WriteF]>; 3831def FMOVD0 : Pseudo<(outs FPR64:$Rd), (ins), [(set f64:$Rd, (fpimm0))]>, 3832 Sched<[WriteF]>; 3833} 3834// Similarly add aliases 3835def : InstAlias<"fmov $Rd, #0.0", (FMOVWHr FPR16:$Rd, WZR), 0>, 3836 Requires<[HasFullFP16]>; 3837def : InstAlias<"fmov $Rd, #0.0", (FMOVWSr FPR32:$Rd, WZR), 0>; 3838def : InstAlias<"fmov $Rd, #0.0", (FMOVXDr FPR64:$Rd, XZR), 0>; 3839 3840//===----------------------------------------------------------------------===// 3841// Floating point conversion instruction. 3842//===----------------------------------------------------------------------===// 3843 3844defm FCVT : FPConversion<"fcvt">; 3845 3846//===----------------------------------------------------------------------===// 3847// Floating point single operand instructions. 3848//===----------------------------------------------------------------------===// 3849 3850defm FABS : SingleOperandFPData<0b0001, "fabs", fabs>; 3851defm FMOV : SingleOperandFPData<0b0000, "fmov">; 3852defm FNEG : SingleOperandFPData<0b0010, "fneg", fneg>; 3853defm FRINTA : SingleOperandFPData<0b1100, "frinta", fround>; 3854defm FRINTI : SingleOperandFPData<0b1111, "frinti", fnearbyint>; 3855defm FRINTM : SingleOperandFPData<0b1010, "frintm", ffloor>; 3856defm FRINTN : SingleOperandFPData<0b1000, "frintn", froundeven>; 3857defm FRINTP : SingleOperandFPData<0b1001, "frintp", fceil>; 3858 3859defm FRINTX : SingleOperandFPData<0b1110, "frintx", frint>; 3860defm FRINTZ : SingleOperandFPData<0b1011, "frintz", ftrunc>; 3861 3862let SchedRW = [WriteFDiv] in { 3863defm FSQRT : SingleOperandFPData<0b0011, "fsqrt", fsqrt>; 3864} 3865 3866let Predicates = [HasFRInt3264] in { 3867 defm FRINT32Z : FRIntNNT<0b00, "frint32z", int_aarch64_frint32z>; 3868 defm FRINT64Z : FRIntNNT<0b10, "frint64z", int_aarch64_frint64z>; 3869 defm FRINT32X : FRIntNNT<0b01, "frint32x", int_aarch64_frint32x>; 3870 defm FRINT64X : FRIntNNT<0b11, "frint64x", int_aarch64_frint64x>; 3871} // HasFRInt3264 3872 3873let Predicates = [HasFullFP16] in { 3874 def : Pat<(i32 (lrint f16:$Rn)), 3875 (FCVTZSUWHr (!cast<Instruction>(FRINTXHr) f16:$Rn))>; 3876 def : Pat<(i64 (lrint f16:$Rn)), 3877 (FCVTZSUXHr (!cast<Instruction>(FRINTXHr) f16:$Rn))>; 3878 def : Pat<(i64 (llrint f16:$Rn)), 3879 (FCVTZSUXHr (!cast<Instruction>(FRINTXHr) f16:$Rn))>; 3880} 3881def : Pat<(i32 (lrint f32:$Rn)), 3882 (FCVTZSUWSr (!cast<Instruction>(FRINTXSr) f32:$Rn))>; 3883def : Pat<(i32 (lrint f64:$Rn)), 3884 (FCVTZSUWDr (!cast<Instruction>(FRINTXDr) f64:$Rn))>; 3885def : Pat<(i64 (lrint f32:$Rn)), 3886 (FCVTZSUXSr (!cast<Instruction>(FRINTXSr) f32:$Rn))>; 3887def : Pat<(i64 (lrint f64:$Rn)), 3888 (FCVTZSUXDr (!cast<Instruction>(FRINTXDr) f64:$Rn))>; 3889def : Pat<(i64 (llrint f32:$Rn)), 3890 (FCVTZSUXSr (!cast<Instruction>(FRINTXSr) f32:$Rn))>; 3891def : Pat<(i64 (llrint f64:$Rn)), 3892 (FCVTZSUXDr (!cast<Instruction>(FRINTXDr) f64:$Rn))>; 3893 3894//===----------------------------------------------------------------------===// 3895// Floating point two operand instructions. 3896//===----------------------------------------------------------------------===// 3897 3898defm FADD : TwoOperandFPData<0b0010, "fadd", fadd>; 3899let SchedRW = [WriteFDiv] in { 3900defm FDIV : TwoOperandFPData<0b0001, "fdiv", fdiv>; 3901} 3902defm FMAXNM : TwoOperandFPData<0b0110, "fmaxnm", fmaxnum>; 3903defm FMAX : TwoOperandFPData<0b0100, "fmax", fmaximum>; 3904defm FMINNM : TwoOperandFPData<0b0111, "fminnm", fminnum>; 3905defm FMIN : TwoOperandFPData<0b0101, "fmin", fminimum>; 3906let SchedRW = [WriteFMul] in { 3907defm FMUL : TwoOperandFPData<0b0000, "fmul", fmul>; 3908defm FNMUL : TwoOperandFPDataNeg<0b1000, "fnmul", fmul>; 3909} 3910defm FSUB : TwoOperandFPData<0b0011, "fsub", fsub>; 3911 3912def : Pat<(v1f64 (fmaximum (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))), 3913 (FMAXDrr FPR64:$Rn, FPR64:$Rm)>; 3914def : Pat<(v1f64 (fminimum (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))), 3915 (FMINDrr FPR64:$Rn, FPR64:$Rm)>; 3916def : Pat<(v1f64 (fmaxnum (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))), 3917 (FMAXNMDrr FPR64:$Rn, FPR64:$Rm)>; 3918def : Pat<(v1f64 (fminnum (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))), 3919 (FMINNMDrr FPR64:$Rn, FPR64:$Rm)>; 3920 3921//===----------------------------------------------------------------------===// 3922// Floating point three operand instructions. 3923//===----------------------------------------------------------------------===// 3924 3925defm FMADD : ThreeOperandFPData<0, 0, "fmadd", fma>; 3926defm FMSUB : ThreeOperandFPData<0, 1, "fmsub", 3927 TriOpFrag<(fma node:$LHS, (fneg node:$MHS), node:$RHS)> >; 3928defm FNMADD : ThreeOperandFPData<1, 0, "fnmadd", 3929 TriOpFrag<(fneg (fma node:$LHS, node:$MHS, node:$RHS))> >; 3930defm FNMSUB : ThreeOperandFPData<1, 1, "fnmsub", 3931 TriOpFrag<(fma node:$LHS, node:$MHS, (fneg node:$RHS))> >; 3932 3933// The following def pats catch the case where the LHS of an FMA is negated. 3934// The TriOpFrag above catches the case where the middle operand is negated. 3935 3936// N.b. FMSUB etc have the accumulator at the *end* of (outs), unlike 3937// the NEON variant. 3938 3939// Here we handle first -(a + b*c) for FNMADD: 3940 3941let Predicates = [HasNEON, HasFullFP16] in 3942def : Pat<(f16 (fma (fneg FPR16:$Rn), FPR16:$Rm, FPR16:$Ra)), 3943 (FMSUBHrrr FPR16:$Rn, FPR16:$Rm, FPR16:$Ra)>; 3944 3945def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, FPR32:$Ra)), 3946 (FMSUBSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>; 3947 3948def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, FPR64:$Ra)), 3949 (FMSUBDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>; 3950 3951// Now it's time for "(-a) + (-b)*c" 3952 3953let Predicates = [HasNEON, HasFullFP16] in 3954def : Pat<(f16 (fma (fneg FPR16:$Rn), FPR16:$Rm, (fneg FPR16:$Ra))), 3955 (FNMADDHrrr FPR16:$Rn, FPR16:$Rm, FPR16:$Ra)>; 3956 3957def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, (fneg FPR32:$Ra))), 3958 (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>; 3959 3960def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, (fneg FPR64:$Ra))), 3961 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>; 3962 3963//===----------------------------------------------------------------------===// 3964// Floating point comparison instructions. 3965//===----------------------------------------------------------------------===// 3966 3967defm FCMPE : FPComparison<1, "fcmpe", AArch64strict_fcmpe>; 3968defm FCMP : FPComparison<0, "fcmp", AArch64any_fcmp>; 3969 3970//===----------------------------------------------------------------------===// 3971// Floating point conditional comparison instructions. 3972//===----------------------------------------------------------------------===// 3973 3974defm FCCMPE : FPCondComparison<1, "fccmpe">; 3975defm FCCMP : FPCondComparison<0, "fccmp", AArch64fccmp>; 3976 3977//===----------------------------------------------------------------------===// 3978// Floating point conditional select instruction. 3979//===----------------------------------------------------------------------===// 3980 3981defm FCSEL : FPCondSelect<"fcsel">; 3982 3983// CSEL instructions providing f128 types need to be handled by a 3984// pseudo-instruction since the eventual code will need to introduce basic 3985// blocks and control flow. 3986def F128CSEL : Pseudo<(outs FPR128:$Rd), 3987 (ins FPR128:$Rn, FPR128:$Rm, ccode:$cond), 3988 [(set (f128 FPR128:$Rd), 3989 (AArch64csel FPR128:$Rn, FPR128:$Rm, 3990 (i32 imm:$cond), NZCV))]> { 3991 let Uses = [NZCV]; 3992 let usesCustomInserter = 1; 3993 let hasNoSchedulingInfo = 1; 3994} 3995 3996//===----------------------------------------------------------------------===// 3997// Instructions used for emitting unwind opcodes on ARM64 Windows. 3998//===----------------------------------------------------------------------===// 3999let isPseudo = 1 in { 4000 def SEH_StackAlloc : Pseudo<(outs), (ins i32imm:$size), []>, Sched<[]>; 4001 def SEH_SaveFPLR : Pseudo<(outs), (ins i32imm:$offs), []>, Sched<[]>; 4002 def SEH_SaveFPLR_X : Pseudo<(outs), (ins i32imm:$offs), []>, Sched<[]>; 4003 def SEH_SaveReg : Pseudo<(outs), (ins i32imm:$reg, i32imm:$offs), []>, Sched<[]>; 4004 def SEH_SaveReg_X : Pseudo<(outs), (ins i32imm:$reg, i32imm:$offs), []>, Sched<[]>; 4005 def SEH_SaveRegP : Pseudo<(outs), (ins i32imm:$reg0, i32imm:$reg1, i32imm:$offs), []>, Sched<[]>; 4006 def SEH_SaveRegP_X : Pseudo<(outs), (ins i32imm:$reg0, i32imm:$reg1, i32imm:$offs), []>, Sched<[]>; 4007 def SEH_SaveFReg : Pseudo<(outs), (ins i32imm:$reg, i32imm:$offs), []>, Sched<[]>; 4008 def SEH_SaveFReg_X : Pseudo<(outs), (ins i32imm:$reg, i32imm:$offs), []>, Sched<[]>; 4009 def SEH_SaveFRegP : Pseudo<(outs), (ins i32imm:$reg0, i32imm:$reg1, i32imm:$offs), []>, Sched<[]>; 4010 def SEH_SaveFRegP_X : Pseudo<(outs), (ins i32imm:$reg0, i32imm:$reg1, i32imm:$offs), []>, Sched<[]>; 4011 def SEH_SetFP : Pseudo<(outs), (ins), []>, Sched<[]>; 4012 def SEH_AddFP : Pseudo<(outs), (ins i32imm:$offs), []>, Sched<[]>; 4013 def SEH_Nop : Pseudo<(outs), (ins), []>, Sched<[]>; 4014 def SEH_PrologEnd : Pseudo<(outs), (ins), []>, Sched<[]>; 4015 def SEH_EpilogStart : Pseudo<(outs), (ins), []>, Sched<[]>; 4016 def SEH_EpilogEnd : Pseudo<(outs), (ins), []>, Sched<[]>; 4017} 4018 4019// Pseudo instructions for Windows EH 4020//===----------------------------------------------------------------------===// 4021let isTerminator = 1, hasSideEffects = 1, isBarrier = 1, hasCtrlDep = 1, 4022 isCodeGenOnly = 1, isReturn = 1, isEHScopeReturn = 1, isPseudo = 1 in { 4023 def CLEANUPRET : Pseudo<(outs), (ins), [(cleanupret)]>, Sched<[]>; 4024 let usesCustomInserter = 1 in 4025 def CATCHRET : Pseudo<(outs), (ins am_brcond:$dst, am_brcond:$src), [(catchret bb:$dst, bb:$src)]>, 4026 Sched<[]>; 4027} 4028 4029// Pseudo instructions for homogeneous prolog/epilog 4030let isPseudo = 1 in { 4031 // Save CSRs in order, {FPOffset} 4032 def HOM_Prolog : Pseudo<(outs), (ins variable_ops), []>, Sched<[]>; 4033 // Restore CSRs in order 4034 def HOM_Epilog : Pseudo<(outs), (ins variable_ops), []>, Sched<[]>; 4035} 4036 4037//===----------------------------------------------------------------------===// 4038// Floating point immediate move. 4039//===----------------------------------------------------------------------===// 4040 4041let isReMaterializable = 1, isAsCheapAsAMove = 1 in { 4042defm FMOV : FPMoveImmediate<"fmov">; 4043} 4044 4045//===----------------------------------------------------------------------===// 4046// Advanced SIMD two vector instructions. 4047//===----------------------------------------------------------------------===// 4048 4049defm UABDL : SIMDLongThreeVectorBHSabdl<1, 0b0111, "uabdl", 4050 AArch64uabd>; 4051// Match UABDL in log2-shuffle patterns. 4052def : Pat<(abs (v8i16 (sub (zext (v8i8 V64:$opA)), 4053 (zext (v8i8 V64:$opB))))), 4054 (UABDLv8i8_v8i16 V64:$opA, V64:$opB)>; 4055def : Pat<(xor (v8i16 (AArch64vashr v8i16:$src, (i32 15))), 4056 (v8i16 (add (sub (zext (v8i8 V64:$opA)), 4057 (zext (v8i8 V64:$opB))), 4058 (AArch64vashr v8i16:$src, (i32 15))))), 4059 (UABDLv8i8_v8i16 V64:$opA, V64:$opB)>; 4060def : Pat<(abs (v8i16 (sub (zext (extract_high_v16i8 V128:$opA)), 4061 (zext (extract_high_v16i8 V128:$opB))))), 4062 (UABDLv16i8_v8i16 V128:$opA, V128:$opB)>; 4063def : Pat<(xor (v8i16 (AArch64vashr v8i16:$src, (i32 15))), 4064 (v8i16 (add (sub (zext (extract_high_v16i8 V128:$opA)), 4065 (zext (extract_high_v16i8 V128:$opB))), 4066 (AArch64vashr v8i16:$src, (i32 15))))), 4067 (UABDLv16i8_v8i16 V128:$opA, V128:$opB)>; 4068def : Pat<(abs (v4i32 (sub (zext (v4i16 V64:$opA)), 4069 (zext (v4i16 V64:$opB))))), 4070 (UABDLv4i16_v4i32 V64:$opA, V64:$opB)>; 4071def : Pat<(abs (v4i32 (sub (zext (extract_high_v8i16 V128:$opA)), 4072 (zext (extract_high_v8i16 V128:$opB))))), 4073 (UABDLv8i16_v4i32 V128:$opA, V128:$opB)>; 4074def : Pat<(abs (v2i64 (sub (zext (v2i32 V64:$opA)), 4075 (zext (v2i32 V64:$opB))))), 4076 (UABDLv2i32_v2i64 V64:$opA, V64:$opB)>; 4077def : Pat<(abs (v2i64 (sub (zext (extract_high_v4i32 V128:$opA)), 4078 (zext (extract_high_v4i32 V128:$opB))))), 4079 (UABDLv4i32_v2i64 V128:$opA, V128:$opB)>; 4080 4081defm ABS : SIMDTwoVectorBHSD<0, 0b01011, "abs", abs>; 4082defm CLS : SIMDTwoVectorBHS<0, 0b00100, "cls", int_aarch64_neon_cls>; 4083defm CLZ : SIMDTwoVectorBHS<1, 0b00100, "clz", ctlz>; 4084defm CMEQ : SIMDCmpTwoVector<0, 0b01001, "cmeq", AArch64cmeqz>; 4085defm CMGE : SIMDCmpTwoVector<1, 0b01000, "cmge", AArch64cmgez>; 4086defm CMGT : SIMDCmpTwoVector<0, 0b01000, "cmgt", AArch64cmgtz>; 4087defm CMLE : SIMDCmpTwoVector<1, 0b01001, "cmle", AArch64cmlez>; 4088defm CMLT : SIMDCmpTwoVector<0, 0b01010, "cmlt", AArch64cmltz>; 4089defm CNT : SIMDTwoVectorB<0, 0b00, 0b00101, "cnt", ctpop>; 4090defm FABS : SIMDTwoVectorFP<0, 1, 0b01111, "fabs", fabs>; 4091 4092defm FCMEQ : SIMDFPCmpTwoVector<0, 1, 0b01101, "fcmeq", AArch64fcmeqz>; 4093defm FCMGE : SIMDFPCmpTwoVector<1, 1, 0b01100, "fcmge", AArch64fcmgez>; 4094defm FCMGT : SIMDFPCmpTwoVector<0, 1, 0b01100, "fcmgt", AArch64fcmgtz>; 4095defm FCMLE : SIMDFPCmpTwoVector<1, 1, 0b01101, "fcmle", AArch64fcmlez>; 4096defm FCMLT : SIMDFPCmpTwoVector<0, 1, 0b01110, "fcmlt", AArch64fcmltz>; 4097defm FCVTAS : SIMDTwoVectorFPToInt<0,0,0b11100, "fcvtas",int_aarch64_neon_fcvtas>; 4098defm FCVTAU : SIMDTwoVectorFPToInt<1,0,0b11100, "fcvtau",int_aarch64_neon_fcvtau>; 4099defm FCVTL : SIMDFPWidenTwoVector<0, 0, 0b10111, "fcvtl">; 4100def : Pat<(v4f32 (int_aarch64_neon_vcvthf2fp (v4i16 V64:$Rn))), 4101 (FCVTLv4i16 V64:$Rn)>; 4102def : Pat<(v4f32 (int_aarch64_neon_vcvthf2fp (extract_subvector (v8i16 V128:$Rn), 4103 (i64 4)))), 4104 (FCVTLv8i16 V128:$Rn)>; 4105def : Pat<(v2f64 (fpextend (v2f32 V64:$Rn))), (FCVTLv2i32 V64:$Rn)>; 4106 4107def : Pat<(v4f32 (fpextend (v4f16 V64:$Rn))), (FCVTLv4i16 V64:$Rn)>; 4108 4109defm FCVTMS : SIMDTwoVectorFPToInt<0,0,0b11011, "fcvtms",int_aarch64_neon_fcvtms>; 4110defm FCVTMU : SIMDTwoVectorFPToInt<1,0,0b11011, "fcvtmu",int_aarch64_neon_fcvtmu>; 4111defm FCVTNS : SIMDTwoVectorFPToInt<0,0,0b11010, "fcvtns",int_aarch64_neon_fcvtns>; 4112defm FCVTNU : SIMDTwoVectorFPToInt<1,0,0b11010, "fcvtnu",int_aarch64_neon_fcvtnu>; 4113defm FCVTN : SIMDFPNarrowTwoVector<0, 0, 0b10110, "fcvtn">; 4114def : Pat<(v4i16 (int_aarch64_neon_vcvtfp2hf (v4f32 V128:$Rn))), 4115 (FCVTNv4i16 V128:$Rn)>; 4116def : Pat<(concat_vectors V64:$Rd, 4117 (v4i16 (int_aarch64_neon_vcvtfp2hf (v4f32 V128:$Rn)))), 4118 (FCVTNv8i16 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>; 4119def : Pat<(v2f32 (fpround (v2f64 V128:$Rn))), (FCVTNv2i32 V128:$Rn)>; 4120def : Pat<(v4f16 (fpround (v4f32 V128:$Rn))), (FCVTNv4i16 V128:$Rn)>; 4121def : Pat<(concat_vectors V64:$Rd, (v2f32 (fpround (v2f64 V128:$Rn)))), 4122 (FCVTNv4i32 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>; 4123defm FCVTPS : SIMDTwoVectorFPToInt<0,1,0b11010, "fcvtps",int_aarch64_neon_fcvtps>; 4124defm FCVTPU : SIMDTwoVectorFPToInt<1,1,0b11010, "fcvtpu",int_aarch64_neon_fcvtpu>; 4125defm FCVTXN : SIMDFPInexactCvtTwoVector<1, 0, 0b10110, "fcvtxn", 4126 int_aarch64_neon_fcvtxn>; 4127defm FCVTZS : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs", fp_to_sint>; 4128defm FCVTZU : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu", fp_to_uint>; 4129 4130def : Pat<(v4i16 (int_aarch64_neon_fcvtzs v4f16:$Rn)), (FCVTZSv4f16 $Rn)>; 4131def : Pat<(v8i16 (int_aarch64_neon_fcvtzs v8f16:$Rn)), (FCVTZSv8f16 $Rn)>; 4132def : Pat<(v2i32 (int_aarch64_neon_fcvtzs v2f32:$Rn)), (FCVTZSv2f32 $Rn)>; 4133def : Pat<(v4i32 (int_aarch64_neon_fcvtzs v4f32:$Rn)), (FCVTZSv4f32 $Rn)>; 4134def : Pat<(v2i64 (int_aarch64_neon_fcvtzs v2f64:$Rn)), (FCVTZSv2f64 $Rn)>; 4135 4136def : Pat<(v4i16 (int_aarch64_neon_fcvtzu v4f16:$Rn)), (FCVTZUv4f16 $Rn)>; 4137def : Pat<(v8i16 (int_aarch64_neon_fcvtzu v8f16:$Rn)), (FCVTZUv8f16 $Rn)>; 4138def : Pat<(v2i32 (int_aarch64_neon_fcvtzu v2f32:$Rn)), (FCVTZUv2f32 $Rn)>; 4139def : Pat<(v4i32 (int_aarch64_neon_fcvtzu v4f32:$Rn)), (FCVTZUv4f32 $Rn)>; 4140def : Pat<(v2i64 (int_aarch64_neon_fcvtzu v2f64:$Rn)), (FCVTZUv2f64 $Rn)>; 4141 4142defm FNEG : SIMDTwoVectorFP<1, 1, 0b01111, "fneg", fneg>; 4143defm FRECPE : SIMDTwoVectorFP<0, 1, 0b11101, "frecpe", int_aarch64_neon_frecpe>; 4144defm FRINTA : SIMDTwoVectorFP<1, 0, 0b11000, "frinta", fround>; 4145defm FRINTI : SIMDTwoVectorFP<1, 1, 0b11001, "frinti", fnearbyint>; 4146defm FRINTM : SIMDTwoVectorFP<0, 0, 0b11001, "frintm", ffloor>; 4147defm FRINTN : SIMDTwoVectorFP<0, 0, 0b11000, "frintn", froundeven>; 4148defm FRINTP : SIMDTwoVectorFP<0, 1, 0b11000, "frintp", fceil>; 4149defm FRINTX : SIMDTwoVectorFP<1, 0, 0b11001, "frintx", frint>; 4150defm FRINTZ : SIMDTwoVectorFP<0, 1, 0b11001, "frintz", ftrunc>; 4151 4152let Predicates = [HasFRInt3264] in { 4153 defm FRINT32Z : FRIntNNTVector<0, 0, "frint32z", int_aarch64_neon_frint32z>; 4154 defm FRINT64Z : FRIntNNTVector<0, 1, "frint64z", int_aarch64_neon_frint64z>; 4155 defm FRINT32X : FRIntNNTVector<1, 0, "frint32x", int_aarch64_neon_frint32x>; 4156 defm FRINT64X : FRIntNNTVector<1, 1, "frint64x", int_aarch64_neon_frint64x>; 4157} // HasFRInt3264 4158 4159defm FRSQRTE: SIMDTwoVectorFP<1, 1, 0b11101, "frsqrte", int_aarch64_neon_frsqrte>; 4160defm FSQRT : SIMDTwoVectorFP<1, 1, 0b11111, "fsqrt", fsqrt>; 4161defm NEG : SIMDTwoVectorBHSD<1, 0b01011, "neg", 4162 UnOpFrag<(sub immAllZerosV, node:$LHS)> >; 4163defm NOT : SIMDTwoVectorB<1, 0b00, 0b00101, "not", vnot>; 4164// Aliases for MVN -> NOT. 4165def : InstAlias<"mvn{ $Vd.8b, $Vn.8b|.8b $Vd, $Vn}", 4166 (NOTv8i8 V64:$Vd, V64:$Vn)>; 4167def : InstAlias<"mvn{ $Vd.16b, $Vn.16b|.16b $Vd, $Vn}", 4168 (NOTv16i8 V128:$Vd, V128:$Vn)>; 4169 4170def : Pat<(vnot (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>; 4171def : Pat<(vnot (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>; 4172def : Pat<(vnot (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>; 4173def : Pat<(vnot (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>; 4174def : Pat<(vnot (v1i64 V64:$Rn)), (NOTv8i8 V64:$Rn)>; 4175def : Pat<(vnot (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>; 4176 4177defm RBIT : SIMDTwoVectorB<1, 0b01, 0b00101, "rbit", bitreverse>; 4178defm REV16 : SIMDTwoVectorB<0, 0b00, 0b00001, "rev16", AArch64rev16>; 4179defm REV32 : SIMDTwoVectorBH<1, 0b00000, "rev32", AArch64rev32>; 4180defm REV64 : SIMDTwoVectorBHS<0, 0b00000, "rev64", AArch64rev64>; 4181defm SADALP : SIMDLongTwoVectorTied<0, 0b00110, "sadalp", 4182 BinOpFrag<(add node:$LHS, (int_aarch64_neon_saddlp node:$RHS))> >; 4183defm SADDLP : SIMDLongTwoVector<0, 0b00010, "saddlp", int_aarch64_neon_saddlp>; 4184defm SCVTF : SIMDTwoVectorIntToFP<0, 0, 0b11101, "scvtf", sint_to_fp>; 4185defm SHLL : SIMDVectorLShiftLongBySizeBHS; 4186defm SQABS : SIMDTwoVectorBHSD<0, 0b00111, "sqabs", int_aarch64_neon_sqabs>; 4187defm SQNEG : SIMDTwoVectorBHSD<1, 0b00111, "sqneg", int_aarch64_neon_sqneg>; 4188defm SQXTN : SIMDMixedTwoVector<0, 0b10100, "sqxtn", int_aarch64_neon_sqxtn>; 4189defm SQXTUN : SIMDMixedTwoVector<1, 0b10010, "sqxtun", int_aarch64_neon_sqxtun>; 4190defm SUQADD : SIMDTwoVectorBHSDTied<0, 0b00011, "suqadd",int_aarch64_neon_suqadd>; 4191defm UADALP : SIMDLongTwoVectorTied<1, 0b00110, "uadalp", 4192 BinOpFrag<(add node:$LHS, (AArch64uaddlp node:$RHS))> >; 4193defm UADDLP : SIMDLongTwoVector<1, 0b00010, "uaddlp", AArch64uaddlp>; 4194defm UCVTF : SIMDTwoVectorIntToFP<1, 0, 0b11101, "ucvtf", uint_to_fp>; 4195defm UQXTN : SIMDMixedTwoVector<1, 0b10100, "uqxtn", int_aarch64_neon_uqxtn>; 4196defm URECPE : SIMDTwoVectorS<0, 1, 0b11100, "urecpe", int_aarch64_neon_urecpe>; 4197defm URSQRTE: SIMDTwoVectorS<1, 1, 0b11100, "ursqrte", int_aarch64_neon_ursqrte>; 4198defm USQADD : SIMDTwoVectorBHSDTied<1, 0b00011, "usqadd",int_aarch64_neon_usqadd>; 4199defm XTN : SIMDMixedTwoVector<0, 0b10010, "xtn", trunc>; 4200 4201def : Pat<(v4f16 (AArch64rev32 V64:$Rn)), (REV32v4i16 V64:$Rn)>; 4202def : Pat<(v4f16 (AArch64rev64 V64:$Rn)), (REV64v4i16 V64:$Rn)>; 4203def : Pat<(v4bf16 (AArch64rev32 V64:$Rn)), (REV32v4i16 V64:$Rn)>; 4204def : Pat<(v4bf16 (AArch64rev64 V64:$Rn)), (REV64v4i16 V64:$Rn)>; 4205def : Pat<(v8f16 (AArch64rev32 V128:$Rn)), (REV32v8i16 V128:$Rn)>; 4206def : Pat<(v8f16 (AArch64rev64 V128:$Rn)), (REV64v8i16 V128:$Rn)>; 4207def : Pat<(v8bf16 (AArch64rev32 V128:$Rn)), (REV32v8i16 V128:$Rn)>; 4208def : Pat<(v8bf16 (AArch64rev64 V128:$Rn)), (REV64v8i16 V128:$Rn)>; 4209def : Pat<(v2f32 (AArch64rev64 V64:$Rn)), (REV64v2i32 V64:$Rn)>; 4210def : Pat<(v4f32 (AArch64rev64 V128:$Rn)), (REV64v4i32 V128:$Rn)>; 4211 4212// Patterns for vector long shift (by element width). These need to match all 4213// three of zext, sext and anyext so it's easier to pull the patterns out of the 4214// definition. 4215multiclass SIMDVectorLShiftLongBySizeBHSPats<SDPatternOperator ext> { 4216 def : Pat<(AArch64vshl (v8i16 (ext (v8i8 V64:$Rn))), (i32 8)), 4217 (SHLLv8i8 V64:$Rn)>; 4218 def : Pat<(AArch64vshl (v8i16 (ext (extract_high_v16i8 V128:$Rn))), (i32 8)), 4219 (SHLLv16i8 V128:$Rn)>; 4220 def : Pat<(AArch64vshl (v4i32 (ext (v4i16 V64:$Rn))), (i32 16)), 4221 (SHLLv4i16 V64:$Rn)>; 4222 def : Pat<(AArch64vshl (v4i32 (ext (extract_high_v8i16 V128:$Rn))), (i32 16)), 4223 (SHLLv8i16 V128:$Rn)>; 4224 def : Pat<(AArch64vshl (v2i64 (ext (v2i32 V64:$Rn))), (i32 32)), 4225 (SHLLv2i32 V64:$Rn)>; 4226 def : Pat<(AArch64vshl (v2i64 (ext (extract_high_v4i32 V128:$Rn))), (i32 32)), 4227 (SHLLv4i32 V128:$Rn)>; 4228} 4229 4230defm : SIMDVectorLShiftLongBySizeBHSPats<anyext>; 4231defm : SIMDVectorLShiftLongBySizeBHSPats<zext>; 4232defm : SIMDVectorLShiftLongBySizeBHSPats<sext>; 4233 4234// Constant vector values, used in the S/UQXTN patterns below. 4235def VImmFF: PatLeaf<(AArch64NvCast (v2i64 (AArch64movi_edit (i32 85))))>; 4236def VImmFFFF: PatLeaf<(AArch64NvCast (v2i64 (AArch64movi_edit (i32 51))))>; 4237def VImm7F: PatLeaf<(AArch64movi_shift (i32 127), (i32 0))>; 4238def VImm80: PatLeaf<(AArch64mvni_shift (i32 127), (i32 0))>; 4239def VImm7FFF: PatLeaf<(AArch64movi_msl (i32 127), (i32 264))>; 4240def VImm8000: PatLeaf<(AArch64mvni_msl (i32 127), (i32 264))>; 4241 4242// trunc(umin(X, 255)) -> UQXTRN v8i8 4243def : Pat<(v8i8 (trunc (umin (v8i16 V128:$Vn), (v8i16 VImmFF)))), 4244 (UQXTNv8i8 V128:$Vn)>; 4245// trunc(umin(X, 65535)) -> UQXTRN v4i16 4246def : Pat<(v4i16 (trunc (umin (v4i32 V128:$Vn), (v4i32 VImmFFFF)))), 4247 (UQXTNv4i16 V128:$Vn)>; 4248// trunc(smin(smax(X, -128), 128)) -> SQXTRN 4249// with reversed min/max 4250def : Pat<(v8i8 (trunc (smin (smax (v8i16 V128:$Vn), (v8i16 VImm80)), 4251 (v8i16 VImm7F)))), 4252 (SQXTNv8i8 V128:$Vn)>; 4253def : Pat<(v8i8 (trunc (smax (smin (v8i16 V128:$Vn), (v8i16 VImm7F)), 4254 (v8i16 VImm80)))), 4255 (SQXTNv8i8 V128:$Vn)>; 4256// trunc(smin(smax(X, -32768), 32767)) -> SQXTRN 4257// with reversed min/max 4258def : Pat<(v4i16 (trunc (smin (smax (v4i32 V128:$Vn), (v4i32 VImm8000)), 4259 (v4i32 VImm7FFF)))), 4260 (SQXTNv4i16 V128:$Vn)>; 4261def : Pat<(v4i16 (trunc (smax (smin (v4i32 V128:$Vn), (v4i32 VImm7FFF)), 4262 (v4i32 VImm8000)))), 4263 (SQXTNv4i16 V128:$Vn)>; 4264 4265//===----------------------------------------------------------------------===// 4266// Advanced SIMD three vector instructions. 4267//===----------------------------------------------------------------------===// 4268 4269defm ADD : SIMDThreeSameVector<0, 0b10000, "add", add>; 4270defm ADDP : SIMDThreeSameVector<0, 0b10111, "addp", int_aarch64_neon_addp>; 4271defm CMEQ : SIMDThreeSameVector<1, 0b10001, "cmeq", AArch64cmeq>; 4272defm CMGE : SIMDThreeSameVector<0, 0b00111, "cmge", AArch64cmge>; 4273defm CMGT : SIMDThreeSameVector<0, 0b00110, "cmgt", AArch64cmgt>; 4274defm CMHI : SIMDThreeSameVector<1, 0b00110, "cmhi", AArch64cmhi>; 4275defm CMHS : SIMDThreeSameVector<1, 0b00111, "cmhs", AArch64cmhs>; 4276defm CMTST : SIMDThreeSameVector<0, 0b10001, "cmtst", AArch64cmtst>; 4277foreach VT = [ v8i8, v16i8, v4i16, v8i16, v2i32, v4i32, v2i64 ] in { 4278def : Pat<(vnot (AArch64cmeqz VT:$Rn)), (!cast<Instruction>("CMTST"#VT) VT:$Rn, VT:$Rn)>; 4279} 4280defm FABD : SIMDThreeSameVectorFP<1,1,0b010,"fabd", int_aarch64_neon_fabd>; 4281let Predicates = [HasNEON] in { 4282foreach VT = [ v2f32, v4f32, v2f64 ] in 4283def : Pat<(fabs (fsub VT:$Rn, VT:$Rm)), (!cast<Instruction>("FABD"#VT) VT:$Rn, VT:$Rm)>; 4284} 4285let Predicates = [HasNEON, HasFullFP16] in { 4286foreach VT = [ v4f16, v8f16 ] in 4287def : Pat<(fabs (fsub VT:$Rn, VT:$Rm)), (!cast<Instruction>("FABD"#VT) VT:$Rn, VT:$Rm)>; 4288} 4289defm FACGE : SIMDThreeSameVectorFPCmp<1,0,0b101,"facge",int_aarch64_neon_facge>; 4290defm FACGT : SIMDThreeSameVectorFPCmp<1,1,0b101,"facgt",int_aarch64_neon_facgt>; 4291defm FADDP : SIMDThreeSameVectorFP<1,0,0b010,"faddp",int_aarch64_neon_faddp>; 4292defm FADD : SIMDThreeSameVectorFP<0,0,0b010,"fadd", fadd>; 4293defm FCMEQ : SIMDThreeSameVectorFPCmp<0, 0, 0b100, "fcmeq", AArch64fcmeq>; 4294defm FCMGE : SIMDThreeSameVectorFPCmp<1, 0, 0b100, "fcmge", AArch64fcmge>; 4295defm FCMGT : SIMDThreeSameVectorFPCmp<1, 1, 0b100, "fcmgt", AArch64fcmgt>; 4296defm FDIV : SIMDThreeSameVectorFP<1,0,0b111,"fdiv", fdiv>; 4297defm FMAXNMP : SIMDThreeSameVectorFP<1,0,0b000,"fmaxnmp", int_aarch64_neon_fmaxnmp>; 4298defm FMAXNM : SIMDThreeSameVectorFP<0,0,0b000,"fmaxnm", fmaxnum>; 4299defm FMAXP : SIMDThreeSameVectorFP<1,0,0b110,"fmaxp", int_aarch64_neon_fmaxp>; 4300defm FMAX : SIMDThreeSameVectorFP<0,0,0b110,"fmax", fmaximum>; 4301defm FMINNMP : SIMDThreeSameVectorFP<1,1,0b000,"fminnmp", int_aarch64_neon_fminnmp>; 4302defm FMINNM : SIMDThreeSameVectorFP<0,1,0b000,"fminnm", fminnum>; 4303defm FMINP : SIMDThreeSameVectorFP<1,1,0b110,"fminp", int_aarch64_neon_fminp>; 4304defm FMIN : SIMDThreeSameVectorFP<0,1,0b110,"fmin", fminimum>; 4305 4306// NOTE: The operands of the PatFrag are reordered on FMLA/FMLS because the 4307// instruction expects the addend first, while the fma intrinsic puts it last. 4308defm FMLA : SIMDThreeSameVectorFPTied<0, 0, 0b001, "fmla", 4309 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >; 4310defm FMLS : SIMDThreeSameVectorFPTied<0, 1, 0b001, "fmls", 4311 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >; 4312 4313defm FMULX : SIMDThreeSameVectorFP<0,0,0b011,"fmulx", int_aarch64_neon_fmulx>; 4314defm FMUL : SIMDThreeSameVectorFP<1,0,0b011,"fmul", fmul>; 4315defm FRECPS : SIMDThreeSameVectorFP<0,0,0b111,"frecps", int_aarch64_neon_frecps>; 4316defm FRSQRTS : SIMDThreeSameVectorFP<0,1,0b111,"frsqrts", int_aarch64_neon_frsqrts>; 4317defm FSUB : SIMDThreeSameVectorFP<0,1,0b010,"fsub", fsub>; 4318 4319// MLA and MLS are generated in MachineCombine 4320defm MLA : SIMDThreeSameVectorBHSTied<0, 0b10010, "mla", null_frag>; 4321defm MLS : SIMDThreeSameVectorBHSTied<1, 0b10010, "mls", null_frag>; 4322 4323defm MUL : SIMDThreeSameVectorBHS<0, 0b10011, "mul", mul>; 4324defm PMUL : SIMDThreeSameVectorB<1, 0b10011, "pmul", int_aarch64_neon_pmul>; 4325defm SABA : SIMDThreeSameVectorBHSTied<0, 0b01111, "saba", 4326 TriOpFrag<(add node:$LHS, (AArch64sabd node:$MHS, node:$RHS))> >; 4327defm SABD : SIMDThreeSameVectorBHS<0,0b01110,"sabd", AArch64sabd>; 4328defm SHADD : SIMDThreeSameVectorBHS<0,0b00000,"shadd", AArch64shadd>; 4329defm SHSUB : SIMDThreeSameVectorBHS<0,0b00100,"shsub", int_aarch64_neon_shsub>; 4330defm SMAXP : SIMDThreeSameVectorBHS<0,0b10100,"smaxp", int_aarch64_neon_smaxp>; 4331defm SMAX : SIMDThreeSameVectorBHS<0,0b01100,"smax", smax>; 4332defm SMINP : SIMDThreeSameVectorBHS<0,0b10101,"sminp", int_aarch64_neon_sminp>; 4333defm SMIN : SIMDThreeSameVectorBHS<0,0b01101,"smin", smin>; 4334defm SQADD : SIMDThreeSameVector<0,0b00001,"sqadd", int_aarch64_neon_sqadd>; 4335defm SQDMULH : SIMDThreeSameVectorHS<0,0b10110,"sqdmulh",int_aarch64_neon_sqdmulh>; 4336defm SQRDMULH : SIMDThreeSameVectorHS<1,0b10110,"sqrdmulh",int_aarch64_neon_sqrdmulh>; 4337defm SQRSHL : SIMDThreeSameVector<0,0b01011,"sqrshl", int_aarch64_neon_sqrshl>; 4338defm SQSHL : SIMDThreeSameVector<0,0b01001,"sqshl", int_aarch64_neon_sqshl>; 4339defm SQSUB : SIMDThreeSameVector<0,0b00101,"sqsub", int_aarch64_neon_sqsub>; 4340defm SRHADD : SIMDThreeSameVectorBHS<0,0b00010,"srhadd", AArch64srhadd>; 4341defm SRSHL : SIMDThreeSameVector<0,0b01010,"srshl", int_aarch64_neon_srshl>; 4342defm SSHL : SIMDThreeSameVector<0,0b01000,"sshl", int_aarch64_neon_sshl>; 4343defm SUB : SIMDThreeSameVector<1,0b10000,"sub", sub>; 4344defm UABA : SIMDThreeSameVectorBHSTied<1, 0b01111, "uaba", 4345 TriOpFrag<(add node:$LHS, (AArch64uabd node:$MHS, node:$RHS))> >; 4346defm UABD : SIMDThreeSameVectorBHS<1,0b01110,"uabd", AArch64uabd>; 4347defm UHADD : SIMDThreeSameVectorBHS<1,0b00000,"uhadd", AArch64uhadd>; 4348defm UHSUB : SIMDThreeSameVectorBHS<1,0b00100,"uhsub", int_aarch64_neon_uhsub>; 4349defm UMAXP : SIMDThreeSameVectorBHS<1,0b10100,"umaxp", int_aarch64_neon_umaxp>; 4350defm UMAX : SIMDThreeSameVectorBHS<1,0b01100,"umax", umax>; 4351defm UMINP : SIMDThreeSameVectorBHS<1,0b10101,"uminp", int_aarch64_neon_uminp>; 4352defm UMIN : SIMDThreeSameVectorBHS<1,0b01101,"umin", umin>; 4353defm UQADD : SIMDThreeSameVector<1,0b00001,"uqadd", int_aarch64_neon_uqadd>; 4354defm UQRSHL : SIMDThreeSameVector<1,0b01011,"uqrshl", int_aarch64_neon_uqrshl>; 4355defm UQSHL : SIMDThreeSameVector<1,0b01001,"uqshl", int_aarch64_neon_uqshl>; 4356defm UQSUB : SIMDThreeSameVector<1,0b00101,"uqsub", int_aarch64_neon_uqsub>; 4357defm URHADD : SIMDThreeSameVectorBHS<1,0b00010,"urhadd", AArch64urhadd>; 4358defm URSHL : SIMDThreeSameVector<1,0b01010,"urshl", int_aarch64_neon_urshl>; 4359defm USHL : SIMDThreeSameVector<1,0b01000,"ushl", int_aarch64_neon_ushl>; 4360defm SQRDMLAH : SIMDThreeSameVectorSQRDMLxHTiedHS<1,0b10000,"sqrdmlah", 4361 int_aarch64_neon_sqadd>; 4362defm SQRDMLSH : SIMDThreeSameVectorSQRDMLxHTiedHS<1,0b10001,"sqrdmlsh", 4363 int_aarch64_neon_sqsub>; 4364 4365// Extra saturate patterns, other than the intrinsics matches above 4366defm : SIMDThreeSameVectorExtraPatterns<"SQADD", saddsat>; 4367defm : SIMDThreeSameVectorExtraPatterns<"UQADD", uaddsat>; 4368defm : SIMDThreeSameVectorExtraPatterns<"SQSUB", ssubsat>; 4369defm : SIMDThreeSameVectorExtraPatterns<"UQSUB", usubsat>; 4370 4371defm AND : SIMDLogicalThreeVector<0, 0b00, "and", and>; 4372defm BIC : SIMDLogicalThreeVector<0, 0b01, "bic", 4373 BinOpFrag<(and node:$LHS, (vnot node:$RHS))> >; 4374defm EOR : SIMDLogicalThreeVector<1, 0b00, "eor", xor>; 4375defm ORN : SIMDLogicalThreeVector<0, 0b11, "orn", 4376 BinOpFrag<(or node:$LHS, (vnot node:$RHS))> >; 4377defm ORR : SIMDLogicalThreeVector<0, 0b10, "orr", or>; 4378 4379// Pseudo bitwise select pattern BSP. 4380// It is expanded into BSL/BIT/BIF after register allocation. 4381defm BSP : SIMDLogicalThreeVectorPseudo<TriOpFrag<(or (and node:$LHS, node:$MHS), 4382 (and (vnot node:$LHS), node:$RHS))>>; 4383defm BSL : SIMDLogicalThreeVectorTied<1, 0b01, "bsl">; 4384defm BIT : SIMDLogicalThreeVectorTied<1, 0b10, "bit", AArch64bit>; 4385defm BIF : SIMDLogicalThreeVectorTied<1, 0b11, "bif">; 4386 4387def : Pat<(AArch64bsp (v8i8 V64:$Rd), V64:$Rn, V64:$Rm), 4388 (BSPv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>; 4389def : Pat<(AArch64bsp (v4i16 V64:$Rd), V64:$Rn, V64:$Rm), 4390 (BSPv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>; 4391def : Pat<(AArch64bsp (v2i32 V64:$Rd), V64:$Rn, V64:$Rm), 4392 (BSPv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>; 4393def : Pat<(AArch64bsp (v1i64 V64:$Rd), V64:$Rn, V64:$Rm), 4394 (BSPv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>; 4395 4396def : Pat<(AArch64bsp (v16i8 V128:$Rd), V128:$Rn, V128:$Rm), 4397 (BSPv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>; 4398def : Pat<(AArch64bsp (v8i16 V128:$Rd), V128:$Rn, V128:$Rm), 4399 (BSPv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>; 4400def : Pat<(AArch64bsp (v4i32 V128:$Rd), V128:$Rn, V128:$Rm), 4401 (BSPv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>; 4402def : Pat<(AArch64bsp (v2i64 V128:$Rd), V128:$Rn, V128:$Rm), 4403 (BSPv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>; 4404 4405def : InstAlias<"mov{\t$dst.16b, $src.16b|.16b\t$dst, $src}", 4406 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 1>; 4407def : InstAlias<"mov{\t$dst.8h, $src.8h|.8h\t$dst, $src}", 4408 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>; 4409def : InstAlias<"mov{\t$dst.4s, $src.4s|.4s\t$dst, $src}", 4410 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>; 4411def : InstAlias<"mov{\t$dst.2d, $src.2d|.2d\t$dst, $src}", 4412 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>; 4413 4414def : InstAlias<"mov{\t$dst.8b, $src.8b|.8b\t$dst, $src}", 4415 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 1>; 4416def : InstAlias<"mov{\t$dst.4h, $src.4h|.4h\t$dst, $src}", 4417 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>; 4418def : InstAlias<"mov{\t$dst.2s, $src.2s|.2s\t$dst, $src}", 4419 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>; 4420def : InstAlias<"mov{\t$dst.1d, $src.1d|.1d\t$dst, $src}", 4421 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>; 4422 4423def : InstAlias<"{cmls\t$dst.8b, $src1.8b, $src2.8b" # 4424 "|cmls.8b\t$dst, $src1, $src2}", 4425 (CMHSv8i8 V64:$dst, V64:$src2, V64:$src1), 0>; 4426def : InstAlias<"{cmls\t$dst.16b, $src1.16b, $src2.16b" # 4427 "|cmls.16b\t$dst, $src1, $src2}", 4428 (CMHSv16i8 V128:$dst, V128:$src2, V128:$src1), 0>; 4429def : InstAlias<"{cmls\t$dst.4h, $src1.4h, $src2.4h" # 4430 "|cmls.4h\t$dst, $src1, $src2}", 4431 (CMHSv4i16 V64:$dst, V64:$src2, V64:$src1), 0>; 4432def : InstAlias<"{cmls\t$dst.8h, $src1.8h, $src2.8h" # 4433 "|cmls.8h\t$dst, $src1, $src2}", 4434 (CMHSv8i16 V128:$dst, V128:$src2, V128:$src1), 0>; 4435def : InstAlias<"{cmls\t$dst.2s, $src1.2s, $src2.2s" # 4436 "|cmls.2s\t$dst, $src1, $src2}", 4437 (CMHSv2i32 V64:$dst, V64:$src2, V64:$src1), 0>; 4438def : InstAlias<"{cmls\t$dst.4s, $src1.4s, $src2.4s" # 4439 "|cmls.4s\t$dst, $src1, $src2}", 4440 (CMHSv4i32 V128:$dst, V128:$src2, V128:$src1), 0>; 4441def : InstAlias<"{cmls\t$dst.2d, $src1.2d, $src2.2d" # 4442 "|cmls.2d\t$dst, $src1, $src2}", 4443 (CMHSv2i64 V128:$dst, V128:$src2, V128:$src1), 0>; 4444 4445def : InstAlias<"{cmlo\t$dst.8b, $src1.8b, $src2.8b" # 4446 "|cmlo.8b\t$dst, $src1, $src2}", 4447 (CMHIv8i8 V64:$dst, V64:$src2, V64:$src1), 0>; 4448def : InstAlias<"{cmlo\t$dst.16b, $src1.16b, $src2.16b" # 4449 "|cmlo.16b\t$dst, $src1, $src2}", 4450 (CMHIv16i8 V128:$dst, V128:$src2, V128:$src1), 0>; 4451def : InstAlias<"{cmlo\t$dst.4h, $src1.4h, $src2.4h" # 4452 "|cmlo.4h\t$dst, $src1, $src2}", 4453 (CMHIv4i16 V64:$dst, V64:$src2, V64:$src1), 0>; 4454def : InstAlias<"{cmlo\t$dst.8h, $src1.8h, $src2.8h" # 4455 "|cmlo.8h\t$dst, $src1, $src2}", 4456 (CMHIv8i16 V128:$dst, V128:$src2, V128:$src1), 0>; 4457def : InstAlias<"{cmlo\t$dst.2s, $src1.2s, $src2.2s" # 4458 "|cmlo.2s\t$dst, $src1, $src2}", 4459 (CMHIv2i32 V64:$dst, V64:$src2, V64:$src1), 0>; 4460def : InstAlias<"{cmlo\t$dst.4s, $src1.4s, $src2.4s" # 4461 "|cmlo.4s\t$dst, $src1, $src2}", 4462 (CMHIv4i32 V128:$dst, V128:$src2, V128:$src1), 0>; 4463def : InstAlias<"{cmlo\t$dst.2d, $src1.2d, $src2.2d" # 4464 "|cmlo.2d\t$dst, $src1, $src2}", 4465 (CMHIv2i64 V128:$dst, V128:$src2, V128:$src1), 0>; 4466 4467def : InstAlias<"{cmle\t$dst.8b, $src1.8b, $src2.8b" # 4468 "|cmle.8b\t$dst, $src1, $src2}", 4469 (CMGEv8i8 V64:$dst, V64:$src2, V64:$src1), 0>; 4470def : InstAlias<"{cmle\t$dst.16b, $src1.16b, $src2.16b" # 4471 "|cmle.16b\t$dst, $src1, $src2}", 4472 (CMGEv16i8 V128:$dst, V128:$src2, V128:$src1), 0>; 4473def : InstAlias<"{cmle\t$dst.4h, $src1.4h, $src2.4h" # 4474 "|cmle.4h\t$dst, $src1, $src2}", 4475 (CMGEv4i16 V64:$dst, V64:$src2, V64:$src1), 0>; 4476def : InstAlias<"{cmle\t$dst.8h, $src1.8h, $src2.8h" # 4477 "|cmle.8h\t$dst, $src1, $src2}", 4478 (CMGEv8i16 V128:$dst, V128:$src2, V128:$src1), 0>; 4479def : InstAlias<"{cmle\t$dst.2s, $src1.2s, $src2.2s" # 4480 "|cmle.2s\t$dst, $src1, $src2}", 4481 (CMGEv2i32 V64:$dst, V64:$src2, V64:$src1), 0>; 4482def : InstAlias<"{cmle\t$dst.4s, $src1.4s, $src2.4s" # 4483 "|cmle.4s\t$dst, $src1, $src2}", 4484 (CMGEv4i32 V128:$dst, V128:$src2, V128:$src1), 0>; 4485def : InstAlias<"{cmle\t$dst.2d, $src1.2d, $src2.2d" # 4486 "|cmle.2d\t$dst, $src1, $src2}", 4487 (CMGEv2i64 V128:$dst, V128:$src2, V128:$src1), 0>; 4488 4489def : InstAlias<"{cmlt\t$dst.8b, $src1.8b, $src2.8b" # 4490 "|cmlt.8b\t$dst, $src1, $src2}", 4491 (CMGTv8i8 V64:$dst, V64:$src2, V64:$src1), 0>; 4492def : InstAlias<"{cmlt\t$dst.16b, $src1.16b, $src2.16b" # 4493 "|cmlt.16b\t$dst, $src1, $src2}", 4494 (CMGTv16i8 V128:$dst, V128:$src2, V128:$src1), 0>; 4495def : InstAlias<"{cmlt\t$dst.4h, $src1.4h, $src2.4h" # 4496 "|cmlt.4h\t$dst, $src1, $src2}", 4497 (CMGTv4i16 V64:$dst, V64:$src2, V64:$src1), 0>; 4498def : InstAlias<"{cmlt\t$dst.8h, $src1.8h, $src2.8h" # 4499 "|cmlt.8h\t$dst, $src1, $src2}", 4500 (CMGTv8i16 V128:$dst, V128:$src2, V128:$src1), 0>; 4501def : InstAlias<"{cmlt\t$dst.2s, $src1.2s, $src2.2s" # 4502 "|cmlt.2s\t$dst, $src1, $src2}", 4503 (CMGTv2i32 V64:$dst, V64:$src2, V64:$src1), 0>; 4504def : InstAlias<"{cmlt\t$dst.4s, $src1.4s, $src2.4s" # 4505 "|cmlt.4s\t$dst, $src1, $src2}", 4506 (CMGTv4i32 V128:$dst, V128:$src2, V128:$src1), 0>; 4507def : InstAlias<"{cmlt\t$dst.2d, $src1.2d, $src2.2d" # 4508 "|cmlt.2d\t$dst, $src1, $src2}", 4509 (CMGTv2i64 V128:$dst, V128:$src2, V128:$src1), 0>; 4510 4511let Predicates = [HasNEON, HasFullFP16] in { 4512def : InstAlias<"{fcmle\t$dst.4h, $src1.4h, $src2.4h" # 4513 "|fcmle.4h\t$dst, $src1, $src2}", 4514 (FCMGEv4f16 V64:$dst, V64:$src2, V64:$src1), 0>; 4515def : InstAlias<"{fcmle\t$dst.8h, $src1.8h, $src2.8h" # 4516 "|fcmle.8h\t$dst, $src1, $src2}", 4517 (FCMGEv8f16 V128:$dst, V128:$src2, V128:$src1), 0>; 4518} 4519def : InstAlias<"{fcmle\t$dst.2s, $src1.2s, $src2.2s" # 4520 "|fcmle.2s\t$dst, $src1, $src2}", 4521 (FCMGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>; 4522def : InstAlias<"{fcmle\t$dst.4s, $src1.4s, $src2.4s" # 4523 "|fcmle.4s\t$dst, $src1, $src2}", 4524 (FCMGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>; 4525def : InstAlias<"{fcmle\t$dst.2d, $src1.2d, $src2.2d" # 4526 "|fcmle.2d\t$dst, $src1, $src2}", 4527 (FCMGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>; 4528 4529let Predicates = [HasNEON, HasFullFP16] in { 4530def : InstAlias<"{fcmlt\t$dst.4h, $src1.4h, $src2.4h" # 4531 "|fcmlt.4h\t$dst, $src1, $src2}", 4532 (FCMGTv4f16 V64:$dst, V64:$src2, V64:$src1), 0>; 4533def : InstAlias<"{fcmlt\t$dst.8h, $src1.8h, $src2.8h" # 4534 "|fcmlt.8h\t$dst, $src1, $src2}", 4535 (FCMGTv8f16 V128:$dst, V128:$src2, V128:$src1), 0>; 4536} 4537def : InstAlias<"{fcmlt\t$dst.2s, $src1.2s, $src2.2s" # 4538 "|fcmlt.2s\t$dst, $src1, $src2}", 4539 (FCMGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>; 4540def : InstAlias<"{fcmlt\t$dst.4s, $src1.4s, $src2.4s" # 4541 "|fcmlt.4s\t$dst, $src1, $src2}", 4542 (FCMGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>; 4543def : InstAlias<"{fcmlt\t$dst.2d, $src1.2d, $src2.2d" # 4544 "|fcmlt.2d\t$dst, $src1, $src2}", 4545 (FCMGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>; 4546 4547let Predicates = [HasNEON, HasFullFP16] in { 4548def : InstAlias<"{facle\t$dst.4h, $src1.4h, $src2.4h" # 4549 "|facle.4h\t$dst, $src1, $src2}", 4550 (FACGEv4f16 V64:$dst, V64:$src2, V64:$src1), 0>; 4551def : InstAlias<"{facle\t$dst.8h, $src1.8h, $src2.8h" # 4552 "|facle.8h\t$dst, $src1, $src2}", 4553 (FACGEv8f16 V128:$dst, V128:$src2, V128:$src1), 0>; 4554} 4555def : InstAlias<"{facle\t$dst.2s, $src1.2s, $src2.2s" # 4556 "|facle.2s\t$dst, $src1, $src2}", 4557 (FACGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>; 4558def : InstAlias<"{facle\t$dst.4s, $src1.4s, $src2.4s" # 4559 "|facle.4s\t$dst, $src1, $src2}", 4560 (FACGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>; 4561def : InstAlias<"{facle\t$dst.2d, $src1.2d, $src2.2d" # 4562 "|facle.2d\t$dst, $src1, $src2}", 4563 (FACGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>; 4564 4565let Predicates = [HasNEON, HasFullFP16] in { 4566def : InstAlias<"{faclt\t$dst.4h, $src1.4h, $src2.4h" # 4567 "|faclt.4h\t$dst, $src1, $src2}", 4568 (FACGTv4f16 V64:$dst, V64:$src2, V64:$src1), 0>; 4569def : InstAlias<"{faclt\t$dst.8h, $src1.8h, $src2.8h" # 4570 "|faclt.8h\t$dst, $src1, $src2}", 4571 (FACGTv8f16 V128:$dst, V128:$src2, V128:$src1), 0>; 4572} 4573def : InstAlias<"{faclt\t$dst.2s, $src1.2s, $src2.2s" # 4574 "|faclt.2s\t$dst, $src1, $src2}", 4575 (FACGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>; 4576def : InstAlias<"{faclt\t$dst.4s, $src1.4s, $src2.4s" # 4577 "|faclt.4s\t$dst, $src1, $src2}", 4578 (FACGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>; 4579def : InstAlias<"{faclt\t$dst.2d, $src1.2d, $src2.2d" # 4580 "|faclt.2d\t$dst, $src1, $src2}", 4581 (FACGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>; 4582 4583//===----------------------------------------------------------------------===// 4584// Advanced SIMD three scalar instructions. 4585//===----------------------------------------------------------------------===// 4586 4587defm ADD : SIMDThreeScalarD<0, 0b10000, "add", add>; 4588defm CMEQ : SIMDThreeScalarD<1, 0b10001, "cmeq", AArch64cmeq>; 4589defm CMGE : SIMDThreeScalarD<0, 0b00111, "cmge", AArch64cmge>; 4590defm CMGT : SIMDThreeScalarD<0, 0b00110, "cmgt", AArch64cmgt>; 4591defm CMHI : SIMDThreeScalarD<1, 0b00110, "cmhi", AArch64cmhi>; 4592defm CMHS : SIMDThreeScalarD<1, 0b00111, "cmhs", AArch64cmhs>; 4593defm CMTST : SIMDThreeScalarD<0, 0b10001, "cmtst", AArch64cmtst>; 4594defm FABD : SIMDFPThreeScalar<1, 1, 0b010, "fabd", int_aarch64_sisd_fabd>; 4595def : Pat<(v1f64 (int_aarch64_neon_fabd (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))), 4596 (FABD64 FPR64:$Rn, FPR64:$Rm)>; 4597let Predicates = [HasFullFP16] in { 4598def : Pat<(fabs (fsub f16:$Rn, f16:$Rm)), (FABD16 f16:$Rn, f16:$Rm)>; 4599} 4600def : Pat<(fabs (fsub f32:$Rn, f32:$Rm)), (FABD32 f32:$Rn, f32:$Rm)>; 4601def : Pat<(fabs (fsub f64:$Rn, f64:$Rm)), (FABD64 f64:$Rn, f64:$Rm)>; 4602defm FACGE : SIMDThreeScalarFPCmp<1, 0, 0b101, "facge", 4603 int_aarch64_neon_facge>; 4604defm FACGT : SIMDThreeScalarFPCmp<1, 1, 0b101, "facgt", 4605 int_aarch64_neon_facgt>; 4606defm FCMEQ : SIMDThreeScalarFPCmp<0, 0, 0b100, "fcmeq", AArch64fcmeq>; 4607defm FCMGE : SIMDThreeScalarFPCmp<1, 0, 0b100, "fcmge", AArch64fcmge>; 4608defm FCMGT : SIMDThreeScalarFPCmp<1, 1, 0b100, "fcmgt", AArch64fcmgt>; 4609defm FMULX : SIMDFPThreeScalar<0, 0, 0b011, "fmulx", int_aarch64_neon_fmulx>; 4610defm FRECPS : SIMDFPThreeScalar<0, 0, 0b111, "frecps", int_aarch64_neon_frecps>; 4611defm FRSQRTS : SIMDFPThreeScalar<0, 1, 0b111, "frsqrts", int_aarch64_neon_frsqrts>; 4612defm SQADD : SIMDThreeScalarBHSD<0, 0b00001, "sqadd", int_aarch64_neon_sqadd>; 4613defm SQDMULH : SIMDThreeScalarHS< 0, 0b10110, "sqdmulh", int_aarch64_neon_sqdmulh>; 4614defm SQRDMULH : SIMDThreeScalarHS< 1, 0b10110, "sqrdmulh", int_aarch64_neon_sqrdmulh>; 4615defm SQRSHL : SIMDThreeScalarBHSD<0, 0b01011, "sqrshl",int_aarch64_neon_sqrshl>; 4616defm SQSHL : SIMDThreeScalarBHSD<0, 0b01001, "sqshl", int_aarch64_neon_sqshl>; 4617defm SQSUB : SIMDThreeScalarBHSD<0, 0b00101, "sqsub", int_aarch64_neon_sqsub>; 4618defm SRSHL : SIMDThreeScalarD< 0, 0b01010, "srshl", int_aarch64_neon_srshl>; 4619defm SSHL : SIMDThreeScalarD< 0, 0b01000, "sshl", int_aarch64_neon_sshl>; 4620defm SUB : SIMDThreeScalarD< 1, 0b10000, "sub", sub>; 4621defm UQADD : SIMDThreeScalarBHSD<1, 0b00001, "uqadd", int_aarch64_neon_uqadd>; 4622defm UQRSHL : SIMDThreeScalarBHSD<1, 0b01011, "uqrshl",int_aarch64_neon_uqrshl>; 4623defm UQSHL : SIMDThreeScalarBHSD<1, 0b01001, "uqshl", int_aarch64_neon_uqshl>; 4624defm UQSUB : SIMDThreeScalarBHSD<1, 0b00101, "uqsub", int_aarch64_neon_uqsub>; 4625defm URSHL : SIMDThreeScalarD< 1, 0b01010, "urshl", int_aarch64_neon_urshl>; 4626defm USHL : SIMDThreeScalarD< 1, 0b01000, "ushl", int_aarch64_neon_ushl>; 4627let Predicates = [HasRDM] in { 4628 defm SQRDMLAH : SIMDThreeScalarHSTied<1, 0, 0b10000, "sqrdmlah">; 4629 defm SQRDMLSH : SIMDThreeScalarHSTied<1, 0, 0b10001, "sqrdmlsh">; 4630 def : Pat<(i32 (int_aarch64_neon_sqadd 4631 (i32 FPR32:$Rd), 4632 (i32 (int_aarch64_neon_sqrdmulh (i32 FPR32:$Rn), 4633 (i32 FPR32:$Rm))))), 4634 (SQRDMLAHv1i32 FPR32:$Rd, FPR32:$Rn, FPR32:$Rm)>; 4635 def : Pat<(i32 (int_aarch64_neon_sqsub 4636 (i32 FPR32:$Rd), 4637 (i32 (int_aarch64_neon_sqrdmulh (i32 FPR32:$Rn), 4638 (i32 FPR32:$Rm))))), 4639 (SQRDMLSHv1i32 FPR32:$Rd, FPR32:$Rn, FPR32:$Rm)>; 4640} 4641 4642def : InstAlias<"cmls $dst, $src1, $src2", 4643 (CMHSv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>; 4644def : InstAlias<"cmle $dst, $src1, $src2", 4645 (CMGEv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>; 4646def : InstAlias<"cmlo $dst, $src1, $src2", 4647 (CMHIv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>; 4648def : InstAlias<"cmlt $dst, $src1, $src2", 4649 (CMGTv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>; 4650def : InstAlias<"fcmle $dst, $src1, $src2", 4651 (FCMGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>; 4652def : InstAlias<"fcmle $dst, $src1, $src2", 4653 (FCMGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>; 4654def : InstAlias<"fcmlt $dst, $src1, $src2", 4655 (FCMGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>; 4656def : InstAlias<"fcmlt $dst, $src1, $src2", 4657 (FCMGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>; 4658def : InstAlias<"facle $dst, $src1, $src2", 4659 (FACGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>; 4660def : InstAlias<"facle $dst, $src1, $src2", 4661 (FACGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>; 4662def : InstAlias<"faclt $dst, $src1, $src2", 4663 (FACGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>; 4664def : InstAlias<"faclt $dst, $src1, $src2", 4665 (FACGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>; 4666 4667//===----------------------------------------------------------------------===// 4668// Advanced SIMD three scalar instructions (mixed operands). 4669//===----------------------------------------------------------------------===// 4670defm SQDMULL : SIMDThreeScalarMixedHS<0, 0b11010, "sqdmull", 4671 int_aarch64_neon_sqdmulls_scalar>; 4672defm SQDMLAL : SIMDThreeScalarMixedTiedHS<0, 0b10010, "sqdmlal">; 4673defm SQDMLSL : SIMDThreeScalarMixedTiedHS<0, 0b10110, "sqdmlsl">; 4674 4675def : Pat<(i64 (int_aarch64_neon_sqadd (i64 FPR64:$Rd), 4676 (i64 (int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn), 4677 (i32 FPR32:$Rm))))), 4678 (SQDMLALi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>; 4679def : Pat<(i64 (int_aarch64_neon_sqsub (i64 FPR64:$Rd), 4680 (i64 (int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn), 4681 (i32 FPR32:$Rm))))), 4682 (SQDMLSLi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>; 4683 4684//===----------------------------------------------------------------------===// 4685// Advanced SIMD two scalar instructions. 4686//===----------------------------------------------------------------------===// 4687 4688defm ABS : SIMDTwoScalarD< 0, 0b01011, "abs", abs>; 4689defm CMEQ : SIMDCmpTwoScalarD< 0, 0b01001, "cmeq", AArch64cmeqz>; 4690defm CMGE : SIMDCmpTwoScalarD< 1, 0b01000, "cmge", AArch64cmgez>; 4691defm CMGT : SIMDCmpTwoScalarD< 0, 0b01000, "cmgt", AArch64cmgtz>; 4692defm CMLE : SIMDCmpTwoScalarD< 1, 0b01001, "cmle", AArch64cmlez>; 4693defm CMLT : SIMDCmpTwoScalarD< 0, 0b01010, "cmlt", AArch64cmltz>; 4694defm FCMEQ : SIMDFPCmpTwoScalar<0, 1, 0b01101, "fcmeq", AArch64fcmeqz>; 4695defm FCMGE : SIMDFPCmpTwoScalar<1, 1, 0b01100, "fcmge", AArch64fcmgez>; 4696defm FCMGT : SIMDFPCmpTwoScalar<0, 1, 0b01100, "fcmgt", AArch64fcmgtz>; 4697defm FCMLE : SIMDFPCmpTwoScalar<1, 1, 0b01101, "fcmle", AArch64fcmlez>; 4698defm FCMLT : SIMDFPCmpTwoScalar<0, 1, 0b01110, "fcmlt", AArch64fcmltz>; 4699defm FCVTAS : SIMDFPTwoScalar< 0, 0, 0b11100, "fcvtas">; 4700defm FCVTAU : SIMDFPTwoScalar< 1, 0, 0b11100, "fcvtau">; 4701defm FCVTMS : SIMDFPTwoScalar< 0, 0, 0b11011, "fcvtms">; 4702defm FCVTMU : SIMDFPTwoScalar< 1, 0, 0b11011, "fcvtmu">; 4703defm FCVTNS : SIMDFPTwoScalar< 0, 0, 0b11010, "fcvtns">; 4704defm FCVTNU : SIMDFPTwoScalar< 1, 0, 0b11010, "fcvtnu">; 4705defm FCVTPS : SIMDFPTwoScalar< 0, 1, 0b11010, "fcvtps">; 4706defm FCVTPU : SIMDFPTwoScalar< 1, 1, 0b11010, "fcvtpu">; 4707def FCVTXNv1i64 : SIMDInexactCvtTwoScalar<0b10110, "fcvtxn">; 4708defm FCVTZS : SIMDFPTwoScalar< 0, 1, 0b11011, "fcvtzs">; 4709defm FCVTZU : SIMDFPTwoScalar< 1, 1, 0b11011, "fcvtzu">; 4710defm FRECPE : SIMDFPTwoScalar< 0, 1, 0b11101, "frecpe">; 4711defm FRECPX : SIMDFPTwoScalar< 0, 1, 0b11111, "frecpx">; 4712defm FRSQRTE : SIMDFPTwoScalar< 1, 1, 0b11101, "frsqrte">; 4713defm NEG : SIMDTwoScalarD< 1, 0b01011, "neg", 4714 UnOpFrag<(sub immAllZerosV, node:$LHS)> >; 4715defm SCVTF : SIMDFPTwoScalarCVT< 0, 0, 0b11101, "scvtf", AArch64sitof>; 4716defm SQABS : SIMDTwoScalarBHSD< 0, 0b00111, "sqabs", int_aarch64_neon_sqabs>; 4717defm SQNEG : SIMDTwoScalarBHSD< 1, 0b00111, "sqneg", int_aarch64_neon_sqneg>; 4718defm SQXTN : SIMDTwoScalarMixedBHS< 0, 0b10100, "sqxtn", int_aarch64_neon_scalar_sqxtn>; 4719defm SQXTUN : SIMDTwoScalarMixedBHS< 1, 0b10010, "sqxtun", int_aarch64_neon_scalar_sqxtun>; 4720defm SUQADD : SIMDTwoScalarBHSDTied< 0, 0b00011, "suqadd", 4721 int_aarch64_neon_suqadd>; 4722defm UCVTF : SIMDFPTwoScalarCVT< 1, 0, 0b11101, "ucvtf", AArch64uitof>; 4723defm UQXTN : SIMDTwoScalarMixedBHS<1, 0b10100, "uqxtn", int_aarch64_neon_scalar_uqxtn>; 4724defm USQADD : SIMDTwoScalarBHSDTied< 1, 0b00011, "usqadd", 4725 int_aarch64_neon_usqadd>; 4726 4727def : Pat<(v1i64 (int_aarch64_neon_fcvtas (v1f64 FPR64:$Rn))), 4728 (FCVTASv1i64 FPR64:$Rn)>; 4729def : Pat<(v1i64 (int_aarch64_neon_fcvtau (v1f64 FPR64:$Rn))), 4730 (FCVTAUv1i64 FPR64:$Rn)>; 4731def : Pat<(v1i64 (int_aarch64_neon_fcvtms (v1f64 FPR64:$Rn))), 4732 (FCVTMSv1i64 FPR64:$Rn)>; 4733def : Pat<(v1i64 (int_aarch64_neon_fcvtmu (v1f64 FPR64:$Rn))), 4734 (FCVTMUv1i64 FPR64:$Rn)>; 4735def : Pat<(v1i64 (int_aarch64_neon_fcvtns (v1f64 FPR64:$Rn))), 4736 (FCVTNSv1i64 FPR64:$Rn)>; 4737def : Pat<(v1i64 (int_aarch64_neon_fcvtnu (v1f64 FPR64:$Rn))), 4738 (FCVTNUv1i64 FPR64:$Rn)>; 4739def : Pat<(v1i64 (int_aarch64_neon_fcvtps (v1f64 FPR64:$Rn))), 4740 (FCVTPSv1i64 FPR64:$Rn)>; 4741def : Pat<(v1i64 (int_aarch64_neon_fcvtpu (v1f64 FPR64:$Rn))), 4742 (FCVTPUv1i64 FPR64:$Rn)>; 4743def : Pat<(v1i64 (int_aarch64_neon_fcvtzs (v1f64 FPR64:$Rn))), 4744 (FCVTZSv1i64 FPR64:$Rn)>; 4745def : Pat<(v1i64 (int_aarch64_neon_fcvtzu (v1f64 FPR64:$Rn))), 4746 (FCVTZUv1i64 FPR64:$Rn)>; 4747 4748def : Pat<(f16 (int_aarch64_neon_frecpe (f16 FPR16:$Rn))), 4749 (FRECPEv1f16 FPR16:$Rn)>; 4750def : Pat<(f32 (int_aarch64_neon_frecpe (f32 FPR32:$Rn))), 4751 (FRECPEv1i32 FPR32:$Rn)>; 4752def : Pat<(f64 (int_aarch64_neon_frecpe (f64 FPR64:$Rn))), 4753 (FRECPEv1i64 FPR64:$Rn)>; 4754def : Pat<(v1f64 (int_aarch64_neon_frecpe (v1f64 FPR64:$Rn))), 4755 (FRECPEv1i64 FPR64:$Rn)>; 4756 4757def : Pat<(f32 (AArch64frecpe (f32 FPR32:$Rn))), 4758 (FRECPEv1i32 FPR32:$Rn)>; 4759def : Pat<(v2f32 (AArch64frecpe (v2f32 V64:$Rn))), 4760 (FRECPEv2f32 V64:$Rn)>; 4761def : Pat<(v4f32 (AArch64frecpe (v4f32 FPR128:$Rn))), 4762 (FRECPEv4f32 FPR128:$Rn)>; 4763def : Pat<(f64 (AArch64frecpe (f64 FPR64:$Rn))), 4764 (FRECPEv1i64 FPR64:$Rn)>; 4765def : Pat<(v1f64 (AArch64frecpe (v1f64 FPR64:$Rn))), 4766 (FRECPEv1i64 FPR64:$Rn)>; 4767def : Pat<(v2f64 (AArch64frecpe (v2f64 FPR128:$Rn))), 4768 (FRECPEv2f64 FPR128:$Rn)>; 4769 4770def : Pat<(f32 (AArch64frecps (f32 FPR32:$Rn), (f32 FPR32:$Rm))), 4771 (FRECPS32 FPR32:$Rn, FPR32:$Rm)>; 4772def : Pat<(v2f32 (AArch64frecps (v2f32 V64:$Rn), (v2f32 V64:$Rm))), 4773 (FRECPSv2f32 V64:$Rn, V64:$Rm)>; 4774def : Pat<(v4f32 (AArch64frecps (v4f32 FPR128:$Rn), (v4f32 FPR128:$Rm))), 4775 (FRECPSv4f32 FPR128:$Rn, FPR128:$Rm)>; 4776def : Pat<(f64 (AArch64frecps (f64 FPR64:$Rn), (f64 FPR64:$Rm))), 4777 (FRECPS64 FPR64:$Rn, FPR64:$Rm)>; 4778def : Pat<(v2f64 (AArch64frecps (v2f64 FPR128:$Rn), (v2f64 FPR128:$Rm))), 4779 (FRECPSv2f64 FPR128:$Rn, FPR128:$Rm)>; 4780 4781def : Pat<(f16 (int_aarch64_neon_frecpx (f16 FPR16:$Rn))), 4782 (FRECPXv1f16 FPR16:$Rn)>; 4783def : Pat<(f32 (int_aarch64_neon_frecpx (f32 FPR32:$Rn))), 4784 (FRECPXv1i32 FPR32:$Rn)>; 4785def : Pat<(f64 (int_aarch64_neon_frecpx (f64 FPR64:$Rn))), 4786 (FRECPXv1i64 FPR64:$Rn)>; 4787 4788def : Pat<(f16 (int_aarch64_neon_frsqrte (f16 FPR16:$Rn))), 4789 (FRSQRTEv1f16 FPR16:$Rn)>; 4790def : Pat<(f32 (int_aarch64_neon_frsqrte (f32 FPR32:$Rn))), 4791 (FRSQRTEv1i32 FPR32:$Rn)>; 4792def : Pat<(f64 (int_aarch64_neon_frsqrte (f64 FPR64:$Rn))), 4793 (FRSQRTEv1i64 FPR64:$Rn)>; 4794def : Pat<(v1f64 (int_aarch64_neon_frsqrte (v1f64 FPR64:$Rn))), 4795 (FRSQRTEv1i64 FPR64:$Rn)>; 4796 4797def : Pat<(f32 (AArch64frsqrte (f32 FPR32:$Rn))), 4798 (FRSQRTEv1i32 FPR32:$Rn)>; 4799def : Pat<(v2f32 (AArch64frsqrte (v2f32 V64:$Rn))), 4800 (FRSQRTEv2f32 V64:$Rn)>; 4801def : Pat<(v4f32 (AArch64frsqrte (v4f32 FPR128:$Rn))), 4802 (FRSQRTEv4f32 FPR128:$Rn)>; 4803def : Pat<(f64 (AArch64frsqrte (f64 FPR64:$Rn))), 4804 (FRSQRTEv1i64 FPR64:$Rn)>; 4805def : Pat<(v1f64 (AArch64frsqrte (v1f64 FPR64:$Rn))), 4806 (FRSQRTEv1i64 FPR64:$Rn)>; 4807def : Pat<(v2f64 (AArch64frsqrte (v2f64 FPR128:$Rn))), 4808 (FRSQRTEv2f64 FPR128:$Rn)>; 4809 4810def : Pat<(f32 (AArch64frsqrts (f32 FPR32:$Rn), (f32 FPR32:$Rm))), 4811 (FRSQRTS32 FPR32:$Rn, FPR32:$Rm)>; 4812def : Pat<(v2f32 (AArch64frsqrts (v2f32 V64:$Rn), (v2f32 V64:$Rm))), 4813 (FRSQRTSv2f32 V64:$Rn, V64:$Rm)>; 4814def : Pat<(v4f32 (AArch64frsqrts (v4f32 FPR128:$Rn), (v4f32 FPR128:$Rm))), 4815 (FRSQRTSv4f32 FPR128:$Rn, FPR128:$Rm)>; 4816def : Pat<(f64 (AArch64frsqrts (f64 FPR64:$Rn), (f64 FPR64:$Rm))), 4817 (FRSQRTS64 FPR64:$Rn, FPR64:$Rm)>; 4818def : Pat<(v2f64 (AArch64frsqrts (v2f64 FPR128:$Rn), (v2f64 FPR128:$Rm))), 4819 (FRSQRTSv2f64 FPR128:$Rn, FPR128:$Rm)>; 4820 4821// Some float -> int -> float conversion patterns for which we want to keep the 4822// int values in FP registers using the corresponding NEON instructions to 4823// avoid more costly int <-> fp register transfers. 4824let Predicates = [HasNEON] in { 4825def : Pat<(f64 (sint_to_fp (i64 (fp_to_sint f64:$Rn)))), 4826 (SCVTFv1i64 (i64 (FCVTZSv1i64 f64:$Rn)))>; 4827def : Pat<(f32 (sint_to_fp (i32 (fp_to_sint f32:$Rn)))), 4828 (SCVTFv1i32 (i32 (FCVTZSv1i32 f32:$Rn)))>; 4829def : Pat<(f64 (uint_to_fp (i64 (fp_to_uint f64:$Rn)))), 4830 (UCVTFv1i64 (i64 (FCVTZUv1i64 f64:$Rn)))>; 4831def : Pat<(f32 (uint_to_fp (i32 (fp_to_uint f32:$Rn)))), 4832 (UCVTFv1i32 (i32 (FCVTZUv1i32 f32:$Rn)))>; 4833 4834let Predicates = [HasFullFP16] in { 4835def : Pat<(f16 (sint_to_fp (i32 (fp_to_sint f16:$Rn)))), 4836 (SCVTFv1i16 (f16 (FCVTZSv1f16 f16:$Rn)))>; 4837def : Pat<(f16 (uint_to_fp (i32 (fp_to_uint f16:$Rn)))), 4838 (UCVTFv1i16 (f16 (FCVTZUv1f16 f16:$Rn)))>; 4839} 4840} 4841 4842// If an integer is about to be converted to a floating point value, 4843// just load it on the floating point unit. 4844// Here are the patterns for 8 and 16-bits to float. 4845// 8-bits -> float. 4846multiclass UIntToFPROLoadPat<ValueType DstTy, ValueType SrcTy, 4847 SDPatternOperator loadop, Instruction UCVTF, 4848 ROAddrMode ro, Instruction LDRW, Instruction LDRX, 4849 SubRegIndex sub> { 4850 def : Pat<(DstTy (uint_to_fp (SrcTy 4851 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, 4852 ro.Wext:$extend))))), 4853 (UCVTF (INSERT_SUBREG (DstTy (IMPLICIT_DEF)), 4854 (LDRW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend), 4855 sub))>; 4856 4857 def : Pat<(DstTy (uint_to_fp (SrcTy 4858 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, 4859 ro.Wext:$extend))))), 4860 (UCVTF (INSERT_SUBREG (DstTy (IMPLICIT_DEF)), 4861 (LDRX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend), 4862 sub))>; 4863} 4864 4865defm : UIntToFPROLoadPat<f32, i32, zextloadi8, 4866 UCVTFv1i32, ro8, LDRBroW, LDRBroX, bsub>; 4867def : Pat <(f32 (uint_to_fp (i32 4868 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))), 4869 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)), 4870 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub))>; 4871def : Pat <(f32 (uint_to_fp (i32 4872 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))))), 4873 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)), 4874 (LDURBi GPR64sp:$Rn, simm9:$offset), bsub))>; 4875// 16-bits -> float. 4876defm : UIntToFPROLoadPat<f32, i32, zextloadi16, 4877 UCVTFv1i32, ro16, LDRHroW, LDRHroX, hsub>; 4878def : Pat <(f32 (uint_to_fp (i32 4879 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))), 4880 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)), 4881 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub))>; 4882def : Pat <(f32 (uint_to_fp (i32 4883 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))))), 4884 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)), 4885 (LDURHi GPR64sp:$Rn, simm9:$offset), hsub))>; 4886// 32-bits are handled in target specific dag combine: 4887// performIntToFpCombine. 4888// 64-bits integer to 32-bits floating point, not possible with 4889// UCVTF on floating point registers (both source and destination 4890// must have the same size). 4891 4892// Here are the patterns for 8, 16, 32, and 64-bits to double. 4893// 8-bits -> double. 4894defm : UIntToFPROLoadPat<f64, i32, zextloadi8, 4895 UCVTFv1i64, ro8, LDRBroW, LDRBroX, bsub>; 4896def : Pat <(f64 (uint_to_fp (i32 4897 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))), 4898 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), 4899 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub))>; 4900def : Pat <(f64 (uint_to_fp (i32 4901 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))))), 4902 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), 4903 (LDURBi GPR64sp:$Rn, simm9:$offset), bsub))>; 4904// 16-bits -> double. 4905defm : UIntToFPROLoadPat<f64, i32, zextloadi16, 4906 UCVTFv1i64, ro16, LDRHroW, LDRHroX, hsub>; 4907def : Pat <(f64 (uint_to_fp (i32 4908 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))), 4909 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), 4910 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub))>; 4911def : Pat <(f64 (uint_to_fp (i32 4912 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))))), 4913 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), 4914 (LDURHi GPR64sp:$Rn, simm9:$offset), hsub))>; 4915// 32-bits -> double. 4916defm : UIntToFPROLoadPat<f64, i32, load, 4917 UCVTFv1i64, ro32, LDRSroW, LDRSroX, ssub>; 4918def : Pat <(f64 (uint_to_fp (i32 4919 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))), 4920 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), 4921 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub))>; 4922def : Pat <(f64 (uint_to_fp (i32 4923 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset))))), 4924 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), 4925 (LDURSi GPR64sp:$Rn, simm9:$offset), ssub))>; 4926// 64-bits -> double are handled in target specific dag combine: 4927// performIntToFpCombine. 4928 4929//===----------------------------------------------------------------------===// 4930// Advanced SIMD three different-sized vector instructions. 4931//===----------------------------------------------------------------------===// 4932 4933defm ADDHN : SIMDNarrowThreeVectorBHS<0,0b0100,"addhn", int_aarch64_neon_addhn>; 4934defm SUBHN : SIMDNarrowThreeVectorBHS<0,0b0110,"subhn", int_aarch64_neon_subhn>; 4935defm RADDHN : SIMDNarrowThreeVectorBHS<1,0b0100,"raddhn",int_aarch64_neon_raddhn>; 4936defm RSUBHN : SIMDNarrowThreeVectorBHS<1,0b0110,"rsubhn",int_aarch64_neon_rsubhn>; 4937defm PMULL : SIMDDifferentThreeVectorBD<0,0b1110,"pmull",int_aarch64_neon_pmull>; 4938defm SABAL : SIMDLongThreeVectorTiedBHSabal<0,0b0101,"sabal", 4939 AArch64sabd>; 4940defm SABDL : SIMDLongThreeVectorBHSabdl<0, 0b0111, "sabdl", 4941 AArch64sabd>; 4942defm SADDL : SIMDLongThreeVectorBHS< 0, 0b0000, "saddl", 4943 BinOpFrag<(add (sext node:$LHS), (sext node:$RHS))>>; 4944defm SADDW : SIMDWideThreeVectorBHS< 0, 0b0001, "saddw", 4945 BinOpFrag<(add node:$LHS, (sext node:$RHS))>>; 4946defm SMLAL : SIMDLongThreeVectorTiedBHS<0, 0b1000, "smlal", 4947 TriOpFrag<(add node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>; 4948defm SMLSL : SIMDLongThreeVectorTiedBHS<0, 0b1010, "smlsl", 4949 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>; 4950defm SMULL : SIMDLongThreeVectorBHS<0, 0b1100, "smull", int_aarch64_neon_smull>; 4951defm SQDMLAL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1001, "sqdmlal", 4952 int_aarch64_neon_sqadd>; 4953defm SQDMLSL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1011, "sqdmlsl", 4954 int_aarch64_neon_sqsub>; 4955defm SQDMULL : SIMDLongThreeVectorHS<0, 0b1101, "sqdmull", 4956 int_aarch64_neon_sqdmull>; 4957defm SSUBL : SIMDLongThreeVectorBHS<0, 0b0010, "ssubl", 4958 BinOpFrag<(sub (sext node:$LHS), (sext node:$RHS))>>; 4959defm SSUBW : SIMDWideThreeVectorBHS<0, 0b0011, "ssubw", 4960 BinOpFrag<(sub node:$LHS, (sext node:$RHS))>>; 4961defm UABAL : SIMDLongThreeVectorTiedBHSabal<1, 0b0101, "uabal", 4962 AArch64uabd>; 4963defm UADDL : SIMDLongThreeVectorBHS<1, 0b0000, "uaddl", 4964 BinOpFrag<(add (zanyext node:$LHS), (zanyext node:$RHS))>>; 4965defm UADDW : SIMDWideThreeVectorBHS<1, 0b0001, "uaddw", 4966 BinOpFrag<(add node:$LHS, (zanyext node:$RHS))>>; 4967defm UMLAL : SIMDLongThreeVectorTiedBHS<1, 0b1000, "umlal", 4968 TriOpFrag<(add node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>; 4969defm UMLSL : SIMDLongThreeVectorTiedBHS<1, 0b1010, "umlsl", 4970 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>; 4971defm UMULL : SIMDLongThreeVectorBHS<1, 0b1100, "umull", int_aarch64_neon_umull>; 4972defm USUBL : SIMDLongThreeVectorBHS<1, 0b0010, "usubl", 4973 BinOpFrag<(sub (zanyext node:$LHS), (zanyext node:$RHS))>>; 4974defm USUBW : SIMDWideThreeVectorBHS< 1, 0b0011, "usubw", 4975 BinOpFrag<(sub node:$LHS, (zanyext node:$RHS))>>; 4976 4977// Additional patterns for [SU]ML[AS]L 4978multiclass Neon_mul_acc_widen_patterns<SDPatternOperator opnode, SDPatternOperator vecopnode, 4979 Instruction INST8B, Instruction INST4H, Instruction INST2S> { 4980 def : Pat<(v4i16 (opnode 4981 V64:$Ra, 4982 (v4i16 (extract_subvector 4983 (vecopnode (v8i8 V64:$Rn),(v8i8 V64:$Rm)), 4984 (i64 0))))), 4985 (EXTRACT_SUBREG (v8i16 (INST8B 4986 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), V64:$Ra, dsub), 4987 V64:$Rn, V64:$Rm)), dsub)>; 4988 def : Pat<(v2i32 (opnode 4989 V64:$Ra, 4990 (v2i32 (extract_subvector 4991 (vecopnode (v4i16 V64:$Rn),(v4i16 V64:$Rm)), 4992 (i64 0))))), 4993 (EXTRACT_SUBREG (v4i32 (INST4H 4994 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), V64:$Ra, dsub), 4995 V64:$Rn, V64:$Rm)), dsub)>; 4996 def : Pat<(v1i64 (opnode 4997 V64:$Ra, 4998 (v1i64 (extract_subvector 4999 (vecopnode (v2i32 V64:$Rn),(v2i32 V64:$Rm)), 5000 (i64 0))))), 5001 (EXTRACT_SUBREG (v2i64 (INST2S 5002 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), V64:$Ra, dsub), 5003 V64:$Rn, V64:$Rm)), dsub)>; 5004} 5005 5006defm : Neon_mul_acc_widen_patterns<add, int_aarch64_neon_umull, 5007 UMLALv8i8_v8i16, UMLALv4i16_v4i32, UMLALv2i32_v2i64>; 5008defm : Neon_mul_acc_widen_patterns<add, int_aarch64_neon_smull, 5009 SMLALv8i8_v8i16, SMLALv4i16_v4i32, SMLALv2i32_v2i64>; 5010defm : Neon_mul_acc_widen_patterns<sub, int_aarch64_neon_umull, 5011 UMLSLv8i8_v8i16, UMLSLv4i16_v4i32, UMLSLv2i32_v2i64>; 5012defm : Neon_mul_acc_widen_patterns<sub, int_aarch64_neon_smull, 5013 SMLSLv8i8_v8i16, SMLSLv4i16_v4i32, SMLSLv2i32_v2i64>; 5014 5015// Additional patterns for SMULL and UMULL 5016multiclass Neon_mul_widen_patterns<SDPatternOperator opnode, 5017 Instruction INST8B, Instruction INST4H, Instruction INST2S> { 5018 def : Pat<(v8i16 (opnode (v8i8 V64:$Rn), (v8i8 V64:$Rm))), 5019 (INST8B V64:$Rn, V64:$Rm)>; 5020 def : Pat<(v4i32 (opnode (v4i16 V64:$Rn), (v4i16 V64:$Rm))), 5021 (INST4H V64:$Rn, V64:$Rm)>; 5022 def : Pat<(v2i64 (opnode (v2i32 V64:$Rn), (v2i32 V64:$Rm))), 5023 (INST2S V64:$Rn, V64:$Rm)>; 5024} 5025 5026defm : Neon_mul_widen_patterns<AArch64smull, SMULLv8i8_v8i16, 5027 SMULLv4i16_v4i32, SMULLv2i32_v2i64>; 5028defm : Neon_mul_widen_patterns<AArch64umull, UMULLv8i8_v8i16, 5029 UMULLv4i16_v4i32, UMULLv2i32_v2i64>; 5030 5031// Patterns for smull2/umull2. 5032multiclass Neon_mul_high_patterns<SDPatternOperator opnode, 5033 Instruction INST8B, Instruction INST4H, Instruction INST2S> { 5034 def : Pat<(v8i16 (opnode (extract_high_v16i8 V128:$Rn), 5035 (extract_high_v16i8 V128:$Rm))), 5036 (INST8B V128:$Rn, V128:$Rm)>; 5037 def : Pat<(v4i32 (opnode (extract_high_v8i16 V128:$Rn), 5038 (extract_high_v8i16 V128:$Rm))), 5039 (INST4H V128:$Rn, V128:$Rm)>; 5040 def : Pat<(v2i64 (opnode (extract_high_v4i32 V128:$Rn), 5041 (extract_high_v4i32 V128:$Rm))), 5042 (INST2S V128:$Rn, V128:$Rm)>; 5043} 5044 5045defm : Neon_mul_high_patterns<AArch64smull, SMULLv16i8_v8i16, 5046 SMULLv8i16_v4i32, SMULLv4i32_v2i64>; 5047defm : Neon_mul_high_patterns<AArch64umull, UMULLv16i8_v8i16, 5048 UMULLv8i16_v4i32, UMULLv4i32_v2i64>; 5049 5050// Additional patterns for SMLAL/SMLSL and UMLAL/UMLSL 5051multiclass Neon_mulacc_widen_patterns<SDPatternOperator opnode, 5052 Instruction INST8B, Instruction INST4H, Instruction INST2S> { 5053 def : Pat<(v8i16 (opnode (v8i16 V128:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm))), 5054 (INST8B V128:$Rd, V64:$Rn, V64:$Rm)>; 5055 def : Pat<(v4i32 (opnode (v4i32 V128:$Rd), (v4i16 V64:$Rn), (v4i16 V64:$Rm))), 5056 (INST4H V128:$Rd, V64:$Rn, V64:$Rm)>; 5057 def : Pat<(v2i64 (opnode (v2i64 V128:$Rd), (v2i32 V64:$Rn), (v2i32 V64:$Rm))), 5058 (INST2S V128:$Rd, V64:$Rn, V64:$Rm)>; 5059} 5060 5061defm : Neon_mulacc_widen_patterns< 5062 TriOpFrag<(add node:$LHS, (AArch64smull node:$MHS, node:$RHS))>, 5063 SMLALv8i8_v8i16, SMLALv4i16_v4i32, SMLALv2i32_v2i64>; 5064defm : Neon_mulacc_widen_patterns< 5065 TriOpFrag<(add node:$LHS, (AArch64umull node:$MHS, node:$RHS))>, 5066 UMLALv8i8_v8i16, UMLALv4i16_v4i32, UMLALv2i32_v2i64>; 5067defm : Neon_mulacc_widen_patterns< 5068 TriOpFrag<(sub node:$LHS, (AArch64smull node:$MHS, node:$RHS))>, 5069 SMLSLv8i8_v8i16, SMLSLv4i16_v4i32, SMLSLv2i32_v2i64>; 5070defm : Neon_mulacc_widen_patterns< 5071 TriOpFrag<(sub node:$LHS, (AArch64umull node:$MHS, node:$RHS))>, 5072 UMLSLv8i8_v8i16, UMLSLv4i16_v4i32, UMLSLv2i32_v2i64>; 5073 5074// Patterns for 64-bit pmull 5075def : Pat<(int_aarch64_neon_pmull64 V64:$Rn, V64:$Rm), 5076 (PMULLv1i64 V64:$Rn, V64:$Rm)>; 5077def : Pat<(int_aarch64_neon_pmull64 (extractelt (v2i64 V128:$Rn), (i64 1)), 5078 (extractelt (v2i64 V128:$Rm), (i64 1))), 5079 (PMULLv2i64 V128:$Rn, V128:$Rm)>; 5080 5081// CodeGen patterns for addhn and subhn instructions, which can actually be 5082// written in LLVM IR without too much difficulty. 5083 5084// ADDHN 5085def : Pat<(v8i8 (trunc (v8i16 (AArch64vlshr (add V128:$Rn, V128:$Rm), (i32 8))))), 5086 (ADDHNv8i16_v8i8 V128:$Rn, V128:$Rm)>; 5087def : Pat<(v4i16 (trunc (v4i32 (AArch64vlshr (add V128:$Rn, V128:$Rm), 5088 (i32 16))))), 5089 (ADDHNv4i32_v4i16 V128:$Rn, V128:$Rm)>; 5090def : Pat<(v2i32 (trunc (v2i64 (AArch64vlshr (add V128:$Rn, V128:$Rm), 5091 (i32 32))))), 5092 (ADDHNv2i64_v2i32 V128:$Rn, V128:$Rm)>; 5093def : Pat<(concat_vectors (v8i8 V64:$Rd), 5094 (trunc (v8i16 (AArch64vlshr (add V128:$Rn, V128:$Rm), 5095 (i32 8))))), 5096 (ADDHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub), 5097 V128:$Rn, V128:$Rm)>; 5098def : Pat<(concat_vectors (v4i16 V64:$Rd), 5099 (trunc (v4i32 (AArch64vlshr (add V128:$Rn, V128:$Rm), 5100 (i32 16))))), 5101 (ADDHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub), 5102 V128:$Rn, V128:$Rm)>; 5103def : Pat<(concat_vectors (v2i32 V64:$Rd), 5104 (trunc (v2i64 (AArch64vlshr (add V128:$Rn, V128:$Rm), 5105 (i32 32))))), 5106 (ADDHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub), 5107 V128:$Rn, V128:$Rm)>; 5108 5109// SUBHN 5110def : Pat<(v8i8 (trunc (v8i16 (AArch64vlshr (sub V128:$Rn, V128:$Rm), (i32 8))))), 5111 (SUBHNv8i16_v8i8 V128:$Rn, V128:$Rm)>; 5112def : Pat<(v4i16 (trunc (v4i32 (AArch64vlshr (sub V128:$Rn, V128:$Rm), 5113 (i32 16))))), 5114 (SUBHNv4i32_v4i16 V128:$Rn, V128:$Rm)>; 5115def : Pat<(v2i32 (trunc (v2i64 (AArch64vlshr (sub V128:$Rn, V128:$Rm), 5116 (i32 32))))), 5117 (SUBHNv2i64_v2i32 V128:$Rn, V128:$Rm)>; 5118def : Pat<(concat_vectors (v8i8 V64:$Rd), 5119 (trunc (v8i16 (AArch64vlshr (sub V128:$Rn, V128:$Rm), 5120 (i32 8))))), 5121 (SUBHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub), 5122 V128:$Rn, V128:$Rm)>; 5123def : Pat<(concat_vectors (v4i16 V64:$Rd), 5124 (trunc (v4i32 (AArch64vlshr (sub V128:$Rn, V128:$Rm), 5125 (i32 16))))), 5126 (SUBHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub), 5127 V128:$Rn, V128:$Rm)>; 5128def : Pat<(concat_vectors (v2i32 V64:$Rd), 5129 (trunc (v2i64 (AArch64vlshr (sub V128:$Rn, V128:$Rm), 5130 (i32 32))))), 5131 (SUBHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub), 5132 V128:$Rn, V128:$Rm)>; 5133 5134//---------------------------------------------------------------------------- 5135// AdvSIMD bitwise extract from vector instruction. 5136//---------------------------------------------------------------------------- 5137 5138defm EXT : SIMDBitwiseExtract<"ext">; 5139 5140def AdjustExtImm : SDNodeXForm<imm, [{ 5141 return CurDAG->getTargetConstant(8 + N->getZExtValue(), SDLoc(N), MVT::i32); 5142}]>; 5143multiclass ExtPat<ValueType VT64, ValueType VT128, int N> { 5144 def : Pat<(VT64 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))), 5145 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>; 5146 def : Pat<(VT128 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))), 5147 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>; 5148 // We use EXT to handle extract_subvector to copy the upper 64-bits of a 5149 // 128-bit vector. 5150 def : Pat<(VT64 (extract_subvector V128:$Rn, (i64 N))), 5151 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>; 5152 // A 64-bit EXT of two halves of the same 128-bit register can be done as a 5153 // single 128-bit EXT. 5154 def : Pat<(VT64 (AArch64ext (extract_subvector V128:$Rn, (i64 0)), 5155 (extract_subvector V128:$Rn, (i64 N)), 5156 (i32 imm:$imm))), 5157 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, imm:$imm), dsub)>; 5158 // A 64-bit EXT of the high half of a 128-bit register can be done using a 5159 // 128-bit EXT of the whole register with an adjustment to the immediate. The 5160 // top half of the other operand will be unset, but that doesn't matter as it 5161 // will not be used. 5162 def : Pat<(VT64 (AArch64ext (extract_subvector V128:$Rn, (i64 N)), 5163 V64:$Rm, 5164 (i32 imm:$imm))), 5165 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, 5166 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), 5167 (AdjustExtImm imm:$imm)), dsub)>; 5168} 5169 5170defm : ExtPat<v8i8, v16i8, 8>; 5171defm : ExtPat<v4i16, v8i16, 4>; 5172defm : ExtPat<v4f16, v8f16, 4>; 5173defm : ExtPat<v4bf16, v8bf16, 4>; 5174defm : ExtPat<v2i32, v4i32, 2>; 5175defm : ExtPat<v2f32, v4f32, 2>; 5176defm : ExtPat<v1i64, v2i64, 1>; 5177defm : ExtPat<v1f64, v2f64, 1>; 5178 5179//---------------------------------------------------------------------------- 5180// AdvSIMD zip vector 5181//---------------------------------------------------------------------------- 5182 5183defm TRN1 : SIMDZipVector<0b010, "trn1", AArch64trn1>; 5184defm TRN2 : SIMDZipVector<0b110, "trn2", AArch64trn2>; 5185defm UZP1 : SIMDZipVector<0b001, "uzp1", AArch64uzp1>; 5186defm UZP2 : SIMDZipVector<0b101, "uzp2", AArch64uzp2>; 5187defm ZIP1 : SIMDZipVector<0b011, "zip1", AArch64zip1>; 5188defm ZIP2 : SIMDZipVector<0b111, "zip2", AArch64zip2>; 5189 5190//---------------------------------------------------------------------------- 5191// AdvSIMD TBL/TBX instructions 5192//---------------------------------------------------------------------------- 5193 5194defm TBL : SIMDTableLookup< 0, "tbl">; 5195defm TBX : SIMDTableLookupTied<1, "tbx">; 5196 5197def : Pat<(v8i8 (int_aarch64_neon_tbl1 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))), 5198 (TBLv8i8One VecListOne128:$Rn, V64:$Ri)>; 5199def : Pat<(v16i8 (int_aarch64_neon_tbl1 (v16i8 V128:$Ri), (v16i8 V128:$Rn))), 5200 (TBLv16i8One V128:$Ri, V128:$Rn)>; 5201 5202def : Pat<(v8i8 (int_aarch64_neon_tbx1 (v8i8 V64:$Rd), 5203 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))), 5204 (TBXv8i8One V64:$Rd, VecListOne128:$Rn, V64:$Ri)>; 5205def : Pat<(v16i8 (int_aarch64_neon_tbx1 (v16i8 V128:$Rd), 5206 (v16i8 V128:$Ri), (v16i8 V128:$Rn))), 5207 (TBXv16i8One V128:$Rd, V128:$Ri, V128:$Rn)>; 5208 5209 5210//---------------------------------------------------------------------------- 5211// AdvSIMD scalar CPY instruction 5212//---------------------------------------------------------------------------- 5213 5214defm CPY : SIMDScalarCPY<"cpy">; 5215 5216//---------------------------------------------------------------------------- 5217// AdvSIMD scalar pairwise instructions 5218//---------------------------------------------------------------------------- 5219 5220defm ADDP : SIMDPairwiseScalarD<0, 0b11011, "addp">; 5221defm FADDP : SIMDFPPairwiseScalar<0, 0b01101, "faddp">; 5222defm FMAXNMP : SIMDFPPairwiseScalar<0, 0b01100, "fmaxnmp">; 5223defm FMAXP : SIMDFPPairwiseScalar<0, 0b01111, "fmaxp">; 5224defm FMINNMP : SIMDFPPairwiseScalar<1, 0b01100, "fminnmp">; 5225defm FMINP : SIMDFPPairwiseScalar<1, 0b01111, "fminp">; 5226 5227let Predicates = [HasFullFP16] in { 5228def : Pat<(f16 (vecreduce_fadd (v8f16 V128:$Rn))), 5229 (FADDPv2i16p 5230 (EXTRACT_SUBREG 5231 (FADDPv8f16 (FADDPv8f16 V128:$Rn, (v8f16 (IMPLICIT_DEF))), (v8f16 (IMPLICIT_DEF))), 5232 dsub))>; 5233def : Pat<(f16 (vecreduce_fadd (v4f16 V64:$Rn))), 5234 (FADDPv2i16p (FADDPv4f16 V64:$Rn, (v4f16 (IMPLICIT_DEF))))>; 5235} 5236def : Pat<(f32 (vecreduce_fadd (v4f32 V128:$Rn))), 5237 (FADDPv2i32p 5238 (EXTRACT_SUBREG 5239 (FADDPv4f32 V128:$Rn, (v4f32 (IMPLICIT_DEF))), 5240 dsub))>; 5241def : Pat<(f32 (vecreduce_fadd (v2f32 V64:$Rn))), 5242 (FADDPv2i32p V64:$Rn)>; 5243def : Pat<(f64 (vecreduce_fadd (v2f64 V128:$Rn))), 5244 (FADDPv2i64p V128:$Rn)>; 5245 5246def : Pat<(v2i64 (AArch64saddv V128:$Rn)), 5247 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), (ADDPv2i64p V128:$Rn), dsub)>; 5248def : Pat<(v2i64 (AArch64uaddv V128:$Rn)), 5249 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), (ADDPv2i64p V128:$Rn), dsub)>; 5250def : Pat<(f32 (int_aarch64_neon_faddv (v2f32 V64:$Rn))), 5251 (FADDPv2i32p V64:$Rn)>; 5252def : Pat<(f32 (int_aarch64_neon_faddv (v4f32 V128:$Rn))), 5253 (FADDPv2i32p (EXTRACT_SUBREG (FADDPv4f32 V128:$Rn, V128:$Rn), dsub))>; 5254def : Pat<(f64 (int_aarch64_neon_faddv (v2f64 V128:$Rn))), 5255 (FADDPv2i64p V128:$Rn)>; 5256def : Pat<(f32 (int_aarch64_neon_fmaxnmv (v2f32 V64:$Rn))), 5257 (FMAXNMPv2i32p V64:$Rn)>; 5258def : Pat<(f64 (int_aarch64_neon_fmaxnmv (v2f64 V128:$Rn))), 5259 (FMAXNMPv2i64p V128:$Rn)>; 5260def : Pat<(f32 (int_aarch64_neon_fmaxv (v2f32 V64:$Rn))), 5261 (FMAXPv2i32p V64:$Rn)>; 5262def : Pat<(f64 (int_aarch64_neon_fmaxv (v2f64 V128:$Rn))), 5263 (FMAXPv2i64p V128:$Rn)>; 5264def : Pat<(f32 (int_aarch64_neon_fminnmv (v2f32 V64:$Rn))), 5265 (FMINNMPv2i32p V64:$Rn)>; 5266def : Pat<(f64 (int_aarch64_neon_fminnmv (v2f64 V128:$Rn))), 5267 (FMINNMPv2i64p V128:$Rn)>; 5268def : Pat<(f32 (int_aarch64_neon_fminv (v2f32 V64:$Rn))), 5269 (FMINPv2i32p V64:$Rn)>; 5270def : Pat<(f64 (int_aarch64_neon_fminv (v2f64 V128:$Rn))), 5271 (FMINPv2i64p V128:$Rn)>; 5272 5273//---------------------------------------------------------------------------- 5274// AdvSIMD INS/DUP instructions 5275//---------------------------------------------------------------------------- 5276 5277def DUPv8i8gpr : SIMDDupFromMain<0, {?,?,?,?,1}, ".8b", v8i8, V64, GPR32>; 5278def DUPv16i8gpr : SIMDDupFromMain<1, {?,?,?,?,1}, ".16b", v16i8, V128, GPR32>; 5279def DUPv4i16gpr : SIMDDupFromMain<0, {?,?,?,1,0}, ".4h", v4i16, V64, GPR32>; 5280def DUPv8i16gpr : SIMDDupFromMain<1, {?,?,?,1,0}, ".8h", v8i16, V128, GPR32>; 5281def DUPv2i32gpr : SIMDDupFromMain<0, {?,?,1,0,0}, ".2s", v2i32, V64, GPR32>; 5282def DUPv4i32gpr : SIMDDupFromMain<1, {?,?,1,0,0}, ".4s", v4i32, V128, GPR32>; 5283def DUPv2i64gpr : SIMDDupFromMain<1, {?,1,0,0,0}, ".2d", v2i64, V128, GPR64>; 5284 5285def DUPv2i64lane : SIMDDup64FromElement; 5286def DUPv2i32lane : SIMDDup32FromElement<0, ".2s", v2i32, V64>; 5287def DUPv4i32lane : SIMDDup32FromElement<1, ".4s", v4i32, V128>; 5288def DUPv4i16lane : SIMDDup16FromElement<0, ".4h", v4i16, V64>; 5289def DUPv8i16lane : SIMDDup16FromElement<1, ".8h", v8i16, V128>; 5290def DUPv8i8lane : SIMDDup8FromElement <0, ".8b", v8i8, V64>; 5291def DUPv16i8lane : SIMDDup8FromElement <1, ".16b", v16i8, V128>; 5292 5293// DUP from a 64-bit register to a 64-bit register is just a copy 5294def : Pat<(v1i64 (AArch64dup (i64 GPR64:$Rn))), 5295 (COPY_TO_REGCLASS GPR64:$Rn, FPR64)>; 5296def : Pat<(v1f64 (AArch64dup (f64 FPR64:$Rn))), 5297 (COPY_TO_REGCLASS FPR64:$Rn, FPR64)>; 5298 5299def : Pat<(v2f32 (AArch64dup (f32 FPR32:$Rn))), 5300 (v2f32 (DUPv2i32lane 5301 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub), 5302 (i64 0)))>; 5303def : Pat<(v4f32 (AArch64dup (f32 FPR32:$Rn))), 5304 (v4f32 (DUPv4i32lane 5305 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub), 5306 (i64 0)))>; 5307def : Pat<(v2f64 (AArch64dup (f64 FPR64:$Rn))), 5308 (v2f64 (DUPv2i64lane 5309 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rn, dsub), 5310 (i64 0)))>; 5311def : Pat<(v4f16 (AArch64dup (f16 FPR16:$Rn))), 5312 (v4f16 (DUPv4i16lane 5313 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR16:$Rn, hsub), 5314 (i64 0)))>; 5315def : Pat<(v4bf16 (AArch64dup (bf16 FPR16:$Rn))), 5316 (v4bf16 (DUPv4i16lane 5317 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR16:$Rn, hsub), 5318 (i64 0)))>; 5319def : Pat<(v8f16 (AArch64dup (f16 FPR16:$Rn))), 5320 (v8f16 (DUPv8i16lane 5321 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR16:$Rn, hsub), 5322 (i64 0)))>; 5323def : Pat<(v8bf16 (AArch64dup (bf16 FPR16:$Rn))), 5324 (v8bf16 (DUPv8i16lane 5325 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR16:$Rn, hsub), 5326 (i64 0)))>; 5327 5328def : Pat<(v4f16 (AArch64duplane16 (v8f16 V128:$Rn), VectorIndexH:$imm)), 5329 (DUPv4i16lane V128:$Rn, VectorIndexH:$imm)>; 5330def : Pat<(v8f16 (AArch64duplane16 (v8f16 V128:$Rn), VectorIndexH:$imm)), 5331 (DUPv8i16lane V128:$Rn, VectorIndexH:$imm)>; 5332 5333def : Pat<(v4bf16 (AArch64duplane16 (v8bf16 V128:$Rn), VectorIndexH:$imm)), 5334 (DUPv4i16lane V128:$Rn, VectorIndexH:$imm)>; 5335def : Pat<(v8bf16 (AArch64duplane16 (v8bf16 V128:$Rn), VectorIndexH:$imm)), 5336 (DUPv8i16lane V128:$Rn, VectorIndexH:$imm)>; 5337 5338def : Pat<(v2f32 (AArch64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)), 5339 (DUPv2i32lane V128:$Rn, VectorIndexS:$imm)>; 5340def : Pat<(v4f32 (AArch64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)), 5341 (DUPv4i32lane V128:$Rn, VectorIndexS:$imm)>; 5342def : Pat<(v2f64 (AArch64duplane64 (v2f64 V128:$Rn), VectorIndexD:$imm)), 5343 (DUPv2i64lane V128:$Rn, VectorIndexD:$imm)>; 5344 5345// If there's an (AArch64dup (vector_extract ...) ...), we can use a duplane 5346// instruction even if the types don't match: we just have to remap the lane 5347// carefully. N.b. this trick only applies to truncations. 5348def VecIndex_x2 : SDNodeXForm<imm, [{ 5349 return CurDAG->getTargetConstant(2 * N->getZExtValue(), SDLoc(N), MVT::i64); 5350}]>; 5351def VecIndex_x4 : SDNodeXForm<imm, [{ 5352 return CurDAG->getTargetConstant(4 * N->getZExtValue(), SDLoc(N), MVT::i64); 5353}]>; 5354def VecIndex_x8 : SDNodeXForm<imm, [{ 5355 return CurDAG->getTargetConstant(8 * N->getZExtValue(), SDLoc(N), MVT::i64); 5356}]>; 5357 5358multiclass DUPWithTruncPats<ValueType ResVT, ValueType Src64VT, 5359 ValueType Src128VT, ValueType ScalVT, 5360 Instruction DUP, SDNodeXForm IdxXFORM> { 5361 def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src128VT V128:$Rn), 5362 imm:$idx)))), 5363 (DUP V128:$Rn, (IdxXFORM imm:$idx))>; 5364 5365 def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src64VT V64:$Rn), 5366 imm:$idx)))), 5367 (DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>; 5368} 5369 5370defm : DUPWithTruncPats<v8i8, v4i16, v8i16, i32, DUPv8i8lane, VecIndex_x2>; 5371defm : DUPWithTruncPats<v8i8, v2i32, v4i32, i32, DUPv8i8lane, VecIndex_x4>; 5372defm : DUPWithTruncPats<v4i16, v2i32, v4i32, i32, DUPv4i16lane, VecIndex_x2>; 5373 5374defm : DUPWithTruncPats<v16i8, v4i16, v8i16, i32, DUPv16i8lane, VecIndex_x2>; 5375defm : DUPWithTruncPats<v16i8, v2i32, v4i32, i32, DUPv16i8lane, VecIndex_x4>; 5376defm : DUPWithTruncPats<v8i16, v2i32, v4i32, i32, DUPv8i16lane, VecIndex_x2>; 5377 5378multiclass DUPWithTrunci64Pats<ValueType ResVT, Instruction DUP, 5379 SDNodeXForm IdxXFORM> { 5380 def : Pat<(ResVT (AArch64dup (i32 (trunc (extractelt (v2i64 V128:$Rn), 5381 imm:$idx))))), 5382 (DUP V128:$Rn, (IdxXFORM imm:$idx))>; 5383 5384 def : Pat<(ResVT (AArch64dup (i32 (trunc (extractelt (v1i64 V64:$Rn), 5385 imm:$idx))))), 5386 (DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>; 5387} 5388 5389defm : DUPWithTrunci64Pats<v8i8, DUPv8i8lane, VecIndex_x8>; 5390defm : DUPWithTrunci64Pats<v4i16, DUPv4i16lane, VecIndex_x4>; 5391defm : DUPWithTrunci64Pats<v2i32, DUPv2i32lane, VecIndex_x2>; 5392 5393defm : DUPWithTrunci64Pats<v16i8, DUPv16i8lane, VecIndex_x8>; 5394defm : DUPWithTrunci64Pats<v8i16, DUPv8i16lane, VecIndex_x4>; 5395defm : DUPWithTrunci64Pats<v4i32, DUPv4i32lane, VecIndex_x2>; 5396 5397// SMOV and UMOV definitions, with some extra patterns for convenience 5398defm SMOV : SMov; 5399defm UMOV : UMov; 5400 5401def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8), 5402 (i32 (SMOVvi8to32 V128:$Rn, VectorIndexB:$idx))>; 5403def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8), 5404 (i64 (SMOVvi8to64 V128:$Rn, VectorIndexB:$idx))>; 5405def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16), 5406 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>; 5407def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16), 5408 (i64 (SMOVvi16to64 V128:$Rn, VectorIndexH:$idx))>; 5409def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16), 5410 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>; 5411def : Pat<(sext (i32 (vector_extract (v4i32 V128:$Rn), VectorIndexS:$idx))), 5412 (i64 (SMOVvi32to64 V128:$Rn, VectorIndexS:$idx))>; 5413 5414def : Pat<(sext_inreg (i64 (anyext (i32 (vector_extract (v16i8 V128:$Rn), 5415 VectorIndexB:$idx)))), i8), 5416 (i64 (SMOVvi8to64 V128:$Rn, VectorIndexB:$idx))>; 5417def : Pat<(sext_inreg (i64 (anyext (i32 (vector_extract (v8i16 V128:$Rn), 5418 VectorIndexH:$idx)))), i16), 5419 (i64 (SMOVvi16to64 V128:$Rn, VectorIndexH:$idx))>; 5420 5421// Extracting i8 or i16 elements will have the zero-extend transformed to 5422// an 'and' mask by type legalization since neither i8 nor i16 are legal types 5423// for AArch64. Match these patterns here since UMOV already zeroes out the high 5424// bits of the destination register. 5425def : Pat<(and (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), 5426 (i32 0xff)), 5427 (i32 (UMOVvi8 V128:$Rn, VectorIndexB:$idx))>; 5428def : Pat<(and (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx), 5429 (i32 0xffff)), 5430 (i32 (UMOVvi16 V128:$Rn, VectorIndexH:$idx))>; 5431 5432def : Pat<(i64 (and (i64 (anyext (i32 (vector_extract (v16i8 V128:$Rn), 5433 VectorIndexB:$idx)))), (i64 0xff))), 5434 (SUBREG_TO_REG (i64 0), (i32 (UMOVvi8 V128:$Rn, VectorIndexB:$idx)), sub_32)>; 5435def : Pat<(i64 (and (i64 (anyext (i32 (vector_extract (v8i16 V128:$Rn), 5436 VectorIndexH:$idx)))), (i64 0xffff))), 5437 (SUBREG_TO_REG (i64 0), (i32 (UMOVvi16 V128:$Rn, VectorIndexH:$idx)), sub_32)>; 5438 5439defm INS : SIMDIns; 5440 5441def : Pat<(v16i8 (scalar_to_vector GPR32:$Rn)), 5442 (SUBREG_TO_REG (i32 0), 5443 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>; 5444def : Pat<(v8i8 (scalar_to_vector GPR32:$Rn)), 5445 (SUBREG_TO_REG (i32 0), 5446 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>; 5447 5448def : Pat<(v8i16 (scalar_to_vector GPR32:$Rn)), 5449 (SUBREG_TO_REG (i32 0), 5450 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>; 5451def : Pat<(v4i16 (scalar_to_vector GPR32:$Rn)), 5452 (SUBREG_TO_REG (i32 0), 5453 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>; 5454 5455def : Pat<(v4f16 (scalar_to_vector (f16 FPR16:$Rn))), 5456 (INSERT_SUBREG (v4f16 (IMPLICIT_DEF)), FPR16:$Rn, hsub)>; 5457def : Pat<(v8f16 (scalar_to_vector (f16 FPR16:$Rn))), 5458 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR16:$Rn, hsub)>; 5459 5460def : Pat<(v4bf16 (scalar_to_vector (bf16 FPR16:$Rn))), 5461 (INSERT_SUBREG (v4bf16 (IMPLICIT_DEF)), FPR16:$Rn, hsub)>; 5462def : Pat<(v8bf16 (scalar_to_vector (bf16 FPR16:$Rn))), 5463 (INSERT_SUBREG (v8bf16 (IMPLICIT_DEF)), FPR16:$Rn, hsub)>; 5464 5465def : Pat<(v2i32 (scalar_to_vector (i32 FPR32:$Rn))), 5466 (v2i32 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)), 5467 (i32 FPR32:$Rn), ssub))>; 5468def : Pat<(v4i32 (scalar_to_vector (i32 FPR32:$Rn))), 5469 (v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), 5470 (i32 FPR32:$Rn), ssub))>; 5471 5472def : Pat<(v2i64 (scalar_to_vector (i64 FPR64:$Rn))), 5473 (v2i64 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), 5474 (i64 FPR64:$Rn), dsub))>; 5475 5476def : Pat<(v4f16 (scalar_to_vector (f16 FPR16:$Rn))), 5477 (INSERT_SUBREG (v4f16 (IMPLICIT_DEF)), FPR16:$Rn, hsub)>; 5478def : Pat<(v8f16 (scalar_to_vector (f16 FPR16:$Rn))), 5479 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR16:$Rn, hsub)>; 5480 5481def : Pat<(v4bf16 (scalar_to_vector (bf16 FPR16:$Rn))), 5482 (INSERT_SUBREG (v4bf16 (IMPLICIT_DEF)), FPR16:$Rn, hsub)>; 5483def : Pat<(v8bf16 (scalar_to_vector (bf16 FPR16:$Rn))), 5484 (INSERT_SUBREG (v8bf16 (IMPLICIT_DEF)), FPR16:$Rn, hsub)>; 5485 5486def : Pat<(v4f32 (scalar_to_vector (f32 FPR32:$Rn))), 5487 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>; 5488def : Pat<(v2f32 (scalar_to_vector (f32 FPR32:$Rn))), 5489 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>; 5490 5491def : Pat<(v2f64 (scalar_to_vector (f64 FPR64:$Rn))), 5492 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rn, dsub)>; 5493 5494def : Pat<(v4f16 (vector_insert (v4f16 V64:$Rn), 5495 (f16 FPR16:$Rm), (i64 VectorIndexS:$imm))), 5496 (EXTRACT_SUBREG 5497 (INSvi16lane 5498 (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), V64:$Rn, dsub)), 5499 VectorIndexS:$imm, 5500 (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR16:$Rm, hsub)), 5501 (i64 0)), 5502 dsub)>; 5503 5504def : Pat<(vector_insert (v8f16 v8f16:$Rn), (f16 fpimm0), 5505 (i64 VectorIndexH:$imm)), 5506 (INSvi16gpr V128:$Rn, VectorIndexH:$imm, WZR)>; 5507def : Pat<(vector_insert v4f32:$Rn, (f32 fpimm0), 5508 (i64 VectorIndexS:$imm)), 5509 (INSvi32gpr V128:$Rn, VectorIndexS:$imm, WZR)>; 5510def : Pat<(vector_insert v2f64:$Rn, (f64 fpimm0), 5511 (i64 VectorIndexD:$imm)), 5512 (INSvi64gpr V128:$Rn, VectorIndexS:$imm, XZR)>; 5513 5514def : Pat<(v8f16 (vector_insert (v8f16 V128:$Rn), 5515 (f16 FPR16:$Rm), (i64 VectorIndexH:$imm))), 5516 (INSvi16lane 5517 V128:$Rn, VectorIndexH:$imm, 5518 (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR16:$Rm, hsub)), 5519 (i64 0))>; 5520 5521def : Pat<(v4bf16 (vector_insert (v4bf16 V64:$Rn), 5522 (bf16 FPR16:$Rm), (i64 VectorIndexS:$imm))), 5523 (EXTRACT_SUBREG 5524 (INSvi16lane 5525 (v8bf16 (INSERT_SUBREG (v8bf16 (IMPLICIT_DEF)), V64:$Rn, dsub)), 5526 VectorIndexS:$imm, 5527 (v8bf16 (INSERT_SUBREG (v8bf16 (IMPLICIT_DEF)), FPR16:$Rm, hsub)), 5528 (i64 0)), 5529 dsub)>; 5530 5531def : Pat<(v8bf16 (vector_insert (v8bf16 V128:$Rn), 5532 (bf16 FPR16:$Rm), (i64 VectorIndexH:$imm))), 5533 (INSvi16lane 5534 V128:$Rn, VectorIndexH:$imm, 5535 (v8bf16 (INSERT_SUBREG (v8bf16 (IMPLICIT_DEF)), FPR16:$Rm, hsub)), 5536 (i64 0))>; 5537 5538def : Pat<(v2f32 (vector_insert (v2f32 V64:$Rn), 5539 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))), 5540 (EXTRACT_SUBREG 5541 (INSvi32lane 5542 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), V64:$Rn, dsub)), 5543 VectorIndexS:$imm, 5544 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)), 5545 (i64 0)), 5546 dsub)>; 5547def : Pat<(v4f32 (vector_insert (v4f32 V128:$Rn), 5548 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))), 5549 (INSvi32lane 5550 V128:$Rn, VectorIndexS:$imm, 5551 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)), 5552 (i64 0))>; 5553def : Pat<(v2f64 (vector_insert (v2f64 V128:$Rn), 5554 (f64 FPR64:$Rm), (i64 VectorIndexD:$imm))), 5555 (INSvi64lane 5556 V128:$Rn, VectorIndexD:$imm, 5557 (v2f64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rm, dsub)), 5558 (i64 0))>; 5559 5560// Copy an element at a constant index in one vector into a constant indexed 5561// element of another. 5562// FIXME refactor to a shared class/dev parameterized on vector type, vector 5563// index type and INS extension 5564def : Pat<(v16i8 (int_aarch64_neon_vcopy_lane 5565 (v16i8 V128:$Vd), VectorIndexB:$idx, (v16i8 V128:$Vs), 5566 VectorIndexB:$idx2)), 5567 (v16i8 (INSvi8lane 5568 V128:$Vd, VectorIndexB:$idx, V128:$Vs, VectorIndexB:$idx2) 5569 )>; 5570def : Pat<(v8i16 (int_aarch64_neon_vcopy_lane 5571 (v8i16 V128:$Vd), VectorIndexH:$idx, (v8i16 V128:$Vs), 5572 VectorIndexH:$idx2)), 5573 (v8i16 (INSvi16lane 5574 V128:$Vd, VectorIndexH:$idx, V128:$Vs, VectorIndexH:$idx2) 5575 )>; 5576def : Pat<(v4i32 (int_aarch64_neon_vcopy_lane 5577 (v4i32 V128:$Vd), VectorIndexS:$idx, (v4i32 V128:$Vs), 5578 VectorIndexS:$idx2)), 5579 (v4i32 (INSvi32lane 5580 V128:$Vd, VectorIndexS:$idx, V128:$Vs, VectorIndexS:$idx2) 5581 )>; 5582def : Pat<(v2i64 (int_aarch64_neon_vcopy_lane 5583 (v2i64 V128:$Vd), VectorIndexD:$idx, (v2i64 V128:$Vs), 5584 VectorIndexD:$idx2)), 5585 (v2i64 (INSvi64lane 5586 V128:$Vd, VectorIndexD:$idx, V128:$Vs, VectorIndexD:$idx2) 5587 )>; 5588 5589multiclass Neon_INS_elt_pattern<ValueType VT128, ValueType VT64, 5590 ValueType VTScal, Instruction INS> { 5591 def : Pat<(VT128 (vector_insert V128:$src, 5592 (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)), 5593 imm:$Immd)), 5594 (INS V128:$src, imm:$Immd, V128:$Rn, imm:$Immn)>; 5595 5596 def : Pat<(VT128 (vector_insert V128:$src, 5597 (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)), 5598 imm:$Immd)), 5599 (INS V128:$src, imm:$Immd, 5600 (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn)>; 5601 5602 def : Pat<(VT64 (vector_insert V64:$src, 5603 (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)), 5604 imm:$Immd)), 5605 (EXTRACT_SUBREG (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub), 5606 imm:$Immd, V128:$Rn, imm:$Immn), 5607 dsub)>; 5608 5609 def : Pat<(VT64 (vector_insert V64:$src, 5610 (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)), 5611 imm:$Immd)), 5612 (EXTRACT_SUBREG 5613 (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub), imm:$Immd, 5614 (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn), 5615 dsub)>; 5616} 5617 5618defm : Neon_INS_elt_pattern<v8f16, v4f16, f16, INSvi16lane>; 5619defm : Neon_INS_elt_pattern<v8bf16, v4bf16, bf16, INSvi16lane>; 5620defm : Neon_INS_elt_pattern<v4f32, v2f32, f32, INSvi32lane>; 5621defm : Neon_INS_elt_pattern<v2f64, v1f64, f64, INSvi64lane>; 5622 5623 5624// Floating point vector extractions are codegen'd as either a sequence of 5625// subregister extractions, or a MOV (aka CPY here, alias for DUP) if 5626// the lane number is anything other than zero. 5627def : Pat<(vector_extract (v2f64 V128:$Rn), 0), 5628 (f64 (EXTRACT_SUBREG V128:$Rn, dsub))>; 5629def : Pat<(vector_extract (v4f32 V128:$Rn), 0), 5630 (f32 (EXTRACT_SUBREG V128:$Rn, ssub))>; 5631def : Pat<(vector_extract (v8f16 V128:$Rn), 0), 5632 (f16 (EXTRACT_SUBREG V128:$Rn, hsub))>; 5633def : Pat<(vector_extract (v8bf16 V128:$Rn), 0), 5634 (bf16 (EXTRACT_SUBREG V128:$Rn, hsub))>; 5635 5636 5637def : Pat<(vector_extract (v2f64 V128:$Rn), VectorIndexD:$idx), 5638 (f64 (CPYi64 V128:$Rn, VectorIndexD:$idx))>; 5639def : Pat<(vector_extract (v4f32 V128:$Rn), VectorIndexS:$idx), 5640 (f32 (CPYi32 V128:$Rn, VectorIndexS:$idx))>; 5641def : Pat<(vector_extract (v8f16 V128:$Rn), VectorIndexH:$idx), 5642 (f16 (CPYi16 V128:$Rn, VectorIndexH:$idx))>; 5643def : Pat<(vector_extract (v8bf16 V128:$Rn), VectorIndexH:$idx), 5644 (bf16 (CPYi16 V128:$Rn, VectorIndexH:$idx))>; 5645 5646// All concat_vectors operations are canonicalised to act on i64 vectors for 5647// AArch64. In the general case we need an instruction, which had just as well be 5648// INS. 5649class ConcatPat<ValueType DstTy, ValueType SrcTy> 5650 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rd), V64:$Rn)), 5651 (INSvi64lane (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), 1, 5652 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub), 0)>; 5653 5654def : ConcatPat<v2i64, v1i64>; 5655def : ConcatPat<v2f64, v1f64>; 5656def : ConcatPat<v4i32, v2i32>; 5657def : ConcatPat<v4f32, v2f32>; 5658def : ConcatPat<v8i16, v4i16>; 5659def : ConcatPat<v8f16, v4f16>; 5660def : ConcatPat<v8bf16, v4bf16>; 5661def : ConcatPat<v16i8, v8i8>; 5662 5663// If the high lanes are undef, though, we can just ignore them: 5664class ConcatUndefPat<ValueType DstTy, ValueType SrcTy> 5665 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rn), undef)), 5666 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub)>; 5667 5668def : ConcatUndefPat<v2i64, v1i64>; 5669def : ConcatUndefPat<v2f64, v1f64>; 5670def : ConcatUndefPat<v4i32, v2i32>; 5671def : ConcatUndefPat<v4f32, v2f32>; 5672def : ConcatUndefPat<v8i16, v4i16>; 5673def : ConcatUndefPat<v16i8, v8i8>; 5674 5675//---------------------------------------------------------------------------- 5676// AdvSIMD across lanes instructions 5677//---------------------------------------------------------------------------- 5678 5679defm ADDV : SIMDAcrossLanesBHS<0, 0b11011, "addv">; 5680defm SMAXV : SIMDAcrossLanesBHS<0, 0b01010, "smaxv">; 5681defm SMINV : SIMDAcrossLanesBHS<0, 0b11010, "sminv">; 5682defm UMAXV : SIMDAcrossLanesBHS<1, 0b01010, "umaxv">; 5683defm UMINV : SIMDAcrossLanesBHS<1, 0b11010, "uminv">; 5684defm SADDLV : SIMDAcrossLanesHSD<0, 0b00011, "saddlv">; 5685defm UADDLV : SIMDAcrossLanesHSD<1, 0b00011, "uaddlv">; 5686defm FMAXNMV : SIMDFPAcrossLanes<0b01100, 0, "fmaxnmv", int_aarch64_neon_fmaxnmv>; 5687defm FMAXV : SIMDFPAcrossLanes<0b01111, 0, "fmaxv", int_aarch64_neon_fmaxv>; 5688defm FMINNMV : SIMDFPAcrossLanes<0b01100, 1, "fminnmv", int_aarch64_neon_fminnmv>; 5689defm FMINV : SIMDFPAcrossLanes<0b01111, 1, "fminv", int_aarch64_neon_fminv>; 5690 5691// Patterns for uaddv(uaddlp(x)) ==> uaddlv 5692def : Pat<(i32 (vector_extract (v8i16 (insert_subvector undef, 5693 (v4i16 (AArch64uaddv (v4i16 (AArch64uaddlp (v8i8 V64:$op))))), 5694 (i64 0))), (i64 0))), 5695 (EXTRACT_SUBREG (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)), 5696 (UADDLVv4i16v V64:$op), ssub), ssub)>; 5697def : Pat<(i32 (vector_extract (v8i16 (AArch64uaddv (v8i16 (AArch64uaddlp 5698 (v16i8 V128:$op))))), (i64 0))), 5699 (EXTRACT_SUBREG (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), 5700 (UADDLVv16i8v V128:$op), hsub), ssub)>; 5701def : Pat<(v4i32 (AArch64uaddv (v4i32 (AArch64uaddlp (v8i16 V128:$op))))), 5702 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), (UADDLVv8i16v V128:$op), ssub)>; 5703 5704// Patterns for addp(uaddlp(x))) ==> uaddlv 5705def : Pat<(v2i32 (AArch64uaddv (v2i32 (AArch64uaddlp (v4i16 V64:$op))))), 5706 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)), (UADDLVv4i16v V64:$op), ssub)>; 5707def : Pat<(v2i64 (AArch64uaddv (v2i64 (AArch64uaddlp (v4i32 V128:$op))))), 5708 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), (UADDLVv4i32v V128:$op), dsub)>; 5709 5710// Patterns for across-vector intrinsics, that have a node equivalent, that 5711// returns a vector (with only the low lane defined) instead of a scalar. 5712// In effect, opNode is the same as (scalar_to_vector (IntNode)). 5713multiclass SIMDAcrossLanesIntrinsic<string baseOpc, 5714 SDPatternOperator opNode> { 5715// If a lane instruction caught the vector_extract around opNode, we can 5716// directly match the latter to the instruction. 5717def : Pat<(v8i8 (opNode V64:$Rn)), 5718 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)), 5719 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub)>; 5720def : Pat<(v16i8 (opNode V128:$Rn)), 5721 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 5722 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub)>; 5723def : Pat<(v4i16 (opNode V64:$Rn)), 5724 (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)), 5725 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub)>; 5726def : Pat<(v8i16 (opNode V128:$Rn)), 5727 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), 5728 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub)>; 5729def : Pat<(v4i32 (opNode V128:$Rn)), 5730 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), 5731 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), ssub)>; 5732 5733 5734// If none did, fallback to the explicit patterns, consuming the vector_extract. 5735def : Pat<(i32 (vector_extract (insert_subvector undef, (v8i8 (opNode V64:$Rn)), 5736 (i64 0)), (i64 0))), 5737 (EXTRACT_SUBREG (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)), 5738 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), 5739 bsub), ssub)>; 5740def : Pat<(i32 (vector_extract (v16i8 (opNode V128:$Rn)), (i64 0))), 5741 (EXTRACT_SUBREG (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 5742 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), 5743 bsub), ssub)>; 5744def : Pat<(i32 (vector_extract (insert_subvector undef, 5745 (v4i16 (opNode V64:$Rn)), (i64 0)), (i64 0))), 5746 (EXTRACT_SUBREG (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)), 5747 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), 5748 hsub), ssub)>; 5749def : Pat<(i32 (vector_extract (v8i16 (opNode V128:$Rn)), (i64 0))), 5750 (EXTRACT_SUBREG (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), 5751 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), 5752 hsub), ssub)>; 5753def : Pat<(i32 (vector_extract (v4i32 (opNode V128:$Rn)), (i64 0))), 5754 (EXTRACT_SUBREG (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), 5755 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), 5756 ssub), ssub)>; 5757 5758} 5759 5760multiclass SIMDAcrossLanesSignedIntrinsic<string baseOpc, 5761 SDPatternOperator opNode> 5762 : SIMDAcrossLanesIntrinsic<baseOpc, opNode> { 5763// If there is a sign extension after this intrinsic, consume it as smov already 5764// performed it 5765def : Pat<(i32 (sext_inreg (i32 (vector_extract (insert_subvector undef, 5766 (opNode (v8i8 V64:$Rn)), (i64 0)), (i64 0))), i8)), 5767 (i32 (SMOVvi8to32 5768 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 5769 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub), 5770 (i64 0)))>; 5771def : Pat<(i32 (sext_inreg (i32 (vector_extract 5772 (opNode (v16i8 V128:$Rn)), (i64 0))), i8)), 5773 (i32 (SMOVvi8to32 5774 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 5775 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub), 5776 (i64 0)))>; 5777def : Pat<(i32 (sext_inreg (i32 (vector_extract (insert_subvector undef, 5778 (opNode (v4i16 V64:$Rn)), (i64 0)), (i64 0))), i16)), 5779 (i32 (SMOVvi16to32 5780 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 5781 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub), 5782 (i64 0)))>; 5783def : Pat<(i32 (sext_inreg (i32 (vector_extract 5784 (opNode (v8i16 V128:$Rn)), (i64 0))), i16)), 5785 (i32 (SMOVvi16to32 5786 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 5787 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub), 5788 (i64 0)))>; 5789} 5790 5791multiclass SIMDAcrossLanesUnsignedIntrinsic<string baseOpc, 5792 SDPatternOperator opNode> 5793 : SIMDAcrossLanesIntrinsic<baseOpc, opNode> { 5794// If there is a masking operation keeping only what has been actually 5795// generated, consume it. 5796def : Pat<(i32 (and (i32 (vector_extract (insert_subvector undef, 5797 (opNode (v8i8 V64:$Rn)), (i64 0)), (i64 0))), maski8_or_more)), 5798 (i32 (EXTRACT_SUBREG 5799 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 5800 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub), 5801 ssub))>; 5802def : Pat<(i32 (and (i32 (vector_extract (opNode (v16i8 V128:$Rn)), (i64 0))), 5803 maski8_or_more)), 5804 (i32 (EXTRACT_SUBREG 5805 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 5806 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub), 5807 ssub))>; 5808def : Pat<(i32 (and (i32 (vector_extract (insert_subvector undef, 5809 (opNode (v4i16 V64:$Rn)), (i64 0)), (i64 0))), maski16_or_more)), 5810 (i32 (EXTRACT_SUBREG 5811 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 5812 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub), 5813 ssub))>; 5814def : Pat<(i32 (and (i32 (vector_extract (opNode (v8i16 V128:$Rn)), (i64 0))), 5815 maski16_or_more)), 5816 (i32 (EXTRACT_SUBREG 5817 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 5818 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub), 5819 ssub))>; 5820} 5821 5822defm : SIMDAcrossLanesSignedIntrinsic<"ADDV", AArch64saddv>; 5823// vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm 5824def : Pat<(v2i32 (AArch64saddv (v2i32 V64:$Rn))), 5825 (ADDPv2i32 V64:$Rn, V64:$Rn)>; 5826 5827defm : SIMDAcrossLanesUnsignedIntrinsic<"ADDV", AArch64uaddv>; 5828// vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm 5829def : Pat<(v2i32 (AArch64uaddv (v2i32 V64:$Rn))), 5830 (ADDPv2i32 V64:$Rn, V64:$Rn)>; 5831 5832defm : SIMDAcrossLanesSignedIntrinsic<"SMAXV", AArch64smaxv>; 5833def : Pat<(v2i32 (AArch64smaxv (v2i32 V64:$Rn))), 5834 (SMAXPv2i32 V64:$Rn, V64:$Rn)>; 5835 5836defm : SIMDAcrossLanesSignedIntrinsic<"SMINV", AArch64sminv>; 5837def : Pat<(v2i32 (AArch64sminv (v2i32 V64:$Rn))), 5838 (SMINPv2i32 V64:$Rn, V64:$Rn)>; 5839 5840defm : SIMDAcrossLanesUnsignedIntrinsic<"UMAXV", AArch64umaxv>; 5841def : Pat<(v2i32 (AArch64umaxv (v2i32 V64:$Rn))), 5842 (UMAXPv2i32 V64:$Rn, V64:$Rn)>; 5843 5844defm : SIMDAcrossLanesUnsignedIntrinsic<"UMINV", AArch64uminv>; 5845def : Pat<(v2i32 (AArch64uminv (v2i32 V64:$Rn))), 5846 (UMINPv2i32 V64:$Rn, V64:$Rn)>; 5847 5848multiclass SIMDAcrossLanesSignedLongIntrinsic<string baseOpc, Intrinsic intOp> { 5849 def : Pat<(i32 (intOp (v8i8 V64:$Rn))), 5850 (i32 (SMOVvi16to32 5851 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 5852 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub), 5853 (i64 0)))>; 5854def : Pat<(i32 (intOp (v16i8 V128:$Rn))), 5855 (i32 (SMOVvi16to32 5856 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 5857 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub), 5858 (i64 0)))>; 5859 5860def : Pat<(i32 (intOp (v4i16 V64:$Rn))), 5861 (i32 (EXTRACT_SUBREG 5862 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 5863 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub), 5864 ssub))>; 5865def : Pat<(i32 (intOp (v8i16 V128:$Rn))), 5866 (i32 (EXTRACT_SUBREG 5867 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 5868 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub), 5869 ssub))>; 5870 5871def : Pat<(i64 (intOp (v4i32 V128:$Rn))), 5872 (i64 (EXTRACT_SUBREG 5873 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 5874 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub), 5875 dsub))>; 5876} 5877 5878multiclass SIMDAcrossLanesUnsignedLongIntrinsic<string baseOpc, 5879 Intrinsic intOp> { 5880 def : Pat<(i32 (intOp (v8i8 V64:$Rn))), 5881 (i32 (EXTRACT_SUBREG 5882 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 5883 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub), 5884 ssub))>; 5885def : Pat<(i32 (intOp (v16i8 V128:$Rn))), 5886 (i32 (EXTRACT_SUBREG 5887 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 5888 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub), 5889 ssub))>; 5890 5891def : Pat<(i32 (intOp (v4i16 V64:$Rn))), 5892 (i32 (EXTRACT_SUBREG 5893 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 5894 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub), 5895 ssub))>; 5896def : Pat<(i32 (intOp (v8i16 V128:$Rn))), 5897 (i32 (EXTRACT_SUBREG 5898 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 5899 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub), 5900 ssub))>; 5901 5902def : Pat<(i64 (intOp (v4i32 V128:$Rn))), 5903 (i64 (EXTRACT_SUBREG 5904 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 5905 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub), 5906 dsub))>; 5907} 5908 5909defm : SIMDAcrossLanesSignedLongIntrinsic<"SADDLV", int_aarch64_neon_saddlv>; 5910defm : SIMDAcrossLanesUnsignedLongIntrinsic<"UADDLV", int_aarch64_neon_uaddlv>; 5911 5912// The vaddlv_s32 intrinsic gets mapped to SADDLP. 5913def : Pat<(i64 (int_aarch64_neon_saddlv (v2i32 V64:$Rn))), 5914 (i64 (EXTRACT_SUBREG 5915 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 5916 (SADDLPv2i32_v1i64 V64:$Rn), dsub), 5917 dsub))>; 5918// The vaddlv_u32 intrinsic gets mapped to UADDLP. 5919def : Pat<(i64 (int_aarch64_neon_uaddlv (v2i32 V64:$Rn))), 5920 (i64 (EXTRACT_SUBREG 5921 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 5922 (UADDLPv2i32_v1i64 V64:$Rn), dsub), 5923 dsub))>; 5924 5925//------------------------------------------------------------------------------ 5926// AdvSIMD modified immediate instructions 5927//------------------------------------------------------------------------------ 5928 5929// AdvSIMD BIC 5930defm BIC : SIMDModifiedImmVectorShiftTied<1, 0b11, 0b01, "bic", AArch64bici>; 5931// AdvSIMD ORR 5932defm ORR : SIMDModifiedImmVectorShiftTied<0, 0b11, 0b01, "orr", AArch64orri>; 5933 5934def : InstAlias<"bic $Vd.4h, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0)>; 5935def : InstAlias<"bic $Vd.8h, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0)>; 5936def : InstAlias<"bic $Vd.2s, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0)>; 5937def : InstAlias<"bic $Vd.4s, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0)>; 5938 5939def : InstAlias<"bic.4h $Vd, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0)>; 5940def : InstAlias<"bic.8h $Vd, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0)>; 5941def : InstAlias<"bic.2s $Vd, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0)>; 5942def : InstAlias<"bic.4s $Vd, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0)>; 5943 5944def : InstAlias<"orr $Vd.4h, $imm", (ORRv4i16 V64:$Vd, imm0_255:$imm, 0)>; 5945def : InstAlias<"orr $Vd.8h, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0)>; 5946def : InstAlias<"orr $Vd.2s, $imm", (ORRv2i32 V64:$Vd, imm0_255:$imm, 0)>; 5947def : InstAlias<"orr $Vd.4s, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0)>; 5948 5949def : InstAlias<"orr.4h $Vd, $imm", (ORRv4i16 V64:$Vd, imm0_255:$imm, 0)>; 5950def : InstAlias<"orr.8h $Vd, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0)>; 5951def : InstAlias<"orr.2s $Vd, $imm", (ORRv2i32 V64:$Vd, imm0_255:$imm, 0)>; 5952def : InstAlias<"orr.4s $Vd, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0)>; 5953 5954// AdvSIMD FMOV 5955def FMOVv2f64_ns : SIMDModifiedImmVectorNoShift<1, 1, 0, 0b1111, V128, fpimm8, 5956 "fmov", ".2d", 5957 [(set (v2f64 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>; 5958def FMOVv2f32_ns : SIMDModifiedImmVectorNoShift<0, 0, 0, 0b1111, V64, fpimm8, 5959 "fmov", ".2s", 5960 [(set (v2f32 V64:$Rd), (AArch64fmov imm0_255:$imm8))]>; 5961def FMOVv4f32_ns : SIMDModifiedImmVectorNoShift<1, 0, 0, 0b1111, V128, fpimm8, 5962 "fmov", ".4s", 5963 [(set (v4f32 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>; 5964let Predicates = [HasNEON, HasFullFP16] in { 5965def FMOVv4f16_ns : SIMDModifiedImmVectorNoShift<0, 0, 1, 0b1111, V64, fpimm8, 5966 "fmov", ".4h", 5967 [(set (v4f16 V64:$Rd), (AArch64fmov imm0_255:$imm8))]>; 5968def FMOVv8f16_ns : SIMDModifiedImmVectorNoShift<1, 0, 1, 0b1111, V128, fpimm8, 5969 "fmov", ".8h", 5970 [(set (v8f16 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>; 5971} // Predicates = [HasNEON, HasFullFP16] 5972 5973// AdvSIMD MOVI 5974 5975// EDIT byte mask: scalar 5976let isReMaterializable = 1, isAsCheapAsAMove = 1 in 5977def MOVID : SIMDModifiedImmScalarNoShift<0, 1, 0b1110, "movi", 5978 [(set FPR64:$Rd, simdimmtype10:$imm8)]>; 5979// The movi_edit node has the immediate value already encoded, so we use 5980// a plain imm0_255 here. 5981def : Pat<(f64 (AArch64movi_edit imm0_255:$shift)), 5982 (MOVID imm0_255:$shift)>; 5983 5984// EDIT byte mask: 2d 5985 5986// The movi_edit node has the immediate value already encoded, so we use 5987// a plain imm0_255 in the pattern 5988let isReMaterializable = 1, isAsCheapAsAMove = 1 in 5989def MOVIv2d_ns : SIMDModifiedImmVectorNoShift<1, 1, 0, 0b1110, V128, 5990 simdimmtype10, 5991 "movi", ".2d", 5992 [(set (v2i64 V128:$Rd), (AArch64movi_edit imm0_255:$imm8))]>; 5993 5994def : Pat<(v2i64 immAllZerosV), (MOVIv2d_ns (i32 0))>; 5995def : Pat<(v4i32 immAllZerosV), (MOVIv2d_ns (i32 0))>; 5996def : Pat<(v8i16 immAllZerosV), (MOVIv2d_ns (i32 0))>; 5997def : Pat<(v16i8 immAllZerosV), (MOVIv2d_ns (i32 0))>; 5998 5999def : Pat<(v2i64 immAllOnesV), (MOVIv2d_ns (i32 255))>; 6000def : Pat<(v4i32 immAllOnesV), (MOVIv2d_ns (i32 255))>; 6001def : Pat<(v8i16 immAllOnesV), (MOVIv2d_ns (i32 255))>; 6002def : Pat<(v16i8 immAllOnesV), (MOVIv2d_ns (i32 255))>; 6003 6004// Set 64-bit vectors to all 0/1 by extracting from a 128-bit register as the 6005// extract is free and this gives better MachineCSE results. 6006def : Pat<(v1i64 immAllZerosV), (EXTRACT_SUBREG (MOVIv2d_ns (i32 0)), dsub)>; 6007def : Pat<(v2i32 immAllZerosV), (EXTRACT_SUBREG (MOVIv2d_ns (i32 0)), dsub)>; 6008def : Pat<(v4i16 immAllZerosV), (EXTRACT_SUBREG (MOVIv2d_ns (i32 0)), dsub)>; 6009def : Pat<(v8i8 immAllZerosV), (EXTRACT_SUBREG (MOVIv2d_ns (i32 0)), dsub)>; 6010 6011def : Pat<(v1i64 immAllOnesV), (EXTRACT_SUBREG (MOVIv2d_ns (i32 255)), dsub)>; 6012def : Pat<(v2i32 immAllOnesV), (EXTRACT_SUBREG (MOVIv2d_ns (i32 255)), dsub)>; 6013def : Pat<(v4i16 immAllOnesV), (EXTRACT_SUBREG (MOVIv2d_ns (i32 255)), dsub)>; 6014def : Pat<(v8i8 immAllOnesV), (EXTRACT_SUBREG (MOVIv2d_ns (i32 255)), dsub)>; 6015 6016// EDIT per word & halfword: 2s, 4h, 4s, & 8h 6017let isReMaterializable = 1, isAsCheapAsAMove = 1 in 6018defm MOVI : SIMDModifiedImmVectorShift<0, 0b10, 0b00, "movi">; 6019 6020def : InstAlias<"movi $Vd.4h, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>; 6021def : InstAlias<"movi $Vd.8h, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>; 6022def : InstAlias<"movi $Vd.2s, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>; 6023def : InstAlias<"movi $Vd.4s, $imm", (MOVIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>; 6024 6025def : InstAlias<"movi.4h $Vd, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>; 6026def : InstAlias<"movi.8h $Vd, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>; 6027def : InstAlias<"movi.2s $Vd, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>; 6028def : InstAlias<"movi.4s $Vd, $imm", (MOVIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>; 6029 6030def : Pat<(v2i32 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))), 6031 (MOVIv2i32 imm0_255:$imm8, imm:$shift)>; 6032def : Pat<(v4i32 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))), 6033 (MOVIv4i32 imm0_255:$imm8, imm:$shift)>; 6034def : Pat<(v4i16 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))), 6035 (MOVIv4i16 imm0_255:$imm8, imm:$shift)>; 6036def : Pat<(v8i16 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))), 6037 (MOVIv8i16 imm0_255:$imm8, imm:$shift)>; 6038 6039let isReMaterializable = 1, isAsCheapAsAMove = 1 in { 6040// EDIT per word: 2s & 4s with MSL shifter 6041def MOVIv2s_msl : SIMDModifiedImmMoveMSL<0, 0, {1,1,0,?}, V64, "movi", ".2s", 6042 [(set (v2i32 V64:$Rd), 6043 (AArch64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>; 6044def MOVIv4s_msl : SIMDModifiedImmMoveMSL<1, 0, {1,1,0,?}, V128, "movi", ".4s", 6045 [(set (v4i32 V128:$Rd), 6046 (AArch64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>; 6047 6048// Per byte: 8b & 16b 6049def MOVIv8b_ns : SIMDModifiedImmVectorNoShift<0, 0, 0, 0b1110, V64, imm0_255, 6050 "movi", ".8b", 6051 [(set (v8i8 V64:$Rd), (AArch64movi imm0_255:$imm8))]>; 6052 6053def MOVIv16b_ns : SIMDModifiedImmVectorNoShift<1, 0, 0, 0b1110, V128, imm0_255, 6054 "movi", ".16b", 6055 [(set (v16i8 V128:$Rd), (AArch64movi imm0_255:$imm8))]>; 6056} 6057 6058// AdvSIMD MVNI 6059 6060// EDIT per word & halfword: 2s, 4h, 4s, & 8h 6061let isReMaterializable = 1, isAsCheapAsAMove = 1 in 6062defm MVNI : SIMDModifiedImmVectorShift<1, 0b10, 0b00, "mvni">; 6063 6064def : InstAlias<"mvni $Vd.4h, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>; 6065def : InstAlias<"mvni $Vd.8h, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>; 6066def : InstAlias<"mvni $Vd.2s, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>; 6067def : InstAlias<"mvni $Vd.4s, $imm", (MVNIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>; 6068 6069def : InstAlias<"mvni.4h $Vd, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>; 6070def : InstAlias<"mvni.8h $Vd, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>; 6071def : InstAlias<"mvni.2s $Vd, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>; 6072def : InstAlias<"mvni.4s $Vd, $imm", (MVNIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>; 6073 6074def : Pat<(v2i32 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))), 6075 (MVNIv2i32 imm0_255:$imm8, imm:$shift)>; 6076def : Pat<(v4i32 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))), 6077 (MVNIv4i32 imm0_255:$imm8, imm:$shift)>; 6078def : Pat<(v4i16 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))), 6079 (MVNIv4i16 imm0_255:$imm8, imm:$shift)>; 6080def : Pat<(v8i16 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))), 6081 (MVNIv8i16 imm0_255:$imm8, imm:$shift)>; 6082 6083// EDIT per word: 2s & 4s with MSL shifter 6084let isReMaterializable = 1, isAsCheapAsAMove = 1 in { 6085def MVNIv2s_msl : SIMDModifiedImmMoveMSL<0, 1, {1,1,0,?}, V64, "mvni", ".2s", 6086 [(set (v2i32 V64:$Rd), 6087 (AArch64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>; 6088def MVNIv4s_msl : SIMDModifiedImmMoveMSL<1, 1, {1,1,0,?}, V128, "mvni", ".4s", 6089 [(set (v4i32 V128:$Rd), 6090 (AArch64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>; 6091} 6092 6093//---------------------------------------------------------------------------- 6094// AdvSIMD indexed element 6095//---------------------------------------------------------------------------- 6096 6097let hasSideEffects = 0 in { 6098 defm FMLA : SIMDFPIndexedTied<0, 0b0001, "fmla">; 6099 defm FMLS : SIMDFPIndexedTied<0, 0b0101, "fmls">; 6100} 6101 6102// NOTE: Operands are reordered in the FMLA/FMLS PatFrags because the 6103// instruction expects the addend first, while the intrinsic expects it last. 6104 6105// On the other hand, there are quite a few valid combinatorial options due to 6106// the commutativity of multiplication and the fact that (-x) * y = x * (-y). 6107defm : SIMDFPIndexedTiedPatterns<"FMLA", 6108 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)>>; 6109defm : SIMDFPIndexedTiedPatterns<"FMLA", 6110 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)>>; 6111 6112defm : SIMDFPIndexedTiedPatterns<"FMLS", 6113 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >; 6114defm : SIMDFPIndexedTiedPatterns<"FMLS", 6115 TriOpFrag<(fma node:$RHS, (fneg node:$MHS), node:$LHS)> >; 6116defm : SIMDFPIndexedTiedPatterns<"FMLS", 6117 TriOpFrag<(fma (fneg node:$RHS), node:$MHS, node:$LHS)> >; 6118defm : SIMDFPIndexedTiedPatterns<"FMLS", 6119 TriOpFrag<(fma (fneg node:$MHS), node:$RHS, node:$LHS)> >; 6120 6121multiclass FMLSIndexedAfterNegPatterns<SDPatternOperator OpNode> { 6122 // 3 variants for the .2s version: DUPLANE from 128-bit, DUPLANE from 64-bit 6123 // and DUP scalar. 6124 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn), 6125 (AArch64duplane32 (v4f32 (fneg V128:$Rm)), 6126 VectorIndexS:$idx))), 6127 (FMLSv2i32_indexed V64:$Rd, V64:$Rn, V128:$Rm, VectorIndexS:$idx)>; 6128 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn), 6129 (v2f32 (AArch64duplane32 6130 (v4f32 (insert_subvector undef, 6131 (v2f32 (fneg V64:$Rm)), 6132 (i64 0))), 6133 VectorIndexS:$idx)))), 6134 (FMLSv2i32_indexed V64:$Rd, V64:$Rn, 6135 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), 6136 VectorIndexS:$idx)>; 6137 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn), 6138 (AArch64dup (f32 (fneg FPR32Op:$Rm))))), 6139 (FMLSv2i32_indexed V64:$Rd, V64:$Rn, 6140 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>; 6141 6142 // 3 variants for the .4s version: DUPLANE from 128-bit, DUPLANE from 64-bit 6143 // and DUP scalar. 6144 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn), 6145 (AArch64duplane32 (v4f32 (fneg V128:$Rm)), 6146 VectorIndexS:$idx))), 6147 (FMLSv4i32_indexed V128:$Rd, V128:$Rn, V128:$Rm, 6148 VectorIndexS:$idx)>; 6149 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn), 6150 (v4f32 (AArch64duplane32 6151 (v4f32 (insert_subvector undef, 6152 (v2f32 (fneg V64:$Rm)), 6153 (i64 0))), 6154 VectorIndexS:$idx)))), 6155 (FMLSv4i32_indexed V128:$Rd, V128:$Rn, 6156 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), 6157 VectorIndexS:$idx)>; 6158 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn), 6159 (AArch64dup (f32 (fneg FPR32Op:$Rm))))), 6160 (FMLSv4i32_indexed V128:$Rd, V128:$Rn, 6161 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>; 6162 6163 // 2 variants for the .2d version: DUPLANE from 128-bit, and DUP scalar 6164 // (DUPLANE from 64-bit would be trivial). 6165 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn), 6166 (AArch64duplane64 (v2f64 (fneg V128:$Rm)), 6167 VectorIndexD:$idx))), 6168 (FMLSv2i64_indexed 6169 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>; 6170 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn), 6171 (AArch64dup (f64 (fneg FPR64Op:$Rm))))), 6172 (FMLSv2i64_indexed V128:$Rd, V128:$Rn, 6173 (SUBREG_TO_REG (i32 0), FPR64Op:$Rm, dsub), (i64 0))>; 6174 6175 // 2 variants for 32-bit scalar version: extract from .2s or from .4s 6176 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn), 6177 (vector_extract (v4f32 (fneg V128:$Rm)), 6178 VectorIndexS:$idx))), 6179 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn, 6180 V128:$Rm, VectorIndexS:$idx)>; 6181 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn), 6182 (vector_extract (v4f32 (insert_subvector undef, 6183 (v2f32 (fneg V64:$Rm)), 6184 (i64 0))), 6185 VectorIndexS:$idx))), 6186 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn, 6187 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), VectorIndexS:$idx)>; 6188 6189 // 1 variant for 64-bit scalar version: extract from .1d or from .2d 6190 def : Pat<(f64 (OpNode (f64 FPR64:$Rd), (f64 FPR64:$Rn), 6191 (vector_extract (v2f64 (fneg V128:$Rm)), 6192 VectorIndexS:$idx))), 6193 (FMLSv1i64_indexed FPR64:$Rd, FPR64:$Rn, 6194 V128:$Rm, VectorIndexS:$idx)>; 6195} 6196 6197defm : FMLSIndexedAfterNegPatterns< 6198 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >; 6199defm : FMLSIndexedAfterNegPatterns< 6200 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)> >; 6201 6202defm FMULX : SIMDFPIndexed<1, 0b1001, "fmulx", int_aarch64_neon_fmulx>; 6203defm FMUL : SIMDFPIndexed<0, 0b1001, "fmul", fmul>; 6204 6205def : Pat<(v2f32 (fmul V64:$Rn, (AArch64dup (f32 FPR32:$Rm)))), 6206 (FMULv2i32_indexed V64:$Rn, 6207 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub), 6208 (i64 0))>; 6209def : Pat<(v4f32 (fmul V128:$Rn, (AArch64dup (f32 FPR32:$Rm)))), 6210 (FMULv4i32_indexed V128:$Rn, 6211 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub), 6212 (i64 0))>; 6213def : Pat<(v2f64 (fmul V128:$Rn, (AArch64dup (f64 FPR64:$Rm)))), 6214 (FMULv2i64_indexed V128:$Rn, 6215 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rm, dsub), 6216 (i64 0))>; 6217 6218defm SQDMULH : SIMDIndexedHS<0, 0b1100, "sqdmulh", int_aarch64_neon_sqdmulh>; 6219defm SQRDMULH : SIMDIndexedHS<0, 0b1101, "sqrdmulh", int_aarch64_neon_sqrdmulh>; 6220 6221defm SQDMULH : SIMDIndexedHSPatterns<int_aarch64_neon_sqdmulh_lane, 6222 int_aarch64_neon_sqdmulh_laneq>; 6223defm SQRDMULH : SIMDIndexedHSPatterns<int_aarch64_neon_sqrdmulh_lane, 6224 int_aarch64_neon_sqrdmulh_laneq>; 6225 6226// Generated by MachineCombine 6227defm MLA : SIMDVectorIndexedHSTied<1, 0b0000, "mla", null_frag>; 6228defm MLS : SIMDVectorIndexedHSTied<1, 0b0100, "mls", null_frag>; 6229 6230defm MUL : SIMDVectorIndexedHS<0, 0b1000, "mul", mul>; 6231defm SMLAL : SIMDVectorIndexedLongSDTied<0, 0b0010, "smlal", 6232 TriOpFrag<(add node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>; 6233defm SMLSL : SIMDVectorIndexedLongSDTied<0, 0b0110, "smlsl", 6234 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>; 6235defm SMULL : SIMDVectorIndexedLongSD<0, 0b1010, "smull", 6236 int_aarch64_neon_smull>; 6237defm SQDMLAL : SIMDIndexedLongSQDMLXSDTied<0, 0b0011, "sqdmlal", 6238 int_aarch64_neon_sqadd>; 6239defm SQDMLSL : SIMDIndexedLongSQDMLXSDTied<0, 0b0111, "sqdmlsl", 6240 int_aarch64_neon_sqsub>; 6241defm SQRDMLAH : SIMDIndexedSQRDMLxHSDTied<1, 0b1101, "sqrdmlah", 6242 int_aarch64_neon_sqadd>; 6243defm SQRDMLSH : SIMDIndexedSQRDMLxHSDTied<1, 0b1111, "sqrdmlsh", 6244 int_aarch64_neon_sqsub>; 6245defm SQDMULL : SIMDIndexedLongSD<0, 0b1011, "sqdmull", int_aarch64_neon_sqdmull>; 6246defm UMLAL : SIMDVectorIndexedLongSDTied<1, 0b0010, "umlal", 6247 TriOpFrag<(add node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>; 6248defm UMLSL : SIMDVectorIndexedLongSDTied<1, 0b0110, "umlsl", 6249 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>; 6250defm UMULL : SIMDVectorIndexedLongSD<1, 0b1010, "umull", 6251 int_aarch64_neon_umull>; 6252 6253// A scalar sqdmull with the second operand being a vector lane can be 6254// handled directly with the indexed instruction encoding. 6255def : Pat<(int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn), 6256 (vector_extract (v4i32 V128:$Vm), 6257 VectorIndexS:$idx)), 6258 (SQDMULLv1i64_indexed FPR32:$Rn, V128:$Vm, VectorIndexS:$idx)>; 6259 6260//---------------------------------------------------------------------------- 6261// AdvSIMD scalar shift instructions 6262//---------------------------------------------------------------------------- 6263defm FCVTZS : SIMDFPScalarRShift<0, 0b11111, "fcvtzs">; 6264defm FCVTZU : SIMDFPScalarRShift<1, 0b11111, "fcvtzu">; 6265defm SCVTF : SIMDFPScalarRShift<0, 0b11100, "scvtf">; 6266defm UCVTF : SIMDFPScalarRShift<1, 0b11100, "ucvtf">; 6267// Codegen patterns for the above. We don't put these directly on the 6268// instructions because TableGen's type inference can't handle the truth. 6269// Having the same base pattern for fp <--> int totally freaks it out. 6270def : Pat<(int_aarch64_neon_vcvtfp2fxs FPR32:$Rn, vecshiftR32:$imm), 6271 (FCVTZSs FPR32:$Rn, vecshiftR32:$imm)>; 6272def : Pat<(int_aarch64_neon_vcvtfp2fxu FPR32:$Rn, vecshiftR32:$imm), 6273 (FCVTZUs FPR32:$Rn, vecshiftR32:$imm)>; 6274def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxs (f64 FPR64:$Rn), vecshiftR64:$imm)), 6275 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>; 6276def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxu (f64 FPR64:$Rn), vecshiftR64:$imm)), 6277 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>; 6278def : Pat<(v1i64 (int_aarch64_neon_vcvtfp2fxs (v1f64 FPR64:$Rn), 6279 vecshiftR64:$imm)), 6280 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>; 6281def : Pat<(v1i64 (int_aarch64_neon_vcvtfp2fxu (v1f64 FPR64:$Rn), 6282 vecshiftR64:$imm)), 6283 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>; 6284def : Pat<(int_aarch64_neon_vcvtfxu2fp FPR32:$Rn, vecshiftR32:$imm), 6285 (UCVTFs FPR32:$Rn, vecshiftR32:$imm)>; 6286def : Pat<(f64 (int_aarch64_neon_vcvtfxu2fp (i64 FPR64:$Rn), vecshiftR64:$imm)), 6287 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>; 6288def : Pat<(v1f64 (int_aarch64_neon_vcvtfxs2fp (v1i64 FPR64:$Rn), 6289 vecshiftR64:$imm)), 6290 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>; 6291def : Pat<(f64 (int_aarch64_neon_vcvtfxs2fp (i64 FPR64:$Rn), vecshiftR64:$imm)), 6292 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>; 6293def : Pat<(v1f64 (int_aarch64_neon_vcvtfxu2fp (v1i64 FPR64:$Rn), 6294 vecshiftR64:$imm)), 6295 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>; 6296def : Pat<(int_aarch64_neon_vcvtfxs2fp FPR32:$Rn, vecshiftR32:$imm), 6297 (SCVTFs FPR32:$Rn, vecshiftR32:$imm)>; 6298 6299// Patterns for FP16 Instrinsics - requires reg copy to/from as i16s not supported. 6300 6301def : Pat<(f16 (int_aarch64_neon_vcvtfxs2fp (i32 (sext_inreg FPR32:$Rn, i16)), vecshiftR16:$imm)), 6302 (SCVTFh (EXTRACT_SUBREG FPR32:$Rn, hsub), vecshiftR16:$imm)>; 6303def : Pat<(f16 (int_aarch64_neon_vcvtfxs2fp (i32 FPR32:$Rn), vecshiftR16:$imm)), 6304 (SCVTFh (EXTRACT_SUBREG FPR32:$Rn, hsub), vecshiftR16:$imm)>; 6305def : Pat<(f16 (int_aarch64_neon_vcvtfxs2fp (i64 FPR64:$Rn), vecshiftR16:$imm)), 6306 (SCVTFh (EXTRACT_SUBREG FPR64:$Rn, hsub), vecshiftR16:$imm)>; 6307def : Pat<(f16 (int_aarch64_neon_vcvtfxu2fp 6308 (and FPR32:$Rn, (i32 65535)), 6309 vecshiftR16:$imm)), 6310 (UCVTFh (EXTRACT_SUBREG FPR32:$Rn, hsub), vecshiftR16:$imm)>; 6311def : Pat<(f16 (int_aarch64_neon_vcvtfxu2fp FPR32:$Rn, vecshiftR16:$imm)), 6312 (UCVTFh (EXTRACT_SUBREG FPR32:$Rn, hsub), vecshiftR16:$imm)>; 6313def : Pat<(f16 (int_aarch64_neon_vcvtfxu2fp (i64 FPR64:$Rn), vecshiftR16:$imm)), 6314 (UCVTFh (EXTRACT_SUBREG FPR64:$Rn, hsub), vecshiftR16:$imm)>; 6315def : Pat<(i32 (int_aarch64_neon_vcvtfp2fxs (f16 FPR16:$Rn), vecshiftR32:$imm)), 6316 (i32 (INSERT_SUBREG 6317 (i32 (IMPLICIT_DEF)), 6318 (FCVTZSh FPR16:$Rn, vecshiftR32:$imm), 6319 hsub))>; 6320def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxs (f16 FPR16:$Rn), vecshiftR64:$imm)), 6321 (i64 (INSERT_SUBREG 6322 (i64 (IMPLICIT_DEF)), 6323 (FCVTZSh FPR16:$Rn, vecshiftR64:$imm), 6324 hsub))>; 6325def : Pat<(i32 (int_aarch64_neon_vcvtfp2fxu (f16 FPR16:$Rn), vecshiftR32:$imm)), 6326 (i32 (INSERT_SUBREG 6327 (i32 (IMPLICIT_DEF)), 6328 (FCVTZUh FPR16:$Rn, vecshiftR32:$imm), 6329 hsub))>; 6330def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxu (f16 FPR16:$Rn), vecshiftR64:$imm)), 6331 (i64 (INSERT_SUBREG 6332 (i64 (IMPLICIT_DEF)), 6333 (FCVTZUh FPR16:$Rn, vecshiftR64:$imm), 6334 hsub))>; 6335def : Pat<(i32 (int_aarch64_neon_facge (f16 FPR16:$Rn), (f16 FPR16:$Rm))), 6336 (i32 (INSERT_SUBREG 6337 (i32 (IMPLICIT_DEF)), 6338 (FACGE16 FPR16:$Rn, FPR16:$Rm), 6339 hsub))>; 6340def : Pat<(i32 (int_aarch64_neon_facgt (f16 FPR16:$Rn), (f16 FPR16:$Rm))), 6341 (i32 (INSERT_SUBREG 6342 (i32 (IMPLICIT_DEF)), 6343 (FACGT16 FPR16:$Rn, FPR16:$Rm), 6344 hsub))>; 6345 6346defm SHL : SIMDScalarLShiftD< 0, 0b01010, "shl", AArch64vshl>; 6347defm SLI : SIMDScalarLShiftDTied<1, 0b01010, "sli">; 6348defm SQRSHRN : SIMDScalarRShiftBHS< 0, 0b10011, "sqrshrn", 6349 int_aarch64_neon_sqrshrn>; 6350defm SQRSHRUN : SIMDScalarRShiftBHS< 1, 0b10001, "sqrshrun", 6351 int_aarch64_neon_sqrshrun>; 6352defm SQSHLU : SIMDScalarLShiftBHSD<1, 0b01100, "sqshlu", AArch64sqshlui>; 6353defm SQSHL : SIMDScalarLShiftBHSD<0, 0b01110, "sqshl", AArch64sqshli>; 6354defm SQSHRN : SIMDScalarRShiftBHS< 0, 0b10010, "sqshrn", 6355 int_aarch64_neon_sqshrn>; 6356defm SQSHRUN : SIMDScalarRShiftBHS< 1, 0b10000, "sqshrun", 6357 int_aarch64_neon_sqshrun>; 6358defm SRI : SIMDScalarRShiftDTied< 1, 0b01000, "sri">; 6359defm SRSHR : SIMDScalarRShiftD< 0, 0b00100, "srshr", AArch64srshri>; 6360defm SRSRA : SIMDScalarRShiftDTied< 0, 0b00110, "srsra", 6361 TriOpFrag<(add node:$LHS, 6362 (AArch64srshri node:$MHS, node:$RHS))>>; 6363defm SSHR : SIMDScalarRShiftD< 0, 0b00000, "sshr", AArch64vashr>; 6364defm SSRA : SIMDScalarRShiftDTied< 0, 0b00010, "ssra", 6365 TriOpFrag<(add node:$LHS, 6366 (AArch64vashr node:$MHS, node:$RHS))>>; 6367defm UQRSHRN : SIMDScalarRShiftBHS< 1, 0b10011, "uqrshrn", 6368 int_aarch64_neon_uqrshrn>; 6369defm UQSHL : SIMDScalarLShiftBHSD<1, 0b01110, "uqshl", AArch64uqshli>; 6370defm UQSHRN : SIMDScalarRShiftBHS< 1, 0b10010, "uqshrn", 6371 int_aarch64_neon_uqshrn>; 6372defm URSHR : SIMDScalarRShiftD< 1, 0b00100, "urshr", AArch64urshri>; 6373defm URSRA : SIMDScalarRShiftDTied< 1, 0b00110, "ursra", 6374 TriOpFrag<(add node:$LHS, 6375 (AArch64urshri node:$MHS, node:$RHS))>>; 6376defm USHR : SIMDScalarRShiftD< 1, 0b00000, "ushr", AArch64vlshr>; 6377defm USRA : SIMDScalarRShiftDTied< 1, 0b00010, "usra", 6378 TriOpFrag<(add node:$LHS, 6379 (AArch64vlshr node:$MHS, node:$RHS))>>; 6380 6381//---------------------------------------------------------------------------- 6382// AdvSIMD vector shift instructions 6383//---------------------------------------------------------------------------- 6384defm FCVTZS:SIMDVectorRShiftSD<0, 0b11111, "fcvtzs", int_aarch64_neon_vcvtfp2fxs>; 6385defm FCVTZU:SIMDVectorRShiftSD<1, 0b11111, "fcvtzu", int_aarch64_neon_vcvtfp2fxu>; 6386defm SCVTF: SIMDVectorRShiftToFP<0, 0b11100, "scvtf", 6387 int_aarch64_neon_vcvtfxs2fp>; 6388defm RSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10001, "rshrn", 6389 int_aarch64_neon_rshrn>; 6390defm SHL : SIMDVectorLShiftBHSD<0, 0b01010, "shl", AArch64vshl>; 6391defm SHRN : SIMDVectorRShiftNarrowBHS<0, 0b10000, "shrn", 6392 BinOpFrag<(trunc (AArch64vashr node:$LHS, node:$RHS))>>; 6393defm SLI : SIMDVectorLShiftBHSDTied<1, 0b01010, "sli", AArch64vsli>; 6394def : Pat<(v1i64 (AArch64vsli (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn), 6395 (i32 vecshiftL64:$imm))), 6396 (SLId FPR64:$Rd, FPR64:$Rn, vecshiftL64:$imm)>; 6397defm SQRSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10011, "sqrshrn", 6398 int_aarch64_neon_sqrshrn>; 6399defm SQRSHRUN: SIMDVectorRShiftNarrowBHS<1, 0b10001, "sqrshrun", 6400 int_aarch64_neon_sqrshrun>; 6401defm SQSHLU : SIMDVectorLShiftBHSD<1, 0b01100, "sqshlu", AArch64sqshlui>; 6402defm SQSHL : SIMDVectorLShiftBHSD<0, 0b01110, "sqshl", AArch64sqshli>; 6403defm SQSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10010, "sqshrn", 6404 int_aarch64_neon_sqshrn>; 6405defm SQSHRUN : SIMDVectorRShiftNarrowBHS<1, 0b10000, "sqshrun", 6406 int_aarch64_neon_sqshrun>; 6407defm SRI : SIMDVectorRShiftBHSDTied<1, 0b01000, "sri", AArch64vsri>; 6408def : Pat<(v1i64 (AArch64vsri (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn), 6409 (i32 vecshiftR64:$imm))), 6410 (SRId FPR64:$Rd, FPR64:$Rn, vecshiftR64:$imm)>; 6411defm SRSHR : SIMDVectorRShiftBHSD<0, 0b00100, "srshr", AArch64srshri>; 6412defm SRSRA : SIMDVectorRShiftBHSDTied<0, 0b00110, "srsra", 6413 TriOpFrag<(add node:$LHS, 6414 (AArch64srshri node:$MHS, node:$RHS))> >; 6415defm SSHLL : SIMDVectorLShiftLongBHSD<0, 0b10100, "sshll", 6416 BinOpFrag<(AArch64vshl (sext node:$LHS), node:$RHS)>>; 6417 6418defm SSHR : SIMDVectorRShiftBHSD<0, 0b00000, "sshr", AArch64vashr>; 6419defm SSRA : SIMDVectorRShiftBHSDTied<0, 0b00010, "ssra", 6420 TriOpFrag<(add node:$LHS, (AArch64vashr node:$MHS, node:$RHS))>>; 6421defm UCVTF : SIMDVectorRShiftToFP<1, 0b11100, "ucvtf", 6422 int_aarch64_neon_vcvtfxu2fp>; 6423defm UQRSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10011, "uqrshrn", 6424 int_aarch64_neon_uqrshrn>; 6425defm UQSHL : SIMDVectorLShiftBHSD<1, 0b01110, "uqshl", AArch64uqshli>; 6426defm UQSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10010, "uqshrn", 6427 int_aarch64_neon_uqshrn>; 6428defm URSHR : SIMDVectorRShiftBHSD<1, 0b00100, "urshr", AArch64urshri>; 6429defm URSRA : SIMDVectorRShiftBHSDTied<1, 0b00110, "ursra", 6430 TriOpFrag<(add node:$LHS, 6431 (AArch64urshri node:$MHS, node:$RHS))> >; 6432defm USHLL : SIMDVectorLShiftLongBHSD<1, 0b10100, "ushll", 6433 BinOpFrag<(AArch64vshl (zext node:$LHS), node:$RHS)>>; 6434defm USHR : SIMDVectorRShiftBHSD<1, 0b00000, "ushr", AArch64vlshr>; 6435defm USRA : SIMDVectorRShiftBHSDTied<1, 0b00010, "usra", 6436 TriOpFrag<(add node:$LHS, (AArch64vlshr node:$MHS, node:$RHS))> >; 6437 6438// SHRN patterns for when a logical right shift was used instead of arithmetic 6439// (the immediate guarantees no sign bits actually end up in the result so it 6440// doesn't matter). 6441def : Pat<(v8i8 (trunc (AArch64vlshr (v8i16 V128:$Rn), vecshiftR16Narrow:$imm))), 6442 (SHRNv8i8_shift V128:$Rn, vecshiftR16Narrow:$imm)>; 6443def : Pat<(v4i16 (trunc (AArch64vlshr (v4i32 V128:$Rn), vecshiftR32Narrow:$imm))), 6444 (SHRNv4i16_shift V128:$Rn, vecshiftR32Narrow:$imm)>; 6445def : Pat<(v2i32 (trunc (AArch64vlshr (v2i64 V128:$Rn), vecshiftR64Narrow:$imm))), 6446 (SHRNv2i32_shift V128:$Rn, vecshiftR64Narrow:$imm)>; 6447 6448def : Pat<(v16i8 (concat_vectors (v8i8 V64:$Rd), 6449 (trunc (AArch64vlshr (v8i16 V128:$Rn), 6450 vecshiftR16Narrow:$imm)))), 6451 (SHRNv16i8_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), 6452 V128:$Rn, vecshiftR16Narrow:$imm)>; 6453def : Pat<(v8i16 (concat_vectors (v4i16 V64:$Rd), 6454 (trunc (AArch64vlshr (v4i32 V128:$Rn), 6455 vecshiftR32Narrow:$imm)))), 6456 (SHRNv8i16_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), 6457 V128:$Rn, vecshiftR32Narrow:$imm)>; 6458def : Pat<(v4i32 (concat_vectors (v2i32 V64:$Rd), 6459 (trunc (AArch64vlshr (v2i64 V128:$Rn), 6460 vecshiftR64Narrow:$imm)))), 6461 (SHRNv4i32_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), 6462 V128:$Rn, vecshiftR32Narrow:$imm)>; 6463 6464// Vector sign and zero extensions are implemented with SSHLL and USSHLL. 6465// Anyexts are implemented as zexts. 6466def : Pat<(v8i16 (sext (v8i8 V64:$Rn))), (SSHLLv8i8_shift V64:$Rn, (i32 0))>; 6467def : Pat<(v8i16 (zext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>; 6468def : Pat<(v8i16 (anyext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>; 6469def : Pat<(v4i32 (sext (v4i16 V64:$Rn))), (SSHLLv4i16_shift V64:$Rn, (i32 0))>; 6470def : Pat<(v4i32 (zext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>; 6471def : Pat<(v4i32 (anyext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>; 6472def : Pat<(v2i64 (sext (v2i32 V64:$Rn))), (SSHLLv2i32_shift V64:$Rn, (i32 0))>; 6473def : Pat<(v2i64 (zext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>; 6474def : Pat<(v2i64 (anyext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>; 6475// Also match an extend from the upper half of a 128 bit source register. 6476def : Pat<(v8i16 (anyext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))), 6477 (USHLLv16i8_shift V128:$Rn, (i32 0))>; 6478def : Pat<(v8i16 (zext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))), 6479 (USHLLv16i8_shift V128:$Rn, (i32 0))>; 6480def : Pat<(v8i16 (sext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))), 6481 (SSHLLv16i8_shift V128:$Rn, (i32 0))>; 6482def : Pat<(v4i32 (anyext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))), 6483 (USHLLv8i16_shift V128:$Rn, (i32 0))>; 6484def : Pat<(v4i32 (zext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))), 6485 (USHLLv8i16_shift V128:$Rn, (i32 0))>; 6486def : Pat<(v4i32 (sext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))), 6487 (SSHLLv8i16_shift V128:$Rn, (i32 0))>; 6488def : Pat<(v2i64 (anyext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))), 6489 (USHLLv4i32_shift V128:$Rn, (i32 0))>; 6490def : Pat<(v2i64 (zext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))), 6491 (USHLLv4i32_shift V128:$Rn, (i32 0))>; 6492def : Pat<(v2i64 (sext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))), 6493 (SSHLLv4i32_shift V128:$Rn, (i32 0))>; 6494 6495// Vector shift sxtl aliases 6496def : InstAlias<"sxtl.8h $dst, $src1", 6497 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>; 6498def : InstAlias<"sxtl $dst.8h, $src1.8b", 6499 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>; 6500def : InstAlias<"sxtl.4s $dst, $src1", 6501 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>; 6502def : InstAlias<"sxtl $dst.4s, $src1.4h", 6503 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>; 6504def : InstAlias<"sxtl.2d $dst, $src1", 6505 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>; 6506def : InstAlias<"sxtl $dst.2d, $src1.2s", 6507 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>; 6508 6509// Vector shift sxtl2 aliases 6510def : InstAlias<"sxtl2.8h $dst, $src1", 6511 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>; 6512def : InstAlias<"sxtl2 $dst.8h, $src1.16b", 6513 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>; 6514def : InstAlias<"sxtl2.4s $dst, $src1", 6515 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>; 6516def : InstAlias<"sxtl2 $dst.4s, $src1.8h", 6517 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>; 6518def : InstAlias<"sxtl2.2d $dst, $src1", 6519 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>; 6520def : InstAlias<"sxtl2 $dst.2d, $src1.4s", 6521 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>; 6522 6523// Vector shift uxtl aliases 6524def : InstAlias<"uxtl.8h $dst, $src1", 6525 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>; 6526def : InstAlias<"uxtl $dst.8h, $src1.8b", 6527 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>; 6528def : InstAlias<"uxtl.4s $dst, $src1", 6529 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>; 6530def : InstAlias<"uxtl $dst.4s, $src1.4h", 6531 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>; 6532def : InstAlias<"uxtl.2d $dst, $src1", 6533 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>; 6534def : InstAlias<"uxtl $dst.2d, $src1.2s", 6535 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>; 6536 6537// Vector shift uxtl2 aliases 6538def : InstAlias<"uxtl2.8h $dst, $src1", 6539 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>; 6540def : InstAlias<"uxtl2 $dst.8h, $src1.16b", 6541 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>; 6542def : InstAlias<"uxtl2.4s $dst, $src1", 6543 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>; 6544def : InstAlias<"uxtl2 $dst.4s, $src1.8h", 6545 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>; 6546def : InstAlias<"uxtl2.2d $dst, $src1", 6547 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>; 6548def : InstAlias<"uxtl2 $dst.2d, $src1.4s", 6549 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>; 6550 6551// If an integer is about to be converted to a floating point value, 6552// just load it on the floating point unit. 6553// These patterns are more complex because floating point loads do not 6554// support sign extension. 6555// The sign extension has to be explicitly added and is only supported for 6556// one step: byte-to-half, half-to-word, word-to-doubleword. 6557// SCVTF GPR -> FPR is 9 cycles. 6558// SCVTF FPR -> FPR is 4 cyclces. 6559// (sign extension with lengthen) SXTL FPR -> FPR is 2 cycles. 6560// Therefore, we can do 2 sign extensions and one SCVTF FPR -> FPR 6561// and still being faster. 6562// However, this is not good for code size. 6563// 8-bits -> float. 2 sizes step-up. 6564class SExtLoadi8CVTf32Pat<dag addrmode, dag INST> 6565 : Pat<(f32 (sint_to_fp (i32 (sextloadi8 addrmode)))), 6566 (SCVTFv1i32 (f32 (EXTRACT_SUBREG 6567 (SSHLLv4i16_shift 6568 (f64 6569 (EXTRACT_SUBREG 6570 (SSHLLv8i8_shift 6571 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), 6572 INST, 6573 bsub), 6574 0), 6575 dsub)), 6576 0), 6577 ssub)))>, 6578 Requires<[NotForCodeSize, UseAlternateSExtLoadCVTF32]>; 6579 6580def : SExtLoadi8CVTf32Pat<(ro8.Wpat GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$ext), 6581 (LDRBroW GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$ext)>; 6582def : SExtLoadi8CVTf32Pat<(ro8.Xpat GPR64sp:$Rn, GPR64:$Rm, ro8.Xext:$ext), 6583 (LDRBroX GPR64sp:$Rn, GPR64:$Rm, ro8.Xext:$ext)>; 6584def : SExtLoadi8CVTf32Pat<(am_indexed8 GPR64sp:$Rn, uimm12s1:$offset), 6585 (LDRBui GPR64sp:$Rn, uimm12s1:$offset)>; 6586def : SExtLoadi8CVTf32Pat<(am_unscaled8 GPR64sp:$Rn, simm9:$offset), 6587 (LDURBi GPR64sp:$Rn, simm9:$offset)>; 6588 6589// 16-bits -> float. 1 size step-up. 6590class SExtLoadi16CVTf32Pat<dag addrmode, dag INST> 6591 : Pat<(f32 (sint_to_fp (i32 (sextloadi16 addrmode)))), 6592 (SCVTFv1i32 (f32 (EXTRACT_SUBREG 6593 (SSHLLv4i16_shift 6594 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), 6595 INST, 6596 hsub), 6597 0), 6598 ssub)))>, Requires<[NotForCodeSize]>; 6599 6600def : SExtLoadi16CVTf32Pat<(ro16.Wpat GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext), 6601 (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext)>; 6602def : SExtLoadi16CVTf32Pat<(ro16.Xpat GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext), 6603 (LDRHroX GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext)>; 6604def : SExtLoadi16CVTf32Pat<(am_indexed16 GPR64sp:$Rn, uimm12s2:$offset), 6605 (LDRHui GPR64sp:$Rn, uimm12s2:$offset)>; 6606def : SExtLoadi16CVTf32Pat<(am_unscaled16 GPR64sp:$Rn, simm9:$offset), 6607 (LDURHi GPR64sp:$Rn, simm9:$offset)>; 6608 6609// 32-bits to 32-bits are handled in target specific dag combine: 6610// performIntToFpCombine. 6611// 64-bits integer to 32-bits floating point, not possible with 6612// SCVTF on floating point registers (both source and destination 6613// must have the same size). 6614 6615// Here are the patterns for 8, 16, 32, and 64-bits to double. 6616// 8-bits -> double. 3 size step-up: give up. 6617// 16-bits -> double. 2 size step. 6618class SExtLoadi16CVTf64Pat<dag addrmode, dag INST> 6619 : Pat <(f64 (sint_to_fp (i32 (sextloadi16 addrmode)))), 6620 (SCVTFv1i64 (f64 (EXTRACT_SUBREG 6621 (SSHLLv2i32_shift 6622 (f64 6623 (EXTRACT_SUBREG 6624 (SSHLLv4i16_shift 6625 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), 6626 INST, 6627 hsub), 6628 0), 6629 dsub)), 6630 0), 6631 dsub)))>, 6632 Requires<[NotForCodeSize, UseAlternateSExtLoadCVTF32]>; 6633 6634def : SExtLoadi16CVTf64Pat<(ro16.Wpat GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext), 6635 (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext)>; 6636def : SExtLoadi16CVTf64Pat<(ro16.Xpat GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext), 6637 (LDRHroX GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext)>; 6638def : SExtLoadi16CVTf64Pat<(am_indexed16 GPR64sp:$Rn, uimm12s2:$offset), 6639 (LDRHui GPR64sp:$Rn, uimm12s2:$offset)>; 6640def : SExtLoadi16CVTf64Pat<(am_unscaled16 GPR64sp:$Rn, simm9:$offset), 6641 (LDURHi GPR64sp:$Rn, simm9:$offset)>; 6642// 32-bits -> double. 1 size step-up. 6643class SExtLoadi32CVTf64Pat<dag addrmode, dag INST> 6644 : Pat <(f64 (sint_to_fp (i32 (load addrmode)))), 6645 (SCVTFv1i64 (f64 (EXTRACT_SUBREG 6646 (SSHLLv2i32_shift 6647 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), 6648 INST, 6649 ssub), 6650 0), 6651 dsub)))>, Requires<[NotForCodeSize]>; 6652 6653def : SExtLoadi32CVTf64Pat<(ro32.Wpat GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$ext), 6654 (LDRSroW GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$ext)>; 6655def : SExtLoadi32CVTf64Pat<(ro32.Xpat GPR64sp:$Rn, GPR64:$Rm, ro32.Xext:$ext), 6656 (LDRSroX GPR64sp:$Rn, GPR64:$Rm, ro32.Xext:$ext)>; 6657def : SExtLoadi32CVTf64Pat<(am_indexed32 GPR64sp:$Rn, uimm12s4:$offset), 6658 (LDRSui GPR64sp:$Rn, uimm12s4:$offset)>; 6659def : SExtLoadi32CVTf64Pat<(am_unscaled32 GPR64sp:$Rn, simm9:$offset), 6660 (LDURSi GPR64sp:$Rn, simm9:$offset)>; 6661 6662// 64-bits -> double are handled in target specific dag combine: 6663// performIntToFpCombine. 6664 6665 6666//---------------------------------------------------------------------------- 6667// AdvSIMD Load-Store Structure 6668//---------------------------------------------------------------------------- 6669defm LD1 : SIMDLd1Multiple<"ld1">; 6670defm LD2 : SIMDLd2Multiple<"ld2">; 6671defm LD3 : SIMDLd3Multiple<"ld3">; 6672defm LD4 : SIMDLd4Multiple<"ld4">; 6673 6674defm ST1 : SIMDSt1Multiple<"st1">; 6675defm ST2 : SIMDSt2Multiple<"st2">; 6676defm ST3 : SIMDSt3Multiple<"st3">; 6677defm ST4 : SIMDSt4Multiple<"st4">; 6678 6679class Ld1Pat<ValueType ty, Instruction INST> 6680 : Pat<(ty (load GPR64sp:$Rn)), (INST GPR64sp:$Rn)>; 6681 6682def : Ld1Pat<v16i8, LD1Onev16b>; 6683def : Ld1Pat<v8i16, LD1Onev8h>; 6684def : Ld1Pat<v4i32, LD1Onev4s>; 6685def : Ld1Pat<v2i64, LD1Onev2d>; 6686def : Ld1Pat<v8i8, LD1Onev8b>; 6687def : Ld1Pat<v4i16, LD1Onev4h>; 6688def : Ld1Pat<v2i32, LD1Onev2s>; 6689def : Ld1Pat<v1i64, LD1Onev1d>; 6690 6691class St1Pat<ValueType ty, Instruction INST> 6692 : Pat<(store ty:$Vt, GPR64sp:$Rn), 6693 (INST ty:$Vt, GPR64sp:$Rn)>; 6694 6695def : St1Pat<v16i8, ST1Onev16b>; 6696def : St1Pat<v8i16, ST1Onev8h>; 6697def : St1Pat<v4i32, ST1Onev4s>; 6698def : St1Pat<v2i64, ST1Onev2d>; 6699def : St1Pat<v8i8, ST1Onev8b>; 6700def : St1Pat<v4i16, ST1Onev4h>; 6701def : St1Pat<v2i32, ST1Onev2s>; 6702def : St1Pat<v1i64, ST1Onev1d>; 6703 6704//--- 6705// Single-element 6706//--- 6707 6708defm LD1R : SIMDLdR<0, 0b110, 0, "ld1r", "One", 1, 2, 4, 8>; 6709defm LD2R : SIMDLdR<1, 0b110, 0, "ld2r", "Two", 2, 4, 8, 16>; 6710defm LD3R : SIMDLdR<0, 0b111, 0, "ld3r", "Three", 3, 6, 12, 24>; 6711defm LD4R : SIMDLdR<1, 0b111, 0, "ld4r", "Four", 4, 8, 16, 32>; 6712let mayLoad = 1, hasSideEffects = 0 in { 6713defm LD1 : SIMDLdSingleBTied<0, 0b000, "ld1", VecListOneb, GPR64pi1>; 6714defm LD1 : SIMDLdSingleHTied<0, 0b010, 0, "ld1", VecListOneh, GPR64pi2>; 6715defm LD1 : SIMDLdSingleSTied<0, 0b100, 0b00, "ld1", VecListOnes, GPR64pi4>; 6716defm LD1 : SIMDLdSingleDTied<0, 0b100, 0b01, "ld1", VecListOned, GPR64pi8>; 6717defm LD2 : SIMDLdSingleBTied<1, 0b000, "ld2", VecListTwob, GPR64pi2>; 6718defm LD2 : SIMDLdSingleHTied<1, 0b010, 0, "ld2", VecListTwoh, GPR64pi4>; 6719defm LD2 : SIMDLdSingleSTied<1, 0b100, 0b00, "ld2", VecListTwos, GPR64pi8>; 6720defm LD2 : SIMDLdSingleDTied<1, 0b100, 0b01, "ld2", VecListTwod, GPR64pi16>; 6721defm LD3 : SIMDLdSingleBTied<0, 0b001, "ld3", VecListThreeb, GPR64pi3>; 6722defm LD3 : SIMDLdSingleHTied<0, 0b011, 0, "ld3", VecListThreeh, GPR64pi6>; 6723defm LD3 : SIMDLdSingleSTied<0, 0b101, 0b00, "ld3", VecListThrees, GPR64pi12>; 6724defm LD3 : SIMDLdSingleDTied<0, 0b101, 0b01, "ld3", VecListThreed, GPR64pi24>; 6725defm LD4 : SIMDLdSingleBTied<1, 0b001, "ld4", VecListFourb, GPR64pi4>; 6726defm LD4 : SIMDLdSingleHTied<1, 0b011, 0, "ld4", VecListFourh, GPR64pi8>; 6727defm LD4 : SIMDLdSingleSTied<1, 0b101, 0b00, "ld4", VecListFours, GPR64pi16>; 6728defm LD4 : SIMDLdSingleDTied<1, 0b101, 0b01, "ld4", VecListFourd, GPR64pi32>; 6729} 6730 6731def : Pat<(v8i8 (AArch64dup (i32 (extloadi8 GPR64sp:$Rn)))), 6732 (LD1Rv8b GPR64sp:$Rn)>; 6733def : Pat<(v16i8 (AArch64dup (i32 (extloadi8 GPR64sp:$Rn)))), 6734 (LD1Rv16b GPR64sp:$Rn)>; 6735def : Pat<(v4i16 (AArch64dup (i32 (extloadi16 GPR64sp:$Rn)))), 6736 (LD1Rv4h GPR64sp:$Rn)>; 6737def : Pat<(v8i16 (AArch64dup (i32 (extloadi16 GPR64sp:$Rn)))), 6738 (LD1Rv8h GPR64sp:$Rn)>; 6739def : Pat<(v2i32 (AArch64dup (i32 (load GPR64sp:$Rn)))), 6740 (LD1Rv2s GPR64sp:$Rn)>; 6741def : Pat<(v4i32 (AArch64dup (i32 (load GPR64sp:$Rn)))), 6742 (LD1Rv4s GPR64sp:$Rn)>; 6743def : Pat<(v2i64 (AArch64dup (i64 (load GPR64sp:$Rn)))), 6744 (LD1Rv2d GPR64sp:$Rn)>; 6745def : Pat<(v1i64 (AArch64dup (i64 (load GPR64sp:$Rn)))), 6746 (LD1Rv1d GPR64sp:$Rn)>; 6747// Grab the floating point version too 6748def : Pat<(v2f32 (AArch64dup (f32 (load GPR64sp:$Rn)))), 6749 (LD1Rv2s GPR64sp:$Rn)>; 6750def : Pat<(v4f32 (AArch64dup (f32 (load GPR64sp:$Rn)))), 6751 (LD1Rv4s GPR64sp:$Rn)>; 6752def : Pat<(v2f64 (AArch64dup (f64 (load GPR64sp:$Rn)))), 6753 (LD1Rv2d GPR64sp:$Rn)>; 6754def : Pat<(v1f64 (AArch64dup (f64 (load GPR64sp:$Rn)))), 6755 (LD1Rv1d GPR64sp:$Rn)>; 6756def : Pat<(v4f16 (AArch64dup (f16 (load GPR64sp:$Rn)))), 6757 (LD1Rv4h GPR64sp:$Rn)>; 6758def : Pat<(v8f16 (AArch64dup (f16 (load GPR64sp:$Rn)))), 6759 (LD1Rv8h GPR64sp:$Rn)>; 6760def : Pat<(v4bf16 (AArch64dup (bf16 (load GPR64sp:$Rn)))), 6761 (LD1Rv4h GPR64sp:$Rn)>; 6762def : Pat<(v8bf16 (AArch64dup (bf16 (load GPR64sp:$Rn)))), 6763 (LD1Rv8h GPR64sp:$Rn)>; 6764 6765class Ld1Lane128Pat<SDPatternOperator scalar_load, Operand VecIndex, 6766 ValueType VTy, ValueType STy, Instruction LD1> 6767 : Pat<(vector_insert (VTy VecListOne128:$Rd), 6768 (STy (scalar_load GPR64sp:$Rn)), VecIndex:$idx), 6769 (LD1 VecListOne128:$Rd, VecIndex:$idx, GPR64sp:$Rn)>; 6770 6771def : Ld1Lane128Pat<extloadi8, VectorIndexB, v16i8, i32, LD1i8>; 6772def : Ld1Lane128Pat<extloadi16, VectorIndexH, v8i16, i32, LD1i16>; 6773def : Ld1Lane128Pat<load, VectorIndexS, v4i32, i32, LD1i32>; 6774def : Ld1Lane128Pat<load, VectorIndexS, v4f32, f32, LD1i32>; 6775def : Ld1Lane128Pat<load, VectorIndexD, v2i64, i64, LD1i64>; 6776def : Ld1Lane128Pat<load, VectorIndexD, v2f64, f64, LD1i64>; 6777def : Ld1Lane128Pat<load, VectorIndexH, v8f16, f16, LD1i16>; 6778def : Ld1Lane128Pat<load, VectorIndexH, v8bf16, bf16, LD1i16>; 6779 6780// Generate LD1 for extload if memory type does not match the 6781// destination type, for example: 6782// 6783// (v4i32 (insert_vector_elt (load anyext from i8) idx)) 6784// 6785// In this case, the index must be adjusted to match LD1 type. 6786// 6787class Ld1Lane128IdxOpPat<SDPatternOperator scalar_load, Operand 6788 VecIndex, ValueType VTy, ValueType STy, 6789 Instruction LD1, SDNodeXForm IdxOp> 6790 : Pat<(vector_insert (VTy VecListOne128:$Rd), 6791 (STy (scalar_load GPR64sp:$Rn)), VecIndex:$idx), 6792 (LD1 VecListOne128:$Rd, (IdxOp VecIndex:$idx), GPR64sp:$Rn)>; 6793 6794def VectorIndexStoH : SDNodeXForm<imm, [{ 6795 return CurDAG->getTargetConstant(N->getZExtValue() * 2, SDLoc(N), MVT::i64); 6796}]>; 6797def VectorIndexStoB : SDNodeXForm<imm, [{ 6798 return CurDAG->getTargetConstant(N->getZExtValue() * 4, SDLoc(N), MVT::i64); 6799}]>; 6800def VectorIndexHtoB : SDNodeXForm<imm, [{ 6801 return CurDAG->getTargetConstant(N->getZExtValue() * 2, SDLoc(N), MVT::i64); 6802}]>; 6803 6804def : Ld1Lane128IdxOpPat<extloadi16, VectorIndexS, v4i32, i32, LD1i16, VectorIndexStoH>; 6805def : Ld1Lane128IdxOpPat<extloadi8, VectorIndexS, v4i32, i32, LD1i8, VectorIndexStoB>; 6806def : Ld1Lane128IdxOpPat<extloadi8, VectorIndexH, v8i16, i32, LD1i8, VectorIndexHtoB>; 6807 6808// Same as above, but the first element is populated using 6809// scalar_to_vector + insert_subvector instead of insert_vector_elt. 6810class Ld1Lane128FirstElm<ValueType ResultTy, ValueType VecTy, 6811 SDPatternOperator ExtLoad, Instruction LD1> 6812 : Pat<(ResultTy (scalar_to_vector (i32 (ExtLoad GPR64sp:$Rn)))), 6813 (ResultTy (EXTRACT_SUBREG 6814 (LD1 (VecTy (IMPLICIT_DEF)), 0, GPR64sp:$Rn), dsub))>; 6815 6816def : Ld1Lane128FirstElm<v2i32, v8i16, extloadi16, LD1i16>; 6817def : Ld1Lane128FirstElm<v2i32, v16i8, extloadi8, LD1i8>; 6818def : Ld1Lane128FirstElm<v4i16, v16i8, extloadi8, LD1i8>; 6819 6820class Ld1Lane64Pat<SDPatternOperator scalar_load, Operand VecIndex, 6821 ValueType VTy, ValueType STy, Instruction LD1> 6822 : Pat<(vector_insert (VTy VecListOne64:$Rd), 6823 (STy (scalar_load GPR64sp:$Rn)), VecIndex:$idx), 6824 (EXTRACT_SUBREG 6825 (LD1 (SUBREG_TO_REG (i32 0), VecListOne64:$Rd, dsub), 6826 VecIndex:$idx, GPR64sp:$Rn), 6827 dsub)>; 6828 6829def : Ld1Lane64Pat<extloadi8, VectorIndexB, v8i8, i32, LD1i8>; 6830def : Ld1Lane64Pat<extloadi16, VectorIndexH, v4i16, i32, LD1i16>; 6831def : Ld1Lane64Pat<load, VectorIndexS, v2i32, i32, LD1i32>; 6832def : Ld1Lane64Pat<load, VectorIndexS, v2f32, f32, LD1i32>; 6833def : Ld1Lane64Pat<load, VectorIndexH, v4f16, f16, LD1i16>; 6834def : Ld1Lane64Pat<load, VectorIndexH, v4bf16, bf16, LD1i16>; 6835 6836 6837defm LD1 : SIMDLdSt1SingleAliases<"ld1">; 6838defm LD2 : SIMDLdSt2SingleAliases<"ld2">; 6839defm LD3 : SIMDLdSt3SingleAliases<"ld3">; 6840defm LD4 : SIMDLdSt4SingleAliases<"ld4">; 6841 6842// Stores 6843defm ST1 : SIMDStSingleB<0, 0b000, "st1", VecListOneb, GPR64pi1>; 6844defm ST1 : SIMDStSingleH<0, 0b010, 0, "st1", VecListOneh, GPR64pi2>; 6845defm ST1 : SIMDStSingleS<0, 0b100, 0b00, "st1", VecListOnes, GPR64pi4>; 6846defm ST1 : SIMDStSingleD<0, 0b100, 0b01, "st1", VecListOned, GPR64pi8>; 6847 6848let AddedComplexity = 19 in 6849class St1Lane128Pat<SDPatternOperator scalar_store, Operand VecIndex, 6850 ValueType VTy, ValueType STy, Instruction ST1> 6851 : Pat<(scalar_store 6852 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)), 6853 GPR64sp:$Rn), 6854 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn)>; 6855 6856def : St1Lane128Pat<truncstorei8, VectorIndexB, v16i8, i32, ST1i8>; 6857def : St1Lane128Pat<truncstorei16, VectorIndexH, v8i16, i32, ST1i16>; 6858def : St1Lane128Pat<store, VectorIndexS, v4i32, i32, ST1i32>; 6859def : St1Lane128Pat<store, VectorIndexS, v4f32, f32, ST1i32>; 6860def : St1Lane128Pat<store, VectorIndexD, v2i64, i64, ST1i64>; 6861def : St1Lane128Pat<store, VectorIndexD, v2f64, f64, ST1i64>; 6862def : St1Lane128Pat<store, VectorIndexH, v8f16, f16, ST1i16>; 6863def : St1Lane128Pat<store, VectorIndexH, v8bf16, bf16, ST1i16>; 6864 6865let AddedComplexity = 19 in 6866class St1Lane64Pat<SDPatternOperator scalar_store, Operand VecIndex, 6867 ValueType VTy, ValueType STy, Instruction ST1> 6868 : Pat<(scalar_store 6869 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)), 6870 GPR64sp:$Rn), 6871 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub), 6872 VecIndex:$idx, GPR64sp:$Rn)>; 6873 6874def : St1Lane64Pat<truncstorei8, VectorIndexB, v8i8, i32, ST1i8>; 6875def : St1Lane64Pat<truncstorei16, VectorIndexH, v4i16, i32, ST1i16>; 6876def : St1Lane64Pat<store, VectorIndexS, v2i32, i32, ST1i32>; 6877def : St1Lane64Pat<store, VectorIndexS, v2f32, f32, ST1i32>; 6878def : St1Lane64Pat<store, VectorIndexH, v4f16, f16, ST1i16>; 6879def : St1Lane64Pat<store, VectorIndexH, v4bf16, bf16, ST1i16>; 6880 6881multiclass St1LanePost64Pat<SDPatternOperator scalar_store, Operand VecIndex, 6882 ValueType VTy, ValueType STy, Instruction ST1, 6883 int offset> { 6884 def : Pat<(scalar_store 6885 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)), 6886 GPR64sp:$Rn, offset), 6887 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub), 6888 VecIndex:$idx, GPR64sp:$Rn, XZR)>; 6889 6890 def : Pat<(scalar_store 6891 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)), 6892 GPR64sp:$Rn, GPR64:$Rm), 6893 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub), 6894 VecIndex:$idx, GPR64sp:$Rn, $Rm)>; 6895} 6896 6897defm : St1LanePost64Pat<post_truncsti8, VectorIndexB, v8i8, i32, ST1i8_POST, 1>; 6898defm : St1LanePost64Pat<post_truncsti16, VectorIndexH, v4i16, i32, ST1i16_POST, 6899 2>; 6900defm : St1LanePost64Pat<post_store, VectorIndexS, v2i32, i32, ST1i32_POST, 4>; 6901defm : St1LanePost64Pat<post_store, VectorIndexS, v2f32, f32, ST1i32_POST, 4>; 6902defm : St1LanePost64Pat<post_store, VectorIndexD, v1i64, i64, ST1i64_POST, 8>; 6903defm : St1LanePost64Pat<post_store, VectorIndexD, v1f64, f64, ST1i64_POST, 8>; 6904defm : St1LanePost64Pat<post_store, VectorIndexH, v4f16, f16, ST1i16_POST, 2>; 6905defm : St1LanePost64Pat<post_store, VectorIndexH, v4bf16, bf16, ST1i16_POST, 2>; 6906 6907multiclass St1LanePost128Pat<SDPatternOperator scalar_store, Operand VecIndex, 6908 ValueType VTy, ValueType STy, Instruction ST1, 6909 int offset> { 6910 def : Pat<(scalar_store 6911 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)), 6912 GPR64sp:$Rn, offset), 6913 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn, XZR)>; 6914 6915 def : Pat<(scalar_store 6916 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)), 6917 GPR64sp:$Rn, GPR64:$Rm), 6918 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn, $Rm)>; 6919} 6920 6921defm : St1LanePost128Pat<post_truncsti8, VectorIndexB, v16i8, i32, ST1i8_POST, 6922 1>; 6923defm : St1LanePost128Pat<post_truncsti16, VectorIndexH, v8i16, i32, ST1i16_POST, 6924 2>; 6925defm : St1LanePost128Pat<post_store, VectorIndexS, v4i32, i32, ST1i32_POST, 4>; 6926defm : St1LanePost128Pat<post_store, VectorIndexS, v4f32, f32, ST1i32_POST, 4>; 6927defm : St1LanePost128Pat<post_store, VectorIndexD, v2i64, i64, ST1i64_POST, 8>; 6928defm : St1LanePost128Pat<post_store, VectorIndexD, v2f64, f64, ST1i64_POST, 8>; 6929defm : St1LanePost128Pat<post_store, VectorIndexH, v8f16, f16, ST1i16_POST, 2>; 6930defm : St1LanePost128Pat<post_store, VectorIndexH, v8bf16, bf16, ST1i16_POST, 2>; 6931 6932let mayStore = 1, hasSideEffects = 0 in { 6933defm ST2 : SIMDStSingleB<1, 0b000, "st2", VecListTwob, GPR64pi2>; 6934defm ST2 : SIMDStSingleH<1, 0b010, 0, "st2", VecListTwoh, GPR64pi4>; 6935defm ST2 : SIMDStSingleS<1, 0b100, 0b00, "st2", VecListTwos, GPR64pi8>; 6936defm ST2 : SIMDStSingleD<1, 0b100, 0b01, "st2", VecListTwod, GPR64pi16>; 6937defm ST3 : SIMDStSingleB<0, 0b001, "st3", VecListThreeb, GPR64pi3>; 6938defm ST3 : SIMDStSingleH<0, 0b011, 0, "st3", VecListThreeh, GPR64pi6>; 6939defm ST3 : SIMDStSingleS<0, 0b101, 0b00, "st3", VecListThrees, GPR64pi12>; 6940defm ST3 : SIMDStSingleD<0, 0b101, 0b01, "st3", VecListThreed, GPR64pi24>; 6941defm ST4 : SIMDStSingleB<1, 0b001, "st4", VecListFourb, GPR64pi4>; 6942defm ST4 : SIMDStSingleH<1, 0b011, 0, "st4", VecListFourh, GPR64pi8>; 6943defm ST4 : SIMDStSingleS<1, 0b101, 0b00, "st4", VecListFours, GPR64pi16>; 6944defm ST4 : SIMDStSingleD<1, 0b101, 0b01, "st4", VecListFourd, GPR64pi32>; 6945} 6946 6947defm ST1 : SIMDLdSt1SingleAliases<"st1">; 6948defm ST2 : SIMDLdSt2SingleAliases<"st2">; 6949defm ST3 : SIMDLdSt3SingleAliases<"st3">; 6950defm ST4 : SIMDLdSt4SingleAliases<"st4">; 6951 6952//---------------------------------------------------------------------------- 6953// Crypto extensions 6954//---------------------------------------------------------------------------- 6955 6956let Predicates = [HasAES] in { 6957def AESErr : AESTiedInst<0b0100, "aese", int_aarch64_crypto_aese>; 6958def AESDrr : AESTiedInst<0b0101, "aesd", int_aarch64_crypto_aesd>; 6959def AESMCrr : AESInst< 0b0110, "aesmc", int_aarch64_crypto_aesmc>; 6960def AESIMCrr : AESInst< 0b0111, "aesimc", int_aarch64_crypto_aesimc>; 6961} 6962 6963// Pseudo instructions for AESMCrr/AESIMCrr with a register constraint required 6964// for AES fusion on some CPUs. 6965let hasSideEffects = 0, mayStore = 0, mayLoad = 0 in { 6966def AESMCrrTied: Pseudo<(outs V128:$Rd), (ins V128:$Rn), [], "$Rn = $Rd">, 6967 Sched<[WriteV]>; 6968def AESIMCrrTied: Pseudo<(outs V128:$Rd), (ins V128:$Rn), [], "$Rn = $Rd">, 6969 Sched<[WriteV]>; 6970} 6971 6972// Only use constrained versions of AES(I)MC instructions if they are paired with 6973// AESE/AESD. 6974def : Pat<(v16i8 (int_aarch64_crypto_aesmc 6975 (v16i8 (int_aarch64_crypto_aese (v16i8 V128:$src1), 6976 (v16i8 V128:$src2))))), 6977 (v16i8 (AESMCrrTied (v16i8 (AESErr (v16i8 V128:$src1), 6978 (v16i8 V128:$src2)))))>, 6979 Requires<[HasFuseAES]>; 6980 6981def : Pat<(v16i8 (int_aarch64_crypto_aesimc 6982 (v16i8 (int_aarch64_crypto_aesd (v16i8 V128:$src1), 6983 (v16i8 V128:$src2))))), 6984 (v16i8 (AESIMCrrTied (v16i8 (AESDrr (v16i8 V128:$src1), 6985 (v16i8 V128:$src2)))))>, 6986 Requires<[HasFuseAES]>; 6987 6988let Predicates = [HasSHA2] in { 6989def SHA1Crrr : SHATiedInstQSV<0b000, "sha1c", int_aarch64_crypto_sha1c>; 6990def SHA1Prrr : SHATiedInstQSV<0b001, "sha1p", int_aarch64_crypto_sha1p>; 6991def SHA1Mrrr : SHATiedInstQSV<0b010, "sha1m", int_aarch64_crypto_sha1m>; 6992def SHA1SU0rrr : SHATiedInstVVV<0b011, "sha1su0", int_aarch64_crypto_sha1su0>; 6993def SHA256Hrrr : SHATiedInstQQV<0b100, "sha256h", int_aarch64_crypto_sha256h>; 6994def SHA256H2rrr : SHATiedInstQQV<0b101, "sha256h2",int_aarch64_crypto_sha256h2>; 6995def SHA256SU1rrr :SHATiedInstVVV<0b110, "sha256su1",int_aarch64_crypto_sha256su1>; 6996 6997def SHA1Hrr : SHAInstSS< 0b0000, "sha1h", int_aarch64_crypto_sha1h>; 6998def SHA1SU1rr : SHATiedInstVV<0b0001, "sha1su1", int_aarch64_crypto_sha1su1>; 6999def SHA256SU0rr : SHATiedInstVV<0b0010, "sha256su0",int_aarch64_crypto_sha256su0>; 7000} 7001 7002//---------------------------------------------------------------------------- 7003// Compiler-pseudos 7004//---------------------------------------------------------------------------- 7005// FIXME: Like for X86, these should go in their own separate .td file. 7006 7007def def32 : PatLeaf<(i32 GPR32:$src), [{ 7008 return isDef32(*N); 7009}]>; 7010 7011// In the case of a 32-bit def that is known to implicitly zero-extend, 7012// we can use a SUBREG_TO_REG. 7013def : Pat<(i64 (zext def32:$src)), (SUBREG_TO_REG (i64 0), GPR32:$src, sub_32)>; 7014 7015// For an anyext, we don't care what the high bits are, so we can perform an 7016// INSERT_SUBREF into an IMPLICIT_DEF. 7017def : Pat<(i64 (anyext GPR32:$src)), 7018 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32)>; 7019 7020// When we need to explicitly zero-extend, we use a 32-bit MOV instruction and 7021// then assert the extension has happened. 7022def : Pat<(i64 (zext GPR32:$src)), 7023 (SUBREG_TO_REG (i32 0), (ORRWrs WZR, GPR32:$src, 0), sub_32)>; 7024 7025// To sign extend, we use a signed bitfield move instruction (SBFM) on the 7026// containing super-reg. 7027def : Pat<(i64 (sext GPR32:$src)), 7028 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32), 0, 31)>; 7029def : Pat<(i64 (sext_inreg GPR64:$src, i32)), (SBFMXri GPR64:$src, 0, 31)>; 7030def : Pat<(i64 (sext_inreg GPR64:$src, i16)), (SBFMXri GPR64:$src, 0, 15)>; 7031def : Pat<(i64 (sext_inreg GPR64:$src, i8)), (SBFMXri GPR64:$src, 0, 7)>; 7032def : Pat<(i64 (sext_inreg GPR64:$src, i1)), (SBFMXri GPR64:$src, 0, 0)>; 7033def : Pat<(i32 (sext_inreg GPR32:$src, i16)), (SBFMWri GPR32:$src, 0, 15)>; 7034def : Pat<(i32 (sext_inreg GPR32:$src, i8)), (SBFMWri GPR32:$src, 0, 7)>; 7035def : Pat<(i32 (sext_inreg GPR32:$src, i1)), (SBFMWri GPR32:$src, 0, 0)>; 7036 7037def : Pat<(shl (sext_inreg GPR32:$Rn, i8), (i64 imm0_31:$imm)), 7038 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)), 7039 (i64 (i32shift_sext_i8 imm0_31:$imm)))>; 7040def : Pat<(shl (sext_inreg GPR64:$Rn, i8), (i64 imm0_63:$imm)), 7041 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)), 7042 (i64 (i64shift_sext_i8 imm0_63:$imm)))>; 7043 7044def : Pat<(shl (sext_inreg GPR32:$Rn, i16), (i64 imm0_31:$imm)), 7045 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)), 7046 (i64 (i32shift_sext_i16 imm0_31:$imm)))>; 7047def : Pat<(shl (sext_inreg GPR64:$Rn, i16), (i64 imm0_63:$imm)), 7048 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)), 7049 (i64 (i64shift_sext_i16 imm0_63:$imm)))>; 7050 7051def : Pat<(shl (i64 (sext GPR32:$Rn)), (i64 imm0_63:$imm)), 7052 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32), 7053 (i64 (i64shift_a imm0_63:$imm)), 7054 (i64 (i64shift_sext_i32 imm0_63:$imm)))>; 7055 7056// sra patterns have an AddedComplexity of 10, so make sure we have a higher 7057// AddedComplexity for the following patterns since we want to match sext + sra 7058// patterns before we attempt to match a single sra node. 7059let AddedComplexity = 20 in { 7060// We support all sext + sra combinations which preserve at least one bit of the 7061// original value which is to be sign extended. E.g. we support shifts up to 7062// bitwidth-1 bits. 7063def : Pat<(sra (sext_inreg GPR32:$Rn, i8), (i64 imm0_7:$imm)), 7064 (SBFMWri GPR32:$Rn, (i64 imm0_7:$imm), 7)>; 7065def : Pat<(sra (sext_inreg GPR64:$Rn, i8), (i64 imm0_7:$imm)), 7066 (SBFMXri GPR64:$Rn, (i64 imm0_7:$imm), 7)>; 7067 7068def : Pat<(sra (sext_inreg GPR32:$Rn, i16), (i64 imm0_15:$imm)), 7069 (SBFMWri GPR32:$Rn, (i64 imm0_15:$imm), 15)>; 7070def : Pat<(sra (sext_inreg GPR64:$Rn, i16), (i64 imm0_15:$imm)), 7071 (SBFMXri GPR64:$Rn, (i64 imm0_15:$imm), 15)>; 7072 7073def : Pat<(sra (i64 (sext GPR32:$Rn)), (i64 imm0_31:$imm)), 7074 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32), 7075 (i64 imm0_31:$imm), 31)>; 7076} // AddedComplexity = 20 7077 7078// To truncate, we can simply extract from a subregister. 7079def : Pat<(i32 (trunc GPR64sp:$src)), 7080 (i32 (EXTRACT_SUBREG GPR64sp:$src, sub_32))>; 7081 7082// __builtin_trap() uses the BRK instruction on AArch64. 7083def : Pat<(trap), (BRK 1)>; 7084def : Pat<(debugtrap), (BRK 0xF000)>; 7085 7086def ubsan_trap_xform : SDNodeXForm<timm, [{ 7087 return CurDAG->getTargetConstant(N->getZExtValue() | ('U' << 8), SDLoc(N), MVT::i32); 7088}]>; 7089 7090def ubsan_trap_imm : TImmLeaf<i32, [{ 7091 return isUInt<8>(Imm); 7092}], ubsan_trap_xform>; 7093 7094def : Pat<(ubsantrap ubsan_trap_imm:$kind), (BRK ubsan_trap_imm:$kind)>; 7095 7096// Multiply high patterns which multiply the lower subvector using smull/umull 7097// and the upper subvector with smull2/umull2. Then shuffle the high the high 7098// part of both results together. 7099def : Pat<(v16i8 (mulhs V128:$Rn, V128:$Rm)), 7100 (UZP2v16i8 7101 (SMULLv8i8_v8i16 (EXTRACT_SUBREG V128:$Rn, dsub), 7102 (EXTRACT_SUBREG V128:$Rm, dsub)), 7103 (SMULLv16i8_v8i16 V128:$Rn, V128:$Rm))>; 7104def : Pat<(v8i16 (mulhs V128:$Rn, V128:$Rm)), 7105 (UZP2v8i16 7106 (SMULLv4i16_v4i32 (EXTRACT_SUBREG V128:$Rn, dsub), 7107 (EXTRACT_SUBREG V128:$Rm, dsub)), 7108 (SMULLv8i16_v4i32 V128:$Rn, V128:$Rm))>; 7109def : Pat<(v4i32 (mulhs V128:$Rn, V128:$Rm)), 7110 (UZP2v4i32 7111 (SMULLv2i32_v2i64 (EXTRACT_SUBREG V128:$Rn, dsub), 7112 (EXTRACT_SUBREG V128:$Rm, dsub)), 7113 (SMULLv4i32_v2i64 V128:$Rn, V128:$Rm))>; 7114 7115def : Pat<(v16i8 (mulhu V128:$Rn, V128:$Rm)), 7116 (UZP2v16i8 7117 (UMULLv8i8_v8i16 (EXTRACT_SUBREG V128:$Rn, dsub), 7118 (EXTRACT_SUBREG V128:$Rm, dsub)), 7119 (UMULLv16i8_v8i16 V128:$Rn, V128:$Rm))>; 7120def : Pat<(v8i16 (mulhu V128:$Rn, V128:$Rm)), 7121 (UZP2v8i16 7122 (UMULLv4i16_v4i32 (EXTRACT_SUBREG V128:$Rn, dsub), 7123 (EXTRACT_SUBREG V128:$Rm, dsub)), 7124 (UMULLv8i16_v4i32 V128:$Rn, V128:$Rm))>; 7125def : Pat<(v4i32 (mulhu V128:$Rn, V128:$Rm)), 7126 (UZP2v4i32 7127 (UMULLv2i32_v2i64 (EXTRACT_SUBREG V128:$Rn, dsub), 7128 (EXTRACT_SUBREG V128:$Rm, dsub)), 7129 (UMULLv4i32_v2i64 V128:$Rn, V128:$Rm))>; 7130 7131// Conversions within AdvSIMD types in the same register size are free. 7132// But because we need a consistent lane ordering, in big endian many 7133// conversions require one or more REV instructions. 7134// 7135// Consider a simple memory load followed by a bitconvert then a store. 7136// v0 = load v2i32 7137// v1 = BITCAST v2i32 v0 to v4i16 7138// store v4i16 v2 7139// 7140// In big endian mode every memory access has an implicit byte swap. LDR and 7141// STR do a 64-bit byte swap, whereas LD1/ST1 do a byte swap per lane - that 7142// is, they treat the vector as a sequence of elements to be byte-swapped. 7143// The two pairs of instructions are fundamentally incompatible. We've decided 7144// to use LD1/ST1 only to simplify compiler implementation. 7145// 7146// LD1/ST1 perform the equivalent of a sequence of LDR/STR + REV. This makes 7147// the original code sequence: 7148// v0 = load v2i32 7149// v1 = REV v2i32 (implicit) 7150// v2 = BITCAST v2i32 v1 to v4i16 7151// v3 = REV v4i16 v2 (implicit) 7152// store v4i16 v3 7153// 7154// But this is now broken - the value stored is different to the value loaded 7155// due to lane reordering. To fix this, on every BITCAST we must perform two 7156// other REVs: 7157// v0 = load v2i32 7158// v1 = REV v2i32 (implicit) 7159// v2 = REV v2i32 7160// v3 = BITCAST v2i32 v2 to v4i16 7161// v4 = REV v4i16 7162// v5 = REV v4i16 v4 (implicit) 7163// store v4i16 v5 7164// 7165// This means an extra two instructions, but actually in most cases the two REV 7166// instructions can be combined into one. For example: 7167// (REV64_2s (REV64_4h X)) === (REV32_4h X) 7168// 7169// There is also no 128-bit REV instruction. This must be synthesized with an 7170// EXT instruction. 7171// 7172// Most bitconverts require some sort of conversion. The only exceptions are: 7173// a) Identity conversions - vNfX <-> vNiX 7174// b) Single-lane-to-scalar - v1fX <-> fX or v1iX <-> iX 7175// 7176 7177// Natural vector casts (64 bit) 7178def : Pat<(v8i8 (AArch64NvCast (v2i32 FPR64:$src))), (v8i8 FPR64:$src)>; 7179def : Pat<(v4i16 (AArch64NvCast (v2i32 FPR64:$src))), (v4i16 FPR64:$src)>; 7180def : Pat<(v4f16 (AArch64NvCast (v2i32 FPR64:$src))), (v4f16 FPR64:$src)>; 7181def : Pat<(v4bf16 (AArch64NvCast (v2i32 FPR64:$src))), (v4bf16 FPR64:$src)>; 7182def : Pat<(v2i32 (AArch64NvCast (v2i32 FPR64:$src))), (v2i32 FPR64:$src)>; 7183def : Pat<(v2f32 (AArch64NvCast (v2i32 FPR64:$src))), (v2f32 FPR64:$src)>; 7184def : Pat<(v1i64 (AArch64NvCast (v2i32 FPR64:$src))), (v1i64 FPR64:$src)>; 7185 7186def : Pat<(v8i8 (AArch64NvCast (v4i16 FPR64:$src))), (v8i8 FPR64:$src)>; 7187def : Pat<(v4i16 (AArch64NvCast (v4i16 FPR64:$src))), (v4i16 FPR64:$src)>; 7188def : Pat<(v4f16 (AArch64NvCast (v4i16 FPR64:$src))), (v4f16 FPR64:$src)>; 7189def : Pat<(v4bf16 (AArch64NvCast (v4i16 FPR64:$src))), (v4bf16 FPR64:$src)>; 7190def : Pat<(v2i32 (AArch64NvCast (v4i16 FPR64:$src))), (v2i32 FPR64:$src)>; 7191def : Pat<(v1i64 (AArch64NvCast (v4i16 FPR64:$src))), (v1i64 FPR64:$src)>; 7192 7193def : Pat<(v8i8 (AArch64NvCast (v8i8 FPR64:$src))), (v8i8 FPR64:$src)>; 7194def : Pat<(v4i16 (AArch64NvCast (v8i8 FPR64:$src))), (v4i16 FPR64:$src)>; 7195def : Pat<(v4f16 (AArch64NvCast (v8i8 FPR64:$src))), (v4f16 FPR64:$src)>; 7196def : Pat<(v4bf16 (AArch64NvCast (v8i8 FPR64:$src))), (v4bf16 FPR64:$src)>; 7197def : Pat<(v2i32 (AArch64NvCast (v8i8 FPR64:$src))), (v2i32 FPR64:$src)>; 7198def : Pat<(v2f32 (AArch64NvCast (v8i8 FPR64:$src))), (v2f32 FPR64:$src)>; 7199def : Pat<(v1i64 (AArch64NvCast (v8i8 FPR64:$src))), (v1i64 FPR64:$src)>; 7200 7201def : Pat<(v8i8 (AArch64NvCast (f64 FPR64:$src))), (v8i8 FPR64:$src)>; 7202def : Pat<(v4i16 (AArch64NvCast (f64 FPR64:$src))), (v4i16 FPR64:$src)>; 7203def : Pat<(v4f16 (AArch64NvCast (f64 FPR64:$src))), (v4f16 FPR64:$src)>; 7204def : Pat<(v4bf16 (AArch64NvCast (f64 FPR64:$src))), (v4bf16 FPR64:$src)>; 7205def : Pat<(v2i32 (AArch64NvCast (f64 FPR64:$src))), (v2i32 FPR64:$src)>; 7206def : Pat<(v2f32 (AArch64NvCast (f64 FPR64:$src))), (v2f32 FPR64:$src)>; 7207def : Pat<(v1i64 (AArch64NvCast (f64 FPR64:$src))), (v1i64 FPR64:$src)>; 7208def : Pat<(v1f64 (AArch64NvCast (f64 FPR64:$src))), (v1f64 FPR64:$src)>; 7209 7210def : Pat<(v8i8 (AArch64NvCast (v2f32 FPR64:$src))), (v8i8 FPR64:$src)>; 7211def : Pat<(v4i16 (AArch64NvCast (v2f32 FPR64:$src))), (v4i16 FPR64:$src)>; 7212def : Pat<(v2i32 (AArch64NvCast (v2f32 FPR64:$src))), (v2i32 FPR64:$src)>; 7213def : Pat<(v2f32 (AArch64NvCast (v2f32 FPR64:$src))), (v2f32 FPR64:$src)>; 7214def : Pat<(v1i64 (AArch64NvCast (v2f32 FPR64:$src))), (v1i64 FPR64:$src)>; 7215def : Pat<(v1f64 (AArch64NvCast (v2f32 FPR64:$src))), (v1f64 FPR64:$src)>; 7216 7217// Natural vector casts (128 bit) 7218def : Pat<(v16i8 (AArch64NvCast (v4i32 FPR128:$src))), (v16i8 FPR128:$src)>; 7219def : Pat<(v8i16 (AArch64NvCast (v4i32 FPR128:$src))), (v8i16 FPR128:$src)>; 7220def : Pat<(v8f16 (AArch64NvCast (v4i32 FPR128:$src))), (v8f16 FPR128:$src)>; 7221def : Pat<(v8bf16 (AArch64NvCast (v4i32 FPR128:$src))), (v8bf16 FPR128:$src)>; 7222def : Pat<(v4i32 (AArch64NvCast (v4i32 FPR128:$src))), (v4i32 FPR128:$src)>; 7223def : Pat<(v4f32 (AArch64NvCast (v4i32 FPR128:$src))), (v4f32 FPR128:$src)>; 7224def : Pat<(v2i64 (AArch64NvCast (v4i32 FPR128:$src))), (v2i64 FPR128:$src)>; 7225def : Pat<(v2f64 (AArch64NvCast (v4i32 FPR128:$src))), (v2f64 FPR128:$src)>; 7226 7227def : Pat<(v16i8 (AArch64NvCast (v8i16 FPR128:$src))), (v16i8 FPR128:$src)>; 7228def : Pat<(v8i16 (AArch64NvCast (v8i16 FPR128:$src))), (v8i16 FPR128:$src)>; 7229def : Pat<(v8f16 (AArch64NvCast (v8i16 FPR128:$src))), (v8f16 FPR128:$src)>; 7230def : Pat<(v8bf16 (AArch64NvCast (v8i16 FPR128:$src))), (v8bf16 FPR128:$src)>; 7231def : Pat<(v4i32 (AArch64NvCast (v8i16 FPR128:$src))), (v4i32 FPR128:$src)>; 7232def : Pat<(v2i64 (AArch64NvCast (v8i16 FPR128:$src))), (v2i64 FPR128:$src)>; 7233def : Pat<(v4f32 (AArch64NvCast (v8i16 FPR128:$src))), (v4f32 FPR128:$src)>; 7234def : Pat<(v2f64 (AArch64NvCast (v8i16 FPR128:$src))), (v2f64 FPR128:$src)>; 7235 7236def : Pat<(v16i8 (AArch64NvCast (v16i8 FPR128:$src))), (v16i8 FPR128:$src)>; 7237def : Pat<(v8i16 (AArch64NvCast (v16i8 FPR128:$src))), (v8i16 FPR128:$src)>; 7238def : Pat<(v8f16 (AArch64NvCast (v16i8 FPR128:$src))), (v8f16 FPR128:$src)>; 7239def : Pat<(v8bf16 (AArch64NvCast (v16i8 FPR128:$src))), (v8bf16 FPR128:$src)>; 7240def : Pat<(v4i32 (AArch64NvCast (v16i8 FPR128:$src))), (v4i32 FPR128:$src)>; 7241def : Pat<(v2i64 (AArch64NvCast (v16i8 FPR128:$src))), (v2i64 FPR128:$src)>; 7242def : Pat<(v4f32 (AArch64NvCast (v16i8 FPR128:$src))), (v4f32 FPR128:$src)>; 7243def : Pat<(v2f64 (AArch64NvCast (v16i8 FPR128:$src))), (v2f64 FPR128:$src)>; 7244 7245def : Pat<(v16i8 (AArch64NvCast (v2i64 FPR128:$src))), (v16i8 FPR128:$src)>; 7246def : Pat<(v8i16 (AArch64NvCast (v2i64 FPR128:$src))), (v8i16 FPR128:$src)>; 7247def : Pat<(v8f16 (AArch64NvCast (v2i64 FPR128:$src))), (v8f16 FPR128:$src)>; 7248def : Pat<(v8bf16 (AArch64NvCast (v2i64 FPR128:$src))), (v8bf16 FPR128:$src)>; 7249def : Pat<(v4i32 (AArch64NvCast (v2i64 FPR128:$src))), (v4i32 FPR128:$src)>; 7250def : Pat<(v2i64 (AArch64NvCast (v2i64 FPR128:$src))), (v2i64 FPR128:$src)>; 7251def : Pat<(v4f32 (AArch64NvCast (v2i64 FPR128:$src))), (v4f32 FPR128:$src)>; 7252def : Pat<(v2f64 (AArch64NvCast (v2i64 FPR128:$src))), (v2f64 FPR128:$src)>; 7253 7254def : Pat<(v16i8 (AArch64NvCast (v4f32 FPR128:$src))), (v16i8 FPR128:$src)>; 7255def : Pat<(v8i16 (AArch64NvCast (v4f32 FPR128:$src))), (v8i16 FPR128:$src)>; 7256def : Pat<(v4i32 (AArch64NvCast (v4f32 FPR128:$src))), (v4i32 FPR128:$src)>; 7257def : Pat<(v4f32 (AArch64NvCast (v4f32 FPR128:$src))), (v4f32 FPR128:$src)>; 7258def : Pat<(v2i64 (AArch64NvCast (v4f32 FPR128:$src))), (v2i64 FPR128:$src)>; 7259def : Pat<(v8f16 (AArch64NvCast (v4f32 FPR128:$src))), (v8f16 FPR128:$src)>; 7260def : Pat<(v8bf16 (AArch64NvCast (v4f32 FPR128:$src))), (v8bf16 FPR128:$src)>; 7261def : Pat<(v2f64 (AArch64NvCast (v4f32 FPR128:$src))), (v2f64 FPR128:$src)>; 7262 7263def : Pat<(v16i8 (AArch64NvCast (v2f64 FPR128:$src))), (v16i8 FPR128:$src)>; 7264def : Pat<(v8i16 (AArch64NvCast (v2f64 FPR128:$src))), (v8i16 FPR128:$src)>; 7265def : Pat<(v4i32 (AArch64NvCast (v2f64 FPR128:$src))), (v4i32 FPR128:$src)>; 7266def : Pat<(v2i64 (AArch64NvCast (v2f64 FPR128:$src))), (v2i64 FPR128:$src)>; 7267def : Pat<(v2f64 (AArch64NvCast (v2f64 FPR128:$src))), (v2f64 FPR128:$src)>; 7268def : Pat<(v8f16 (AArch64NvCast (v2f64 FPR128:$src))), (v8f16 FPR128:$src)>; 7269def : Pat<(v8bf16 (AArch64NvCast (v2f64 FPR128:$src))), (v8bf16 FPR128:$src)>; 7270def : Pat<(v4f32 (AArch64NvCast (v2f64 FPR128:$src))), (v4f32 FPR128:$src)>; 7271 7272let Predicates = [IsLE] in { 7273def : Pat<(v8i8 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>; 7274def : Pat<(v4i16 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>; 7275def : Pat<(v2i32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>; 7276def : Pat<(v4f16 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>; 7277def : Pat<(v4bf16 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>; 7278def : Pat<(v2f32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>; 7279 7280def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))), 7281 (COPY_TO_REGCLASS V64:$Vn, GPR64)>; 7282def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))), 7283 (COPY_TO_REGCLASS V64:$Vn, GPR64)>; 7284def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))), 7285 (COPY_TO_REGCLASS V64:$Vn, GPR64)>; 7286def : Pat<(i64 (bitconvert (v4f16 V64:$Vn))), 7287 (COPY_TO_REGCLASS V64:$Vn, GPR64)>; 7288def : Pat<(i64 (bitconvert (v4bf16 V64:$Vn))), 7289 (COPY_TO_REGCLASS V64:$Vn, GPR64)>; 7290def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))), 7291 (COPY_TO_REGCLASS V64:$Vn, GPR64)>; 7292def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))), 7293 (COPY_TO_REGCLASS V64:$Vn, GPR64)>; 7294} 7295let Predicates = [IsBE] in { 7296def : Pat<(v8i8 (bitconvert GPR64:$Xn)), 7297 (REV64v8i8 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>; 7298def : Pat<(v4i16 (bitconvert GPR64:$Xn)), 7299 (REV64v4i16 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>; 7300def : Pat<(v2i32 (bitconvert GPR64:$Xn)), 7301 (REV64v2i32 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>; 7302def : Pat<(v4f16 (bitconvert GPR64:$Xn)), 7303 (REV64v4i16 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>; 7304def : Pat<(v4bf16 (bitconvert GPR64:$Xn)), 7305 (REV64v4i16 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>; 7306def : Pat<(v2f32 (bitconvert GPR64:$Xn)), 7307 (REV64v2i32 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>; 7308 7309def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))), 7310 (REV64v8i8 (COPY_TO_REGCLASS V64:$Vn, GPR64))>; 7311def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))), 7312 (REV64v4i16 (COPY_TO_REGCLASS V64:$Vn, GPR64))>; 7313def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))), 7314 (REV64v2i32 (COPY_TO_REGCLASS V64:$Vn, GPR64))>; 7315def : Pat<(i64 (bitconvert (v4f16 V64:$Vn))), 7316 (REV64v4i16 (COPY_TO_REGCLASS V64:$Vn, GPR64))>; 7317def : Pat<(i64 (bitconvert (v4bf16 V64:$Vn))), 7318 (REV64v4i16 (COPY_TO_REGCLASS V64:$Vn, GPR64))>; 7319def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))), 7320 (REV64v2i32 (COPY_TO_REGCLASS V64:$Vn, GPR64))>; 7321} 7322def : Pat<(v1i64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>; 7323def : Pat<(v1f64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>; 7324def : Pat<(i64 (bitconvert (v1i64 V64:$Vn))), 7325 (COPY_TO_REGCLASS V64:$Vn, GPR64)>; 7326def : Pat<(v1i64 (scalar_to_vector GPR64:$Xn)), 7327 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>; 7328def : Pat<(v1f64 (scalar_to_vector GPR64:$Xn)), 7329 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>; 7330def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$Xn))), (v1f64 FPR64:$Xn)>; 7331 7332def : Pat<(f32 (bitconvert (i32 GPR32:$Xn))), 7333 (COPY_TO_REGCLASS GPR32:$Xn, FPR32)>; 7334def : Pat<(i32 (bitconvert (f32 FPR32:$Xn))), 7335 (COPY_TO_REGCLASS FPR32:$Xn, GPR32)>; 7336def : Pat<(f64 (bitconvert (i64 GPR64:$Xn))), 7337 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>; 7338def : Pat<(i64 (bitconvert (f64 FPR64:$Xn))), 7339 (COPY_TO_REGCLASS FPR64:$Xn, GPR64)>; 7340def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))), 7341 (COPY_TO_REGCLASS V64:$Vn, GPR64)>; 7342 7343let Predicates = [IsLE] in { 7344def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))), (v1i64 FPR64:$src)>; 7345def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))), (v1i64 FPR64:$src)>; 7346def : Pat<(v1i64 (bitconvert (v8i8 FPR64:$src))), (v1i64 FPR64:$src)>; 7347def : Pat<(v1i64 (bitconvert (v4f16 FPR64:$src))), (v1i64 FPR64:$src)>; 7348def : Pat<(v1i64 (bitconvert (v4bf16 FPR64:$src))), (v1i64 FPR64:$src)>; 7349def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))), (v1i64 FPR64:$src)>; 7350} 7351let Predicates = [IsBE] in { 7352def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))), 7353 (v1i64 (REV64v2i32 FPR64:$src))>; 7354def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))), 7355 (v1i64 (REV64v4i16 FPR64:$src))>; 7356def : Pat<(v1i64 (bitconvert (v8i8 FPR64:$src))), 7357 (v1i64 (REV64v8i8 FPR64:$src))>; 7358def : Pat<(v1i64 (bitconvert (v4f16 FPR64:$src))), 7359 (v1i64 (REV64v4i16 FPR64:$src))>; 7360def : Pat<(v1i64 (bitconvert (v4bf16 FPR64:$src))), 7361 (v1i64 (REV64v4i16 FPR64:$src))>; 7362def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))), 7363 (v1i64 (REV64v2i32 FPR64:$src))>; 7364} 7365def : Pat<(v1i64 (bitconvert (v1f64 FPR64:$src))), (v1i64 FPR64:$src)>; 7366def : Pat<(v1i64 (bitconvert (f64 FPR64:$src))), (v1i64 FPR64:$src)>; 7367 7368let Predicates = [IsLE] in { 7369def : Pat<(v2i32 (bitconvert (v1i64 FPR64:$src))), (v2i32 FPR64:$src)>; 7370def : Pat<(v2i32 (bitconvert (v4i16 FPR64:$src))), (v2i32 FPR64:$src)>; 7371def : Pat<(v2i32 (bitconvert (v8i8 FPR64:$src))), (v2i32 FPR64:$src)>; 7372def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))), (v2i32 FPR64:$src)>; 7373def : Pat<(v2i32 (bitconvert (v1f64 FPR64:$src))), (v2i32 FPR64:$src)>; 7374def : Pat<(v2i32 (bitconvert (v4f16 FPR64:$src))), (v2i32 FPR64:$src)>; 7375def : Pat<(v2i32 (bitconvert (v4bf16 FPR64:$src))), (v2i32 FPR64:$src)>; 7376} 7377let Predicates = [IsBE] in { 7378def : Pat<(v2i32 (bitconvert (v1i64 FPR64:$src))), 7379 (v2i32 (REV64v2i32 FPR64:$src))>; 7380def : Pat<(v2i32 (bitconvert (v4i16 FPR64:$src))), 7381 (v2i32 (REV32v4i16 FPR64:$src))>; 7382def : Pat<(v2i32 (bitconvert (v8i8 FPR64:$src))), 7383 (v2i32 (REV32v8i8 FPR64:$src))>; 7384def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))), 7385 (v2i32 (REV64v2i32 FPR64:$src))>; 7386def : Pat<(v2i32 (bitconvert (v1f64 FPR64:$src))), 7387 (v2i32 (REV64v2i32 FPR64:$src))>; 7388def : Pat<(v2i32 (bitconvert (v4f16 FPR64:$src))), 7389 (v2i32 (REV32v4i16 FPR64:$src))>; 7390def : Pat<(v2i32 (bitconvert (v4bf16 FPR64:$src))), 7391 (v2i32 (REV32v4i16 FPR64:$src))>; 7392} 7393def : Pat<(v2i32 (bitconvert (v2f32 FPR64:$src))), (v2i32 FPR64:$src)>; 7394 7395let Predicates = [IsLE] in { 7396def : Pat<(v4i16 (bitconvert (v1i64 FPR64:$src))), (v4i16 FPR64:$src)>; 7397def : Pat<(v4i16 (bitconvert (v2i32 FPR64:$src))), (v4i16 FPR64:$src)>; 7398def : Pat<(v4i16 (bitconvert (v8i8 FPR64:$src))), (v4i16 FPR64:$src)>; 7399def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))), (v4i16 FPR64:$src)>; 7400def : Pat<(v4i16 (bitconvert (v2f32 FPR64:$src))), (v4i16 FPR64:$src)>; 7401def : Pat<(v4i16 (bitconvert (v1f64 FPR64:$src))), (v4i16 FPR64:$src)>; 7402} 7403let Predicates = [IsBE] in { 7404def : Pat<(v4i16 (bitconvert (v1i64 FPR64:$src))), 7405 (v4i16 (REV64v4i16 FPR64:$src))>; 7406def : Pat<(v4i16 (bitconvert (v2i32 FPR64:$src))), 7407 (v4i16 (REV32v4i16 FPR64:$src))>; 7408def : Pat<(v4i16 (bitconvert (v8i8 FPR64:$src))), 7409 (v4i16 (REV16v8i8 FPR64:$src))>; 7410def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))), 7411 (v4i16 (REV64v4i16 FPR64:$src))>; 7412def : Pat<(v4i16 (bitconvert (v2f32 FPR64:$src))), 7413 (v4i16 (REV32v4i16 FPR64:$src))>; 7414def : Pat<(v4i16 (bitconvert (v1f64 FPR64:$src))), 7415 (v4i16 (REV64v4i16 FPR64:$src))>; 7416} 7417def : Pat<(v4i16 (bitconvert (v4f16 FPR64:$src))), (v4i16 FPR64:$src)>; 7418def : Pat<(v4i16 (bitconvert (v4bf16 FPR64:$src))), (v4i16 FPR64:$src)>; 7419 7420let Predicates = [IsLE] in { 7421def : Pat<(v4f16 (bitconvert (v1i64 FPR64:$src))), (v4f16 FPR64:$src)>; 7422def : Pat<(v4f16 (bitconvert (v2i32 FPR64:$src))), (v4f16 FPR64:$src)>; 7423def : Pat<(v4f16 (bitconvert (v8i8 FPR64:$src))), (v4f16 FPR64:$src)>; 7424def : Pat<(v4f16 (bitconvert (f64 FPR64:$src))), (v4f16 FPR64:$src)>; 7425def : Pat<(v4f16 (bitconvert (v2f32 FPR64:$src))), (v4f16 FPR64:$src)>; 7426def : Pat<(v4f16 (bitconvert (v1f64 FPR64:$src))), (v4f16 FPR64:$src)>; 7427 7428def : Pat<(v4bf16 (bitconvert (v1i64 FPR64:$src))), (v4bf16 FPR64:$src)>; 7429def : Pat<(v4bf16 (bitconvert (v2i32 FPR64:$src))), (v4bf16 FPR64:$src)>; 7430def : Pat<(v4bf16 (bitconvert (v8i8 FPR64:$src))), (v4bf16 FPR64:$src)>; 7431def : Pat<(v4bf16 (bitconvert (f64 FPR64:$src))), (v4bf16 FPR64:$src)>; 7432def : Pat<(v4bf16 (bitconvert (v2f32 FPR64:$src))), (v4bf16 FPR64:$src)>; 7433def : Pat<(v4bf16 (bitconvert (v1f64 FPR64:$src))), (v4bf16 FPR64:$src)>; 7434} 7435let Predicates = [IsBE] in { 7436def : Pat<(v4f16 (bitconvert (v1i64 FPR64:$src))), 7437 (v4f16 (REV64v4i16 FPR64:$src))>; 7438def : Pat<(v4f16 (bitconvert (v2i32 FPR64:$src))), 7439 (v4f16 (REV32v4i16 FPR64:$src))>; 7440def : Pat<(v4f16 (bitconvert (v8i8 FPR64:$src))), 7441 (v4f16 (REV16v8i8 FPR64:$src))>; 7442def : Pat<(v4f16 (bitconvert (f64 FPR64:$src))), 7443 (v4f16 (REV64v4i16 FPR64:$src))>; 7444def : Pat<(v4f16 (bitconvert (v2f32 FPR64:$src))), 7445 (v4f16 (REV32v4i16 FPR64:$src))>; 7446def : Pat<(v4f16 (bitconvert (v1f64 FPR64:$src))), 7447 (v4f16 (REV64v4i16 FPR64:$src))>; 7448 7449def : Pat<(v4bf16 (bitconvert (v1i64 FPR64:$src))), 7450 (v4bf16 (REV64v4i16 FPR64:$src))>; 7451def : Pat<(v4bf16 (bitconvert (v2i32 FPR64:$src))), 7452 (v4bf16 (REV32v4i16 FPR64:$src))>; 7453def : Pat<(v4bf16 (bitconvert (v8i8 FPR64:$src))), 7454 (v4bf16 (REV16v8i8 FPR64:$src))>; 7455def : Pat<(v4bf16 (bitconvert (f64 FPR64:$src))), 7456 (v4bf16 (REV64v4i16 FPR64:$src))>; 7457def : Pat<(v4bf16 (bitconvert (v2f32 FPR64:$src))), 7458 (v4bf16 (REV32v4i16 FPR64:$src))>; 7459def : Pat<(v4bf16 (bitconvert (v1f64 FPR64:$src))), 7460 (v4bf16 (REV64v4i16 FPR64:$src))>; 7461} 7462def : Pat<(v4f16 (bitconvert (v4i16 FPR64:$src))), (v4f16 FPR64:$src)>; 7463def : Pat<(v4bf16 (bitconvert (v4i16 FPR64:$src))), (v4bf16 FPR64:$src)>; 7464 7465let Predicates = [IsLE] in { 7466def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))), (v8i8 FPR64:$src)>; 7467def : Pat<(v8i8 (bitconvert (v2i32 FPR64:$src))), (v8i8 FPR64:$src)>; 7468def : Pat<(v8i8 (bitconvert (v4i16 FPR64:$src))), (v8i8 FPR64:$src)>; 7469def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))), (v8i8 FPR64:$src)>; 7470def : Pat<(v8i8 (bitconvert (v2f32 FPR64:$src))), (v8i8 FPR64:$src)>; 7471def : Pat<(v8i8 (bitconvert (v1f64 FPR64:$src))), (v8i8 FPR64:$src)>; 7472def : Pat<(v8i8 (bitconvert (v4f16 FPR64:$src))), (v8i8 FPR64:$src)>; 7473def : Pat<(v8i8 (bitconvert (v4bf16 FPR64:$src))), (v8i8 FPR64:$src)>; 7474} 7475let Predicates = [IsBE] in { 7476def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))), 7477 (v8i8 (REV64v8i8 FPR64:$src))>; 7478def : Pat<(v8i8 (bitconvert (v2i32 FPR64:$src))), 7479 (v8i8 (REV32v8i8 FPR64:$src))>; 7480def : Pat<(v8i8 (bitconvert (v4i16 FPR64:$src))), 7481 (v8i8 (REV16v8i8 FPR64:$src))>; 7482def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))), 7483 (v8i8 (REV64v8i8 FPR64:$src))>; 7484def : Pat<(v8i8 (bitconvert (v2f32 FPR64:$src))), 7485 (v8i8 (REV32v8i8 FPR64:$src))>; 7486def : Pat<(v8i8 (bitconvert (v1f64 FPR64:$src))), 7487 (v8i8 (REV64v8i8 FPR64:$src))>; 7488def : Pat<(v8i8 (bitconvert (v4f16 FPR64:$src))), 7489 (v8i8 (REV16v8i8 FPR64:$src))>; 7490def : Pat<(v8i8 (bitconvert (v4bf16 FPR64:$src))), 7491 (v8i8 (REV16v8i8 FPR64:$src))>; 7492} 7493 7494let Predicates = [IsLE] in { 7495def : Pat<(f64 (bitconvert (v2i32 FPR64:$src))), (f64 FPR64:$src)>; 7496def : Pat<(f64 (bitconvert (v4i16 FPR64:$src))), (f64 FPR64:$src)>; 7497def : Pat<(f64 (bitconvert (v2f32 FPR64:$src))), (f64 FPR64:$src)>; 7498def : Pat<(f64 (bitconvert (v8i8 FPR64:$src))), (f64 FPR64:$src)>; 7499def : Pat<(f64 (bitconvert (v4f16 FPR64:$src))), (f64 FPR64:$src)>; 7500def : Pat<(f64 (bitconvert (v4bf16 FPR64:$src))), (f64 FPR64:$src)>; 7501} 7502let Predicates = [IsBE] in { 7503def : Pat<(f64 (bitconvert (v2i32 FPR64:$src))), 7504 (f64 (REV64v2i32 FPR64:$src))>; 7505def : Pat<(f64 (bitconvert (v4i16 FPR64:$src))), 7506 (f64 (REV64v4i16 FPR64:$src))>; 7507def : Pat<(f64 (bitconvert (v2f32 FPR64:$src))), 7508 (f64 (REV64v2i32 FPR64:$src))>; 7509def : Pat<(f64 (bitconvert (v8i8 FPR64:$src))), 7510 (f64 (REV64v8i8 FPR64:$src))>; 7511def : Pat<(f64 (bitconvert (v4f16 FPR64:$src))), 7512 (f64 (REV64v4i16 FPR64:$src))>; 7513def : Pat<(f64 (bitconvert (v4bf16 FPR64:$src))), 7514 (f64 (REV64v4i16 FPR64:$src))>; 7515} 7516def : Pat<(f64 (bitconvert (v1i64 FPR64:$src))), (f64 FPR64:$src)>; 7517def : Pat<(f64 (bitconvert (v1f64 FPR64:$src))), (f64 FPR64:$src)>; 7518 7519let Predicates = [IsLE] in { 7520def : Pat<(v1f64 (bitconvert (v2i32 FPR64:$src))), (v1f64 FPR64:$src)>; 7521def : Pat<(v1f64 (bitconvert (v4i16 FPR64:$src))), (v1f64 FPR64:$src)>; 7522def : Pat<(v1f64 (bitconvert (v8i8 FPR64:$src))), (v1f64 FPR64:$src)>; 7523def : Pat<(v1f64 (bitconvert (v2f32 FPR64:$src))), (v1f64 FPR64:$src)>; 7524def : Pat<(v1f64 (bitconvert (v4f16 FPR64:$src))), (v1f64 FPR64:$src)>; 7525def : Pat<(v1f64 (bitconvert (v4bf16 FPR64:$src))), (v1f64 FPR64:$src)>; 7526} 7527let Predicates = [IsBE] in { 7528def : Pat<(v1f64 (bitconvert (v2i32 FPR64:$src))), 7529 (v1f64 (REV64v2i32 FPR64:$src))>; 7530def : Pat<(v1f64 (bitconvert (v4i16 FPR64:$src))), 7531 (v1f64 (REV64v4i16 FPR64:$src))>; 7532def : Pat<(v1f64 (bitconvert (v8i8 FPR64:$src))), 7533 (v1f64 (REV64v8i8 FPR64:$src))>; 7534def : Pat<(v1f64 (bitconvert (v2f32 FPR64:$src))), 7535 (v1f64 (REV64v2i32 FPR64:$src))>; 7536def : Pat<(v1f64 (bitconvert (v4f16 FPR64:$src))), 7537 (v1f64 (REV64v4i16 FPR64:$src))>; 7538def : Pat<(v1f64 (bitconvert (v4bf16 FPR64:$src))), 7539 (v1f64 (REV64v4i16 FPR64:$src))>; 7540} 7541def : Pat<(v1f64 (bitconvert (v1i64 FPR64:$src))), (v1f64 FPR64:$src)>; 7542def : Pat<(v1f64 (bitconvert (f64 FPR64:$src))), (v1f64 FPR64:$src)>; 7543 7544let Predicates = [IsLE] in { 7545def : Pat<(v2f32 (bitconvert (v1i64 FPR64:$src))), (v2f32 FPR64:$src)>; 7546def : Pat<(v2f32 (bitconvert (v4i16 FPR64:$src))), (v2f32 FPR64:$src)>; 7547def : Pat<(v2f32 (bitconvert (v8i8 FPR64:$src))), (v2f32 FPR64:$src)>; 7548def : Pat<(v2f32 (bitconvert (v1f64 FPR64:$src))), (v2f32 FPR64:$src)>; 7549def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))), (v2f32 FPR64:$src)>; 7550def : Pat<(v2f32 (bitconvert (v4f16 FPR64:$src))), (v2f32 FPR64:$src)>; 7551def : Pat<(v2f32 (bitconvert (v4bf16 FPR64:$src))), (v2f32 FPR64:$src)>; 7552} 7553let Predicates = [IsBE] in { 7554def : Pat<(v2f32 (bitconvert (v1i64 FPR64:$src))), 7555 (v2f32 (REV64v2i32 FPR64:$src))>; 7556def : Pat<(v2f32 (bitconvert (v4i16 FPR64:$src))), 7557 (v2f32 (REV32v4i16 FPR64:$src))>; 7558def : Pat<(v2f32 (bitconvert (v8i8 FPR64:$src))), 7559 (v2f32 (REV32v8i8 FPR64:$src))>; 7560def : Pat<(v2f32 (bitconvert (v1f64 FPR64:$src))), 7561 (v2f32 (REV64v2i32 FPR64:$src))>; 7562def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))), 7563 (v2f32 (REV64v2i32 FPR64:$src))>; 7564def : Pat<(v2f32 (bitconvert (v4f16 FPR64:$src))), 7565 (v2f32 (REV32v4i16 FPR64:$src))>; 7566def : Pat<(v2f32 (bitconvert (v4bf16 FPR64:$src))), 7567 (v2f32 (REV32v4i16 FPR64:$src))>; 7568} 7569def : Pat<(v2f32 (bitconvert (v2i32 FPR64:$src))), (v2f32 FPR64:$src)>; 7570 7571let Predicates = [IsLE] in { 7572def : Pat<(f128 (bitconvert (v2i64 FPR128:$src))), (f128 FPR128:$src)>; 7573def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))), (f128 FPR128:$src)>; 7574def : Pat<(f128 (bitconvert (v8i16 FPR128:$src))), (f128 FPR128:$src)>; 7575def : Pat<(f128 (bitconvert (v2f64 FPR128:$src))), (f128 FPR128:$src)>; 7576def : Pat<(f128 (bitconvert (v4f32 FPR128:$src))), (f128 FPR128:$src)>; 7577def : Pat<(f128 (bitconvert (v8f16 FPR128:$src))), (f128 FPR128:$src)>; 7578def : Pat<(f128 (bitconvert (v8bf16 FPR128:$src))), (f128 FPR128:$src)>; 7579def : Pat<(f128 (bitconvert (v16i8 FPR128:$src))), (f128 FPR128:$src)>; 7580} 7581let Predicates = [IsBE] in { 7582def : Pat<(f128 (bitconvert (v2i64 FPR128:$src))), 7583 (f128 (EXTv16i8 FPR128:$src, FPR128:$src, (i32 8)))>; 7584def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))), 7585 (f128 (EXTv16i8 (REV64v4i32 FPR128:$src), 7586 (REV64v4i32 FPR128:$src), (i32 8)))>; 7587def : Pat<(f128 (bitconvert (v8i16 FPR128:$src))), 7588 (f128 (EXTv16i8 (REV64v8i16 FPR128:$src), 7589 (REV64v8i16 FPR128:$src), (i32 8)))>; 7590def : Pat<(f128 (bitconvert (v8f16 FPR128:$src))), 7591 (f128 (EXTv16i8 (REV64v8i16 FPR128:$src), 7592 (REV64v8i16 FPR128:$src), (i32 8)))>; 7593def : Pat<(f128 (bitconvert (v8bf16 FPR128:$src))), 7594 (f128 (EXTv16i8 (REV64v8i16 FPR128:$src), 7595 (REV64v8i16 FPR128:$src), (i32 8)))>; 7596def : Pat<(f128 (bitconvert (v2f64 FPR128:$src))), 7597 (f128 (EXTv16i8 FPR128:$src, FPR128:$src, (i32 8)))>; 7598def : Pat<(f128 (bitconvert (v4f32 FPR128:$src))), 7599 (f128 (EXTv16i8 (REV64v4i32 FPR128:$src), 7600 (REV64v4i32 FPR128:$src), (i32 8)))>; 7601def : Pat<(f128 (bitconvert (v16i8 FPR128:$src))), 7602 (f128 (EXTv16i8 (REV64v16i8 FPR128:$src), 7603 (REV64v16i8 FPR128:$src), (i32 8)))>; 7604} 7605 7606let Predicates = [IsLE] in { 7607def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))), (v2f64 FPR128:$src)>; 7608def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))), (v2f64 FPR128:$src)>; 7609def : Pat<(v2f64 (bitconvert (v8i16 FPR128:$src))), (v2f64 FPR128:$src)>; 7610def : Pat<(v2f64 (bitconvert (v8f16 FPR128:$src))), (v2f64 FPR128:$src)>; 7611def : Pat<(v2f64 (bitconvert (v8bf16 FPR128:$src))), (v2f64 FPR128:$src)>; 7612def : Pat<(v2f64 (bitconvert (v16i8 FPR128:$src))), (v2f64 FPR128:$src)>; 7613def : Pat<(v2f64 (bitconvert (v4f32 FPR128:$src))), (v2f64 FPR128:$src)>; 7614} 7615let Predicates = [IsBE] in { 7616def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))), 7617 (v2f64 (EXTv16i8 FPR128:$src, 7618 FPR128:$src, (i32 8)))>; 7619def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))), 7620 (v2f64 (REV64v4i32 FPR128:$src))>; 7621def : Pat<(v2f64 (bitconvert (v8i16 FPR128:$src))), 7622 (v2f64 (REV64v8i16 FPR128:$src))>; 7623def : Pat<(v2f64 (bitconvert (v8f16 FPR128:$src))), 7624 (v2f64 (REV64v8i16 FPR128:$src))>; 7625def : Pat<(v2f64 (bitconvert (v8bf16 FPR128:$src))), 7626 (v2f64 (REV64v8i16 FPR128:$src))>; 7627def : Pat<(v2f64 (bitconvert (v16i8 FPR128:$src))), 7628 (v2f64 (REV64v16i8 FPR128:$src))>; 7629def : Pat<(v2f64 (bitconvert (v4f32 FPR128:$src))), 7630 (v2f64 (REV64v4i32 FPR128:$src))>; 7631} 7632def : Pat<(v2f64 (bitconvert (v2i64 FPR128:$src))), (v2f64 FPR128:$src)>; 7633 7634let Predicates = [IsLE] in { 7635def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))), (v4f32 FPR128:$src)>; 7636def : Pat<(v4f32 (bitconvert (v8i16 FPR128:$src))), (v4f32 FPR128:$src)>; 7637def : Pat<(v4f32 (bitconvert (v8f16 FPR128:$src))), (v4f32 FPR128:$src)>; 7638def : Pat<(v4f32 (bitconvert (v8bf16 FPR128:$src))), (v4f32 FPR128:$src)>; 7639def : Pat<(v4f32 (bitconvert (v16i8 FPR128:$src))), (v4f32 FPR128:$src)>; 7640def : Pat<(v4f32 (bitconvert (v2i64 FPR128:$src))), (v4f32 FPR128:$src)>; 7641def : Pat<(v4f32 (bitconvert (v2f64 FPR128:$src))), (v4f32 FPR128:$src)>; 7642} 7643let Predicates = [IsBE] in { 7644def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))), 7645 (v4f32 (EXTv16i8 (REV64v4i32 FPR128:$src), 7646 (REV64v4i32 FPR128:$src), (i32 8)))>; 7647def : Pat<(v4f32 (bitconvert (v8i16 FPR128:$src))), 7648 (v4f32 (REV32v8i16 FPR128:$src))>; 7649def : Pat<(v4f32 (bitconvert (v8f16 FPR128:$src))), 7650 (v4f32 (REV32v8i16 FPR128:$src))>; 7651def : Pat<(v4f32 (bitconvert (v8bf16 FPR128:$src))), 7652 (v4f32 (REV32v8i16 FPR128:$src))>; 7653def : Pat<(v4f32 (bitconvert (v16i8 FPR128:$src))), 7654 (v4f32 (REV32v16i8 FPR128:$src))>; 7655def : Pat<(v4f32 (bitconvert (v2i64 FPR128:$src))), 7656 (v4f32 (REV64v4i32 FPR128:$src))>; 7657def : Pat<(v4f32 (bitconvert (v2f64 FPR128:$src))), 7658 (v4f32 (REV64v4i32 FPR128:$src))>; 7659} 7660def : Pat<(v4f32 (bitconvert (v4i32 FPR128:$src))), (v4f32 FPR128:$src)>; 7661 7662let Predicates = [IsLE] in { 7663def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))), (v2i64 FPR128:$src)>; 7664def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))), (v2i64 FPR128:$src)>; 7665def : Pat<(v2i64 (bitconvert (v8i16 FPR128:$src))), (v2i64 FPR128:$src)>; 7666def : Pat<(v2i64 (bitconvert (v16i8 FPR128:$src))), (v2i64 FPR128:$src)>; 7667def : Pat<(v2i64 (bitconvert (v4f32 FPR128:$src))), (v2i64 FPR128:$src)>; 7668def : Pat<(v2i64 (bitconvert (v8f16 FPR128:$src))), (v2i64 FPR128:$src)>; 7669def : Pat<(v2i64 (bitconvert (v8bf16 FPR128:$src))), (v2i64 FPR128:$src)>; 7670} 7671let Predicates = [IsBE] in { 7672def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))), 7673 (v2i64 (EXTv16i8 FPR128:$src, 7674 FPR128:$src, (i32 8)))>; 7675def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))), 7676 (v2i64 (REV64v4i32 FPR128:$src))>; 7677def : Pat<(v2i64 (bitconvert (v8i16 FPR128:$src))), 7678 (v2i64 (REV64v8i16 FPR128:$src))>; 7679def : Pat<(v2i64 (bitconvert (v16i8 FPR128:$src))), 7680 (v2i64 (REV64v16i8 FPR128:$src))>; 7681def : Pat<(v2i64 (bitconvert (v4f32 FPR128:$src))), 7682 (v2i64 (REV64v4i32 FPR128:$src))>; 7683def : Pat<(v2i64 (bitconvert (v8f16 FPR128:$src))), 7684 (v2i64 (REV64v8i16 FPR128:$src))>; 7685def : Pat<(v2i64 (bitconvert (v8bf16 FPR128:$src))), 7686 (v2i64 (REV64v8i16 FPR128:$src))>; 7687} 7688def : Pat<(v2i64 (bitconvert (v2f64 FPR128:$src))), (v2i64 FPR128:$src)>; 7689 7690let Predicates = [IsLE] in { 7691def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))), (v4i32 FPR128:$src)>; 7692def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))), (v4i32 FPR128:$src)>; 7693def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))), (v4i32 FPR128:$src)>; 7694def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))), (v4i32 FPR128:$src)>; 7695def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))), (v4i32 FPR128:$src)>; 7696def : Pat<(v4i32 (bitconvert (v8f16 FPR128:$src))), (v4i32 FPR128:$src)>; 7697def : Pat<(v4i32 (bitconvert (v8bf16 FPR128:$src))), (v4i32 FPR128:$src)>; 7698} 7699let Predicates = [IsBE] in { 7700def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))), 7701 (v4i32 (EXTv16i8 (REV64v4i32 FPR128:$src), 7702 (REV64v4i32 FPR128:$src), 7703 (i32 8)))>; 7704def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))), 7705 (v4i32 (REV64v4i32 FPR128:$src))>; 7706def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))), 7707 (v4i32 (REV32v8i16 FPR128:$src))>; 7708def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))), 7709 (v4i32 (REV32v16i8 FPR128:$src))>; 7710def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))), 7711 (v4i32 (REV64v4i32 FPR128:$src))>; 7712def : Pat<(v4i32 (bitconvert (v8f16 FPR128:$src))), 7713 (v4i32 (REV32v8i16 FPR128:$src))>; 7714def : Pat<(v4i32 (bitconvert (v8bf16 FPR128:$src))), 7715 (v4i32 (REV32v8i16 FPR128:$src))>; 7716} 7717def : Pat<(v4i32 (bitconvert (v4f32 FPR128:$src))), (v4i32 FPR128:$src)>; 7718 7719let Predicates = [IsLE] in { 7720def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))), (v8i16 FPR128:$src)>; 7721def : Pat<(v8i16 (bitconvert (v2i64 FPR128:$src))), (v8i16 FPR128:$src)>; 7722def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))), (v8i16 FPR128:$src)>; 7723def : Pat<(v8i16 (bitconvert (v16i8 FPR128:$src))), (v8i16 FPR128:$src)>; 7724def : Pat<(v8i16 (bitconvert (v2f64 FPR128:$src))), (v8i16 FPR128:$src)>; 7725def : Pat<(v8i16 (bitconvert (v4f32 FPR128:$src))), (v8i16 FPR128:$src)>; 7726} 7727let Predicates = [IsBE] in { 7728def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))), 7729 (v8i16 (EXTv16i8 (REV64v8i16 FPR128:$src), 7730 (REV64v8i16 FPR128:$src), 7731 (i32 8)))>; 7732def : Pat<(v8i16 (bitconvert (v2i64 FPR128:$src))), 7733 (v8i16 (REV64v8i16 FPR128:$src))>; 7734def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))), 7735 (v8i16 (REV32v8i16 FPR128:$src))>; 7736def : Pat<(v8i16 (bitconvert (v16i8 FPR128:$src))), 7737 (v8i16 (REV16v16i8 FPR128:$src))>; 7738def : Pat<(v8i16 (bitconvert (v2f64 FPR128:$src))), 7739 (v8i16 (REV64v8i16 FPR128:$src))>; 7740def : Pat<(v8i16 (bitconvert (v4f32 FPR128:$src))), 7741 (v8i16 (REV32v8i16 FPR128:$src))>; 7742} 7743def : Pat<(v8i16 (bitconvert (v8f16 FPR128:$src))), (v8i16 FPR128:$src)>; 7744def : Pat<(v8i16 (bitconvert (v8bf16 FPR128:$src))), (v8i16 FPR128:$src)>; 7745 7746let Predicates = [IsLE] in { 7747def : Pat<(v8f16 (bitconvert (f128 FPR128:$src))), (v8f16 FPR128:$src)>; 7748def : Pat<(v8f16 (bitconvert (v2i64 FPR128:$src))), (v8f16 FPR128:$src)>; 7749def : Pat<(v8f16 (bitconvert (v4i32 FPR128:$src))), (v8f16 FPR128:$src)>; 7750def : Pat<(v8f16 (bitconvert (v16i8 FPR128:$src))), (v8f16 FPR128:$src)>; 7751def : Pat<(v8f16 (bitconvert (v2f64 FPR128:$src))), (v8f16 FPR128:$src)>; 7752def : Pat<(v8f16 (bitconvert (v4f32 FPR128:$src))), (v8f16 FPR128:$src)>; 7753 7754def : Pat<(v8bf16 (bitconvert (f128 FPR128:$src))), (v8bf16 FPR128:$src)>; 7755def : Pat<(v8bf16 (bitconvert (v2i64 FPR128:$src))), (v8bf16 FPR128:$src)>; 7756def : Pat<(v8bf16 (bitconvert (v4i32 FPR128:$src))), (v8bf16 FPR128:$src)>; 7757def : Pat<(v8bf16 (bitconvert (v16i8 FPR128:$src))), (v8bf16 FPR128:$src)>; 7758def : Pat<(v8bf16 (bitconvert (v2f64 FPR128:$src))), (v8bf16 FPR128:$src)>; 7759def : Pat<(v8bf16 (bitconvert (v4f32 FPR128:$src))), (v8bf16 FPR128:$src)>; 7760} 7761let Predicates = [IsBE] in { 7762def : Pat<(v8f16 (bitconvert (f128 FPR128:$src))), 7763 (v8f16 (EXTv16i8 (REV64v8i16 FPR128:$src), 7764 (REV64v8i16 FPR128:$src), 7765 (i32 8)))>; 7766def : Pat<(v8f16 (bitconvert (v2i64 FPR128:$src))), 7767 (v8f16 (REV64v8i16 FPR128:$src))>; 7768def : Pat<(v8f16 (bitconvert (v4i32 FPR128:$src))), 7769 (v8f16 (REV32v8i16 FPR128:$src))>; 7770def : Pat<(v8f16 (bitconvert (v16i8 FPR128:$src))), 7771 (v8f16 (REV16v16i8 FPR128:$src))>; 7772def : Pat<(v8f16 (bitconvert (v2f64 FPR128:$src))), 7773 (v8f16 (REV64v8i16 FPR128:$src))>; 7774def : Pat<(v8f16 (bitconvert (v4f32 FPR128:$src))), 7775 (v8f16 (REV32v8i16 FPR128:$src))>; 7776 7777def : Pat<(v8bf16 (bitconvert (f128 FPR128:$src))), 7778 (v8bf16 (EXTv16i8 (REV64v8i16 FPR128:$src), 7779 (REV64v8i16 FPR128:$src), 7780 (i32 8)))>; 7781def : Pat<(v8bf16 (bitconvert (v2i64 FPR128:$src))), 7782 (v8bf16 (REV64v8i16 FPR128:$src))>; 7783def : Pat<(v8bf16 (bitconvert (v4i32 FPR128:$src))), 7784 (v8bf16 (REV32v8i16 FPR128:$src))>; 7785def : Pat<(v8bf16 (bitconvert (v16i8 FPR128:$src))), 7786 (v8bf16 (REV16v16i8 FPR128:$src))>; 7787def : Pat<(v8bf16 (bitconvert (v2f64 FPR128:$src))), 7788 (v8bf16 (REV64v8i16 FPR128:$src))>; 7789def : Pat<(v8bf16 (bitconvert (v4f32 FPR128:$src))), 7790 (v8bf16 (REV32v8i16 FPR128:$src))>; 7791} 7792def : Pat<(v8f16 (bitconvert (v8i16 FPR128:$src))), (v8f16 FPR128:$src)>; 7793def : Pat<(v8bf16 (bitconvert (v8i16 FPR128:$src))), (v8bf16 FPR128:$src)>; 7794 7795let Predicates = [IsLE] in { 7796def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))), (v16i8 FPR128:$src)>; 7797def : Pat<(v16i8 (bitconvert (v2i64 FPR128:$src))), (v16i8 FPR128:$src)>; 7798def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))), (v16i8 FPR128:$src)>; 7799def : Pat<(v16i8 (bitconvert (v8i16 FPR128:$src))), (v16i8 FPR128:$src)>; 7800def : Pat<(v16i8 (bitconvert (v2f64 FPR128:$src))), (v16i8 FPR128:$src)>; 7801def : Pat<(v16i8 (bitconvert (v4f32 FPR128:$src))), (v16i8 FPR128:$src)>; 7802def : Pat<(v16i8 (bitconvert (v8f16 FPR128:$src))), (v16i8 FPR128:$src)>; 7803def : Pat<(v16i8 (bitconvert (v8bf16 FPR128:$src))), (v16i8 FPR128:$src)>; 7804} 7805let Predicates = [IsBE] in { 7806def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))), 7807 (v16i8 (EXTv16i8 (REV64v16i8 FPR128:$src), 7808 (REV64v16i8 FPR128:$src), 7809 (i32 8)))>; 7810def : Pat<(v16i8 (bitconvert (v2i64 FPR128:$src))), 7811 (v16i8 (REV64v16i8 FPR128:$src))>; 7812def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))), 7813 (v16i8 (REV32v16i8 FPR128:$src))>; 7814def : Pat<(v16i8 (bitconvert (v8i16 FPR128:$src))), 7815 (v16i8 (REV16v16i8 FPR128:$src))>; 7816def : Pat<(v16i8 (bitconvert (v2f64 FPR128:$src))), 7817 (v16i8 (REV64v16i8 FPR128:$src))>; 7818def : Pat<(v16i8 (bitconvert (v4f32 FPR128:$src))), 7819 (v16i8 (REV32v16i8 FPR128:$src))>; 7820def : Pat<(v16i8 (bitconvert (v8f16 FPR128:$src))), 7821 (v16i8 (REV16v16i8 FPR128:$src))>; 7822def : Pat<(v16i8 (bitconvert (v8bf16 FPR128:$src))), 7823 (v16i8 (REV16v16i8 FPR128:$src))>; 7824} 7825 7826def : Pat<(v4i16 (extract_subvector V128:$Rn, (i64 0))), 7827 (EXTRACT_SUBREG V128:$Rn, dsub)>; 7828def : Pat<(v8i8 (extract_subvector V128:$Rn, (i64 0))), 7829 (EXTRACT_SUBREG V128:$Rn, dsub)>; 7830def : Pat<(v2f32 (extract_subvector V128:$Rn, (i64 0))), 7831 (EXTRACT_SUBREG V128:$Rn, dsub)>; 7832def : Pat<(v4f16 (extract_subvector V128:$Rn, (i64 0))), 7833 (EXTRACT_SUBREG V128:$Rn, dsub)>; 7834def : Pat<(v4bf16 (extract_subvector V128:$Rn, (i64 0))), 7835 (EXTRACT_SUBREG V128:$Rn, dsub)>; 7836def : Pat<(v2i32 (extract_subvector V128:$Rn, (i64 0))), 7837 (EXTRACT_SUBREG V128:$Rn, dsub)>; 7838def : Pat<(v1i64 (extract_subvector V128:$Rn, (i64 0))), 7839 (EXTRACT_SUBREG V128:$Rn, dsub)>; 7840def : Pat<(v1f64 (extract_subvector V128:$Rn, (i64 0))), 7841 (EXTRACT_SUBREG V128:$Rn, dsub)>; 7842 7843def : Pat<(v8i8 (extract_subvector (v16i8 FPR128:$Rn), (i64 1))), 7844 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>; 7845def : Pat<(v4i16 (extract_subvector (v8i16 FPR128:$Rn), (i64 1))), 7846 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>; 7847def : Pat<(v2i32 (extract_subvector (v4i32 FPR128:$Rn), (i64 1))), 7848 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>; 7849def : Pat<(v1i64 (extract_subvector (v2i64 FPR128:$Rn), (i64 1))), 7850 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>; 7851 7852// A 64-bit subvector insert to the first 128-bit vector position 7853// is a subregister copy that needs no instruction. 7854multiclass InsertSubvectorUndef<ValueType Ty> { 7855 def : Pat<(insert_subvector undef, (v1i64 FPR64:$src), (Ty 0)), 7856 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), FPR64:$src, dsub)>; 7857 def : Pat<(insert_subvector undef, (v1f64 FPR64:$src), (Ty 0)), 7858 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$src, dsub)>; 7859 def : Pat<(insert_subvector undef, (v2i32 FPR64:$src), (Ty 0)), 7860 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$src, dsub)>; 7861 def : Pat<(insert_subvector undef, (v2f32 FPR64:$src), (Ty 0)), 7862 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR64:$src, dsub)>; 7863 def : Pat<(insert_subvector undef, (v4i16 FPR64:$src), (Ty 0)), 7864 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR64:$src, dsub)>; 7865 def : Pat<(insert_subvector undef, (v4f16 FPR64:$src), (Ty 0)), 7866 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR64:$src, dsub)>; 7867 def : Pat<(insert_subvector undef, (v4bf16 FPR64:$src), (Ty 0)), 7868 (INSERT_SUBREG (v8bf16 (IMPLICIT_DEF)), FPR64:$src, dsub)>; 7869 def : Pat<(insert_subvector undef, (v8i8 FPR64:$src), (Ty 0)), 7870 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), FPR64:$src, dsub)>; 7871} 7872 7873defm : InsertSubvectorUndef<i32>; 7874defm : InsertSubvectorUndef<i64>; 7875 7876// Use pair-wise add instructions when summing up the lanes for v2f64, v2i64 7877// or v2f32. 7878def : Pat<(i64 (add (vector_extract (v2i64 FPR128:$Rn), (i64 0)), 7879 (vector_extract (v2i64 FPR128:$Rn), (i64 1)))), 7880 (i64 (ADDPv2i64p (v2i64 FPR128:$Rn)))>; 7881def : Pat<(f64 (fadd (vector_extract (v2f64 FPR128:$Rn), (i64 0)), 7882 (vector_extract (v2f64 FPR128:$Rn), (i64 1)))), 7883 (f64 (FADDPv2i64p (v2f64 FPR128:$Rn)))>; 7884 // vector_extract on 64-bit vectors gets promoted to a 128 bit vector, 7885 // so we match on v4f32 here, not v2f32. This will also catch adding 7886 // the low two lanes of a true v4f32 vector. 7887def : Pat<(fadd (vector_extract (v4f32 FPR128:$Rn), (i64 0)), 7888 (vector_extract (v4f32 FPR128:$Rn), (i64 1))), 7889 (f32 (FADDPv2i32p (EXTRACT_SUBREG FPR128:$Rn, dsub)))>; 7890def : Pat<(fadd (vector_extract (v8f16 FPR128:$Rn), (i64 0)), 7891 (vector_extract (v8f16 FPR128:$Rn), (i64 1))), 7892 (f16 (FADDPv2i16p (EXTRACT_SUBREG FPR128:$Rn, dsub)))>; 7893 7894// Scalar 64-bit shifts in FPR64 registers. 7895def : Pat<(i64 (int_aarch64_neon_sshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))), 7896 (SSHLv1i64 FPR64:$Rn, FPR64:$Rm)>; 7897def : Pat<(i64 (int_aarch64_neon_ushl (i64 FPR64:$Rn), (i64 FPR64:$Rm))), 7898 (USHLv1i64 FPR64:$Rn, FPR64:$Rm)>; 7899def : Pat<(i64 (int_aarch64_neon_srshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))), 7900 (SRSHLv1i64 FPR64:$Rn, FPR64:$Rm)>; 7901def : Pat<(i64 (int_aarch64_neon_urshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))), 7902 (URSHLv1i64 FPR64:$Rn, FPR64:$Rm)>; 7903 7904// Patterns for nontemporal/no-allocate stores. 7905// We have to resort to tricks to turn a single-input store into a store pair, 7906// because there is no single-input nontemporal store, only STNP. 7907let Predicates = [IsLE] in { 7908let AddedComplexity = 15 in { 7909class NTStore128Pat<ValueType VT> : 7910 Pat<(nontemporalstore (VT FPR128:$Rt), 7911 (am_indexed7s64 GPR64sp:$Rn, simm7s8:$offset)), 7912 (STNPDi (EXTRACT_SUBREG FPR128:$Rt, dsub), 7913 (CPYi64 FPR128:$Rt, (i64 1)), 7914 GPR64sp:$Rn, simm7s8:$offset)>; 7915 7916def : NTStore128Pat<v2i64>; 7917def : NTStore128Pat<v4i32>; 7918def : NTStore128Pat<v8i16>; 7919def : NTStore128Pat<v16i8>; 7920 7921class NTStore64Pat<ValueType VT> : 7922 Pat<(nontemporalstore (VT FPR64:$Rt), 7923 (am_indexed7s32 GPR64sp:$Rn, simm7s4:$offset)), 7924 (STNPSi (EXTRACT_SUBREG FPR64:$Rt, ssub), 7925 (CPYi32 (SUBREG_TO_REG (i64 0), FPR64:$Rt, dsub), (i64 1)), 7926 GPR64sp:$Rn, simm7s4:$offset)>; 7927 7928// FIXME: Shouldn't v1f64 loads/stores be promoted to v1i64? 7929def : NTStore64Pat<v1f64>; 7930def : NTStore64Pat<v1i64>; 7931def : NTStore64Pat<v2i32>; 7932def : NTStore64Pat<v4i16>; 7933def : NTStore64Pat<v8i8>; 7934 7935def : Pat<(nontemporalstore GPR64:$Rt, 7936 (am_indexed7s32 GPR64sp:$Rn, simm7s4:$offset)), 7937 (STNPWi (EXTRACT_SUBREG GPR64:$Rt, sub_32), 7938 (EXTRACT_SUBREG (UBFMXri GPR64:$Rt, 32, 63), sub_32), 7939 GPR64sp:$Rn, simm7s4:$offset)>; 7940} // AddedComplexity=10 7941} // Predicates = [IsLE] 7942 7943// Tail call return handling. These are all compiler pseudo-instructions, 7944// so no encoding information or anything like that. 7945let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in { 7946 def TCRETURNdi : Pseudo<(outs), (ins i64imm:$dst, i32imm:$FPDiff), []>, 7947 Sched<[WriteBrReg]>; 7948 def TCRETURNri : Pseudo<(outs), (ins tcGPR64:$dst, i32imm:$FPDiff), []>, 7949 Sched<[WriteBrReg]>; 7950 // Indirect tail-call with any register allowed, used by MachineOutliner when 7951 // this is proven safe. 7952 // FIXME: If we have to add any more hacks like this, we should instead relax 7953 // some verifier checks for outlined functions. 7954 def TCRETURNriALL : Pseudo<(outs), (ins GPR64:$dst, i32imm:$FPDiff), []>, 7955 Sched<[WriteBrReg]>; 7956 // Indirect tail-call limited to only use registers (x16 and x17) which are 7957 // allowed to tail-call a "BTI c" instruction. 7958 def TCRETURNriBTI : Pseudo<(outs), (ins rtcGPR64:$dst, i32imm:$FPDiff), []>, 7959 Sched<[WriteBrReg]>; 7960} 7961 7962def : Pat<(AArch64tcret tcGPR64:$dst, (i32 timm:$FPDiff)), 7963 (TCRETURNri tcGPR64:$dst, imm:$FPDiff)>, 7964 Requires<[NotUseBTI]>; 7965def : Pat<(AArch64tcret rtcGPR64:$dst, (i32 timm:$FPDiff)), 7966 (TCRETURNriBTI rtcGPR64:$dst, imm:$FPDiff)>, 7967 Requires<[UseBTI]>; 7968def : Pat<(AArch64tcret tglobaladdr:$dst, (i32 timm:$FPDiff)), 7969 (TCRETURNdi texternalsym:$dst, imm:$FPDiff)>; 7970def : Pat<(AArch64tcret texternalsym:$dst, (i32 timm:$FPDiff)), 7971 (TCRETURNdi texternalsym:$dst, imm:$FPDiff)>; 7972 7973def MOVMCSym : Pseudo<(outs GPR64:$dst), (ins i64imm:$sym), []>, Sched<[]>; 7974def : Pat<(i64 (AArch64LocalRecover mcsym:$sym)), (MOVMCSym mcsym:$sym)>; 7975 7976// Extracting lane zero is a special case where we can just use a plain 7977// EXTRACT_SUBREG instruction, which will become FMOV. This is easier for the 7978// rest of the compiler, especially the register allocator and copy propagation, 7979// to reason about, so is preferred when it's possible to use it. 7980let AddedComplexity = 10 in { 7981 def : Pat<(i64 (extractelt (v2i64 V128:$V), (i64 0))), (EXTRACT_SUBREG V128:$V, dsub)>; 7982 def : Pat<(i32 (extractelt (v4i32 V128:$V), (i64 0))), (EXTRACT_SUBREG V128:$V, ssub)>; 7983 def : Pat<(i32 (extractelt (v2i32 V64:$V), (i64 0))), (EXTRACT_SUBREG V64:$V, ssub)>; 7984} 7985 7986// dot_v4i8 7987class mul_v4i8<SDPatternOperator ldop> : 7988 PatFrag<(ops node:$Rn, node:$Rm, node:$offset), 7989 (mul (ldop (add node:$Rn, node:$offset)), 7990 (ldop (add node:$Rm, node:$offset)))>; 7991class mulz_v4i8<SDPatternOperator ldop> : 7992 PatFrag<(ops node:$Rn, node:$Rm), 7993 (mul (ldop node:$Rn), (ldop node:$Rm))>; 7994 7995def load_v4i8 : 7996 OutPatFrag<(ops node:$R), 7997 (INSERT_SUBREG 7998 (v2i32 (IMPLICIT_DEF)), 7999 (i32 (COPY_TO_REGCLASS (LDRWui node:$R, (i64 0)), FPR32)), 8000 ssub)>; 8001 8002class dot_v4i8<Instruction DOT, SDPatternOperator ldop> : 8003 Pat<(i32 (add (mul_v4i8<ldop> GPR64sp:$Rn, GPR64sp:$Rm, (i64 3)), 8004 (add (mul_v4i8<ldop> GPR64sp:$Rn, GPR64sp:$Rm, (i64 2)), 8005 (add (mul_v4i8<ldop> GPR64sp:$Rn, GPR64sp:$Rm, (i64 1)), 8006 (mulz_v4i8<ldop> GPR64sp:$Rn, GPR64sp:$Rm))))), 8007 (EXTRACT_SUBREG (i64 (DOT (DUPv2i32gpr WZR), 8008 (load_v4i8 GPR64sp:$Rn), 8009 (load_v4i8 GPR64sp:$Rm))), 8010 sub_32)>, Requires<[HasDotProd]>; 8011 8012// dot_v8i8 8013class ee_v8i8<SDPatternOperator extend> : 8014 PatFrag<(ops node:$V, node:$K), 8015 (v4i16 (extract_subvector (v8i16 (extend node:$V)), node:$K))>; 8016 8017class mul_v8i8<SDPatternOperator mulop, SDPatternOperator extend> : 8018 PatFrag<(ops node:$M, node:$N, node:$K), 8019 (mulop (v4i16 (ee_v8i8<extend> node:$M, node:$K)), 8020 (v4i16 (ee_v8i8<extend> node:$N, node:$K)))>; 8021 8022class idot_v8i8<SDPatternOperator mulop, SDPatternOperator extend> : 8023 PatFrag<(ops node:$M, node:$N), 8024 (i32 (extractelt 8025 (v4i32 (AArch64uaddv 8026 (add (mul_v8i8<mulop, extend> node:$M, node:$N, (i64 0)), 8027 (mul_v8i8<mulop, extend> node:$M, node:$N, (i64 4))))), 8028 (i64 0)))>; 8029 8030// vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm 8031def VADDV_32 : OutPatFrag<(ops node:$R), (ADDPv2i32 node:$R, node:$R)>; 8032 8033class odot_v8i8<Instruction DOT> : 8034 OutPatFrag<(ops node:$Vm, node:$Vn), 8035 (EXTRACT_SUBREG 8036 (VADDV_32 8037 (i64 (DOT (DUPv2i32gpr WZR), 8038 (v8i8 node:$Vm), 8039 (v8i8 node:$Vn)))), 8040 sub_32)>; 8041 8042class dot_v8i8<Instruction DOT, SDPatternOperator mulop, 8043 SDPatternOperator extend> : 8044 Pat<(idot_v8i8<mulop, extend> V64:$Vm, V64:$Vn), 8045 (odot_v8i8<DOT> V64:$Vm, V64:$Vn)>, 8046 Requires<[HasDotProd]>; 8047 8048// dot_v16i8 8049class ee_v16i8<SDPatternOperator extend> : 8050 PatFrag<(ops node:$V, node:$K1, node:$K2), 8051 (v4i16 (extract_subvector 8052 (v8i16 (extend 8053 (v8i8 (extract_subvector node:$V, node:$K1)))), node:$K2))>; 8054 8055class mul_v16i8<SDPatternOperator mulop, SDPatternOperator extend> : 8056 PatFrag<(ops node:$M, node:$N, node:$K1, node:$K2), 8057 (v4i32 8058 (mulop (v4i16 (ee_v16i8<extend> node:$M, node:$K1, node:$K2)), 8059 (v4i16 (ee_v16i8<extend> node:$N, node:$K1, node:$K2))))>; 8060 8061class idot_v16i8<SDPatternOperator m, SDPatternOperator x> : 8062 PatFrag<(ops node:$M, node:$N), 8063 (i32 (extractelt 8064 (v4i32 (AArch64uaddv 8065 (add 8066 (add (mul_v16i8<m, x> node:$M, node:$N, (i64 0), (i64 0)), 8067 (mul_v16i8<m, x> node:$M, node:$N, (i64 8), (i64 0))), 8068 (add (mul_v16i8<m, x> node:$M, node:$N, (i64 0), (i64 4)), 8069 (mul_v16i8<m, x> node:$M, node:$N, (i64 8), (i64 4)))))), 8070 (i64 0)))>; 8071 8072class odot_v16i8<Instruction DOT> : 8073 OutPatFrag<(ops node:$Vm, node:$Vn), 8074 (i32 (ADDVv4i32v 8075 (DOT (DUPv4i32gpr WZR), node:$Vm, node:$Vn)))>; 8076 8077class dot_v16i8<Instruction DOT, SDPatternOperator mulop, 8078 SDPatternOperator extend> : 8079 Pat<(idot_v16i8<mulop, extend> V128:$Vm, V128:$Vn), 8080 (odot_v16i8<DOT> V128:$Vm, V128:$Vn)>, 8081 Requires<[HasDotProd]>; 8082 8083let AddedComplexity = 10 in { 8084 def : dot_v4i8<SDOTv8i8, sextloadi8>; 8085 def : dot_v4i8<UDOTv8i8, zextloadi8>; 8086 def : dot_v8i8<SDOTv8i8, AArch64smull, sext>; 8087 def : dot_v8i8<UDOTv8i8, AArch64umull, zext>; 8088 def : dot_v16i8<SDOTv16i8, AArch64smull, sext>; 8089 def : dot_v16i8<UDOTv16i8, AArch64umull, zext>; 8090 8091 // FIXME: add patterns to generate vector by element dot product. 8092 // FIXME: add SVE dot-product patterns. 8093} 8094 8095let Predicates = [HasLS64] in { 8096 def LD64B: LoadStore64B<0b101, "ld64b", (ins GPR64sp:$Rn), 8097 (outs GPR64x8:$Rt)>; 8098 def ST64B: LoadStore64B<0b001, "st64b", (ins GPR64x8:$Rt, GPR64sp:$Rn), 8099 (outs)>; 8100 def ST64BV: Store64BV<0b011, "st64bv">; 8101 def ST64BV0: Store64BV<0b010, "st64bv0">; 8102 8103 class ST64BPattern<Intrinsic intrinsic, Instruction instruction> 8104 : Pat<(intrinsic GPR64sp:$addr, GPR64:$x0, GPR64:$x1, GPR64:$x2, GPR64:$x3, GPR64:$x4, GPR64:$x5, GPR64:$x6, GPR64:$x7), 8105 (instruction (REG_SEQUENCE GPR64x8Class, $x0, x8sub_0, $x1, x8sub_1, $x2, x8sub_2, $x3, x8sub_3, $x4, x8sub_4, $x5, x8sub_5, $x6, x8sub_6, $x7, x8sub_7), $addr)>; 8106 8107 def : ST64BPattern<int_aarch64_st64b, ST64B>; 8108 def : ST64BPattern<int_aarch64_st64bv, ST64BV>; 8109 def : ST64BPattern<int_aarch64_st64bv0, ST64BV0>; 8110} 8111 8112let Defs = [X16, X17], mayStore = 1, isCodeGenOnly = 1 in 8113def StoreSwiftAsyncContext 8114 : Pseudo<(outs), (ins GPR64:$ctx, GPR64sp:$base, simm9:$offset), 8115 []>, Sched<[]>; 8116 8117include "AArch64InstrAtomics.td" 8118include "AArch64SVEInstrInfo.td" 8119include "AArch64SMEInstrInfo.td" 8120include "AArch64InstrGISel.td" 8121