1//==- AArch64SchedA53.td - Cortex-A53 Scheduling Definitions -*- tablegen -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the itinerary class data for the ARM Cortex A53 processors.
10//
11//===----------------------------------------------------------------------===//
12
13// ===---------------------------------------------------------------------===//
14// The following definitions describe the simpler per-operand machine model.
15// This works with MachineScheduler. See MCSchedule.h for details.
16
17// Cortex-A53 machine model for scheduling and other instruction cost heuristics.
18def CortexA53Model : SchedMachineModel {
19  let MicroOpBufferSize = 0; // Explicitly set to zero since A53 is in-order.
20  let IssueWidth = 2;        // 2 micro-ops are dispatched per cycle.
21  let LoadLatency = 3;       // Optimistic load latency assuming bypass.
22                             // This is overriden by OperandCycles if the
23                             // Itineraries are queried instead.
24  let MispredictPenalty = 9; // Based on "Cortex-A53 Software Optimisation
25                             // Specification - Instruction Timings"
26                             // v 1.0 Spreadsheet
27  let CompleteModel = 1;
28
29  list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
30                                                    PAUnsupported.F,
31                                                    SMEUnsupported.F);
32}
33
34
35//===----------------------------------------------------------------------===//
36// Define each kind of processor resource and number available.
37
38// Modeling each pipeline as a ProcResource using the BufferSize = 0 since
39// Cortex-A53 is in-order.
40
41def A53UnitALU    : ProcResource<2> { let BufferSize = 0; } // Int ALU
42def A53UnitMAC    : ProcResource<1> { let BufferSize = 0; } // Int MAC
43def A53UnitDiv    : ProcResource<1> { let BufferSize = 0; } // Int Division
44def A53UnitLdSt   : ProcResource<1> { let BufferSize = 0; } // Load/Store
45def A53UnitB      : ProcResource<1> { let BufferSize = 0; } // Branch
46def A53UnitFPALU  : ProcResource<1> { let BufferSize = 0; } // FP ALU
47def A53UnitFPMDS  : ProcResource<1> { let BufferSize = 0; } // FP Mult/Div/Sqrt
48
49
50//===----------------------------------------------------------------------===//
51// Subtarget-specific SchedWrite types which both map the ProcResources and
52// set the latency.
53
54let SchedModel = CortexA53Model in {
55
56// ALU - Despite having a full latency of 4, most of the ALU instructions can
57//       forward a cycle earlier and then two cycles earlier in the case of a
58//       shift-only instruction. These latencies will be incorrect when the
59//       result cannot be forwarded, but modeling isn't rocket surgery.
60def : WriteRes<WriteImm, [A53UnitALU]> { let Latency = 3; }
61def : WriteRes<WriteI, [A53UnitALU]> { let Latency = 3; }
62def : WriteRes<WriteISReg, [A53UnitALU]> { let Latency = 3; }
63def : WriteRes<WriteIEReg, [A53UnitALU]> { let Latency = 3; }
64def : WriteRes<WriteIS, [A53UnitALU]> { let Latency = 2; }
65def : WriteRes<WriteExtr, [A53UnitALU]> { let Latency = 3; }
66
67// MAC
68def : WriteRes<WriteIM32, [A53UnitMAC]> { let Latency = 4; }
69def : WriteRes<WriteIM64, [A53UnitMAC]> { let Latency = 4; }
70
71// Div
72def : WriteRes<WriteID32, [A53UnitDiv]> { let Latency = 4; }
73def : WriteRes<WriteID64, [A53UnitDiv]> { let Latency = 4; }
74
75// Load
76def : WriteRes<WriteLD, [A53UnitLdSt]> { let Latency = 4; }
77def : WriteRes<WriteLDIdx, [A53UnitLdSt]> { let Latency = 4; }
78def : WriteRes<WriteLDHi, [A53UnitLdSt]> { let Latency = 4; }
79
80// Vector Load - Vector loads take 1-5 cycles to issue. For the WriteVecLd
81//               below, choosing the median of 3 which makes the latency 6.
82//               May model this more carefully in the future. The remaining
83//               A53WriteVLD# types represent the 1-5 cycle issues explicitly.
84def : WriteRes<WriteVLD, [A53UnitLdSt]> { let Latency = 6;
85                                          let ResourceCycles = [3]; }
86def A53WriteVLD1 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 4; }
87def A53WriteVLD2 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 5;
88                                                  let ResourceCycles = [2]; }
89def A53WriteVLD3 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 6;
90                                                  let ResourceCycles = [3]; }
91def A53WriteVLD4 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 7;
92                                                  let ResourceCycles = [4]; }
93def A53WriteVLD5 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 8;
94                                                  let ResourceCycles = [5]; }
95
96// Pre/Post Indexing - Performed as part of address generation which is already
97//                     accounted for in the WriteST* latencies below
98def : WriteRes<WriteAdr, []> { let Latency = 0; }
99
100// Store
101def : WriteRes<WriteST, [A53UnitLdSt]> { let Latency = 4; }
102def : WriteRes<WriteSTP, [A53UnitLdSt]> { let Latency = 4; }
103def : WriteRes<WriteSTIdx, [A53UnitLdSt]> { let Latency = 4; }
104def : WriteRes<WriteSTX, [A53UnitLdSt]> { let Latency = 4; }
105
106// Vector Store - Similar to vector loads, can take 1-3 cycles to issue.
107def : WriteRes<WriteVST, [A53UnitLdSt]> { let Latency = 5;
108                                          let ResourceCycles = [2];}
109def A53WriteVST1 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 4; }
110def A53WriteVST2 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 5;
111                                                  let ResourceCycles = [2]; }
112def A53WriteVST3 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 6;
113                                                  let ResourceCycles = [3]; }
114
115def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }
116
117// Branch
118def : WriteRes<WriteBr, [A53UnitB]>;
119def : WriteRes<WriteBrReg, [A53UnitB]>;
120def : WriteRes<WriteSys, [A53UnitB]>;
121def : WriteRes<WriteBarrier, [A53UnitB]>;
122def : WriteRes<WriteHint, [A53UnitB]>;
123
124// FP ALU
125def : WriteRes<WriteF, [A53UnitFPALU]> { let Latency = 6; }
126def : WriteRes<WriteFCmp, [A53UnitFPALU]> { let Latency = 6; }
127def : WriteRes<WriteFCvt, [A53UnitFPALU]> { let Latency = 6; }
128def : WriteRes<WriteFCopy, [A53UnitFPALU]> { let Latency = 6; }
129def : WriteRes<WriteFImm, [A53UnitFPALU]> { let Latency = 6; }
130def : WriteRes<WriteV, [A53UnitFPALU]> { let Latency = 6; }
131
132// FP Mul, Div, Sqrt
133def : WriteRes<WriteFMul, [A53UnitFPMDS]> { let Latency = 6; }
134def : WriteRes<WriteFDiv, [A53UnitFPMDS]> { let Latency = 33;
135                                            let ResourceCycles = [29]; }
136def A53WriteFMAC : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 10; }
137def A53WriteFDivSP : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 18;
138                                                     let ResourceCycles = [14]; }
139def A53WriteFDivDP : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 33;
140                                                     let ResourceCycles = [29]; }
141def A53WriteFSqrtSP : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 17;
142                                                      let ResourceCycles = [13]; }
143def A53WriteFSqrtDP : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 32;
144                                                      let ResourceCycles = [28]; }
145
146//===----------------------------------------------------------------------===//
147// Subtarget-specific SchedRead types.
148
149// No forwarding for these reads.
150def : ReadAdvance<ReadExtrHi, 0>;
151def : ReadAdvance<ReadAdrBase, 0>;
152def : ReadAdvance<ReadVLD, 0>;
153
154// ALU - Most operands in the ALU pipes are not needed for two cycles. Shiftable
155//       operands are needed one cycle later if and only if they are to be
156//       shifted. Otherwise, they too are needed two cycles later. This same
157//       ReadAdvance applies to Extended registers as well, even though there is
158//       a separate SchedPredicate for them.
159def : ReadAdvance<ReadI, 2, [WriteImm,WriteI,
160                             WriteISReg, WriteIEReg,WriteIS,
161                             WriteID32,WriteID64,
162                             WriteIM32,WriteIM64]>;
163def A53ReadShifted : SchedReadAdvance<1, [WriteImm,WriteI,
164                                          WriteISReg, WriteIEReg,WriteIS,
165                                          WriteID32,WriteID64,
166                                          WriteIM32,WriteIM64]>;
167def A53ReadNotShifted : SchedReadAdvance<2, [WriteImm,WriteI,
168                                             WriteISReg, WriteIEReg,WriteIS,
169                                             WriteID32,WriteID64,
170                                             WriteIM32,WriteIM64]>;
171def A53ReadISReg : SchedReadVariant<[
172	SchedVar<RegShiftedPred, [A53ReadShifted]>,
173	SchedVar<NoSchedPred, [A53ReadNotShifted]>]>;
174def : SchedAlias<ReadISReg, A53ReadISReg>;
175
176def A53ReadIEReg : SchedReadVariant<[
177	SchedVar<RegExtendedPred, [A53ReadShifted]>,
178	SchedVar<NoSchedPred, [A53ReadNotShifted]>]>;
179def : SchedAlias<ReadIEReg, A53ReadIEReg>;
180
181// MAC - Operands are generally needed one cycle later in the MAC pipe.
182//       Accumulator operands are needed two cycles later.
183def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI,
184                              WriteISReg, WriteIEReg,WriteIS,
185                              WriteID32,WriteID64,
186                              WriteIM32,WriteIM64]>;
187def : ReadAdvance<ReadIMA, 2, [WriteImm,WriteI,
188                               WriteISReg, WriteIEReg,WriteIS,
189                               WriteID32,WriteID64,
190                               WriteIM32,WriteIM64]>;
191
192// Div
193def : ReadAdvance<ReadID, 1, [WriteImm,WriteI,
194                              WriteISReg, WriteIEReg,WriteIS,
195                              WriteID32,WriteID64,
196                              WriteIM32,WriteIM64]>;
197
198//===----------------------------------------------------------------------===//
199// Subtarget-specific InstRWs.
200
201//---
202// Miscellaneous
203//---
204def : InstRW<[WriteI], (instrs COPY)>;
205
206//---
207// Vector Loads
208//---
209def : InstRW<[A53WriteVLD1], (instregex "LD1i(8|16|32|64)$")>;
210def : InstRW<[A53WriteVLD1], (instregex "LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
211def : InstRW<[A53WriteVLD1], (instregex "LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
212def : InstRW<[A53WriteVLD2], (instregex "LD1Twov(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
213def : InstRW<[A53WriteVLD3], (instregex "LD1Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
214def : InstRW<[A53WriteVLD4], (instregex "LD1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
215def : InstRW<[A53WriteVLD1, WriteAdr], (instregex "LD1i(8|16|32|64)_POST$")>;
216def : InstRW<[A53WriteVLD1, WriteAdr], (instregex "LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
217def : InstRW<[A53WriteVLD1, WriteAdr], (instregex "LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
218def : InstRW<[A53WriteVLD2, WriteAdr], (instregex "LD1Twov(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
219def : InstRW<[A53WriteVLD3, WriteAdr], (instregex "LD1Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
220def : InstRW<[A53WriteVLD4, WriteAdr], (instregex "LD1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
221
222def : InstRW<[A53WriteVLD1], (instregex "LD2i(8|16|32|64)$")>;
223def : InstRW<[A53WriteVLD1], (instregex "LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
224def : InstRW<[A53WriteVLD2], (instregex "LD2Twov(8b|4h|2s)$")>;
225def : InstRW<[A53WriteVLD4], (instregex "LD2Twov(16b|8h|4s|2d)$")>;
226def : InstRW<[A53WriteVLD1, WriteAdr], (instregex "LD2i(8|16|32|64)_POST$")>;
227def : InstRW<[A53WriteVLD1, WriteAdr], (instregex "LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
228def : InstRW<[A53WriteVLD2, WriteAdr], (instregex "LD2Twov(8b|4h|2s)_POST$")>;
229def : InstRW<[A53WriteVLD4, WriteAdr], (instregex "LD2Twov(16b|8h|4s|2d)_POST$")>;
230
231def : InstRW<[A53WriteVLD2], (instregex "LD3i(8|16|32|64)$")>;
232def : InstRW<[A53WriteVLD2], (instregex "LD3Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
233def : InstRW<[A53WriteVLD4], (instregex "LD3Threev(8b|4h|2s|1d|16b|8h|4s)$")>;
234def : InstRW<[A53WriteVLD3], (instregex "LD3Threev2d$")>;
235def : InstRW<[A53WriteVLD2, WriteAdr], (instregex "LD3i(8|16|32|64)_POST$")>;
236def : InstRW<[A53WriteVLD2, WriteAdr], (instregex "LD3Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
237def : InstRW<[A53WriteVLD4, WriteAdr], (instregex "LD3Threev(8b|4h|2s|1d|16b|8h|4s)_POST$")>;
238def : InstRW<[A53WriteVLD3, WriteAdr], (instregex "LD3Threev2d_POST$")>;
239
240def : InstRW<[A53WriteVLD2], (instregex "LD4i(8|16|32|64)$")>;
241def : InstRW<[A53WriteVLD2], (instregex "LD4Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
242def : InstRW<[A53WriteVLD5], (instregex "LD4Fourv(8b|4h|2s|1d|16b|8h|4s)$")>;
243def : InstRW<[A53WriteVLD4], (instregex "LD4Fourv(2d)$")>;
244def : InstRW<[A53WriteVLD2, WriteAdr], (instregex "LD4i(8|16|32|64)_POST$")>;
245def : InstRW<[A53WriteVLD2, WriteAdr], (instregex "LD4Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
246def : InstRW<[A53WriteVLD5, WriteAdr], (instregex "LD4Fourv(8b|4h|2s|1d|16b|8h|4s)_POST$")>;
247def : InstRW<[A53WriteVLD4, WriteAdr], (instregex "LD4Fourv(2d)_POST$")>;
248
249//---
250// Vector Stores
251//---
252def : InstRW<[A53WriteVST1], (instregex "ST1i(8|16|32|64)$")>;
253def : InstRW<[A53WriteVST1], (instregex "ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
254def : InstRW<[A53WriteVST1], (instregex "ST1Twov(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
255def : InstRW<[A53WriteVST2], (instregex "ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
256def : InstRW<[A53WriteVST2], (instregex "ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
257def : InstRW<[A53WriteVST1, WriteAdr], (instregex "ST1i(8|16|32|64)_POST$")>;
258def : InstRW<[A53WriteVST1, WriteAdr], (instregex "ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
259def : InstRW<[A53WriteVST1, WriteAdr], (instregex "ST1Twov(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
260def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
261def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
262
263def : InstRW<[A53WriteVST1], (instregex "ST2i(8|16|32|64)$")>;
264def : InstRW<[A53WriteVST1], (instregex "ST2Twov(8b|4h|2s)$")>;
265def : InstRW<[A53WriteVST2], (instregex "ST2Twov(16b|8h|4s|2d)$")>;
266def : InstRW<[A53WriteVST1, WriteAdr], (instregex "ST2i(8|16|32|64)_POST$")>;
267def : InstRW<[A53WriteVST1, WriteAdr], (instregex "ST2Twov(8b|4h|2s)_POST$")>;
268def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST2Twov(16b|8h|4s|2d)_POST$")>;
269
270def : InstRW<[A53WriteVST2], (instregex "ST3i(8|16|32|64)$")>;
271def : InstRW<[A53WriteVST3], (instregex "ST3Threev(8b|4h|2s|1d|16b|8h|4s)$")>;
272def : InstRW<[A53WriteVST2], (instregex "ST3Threev(2d)$")>;
273def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST3i(8|16|32|64)_POST$")>;
274def : InstRW<[A53WriteVST3, WriteAdr], (instregex "ST3Threev(8b|4h|2s|1d|16b|8h|4s)_POST$")>;
275def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST3Threev(2d)_POST$")>;
276
277def : InstRW<[A53WriteVST2], (instregex "ST4i(8|16|32|64)$")>;
278def : InstRW<[A53WriteVST3], (instregex "ST4Fourv(8b|4h|2s|1d|16b|8h|4s)$")>;
279def : InstRW<[A53WriteVST2], (instregex "ST4Fourv(2d)$")>;
280def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST4i(8|16|32|64)_POST$")>;
281def : InstRW<[A53WriteVST3, WriteAdr], (instregex "ST4Fourv(8b|4h|2s|1d|16b|8h|4s)_POST$")>;
282def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST4Fourv(2d)_POST$")>;
283
284//---
285// Floating Point MAC, DIV, SQRT
286//---
287def : InstRW<[A53WriteFMAC], (instregex "^FN?M(ADD|SUB).*")>;
288def : InstRW<[A53WriteFMAC], (instregex "^FML(A|S).*")>;
289def : InstRW<[A53WriteFDivSP], (instrs FDIVSrr)>;
290def : InstRW<[A53WriteFDivDP], (instrs FDIVDrr)>;
291def : InstRW<[A53WriteFDivSP], (instregex "^FDIVv.*32$")>;
292def : InstRW<[A53WriteFDivDP], (instregex "^FDIVv.*64$")>;
293def : InstRW<[A53WriteFSqrtSP], (instregex "^.*SQRT.*32$")>;
294def : InstRW<[A53WriteFSqrtDP], (instregex "^.*SQRT.*64$")>;
295
296}
297