12a66634dSDimitry Andric//=- AArch64SchedAmpere1.td - Ampere-1 scheduling def -----*- tablegen -*-=// 22a66634dSDimitry Andric// 32a66634dSDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 42a66634dSDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 52a66634dSDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 62a66634dSDimitry Andric// 72a66634dSDimitry Andric//===----------------------------------------------------------------------===// 82a66634dSDimitry Andric// 92a66634dSDimitry Andric// This file defines the machine model for the Ampere Computing Ampere-1 to 102a66634dSDimitry Andric// support instruction scheduling and other instruction cost heuristics. 112a66634dSDimitry Andric// 122a66634dSDimitry Andric//===----------------------------------------------------------------------===// 132a66634dSDimitry Andric 142a66634dSDimitry Andric// The Ampere-1 core is an out-of-order micro-architecture. The front 152a66634dSDimitry Andric// end has branch prediction, with a 10-cycle recovery time from a 162a66634dSDimitry Andric// mispredicted branch. Instructions coming out of the front end are 172a66634dSDimitry Andric// decoded into internal micro-ops (uops). 182a66634dSDimitry Andric 192a66634dSDimitry Andricdef Ampere1Model : SchedMachineModel { 202a66634dSDimitry Andric let IssueWidth = 4; // 4-way decode and dispatch 212a66634dSDimitry Andric let MicroOpBufferSize = 174; // micro-op re-order buffer size 222a66634dSDimitry Andric let LoadLatency = 4; // Optimistic load latency 232a66634dSDimitry Andric let MispredictPenalty = 10; // Branch mispredict penalty 242a66634dSDimitry Andric let LoopMicroOpBufferSize = 32; // Instruction queue size 25*5f757f3fSDimitry Andric let CompleteModel = 0; 262a66634dSDimitry Andric 272a66634dSDimitry Andric list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F, 28753f127fSDimitry Andric SMEUnsupported.F, 29753f127fSDimitry Andric PAUnsupported.F, 30753f127fSDimitry Andric [HasMTE]); 312a66634dSDimitry Andric} 322a66634dSDimitry Andric 332a66634dSDimitry Andriclet SchedModel = Ampere1Model in { 342a66634dSDimitry Andric 352a66634dSDimitry Andric//===----------------------------------------------------------------------===// 362a66634dSDimitry Andric// Define each kind of processor resource and number available on Ampere-1. 372a66634dSDimitry Andric// Ampere-1 has 12 pipelines that 8 independent scheduler (4 integer, 2 FP, 382a66634dSDimitry Andric// and 2 memory) issue into. The integer and FP schedulers can each issue 392a66634dSDimitry Andric// one uop per cycle, while the memory schedulers can each issue one load 402a66634dSDimitry Andric// and one store address calculation per cycle. 412a66634dSDimitry Andric 422a66634dSDimitry Andricdef Ampere1UnitA : ProcResource<2>; // integer single-cycle, branch, and flags r/w 432a66634dSDimitry Andricdef Ampere1UnitB : ProcResource<2>; // integer single-cycle, and complex shifts 442a66634dSDimitry Andricdef Ampere1UnitBS : ProcResource<1>; // integer multi-cycle 452a66634dSDimitry Andricdef Ampere1UnitL : ProcResource<2>; // load 462a66634dSDimitry Andricdef Ampere1UnitS : ProcResource<2>; // store address calculation 472a66634dSDimitry Andricdef Ampere1UnitX : ProcResource<1>; // FP and vector operations, and flag write 482a66634dSDimitry Andricdef Ampere1UnitY : ProcResource<1>; // FP and vector operations, and crypto 492a66634dSDimitry Andricdef Ampere1UnitZ : ProcResource<1>; // FP store data and FP-to-integer moves 502a66634dSDimitry Andric 512a66634dSDimitry Andricdef Ampere1UnitAB : ProcResGroup<[Ampere1UnitA, Ampere1UnitB]>; 522a66634dSDimitry Andricdef Ampere1UnitXY : ProcResGroup<[Ampere1UnitX, Ampere1UnitY]>; 532a66634dSDimitry Andric 542a66634dSDimitry Andric//===----------------------------------------------------------------------===// 552a66634dSDimitry Andric// Define customized scheduler read/write types specific to the Ampere-1. 562a66634dSDimitry Andric 572a66634dSDimitry Andricdef Ampere1Write_1cyc_1A : SchedWriteRes<[Ampere1UnitA]> { 582a66634dSDimitry Andric let Latency = 1; 592a66634dSDimitry Andric let NumMicroOps = 1; 602a66634dSDimitry Andric} 612a66634dSDimitry Andric 622a66634dSDimitry Andricdef Ampere1Write_1cyc_2A : SchedWriteRes<[Ampere1UnitA, Ampere1UnitA]> { 632a66634dSDimitry Andric let Latency = 1; 642a66634dSDimitry Andric let NumMicroOps = 2; 652a66634dSDimitry Andric} 662a66634dSDimitry Andric 672a66634dSDimitry Andricdef Ampere1Write_1cyc_1B : SchedWriteRes<[Ampere1UnitB]> { 682a66634dSDimitry Andric let Latency = 1; 692a66634dSDimitry Andric let NumMicroOps = 1; 702a66634dSDimitry Andric} 712a66634dSDimitry Andric 722a66634dSDimitry Andricdef Ampere1Write_1cyc_1AB : SchedWriteRes<[Ampere1UnitAB]> { 732a66634dSDimitry Andric let Latency = 1; 742a66634dSDimitry Andric let NumMicroOps = 1; 752a66634dSDimitry Andric} 762a66634dSDimitry Andric 772a66634dSDimitry Andricdef Ampere1Write_1cyc_1L : SchedWriteRes<[Ampere1UnitL]> { 782a66634dSDimitry Andric let Latency = 1; 792a66634dSDimitry Andric let NumMicroOps = 1; 802a66634dSDimitry Andric} 812a66634dSDimitry Andric 822a66634dSDimitry Andricdef Ampere1Write_1cyc_1S : SchedWriteRes<[Ampere1UnitS]> { 832a66634dSDimitry Andric let Latency = 1; 842a66634dSDimitry Andric let NumMicroOps = 1; 852a66634dSDimitry Andric} 862a66634dSDimitry Andric 872a66634dSDimitry Andricdef Ampere1Write_1cyc_2S : SchedWriteRes<[Ampere1UnitS, Ampere1UnitS]> { 882a66634dSDimitry Andric let Latency = 1; 892a66634dSDimitry Andric let NumMicroOps = 2; 902a66634dSDimitry Andric} 912a66634dSDimitry Andric 922a66634dSDimitry Andricdef Ampere1Write_2cyc_1Y : SchedWriteRes<[Ampere1UnitY]> { 932a66634dSDimitry Andric let Latency = 2; 942a66634dSDimitry Andric let NumMicroOps = 1; 952a66634dSDimitry Andric} 962a66634dSDimitry Andric 972a66634dSDimitry Andricdef Ampere1Write_2cyc_2AB : SchedWriteRes<[Ampere1UnitAB, Ampere1UnitAB]> { 982a66634dSDimitry Andric let Latency = 2; 992a66634dSDimitry Andric let NumMicroOps = 2; 1002a66634dSDimitry Andric} 1012a66634dSDimitry Andric 1022a66634dSDimitry Andricdef Ampere1Write_2cyc_1B_1AB : SchedWriteRes<[Ampere1UnitB, Ampere1UnitAB]> { 1032a66634dSDimitry Andric let Latency = 2; 1042a66634dSDimitry Andric let NumMicroOps = 2; 1052a66634dSDimitry Andric} 1062a66634dSDimitry Andric 1072a66634dSDimitry Andricdef Ampere1Write_2cyc_1B_1A : SchedWriteRes<[Ampere1UnitB, Ampere1UnitA]> { 1082a66634dSDimitry Andric let Latency = 2; 1092a66634dSDimitry Andric let NumMicroOps = 2; 1102a66634dSDimitry Andric} 1112a66634dSDimitry Andric 1122a66634dSDimitry Andricdef Ampere1Write_2cyc_1AB_1A : SchedWriteRes<[Ampere1UnitAB, Ampere1UnitA]> { 1132a66634dSDimitry Andric let Latency = 2; 1142a66634dSDimitry Andric let NumMicroOps = 2; 1152a66634dSDimitry Andric} 1162a66634dSDimitry Andric 1172a66634dSDimitry Andricdef Ampere1Write_2cyc_1AB_1L : SchedWriteRes<[Ampere1UnitAB, Ampere1UnitL]> { 1182a66634dSDimitry Andric let Latency = 2; 1192a66634dSDimitry Andric let NumMicroOps = 2; 1202a66634dSDimitry Andric} 1212a66634dSDimitry Andric 1222a66634dSDimitry Andricdef Ampere1Write_2cyc_1AB_2S : SchedWriteRes<[Ampere1UnitAB, Ampere1UnitS, 1232a66634dSDimitry Andric Ampere1UnitS]> { 1242a66634dSDimitry Andric let Latency = 2; 1252a66634dSDimitry Andric let NumMicroOps = 3; 1262a66634dSDimitry Andric} 1272a66634dSDimitry Andric 1282a66634dSDimitry Andricdef Ampere1Write_2cyc_1AB_1S_1Z : SchedWriteRes<[Ampere1UnitAB, Ampere1UnitS, 1292a66634dSDimitry Andric Ampere1UnitZ]> { 1302a66634dSDimitry Andric let Latency = 2; 1312a66634dSDimitry Andric let NumMicroOps = 3; 1322a66634dSDimitry Andric} 1332a66634dSDimitry Andric 1342a66634dSDimitry Andricdef Ampere1Write_2cyc_1B_1S : SchedWriteRes<[Ampere1UnitB, Ampere1UnitS]> { 1352a66634dSDimitry Andric let Latency = 2; 1362a66634dSDimitry Andric let NumMicroOps = 2; 1372a66634dSDimitry Andric} 1382a66634dSDimitry Andric 1392a66634dSDimitry Andricdef Ampere1Write_2cyc_1XY : SchedWriteRes<[Ampere1UnitXY]> { 1402a66634dSDimitry Andric let Latency = 2; 1412a66634dSDimitry Andric let NumMicroOps = 1; 1422a66634dSDimitry Andric} 1432a66634dSDimitry Andric 1442a66634dSDimitry Andricdef Ampere1Write_2cyc_1S_1Z : SchedWriteRes<[Ampere1UnitS, Ampere1UnitZ]> { 1452a66634dSDimitry Andric let Latency = 2; 1462a66634dSDimitry Andric let NumMicroOps = 2; 1472a66634dSDimitry Andric} 1482a66634dSDimitry Andric 1492a66634dSDimitry Andricdef Ampere1Write_3cyc_1BS : SchedWriteRes<[Ampere1UnitBS]> { 1502a66634dSDimitry Andric let Latency = 3; 1512a66634dSDimitry Andric let NumMicroOps = 1; 1522a66634dSDimitry Andric} 1532a66634dSDimitry Andric 1542a66634dSDimitry Andricdef Ampere1Write_3cyc_1XY : SchedWriteRes<[Ampere1UnitXY]> { 1552a66634dSDimitry Andric let Latency = 3; 1562a66634dSDimitry Andric let NumMicroOps = 1; 1572a66634dSDimitry Andric} 1582a66634dSDimitry Andric 1592a66634dSDimitry Andricdef Ampere1Write_3cyc_1B_1S_1AB : SchedWriteRes<[Ampere1UnitB, Ampere1UnitS, 1602a66634dSDimitry Andric Ampere1UnitAB]> { 1612a66634dSDimitry Andric let Latency = 2; 1622a66634dSDimitry Andric let NumMicroOps = 3; 1632a66634dSDimitry Andric} 1642a66634dSDimitry Andric 1652a66634dSDimitry Andricdef Ampere1Write_3cyc_1S_2Z : SchedWriteRes<[Ampere1UnitS, Ampere1UnitZ, Ampere1UnitZ]> { 1662a66634dSDimitry Andric let Latency = 2; 1672a66634dSDimitry Andric let NumMicroOps = 3; 1682a66634dSDimitry Andric} 1692a66634dSDimitry Andric 1702a66634dSDimitry Andricdef Ampere1Write_3cyc_2S_2Z : SchedWriteRes<[Ampere1UnitS, Ampere1UnitS, 1712a66634dSDimitry Andric Ampere1UnitZ, Ampere1UnitZ]> { 1722a66634dSDimitry Andric let Latency = 2; 1732a66634dSDimitry Andric let NumMicroOps = 4; 1742a66634dSDimitry Andric} 1752a66634dSDimitry Andric 1762a66634dSDimitry Andricdef Ampere1Write_4cyc_1BS : SchedWriteRes<[Ampere1UnitBS]> { 1772a66634dSDimitry Andric let Latency = 4; 1782a66634dSDimitry Andric let NumMicroOps = 1; 1792a66634dSDimitry Andric} 1802a66634dSDimitry Andric 1812a66634dSDimitry Andricdef Ampere1Write_4cyc_1L : SchedWriteRes<[Ampere1UnitL]> { 1822a66634dSDimitry Andric let Latency = 4; 1832a66634dSDimitry Andric let NumMicroOps = 1; 1842a66634dSDimitry Andric} 1852a66634dSDimitry Andric 1862a66634dSDimitry Andricdef Ampere1Write_4cyc_1X : SchedWriteRes<[Ampere1UnitX]> { 1872a66634dSDimitry Andric let Latency = 4; 1882a66634dSDimitry Andric let NumMicroOps = 1; 1892a66634dSDimitry Andric} 1902a66634dSDimitry Andric 1912a66634dSDimitry Andricdef Ampere1Write_4cyc_1Y : SchedWriteRes<[Ampere1UnitY]> { 1922a66634dSDimitry Andric let Latency = 4; 1932a66634dSDimitry Andric let NumMicroOps = 1; 1942a66634dSDimitry Andric} 1952a66634dSDimitry Andric 1962a66634dSDimitry Andricdef Ampere1Write_4cyc_1Z : SchedWriteRes<[Ampere1UnitZ]> { 1972a66634dSDimitry Andric let Latency = 4; 1982a66634dSDimitry Andric let NumMicroOps = 1; 1992a66634dSDimitry Andric} 2002a66634dSDimitry Andric 2012a66634dSDimitry Andricdef Ampere1Write_4cyc_2L : SchedWriteRes<[Ampere1UnitL, Ampere1UnitL]> { 2022a66634dSDimitry Andric let Latency = 4; 2032a66634dSDimitry Andric let NumMicroOps = 2; 2042a66634dSDimitry Andric} 2052a66634dSDimitry Andric 2062a66634dSDimitry Andricdef Ampere1Write_4cyc_1XY : SchedWriteRes<[Ampere1UnitXY]> { 2072a66634dSDimitry Andric let Latency = 4; 2082a66634dSDimitry Andric let NumMicroOps = 1; 2092a66634dSDimitry Andric} 2102a66634dSDimitry Andric 2112a66634dSDimitry Andricdef Ampere1Write_4cyc_2XY : SchedWriteRes<[Ampere1UnitXY, Ampere1UnitXY]> { 2122a66634dSDimitry Andric let Latency = 4; 2132a66634dSDimitry Andric let NumMicroOps = 2; 2142a66634dSDimitry Andric} 2152a66634dSDimitry Andric 2162a66634dSDimitry Andricdef Ampere1Write_4cyc_1XY_1S_1Z : SchedWriteRes<[Ampere1UnitXY, Ampere1UnitS, Ampere1UnitZ]> { 2172a66634dSDimitry Andric let Latency = 4; 2182a66634dSDimitry Andric let NumMicroOps = 3; 2192a66634dSDimitry Andric} 2202a66634dSDimitry Andric 2212a66634dSDimitry Andricdef Ampere1Write_4cyc_3S_3Z : SchedWriteRes<[Ampere1UnitS, Ampere1UnitS, Ampere1UnitS, 2222a66634dSDimitry Andric Ampere1UnitZ, Ampere1UnitZ, Ampere1UnitZ]> { 2232a66634dSDimitry Andric let Latency = 4; 2242a66634dSDimitry Andric let NumMicroOps = 6; 2252a66634dSDimitry Andric} 2262a66634dSDimitry Andric 2272a66634dSDimitry Andricdef Ampere1Write_5cyc_1AB_1L : SchedWriteRes<[Ampere1UnitAB, Ampere1UnitL]> { 2282a66634dSDimitry Andric let Latency = 5; 2292a66634dSDimitry Andric let NumMicroOps = 2; 2302a66634dSDimitry Andric} 2312a66634dSDimitry Andric 2322a66634dSDimitry Andricdef Ampere1Write_5cyc_1BS : SchedWriteRes<[Ampere1UnitBS]> { 2332a66634dSDimitry Andric let Latency = 5; 2342a66634dSDimitry Andric let NumMicroOps = 1; 2352a66634dSDimitry Andric} 2362a66634dSDimitry Andric 2372a66634dSDimitry Andricdef Ampere1Write_5cyc_1X : SchedWriteRes<[Ampere1UnitX]> { 2382a66634dSDimitry Andric let Latency = 5; 2392a66634dSDimitry Andric let NumMicroOps = 1; 2402a66634dSDimitry Andric} 2412a66634dSDimitry Andric 2422a66634dSDimitry Andricdef Ampere1Write_5cyc_1L : SchedWriteRes<[Ampere1UnitL]> { 2432a66634dSDimitry Andric let Latency = 5; 2442a66634dSDimitry Andric let NumMicroOps = 1; 2452a66634dSDimitry Andric} 2462a66634dSDimitry Andric 2472a66634dSDimitry Andricdef Ampere1Write_5cyc_2L : SchedWriteRes<[Ampere1UnitL, Ampere1UnitL]> { 2482a66634dSDimitry Andric let Latency = 5; 2492a66634dSDimitry Andric let NumMicroOps = 2; 2502a66634dSDimitry Andric} 2512a66634dSDimitry Andric 2522a66634dSDimitry Andricdef Ampere1Write_5cyc_1L_1BS : SchedWriteRes<[Ampere1UnitL, Ampere1UnitBS]> { 2532a66634dSDimitry Andric let Latency = 5; 2542a66634dSDimitry Andric let NumMicroOps = 2; 2552a66634dSDimitry Andric} 2562a66634dSDimitry Andric 2572a66634dSDimitry Andricdef Ampere1Write_5cyc_1XY : SchedWriteRes<[Ampere1UnitXY]> { 2582a66634dSDimitry Andric let Latency = 5; 2592a66634dSDimitry Andric let NumMicroOps = 1; 2602a66634dSDimitry Andric} 2612a66634dSDimitry Andric 2622a66634dSDimitry Andricdef Ampere1Write_5cyc_2XY : SchedWriteRes<[Ampere1UnitXY, Ampere1UnitXY]> { 2632a66634dSDimitry Andric let Latency = 5; 2642a66634dSDimitry Andric let NumMicroOps = 2; 2652a66634dSDimitry Andric} 2662a66634dSDimitry Andric 2672a66634dSDimitry Andricdef Ampere1Write_5cyc_4S_4Z : SchedWriteRes<[Ampere1UnitS, Ampere1UnitS, 2682a66634dSDimitry Andric Ampere1UnitS, Ampere1UnitS, 2692a66634dSDimitry Andric Ampere1UnitZ, Ampere1UnitZ, 2702a66634dSDimitry Andric Ampere1UnitZ, Ampere1UnitZ]> { 2712a66634dSDimitry Andric let Latency = 5; 2722a66634dSDimitry Andric let NumMicroOps = 8; 2732a66634dSDimitry Andric} 2742a66634dSDimitry Andric 2752a66634dSDimitry Andricdef Ampere1Write_5cyc_2XY_2S_2Z : SchedWriteRes<[Ampere1UnitXY, Ampere1UnitXY, 2762a66634dSDimitry Andric Ampere1UnitS, Ampere1UnitS, 2772a66634dSDimitry Andric Ampere1UnitZ, Ampere1UnitZ]> { 2782a66634dSDimitry Andric let Latency = 5; 2792a66634dSDimitry Andric let NumMicroOps = 6; 2802a66634dSDimitry Andric} 2812a66634dSDimitry Andric 2822a66634dSDimitry Andricdef Ampere1Write_6cyc_2XY_2S_2Z : SchedWriteRes<[Ampere1UnitXY, Ampere1UnitXY, 2832a66634dSDimitry Andric Ampere1UnitS, Ampere1UnitS, 2842a66634dSDimitry Andric Ampere1UnitZ, Ampere1UnitZ]> { 2852a66634dSDimitry Andric let Latency = 6; 2862a66634dSDimitry Andric let NumMicroOps = 6; 2872a66634dSDimitry Andric} 2882a66634dSDimitry Andric 2892a66634dSDimitry Andricdef Ampere1Write_6cyc_3XY_3S_3Z : SchedWriteRes<[Ampere1UnitXY, Ampere1UnitXY, Ampere1UnitXY, 2902a66634dSDimitry Andric Ampere1UnitS, Ampere1UnitS, Ampere1UnitS, 2912a66634dSDimitry Andric Ampere1UnitZ, Ampere1UnitZ, Ampere1UnitZ]> { 2922a66634dSDimitry Andric let Latency = 6; 2932a66634dSDimitry Andric let NumMicroOps = 9; 2942a66634dSDimitry Andric} 2952a66634dSDimitry Andric 2962a66634dSDimitry Andricdef Ampere1Write_6cyc_1AB_1L : SchedWriteRes<[Ampere1UnitAB, Ampere1UnitL]> { 2972a66634dSDimitry Andric let Latency = 6; 2982a66634dSDimitry Andric let NumMicroOps = 2; 2992a66634dSDimitry Andric} 3002a66634dSDimitry Andric 3012a66634dSDimitry Andricdef Ampere1Write_6cyc_1XY : SchedWriteRes<[Ampere1UnitXY]> { 3022a66634dSDimitry Andric let Latency = 6; 3032a66634dSDimitry Andric let NumMicroOps = 1; 3042a66634dSDimitry Andric} 3052a66634dSDimitry Andric 3062a66634dSDimitry Andricdef Ampere1Write_6cyc_2XY : SchedWriteRes<[Ampere1UnitXY, Ampere1UnitXY]> { 3072a66634dSDimitry Andric let Latency = 6; 3082a66634dSDimitry Andric let NumMicroOps = 2; 3092a66634dSDimitry Andric} 3102a66634dSDimitry Andric 3112a66634dSDimitry Andricdef Ampere1Write_6cyc_3XY : SchedWriteRes<[Ampere1UnitXY, Ampere1UnitXY, Ampere1UnitXY]> { 3122a66634dSDimitry Andric let Latency = 6; 3132a66634dSDimitry Andric let NumMicroOps = 3; 3142a66634dSDimitry Andric} 3152a66634dSDimitry Andric 3162a66634dSDimitry Andricdef Ampere1Write_6cyc_3L : SchedWriteRes<[Ampere1UnitL, Ampere1UnitL, Ampere1UnitL]> { 3172a66634dSDimitry Andric let Latency = 6; 3182a66634dSDimitry Andric let NumMicroOps = 3; 3192a66634dSDimitry Andric} 3202a66634dSDimitry Andric 3212a66634dSDimitry Andricdef Ampere1Write_6cyc_4L : SchedWriteRes<[Ampere1UnitL, Ampere1UnitL, 3222a66634dSDimitry Andric Ampere1UnitL, Ampere1UnitL]> { 3232a66634dSDimitry Andric let Latency = 6; 3242a66634dSDimitry Andric let NumMicroOps = 4; 3252a66634dSDimitry Andric} 3262a66634dSDimitry Andric 3272a66634dSDimitry Andricdef Ampere1Write_6cyc_1XY_1Z : SchedWriteRes<[Ampere1UnitXY, Ampere1UnitZ]> { 3282a66634dSDimitry Andric let Latency = 6; 3292a66634dSDimitry Andric let NumMicroOps = 2; 3302a66634dSDimitry Andric} 3312a66634dSDimitry Andric 3322a66634dSDimitry Andricdef Ampere1Write_7cyc_1BS : SchedWriteRes<[Ampere1UnitBS]> { 3332a66634dSDimitry Andric let Latency = 7; 3342a66634dSDimitry Andric let NumMicroOps = 1; 3352a66634dSDimitry Andric} 3362a66634dSDimitry Andric 3372a66634dSDimitry Andricdef Ampere1Write_7cyc_1BS_1XY : SchedWriteRes<[Ampere1UnitBS, Ampere1UnitXY]> { 3382a66634dSDimitry Andric let Latency = 7; 3392a66634dSDimitry Andric let NumMicroOps = 2; 3402a66634dSDimitry Andric} 3412a66634dSDimitry Andric 3422a66634dSDimitry Andricdef Ampere1Write_7cyc_1L_1XY : SchedWriteRes<[Ampere1UnitL, Ampere1UnitXY]> { 3432a66634dSDimitry Andric let Latency = 7; 3442a66634dSDimitry Andric let NumMicroOps = 2; 3452a66634dSDimitry Andric} 3462a66634dSDimitry Andric 3472a66634dSDimitry Andricdef Ampere1Write_7cyc_2L_2XY : SchedWriteRes<[Ampere1UnitL, Ampere1UnitL, 3482a66634dSDimitry Andric Ampere1UnitXY, Ampere1UnitXY]> { 3492a66634dSDimitry Andric let Latency = 7; 3502a66634dSDimitry Andric let NumMicroOps = 4; 3512a66634dSDimitry Andric} 3522a66634dSDimitry Andric 3532a66634dSDimitry Andricdef Ampere1Write_7cyc_2XY : SchedWriteRes<[Ampere1UnitXY, Ampere1UnitXY]> { 3542a66634dSDimitry Andric let Latency = 7; 3552a66634dSDimitry Andric let NumMicroOps = 2; 3562a66634dSDimitry Andric} 3572a66634dSDimitry Andric 3582a66634dSDimitry Andricdef Ampere1Write_7cyc_4XY_4S_4Z : SchedWriteRes<[Ampere1UnitXY, Ampere1UnitXY, 3592a66634dSDimitry Andric Ampere1UnitXY, Ampere1UnitXY, 3602a66634dSDimitry Andric Ampere1UnitS, Ampere1UnitS, 3612a66634dSDimitry Andric Ampere1UnitS, Ampere1UnitS, 3622a66634dSDimitry Andric Ampere1UnitZ, Ampere1UnitZ, 3632a66634dSDimitry Andric Ampere1UnitZ, Ampere1UnitZ]> { 3642a66634dSDimitry Andric let Latency = 7; 3652a66634dSDimitry Andric let NumMicroOps = 12; 3662a66634dSDimitry Andric} 3672a66634dSDimitry Andric 3682a66634dSDimitry Andricdef Ampere1Write_8cyc_1BS_1A : SchedWriteRes<[Ampere1UnitBS, Ampere1UnitA]> { 3692a66634dSDimitry Andric let Latency = 8; 3702a66634dSDimitry Andric let NumMicroOps = 2; 3712a66634dSDimitry Andric} 3722a66634dSDimitry Andric 3732a66634dSDimitry Andricdef Ampere1Write_8cyc_1BS_2A : SchedWriteRes<[Ampere1UnitBS, Ampere1UnitA, 3742a66634dSDimitry Andric Ampere1UnitA]> { 3752a66634dSDimitry Andric let Latency = 8; 3762a66634dSDimitry Andric let NumMicroOps = 3; 3772a66634dSDimitry Andric} 3782a66634dSDimitry Andric 3792a66634dSDimitry Andricdef Ampere1Write_8cyc_2XY : SchedWriteRes<[Ampere1UnitXY, Ampere1UnitXY]> { 3802a66634dSDimitry Andric let Latency = 8; 3812a66634dSDimitry Andric let NumMicroOps = 2; 3822a66634dSDimitry Andric} 3832a66634dSDimitry Andric 3842a66634dSDimitry Andricdef Ampere1Write_8cyc_4XY : SchedWriteRes<[Ampere1UnitXY, Ampere1UnitXY, 3852a66634dSDimitry Andric Ampere1UnitXY, Ampere1UnitXY]> { 3862a66634dSDimitry Andric let Latency = 8; 3872a66634dSDimitry Andric let NumMicroOps = 4; 3882a66634dSDimitry Andric} 3892a66634dSDimitry Andric 3902a66634dSDimitry Andricdef Ampere1Write_8cyc_3L_3XY : SchedWriteRes<[Ampere1UnitL, Ampere1UnitL, Ampere1UnitL, 3912a66634dSDimitry Andric Ampere1UnitXY, Ampere1UnitXY, Ampere1UnitXY]> { 3922a66634dSDimitry Andric let Latency = 8; 3932a66634dSDimitry Andric let NumMicroOps = 6; 3942a66634dSDimitry Andric} 3952a66634dSDimitry Andric 3962a66634dSDimitry Andricdef Ampere1Write_8cyc_4L_4XY : SchedWriteRes<[Ampere1UnitL, Ampere1UnitL, 3972a66634dSDimitry Andric Ampere1UnitL, Ampere1UnitL, 3982a66634dSDimitry Andric Ampere1UnitXY, Ampere1UnitXY, 3992a66634dSDimitry Andric Ampere1UnitXY, Ampere1UnitXY]> { 4002a66634dSDimitry Andric let Latency = 8; 4012a66634dSDimitry Andric let NumMicroOps = 8; 4022a66634dSDimitry Andric} 4032a66634dSDimitry Andric 4042a66634dSDimitry Andricdef Ampere1Write_9cyc_3L_3XY : SchedWriteRes<[Ampere1UnitL, Ampere1UnitL, Ampere1UnitL, 4052a66634dSDimitry Andric Ampere1UnitXY, Ampere1UnitXY, Ampere1UnitXY]> { 4062a66634dSDimitry Andric let Latency = 9; 4072a66634dSDimitry Andric let NumMicroOps = 6; 4082a66634dSDimitry Andric} 4092a66634dSDimitry Andric 4102a66634dSDimitry Andricdef Ampere1Write_9cyc_4L_4XY : SchedWriteRes<[Ampere1UnitL, Ampere1UnitL, 4112a66634dSDimitry Andric Ampere1UnitL, Ampere1UnitL, 4122a66634dSDimitry Andric Ampere1UnitXY, Ampere1UnitXY, 4132a66634dSDimitry Andric Ampere1UnitXY, Ampere1UnitXY]> { 4142a66634dSDimitry Andric let Latency = 9; 4152a66634dSDimitry Andric let NumMicroOps = 8; 4162a66634dSDimitry Andric} 4172a66634dSDimitry Andric 4182a66634dSDimitry Andricdef Ampere1Write_9cyc_3XY : SchedWriteRes<[Ampere1UnitXY, Ampere1UnitXY, Ampere1UnitXY]> { 4192a66634dSDimitry Andric let Latency = 9; 4202a66634dSDimitry Andric let NumMicroOps = 3; 4212a66634dSDimitry Andric} 4222a66634dSDimitry Andric 4232a66634dSDimitry Andricdef Ampere1Write_9cyc_2L_3XY : SchedWriteRes<[Ampere1UnitL, Ampere1UnitL, 4242a66634dSDimitry Andric Ampere1UnitXY, Ampere1UnitXY, Ampere1UnitXY]> { 4252a66634dSDimitry Andric let Latency = 9; 4262a66634dSDimitry Andric let NumMicroOps = 5; 4272a66634dSDimitry Andric} 4282a66634dSDimitry Andric 4292a66634dSDimitry Andricdef Ampere1Write_9cyc_6XY_4S_4Z : SchedWriteRes<[Ampere1UnitXY, Ampere1UnitXY, 4302a66634dSDimitry Andric Ampere1UnitXY, Ampere1UnitXY, 4312a66634dSDimitry Andric Ampere1UnitXY, Ampere1UnitXY, 4322a66634dSDimitry Andric Ampere1UnitS, Ampere1UnitS, 4332a66634dSDimitry Andric Ampere1UnitS, Ampere1UnitS, 4342a66634dSDimitry Andric Ampere1UnitZ, Ampere1UnitZ, 4352a66634dSDimitry Andric Ampere1UnitZ, Ampere1UnitZ]> { 4362a66634dSDimitry Andric let Latency = 9; 4372a66634dSDimitry Andric let NumMicroOps = 14; 4382a66634dSDimitry Andric} 4392a66634dSDimitry Andric 4402a66634dSDimitry Andricdef Ampere1Write_9cyc_8XY_4S_4Z : SchedWriteRes<[Ampere1UnitXY, Ampere1UnitXY, 4412a66634dSDimitry Andric Ampere1UnitXY, Ampere1UnitXY, 4422a66634dSDimitry Andric Ampere1UnitXY, Ampere1UnitXY, 4432a66634dSDimitry Andric Ampere1UnitXY, Ampere1UnitXY, 4442a66634dSDimitry Andric Ampere1UnitS, Ampere1UnitS, 4452a66634dSDimitry Andric Ampere1UnitS, Ampere1UnitS, 4462a66634dSDimitry Andric Ampere1UnitZ, Ampere1UnitZ, 4472a66634dSDimitry Andric Ampere1UnitZ, Ampere1UnitZ]> { 4482a66634dSDimitry Andric let Latency = 9; 4492a66634dSDimitry Andric let NumMicroOps = 16; 4502a66634dSDimitry Andric} 4512a66634dSDimitry Andric 4522a66634dSDimitry Andricdef Ampere1Write_10cyc_2XY : SchedWriteRes<[Ampere1UnitXY, Ampere1UnitXY]> { 4532a66634dSDimitry Andric let Latency = 10; 4542a66634dSDimitry Andric let NumMicroOps = 2; 4552a66634dSDimitry Andric} 4562a66634dSDimitry Andric 4572a66634dSDimitry Andricdef Ampere1Write_10cyc_1XY_1Z : SchedWriteRes<[Ampere1UnitXY, Ampere1UnitZ]> { 4582a66634dSDimitry Andric let Latency = 10; 4592a66634dSDimitry Andric let NumMicroOps = 2; 4602a66634dSDimitry Andric} 4612a66634dSDimitry Andric 4622a66634dSDimitry Andricdef Ampere1Write_10cyc_1X_1Z : SchedWriteRes<[Ampere1UnitX, Ampere1UnitZ]> { 4632a66634dSDimitry Andric let Latency = 10; 4642a66634dSDimitry Andric let NumMicroOps = 2; 4652a66634dSDimitry Andric} 4662a66634dSDimitry Andric 4672a66634dSDimitry Andricdef Ampere1Write_10cyc_3L_3XY : SchedWriteRes<[Ampere1UnitL, Ampere1UnitL, Ampere1UnitL, 4682a66634dSDimitry Andric Ampere1UnitXY, Ampere1UnitXY, Ampere1UnitXY]> { 4692a66634dSDimitry Andric let Latency = 10; 4702a66634dSDimitry Andric let NumMicroOps = 6; 4712a66634dSDimitry Andric} 4722a66634dSDimitry Andric 4732a66634dSDimitry Andricdef Ampere1Write_10cyc_1A_1BS_1X : SchedWriteRes<[Ampere1UnitA, Ampere1UnitBS, Ampere1UnitX]> { 4742a66634dSDimitry Andric let Latency = 10; 4752a66634dSDimitry Andric let NumMicroOps = 3; 4762a66634dSDimitry Andric} 4772a66634dSDimitry Andric 4782a66634dSDimitry Andricdef Ampere1Write_10cyc_1A_1BS_1XY : SchedWriteRes<[Ampere1UnitA, Ampere1UnitBS, Ampere1UnitXY]> { 4792a66634dSDimitry Andric let Latency = 10; 4802a66634dSDimitry Andric let NumMicroOps = 3; 4812a66634dSDimitry Andric} 4822a66634dSDimitry Andric 4832a66634dSDimitry Andricdef Ampere1Write_11cyc_1BS_1L : SchedWriteRes<[Ampere1UnitBS, Ampere1UnitL]> { 4842a66634dSDimitry Andric let Latency = 11; 4852a66634dSDimitry Andric let NumMicroOps = 2; 4862a66634dSDimitry Andric} 4872a66634dSDimitry Andric 4882a66634dSDimitry Andricdef Ampere1Write_11cyc_1A_1BS_1X : SchedWriteRes<[Ampere1UnitA, Ampere1UnitBS, Ampere1UnitX]> { 4892a66634dSDimitry Andric let Latency = 11; 4902a66634dSDimitry Andric let NumMicroOps = 3; 4912a66634dSDimitry Andric} 4922a66634dSDimitry Andric 4932a66634dSDimitry Andricdef Ampere1Write_11cyc_1A_1BS_1XY : SchedWriteRes<[Ampere1UnitA, Ampere1UnitBS, Ampere1UnitXY]> { 4942a66634dSDimitry Andric let Latency = 11; 4952a66634dSDimitry Andric let NumMicroOps = 3; 4962a66634dSDimitry Andric} 4972a66634dSDimitry Andric 4982a66634dSDimitry Andricdef Ampere1Write_11cyc_4L_8XY : SchedWriteRes<[Ampere1UnitL, Ampere1UnitL, 4992a66634dSDimitry Andric Ampere1UnitL, Ampere1UnitL, 5002a66634dSDimitry Andric Ampere1UnitXY, Ampere1UnitXY, 5012a66634dSDimitry Andric Ampere1UnitXY, Ampere1UnitXY, 5022a66634dSDimitry Andric Ampere1UnitXY, Ampere1UnitXY, 5032a66634dSDimitry Andric Ampere1UnitXY, Ampere1UnitXY]> { 5042a66634dSDimitry Andric let Latency = 11; 5052a66634dSDimitry Andric let NumMicroOps = 12; 5062a66634dSDimitry Andric} 5072a66634dSDimitry Andric 5082a66634dSDimitry Andricdef Ampere1Write_12cyc_4L_8XY : SchedWriteRes<[Ampere1UnitL, Ampere1UnitL, 5092a66634dSDimitry Andric Ampere1UnitL, Ampere1UnitL, 5102a66634dSDimitry Andric Ampere1UnitXY, Ampere1UnitXY, 5112a66634dSDimitry Andric Ampere1UnitXY, Ampere1UnitXY, 5122a66634dSDimitry Andric Ampere1UnitXY, Ampere1UnitXY, 5132a66634dSDimitry Andric Ampere1UnitXY, Ampere1UnitXY]> { 5142a66634dSDimitry Andric let Latency = 12; 5152a66634dSDimitry Andric let NumMicroOps = 12; 5162a66634dSDimitry Andric} 5172a66634dSDimitry Andric 5182a66634dSDimitry Andricdef Ampere1Write_12cyc_3XY : SchedWriteRes<[Ampere1UnitXY, Ampere1UnitXY, Ampere1UnitXY]> { 5192a66634dSDimitry Andric let Latency = 12; 5202a66634dSDimitry Andric let NumMicroOps = 3; 5212a66634dSDimitry Andric} 5222a66634dSDimitry Andric 5232a66634dSDimitry Andricdef Ampere1Write_12cyc_4XY : SchedWriteRes<[Ampere1UnitXY, Ampere1UnitXY, 5242a66634dSDimitry Andric Ampere1UnitXY, Ampere1UnitXY]> { 5252a66634dSDimitry Andric let Latency = 12; 5262a66634dSDimitry Andric let NumMicroOps = 4; 5272a66634dSDimitry Andric} 5282a66634dSDimitry Andric 5292a66634dSDimitry Andricdef Ampere1Write_18cyc_1BS : SchedWriteRes<[Ampere1UnitBS]> { 5302a66634dSDimitry Andric let Latency = 18; 5312a66634dSDimitry Andric let NumMicroOps = 1; 5322a66634dSDimitry Andric} 5332a66634dSDimitry Andric 5342a66634dSDimitry Andricdef Ampere1Write_19cyc_1XY : SchedWriteRes<[Ampere1UnitXY]> { 5352a66634dSDimitry Andric let Latency = 19; 5362a66634dSDimitry Andric let NumMicroOps = 1; 5372a66634dSDimitry Andric} 5382a66634dSDimitry Andric 5392a66634dSDimitry Andricdef Ampere1Write_25cyc_1XY : SchedWriteRes<[Ampere1UnitXY]> { 5402a66634dSDimitry Andric let Latency = 25; 5412a66634dSDimitry Andric let NumMicroOps = 1; 5422a66634dSDimitry Andric} 5432a66634dSDimitry Andric 5442a66634dSDimitry Andricdef Ampere1Write_32cyc_1XY : SchedWriteRes<[Ampere1UnitXY]> { 5452a66634dSDimitry Andric let Latency = 32; 5462a66634dSDimitry Andric let NumMicroOps = 1; 5472a66634dSDimitry Andric} 5482a66634dSDimitry Andric 5492a66634dSDimitry Andricdef Ampere1Write_34cyc_1BS : SchedWriteRes<[Ampere1UnitBS]> { 5502a66634dSDimitry Andric let Latency = 34; 5512a66634dSDimitry Andric let NumMicroOps = 1; 5522a66634dSDimitry Andric} 5532a66634dSDimitry Andric 5542a66634dSDimitry Andricdef Ampere1Write_34cyc_1XY : SchedWriteRes<[Ampere1UnitXY]> { 5552a66634dSDimitry Andric let Latency = 34; 5562a66634dSDimitry Andric let NumMicroOps = 1; 5572a66634dSDimitry Andric} 5582a66634dSDimitry Andric 5592a66634dSDimitry Andricdef Ampere1Write_39cyc_1XY : SchedWriteRes<[Ampere1UnitXY]> { 5602a66634dSDimitry Andric let Latency = 39; 5612a66634dSDimitry Andric let NumMicroOps = 1; 5622a66634dSDimitry Andric} 5632a66634dSDimitry Andric 5642a66634dSDimitry Andricdef Ampere1Write_62cyc_1XY : SchedWriteRes<[Ampere1UnitXY]> { 5652a66634dSDimitry Andric let Latency = 62; 5662a66634dSDimitry Andric let NumMicroOps = 1; 5672a66634dSDimitry Andric} 5682a66634dSDimitry Andric 5692a66634dSDimitry Andric// For basic arithmetic, we have more flexibility for short shifts (LSL shift <= 4), 5702a66634dSDimitry Andric// which are a single uop, and for extended registers, which have full flexibility 5712a66634dSDimitry Andric// across Unit A or B for both uops. 5722a66634dSDimitry Andricdef Ampere1Write_Arith : SchedWriteVariant<[ 5732a66634dSDimitry Andric SchedVar<RegExtendedPred, [Ampere1Write_2cyc_2AB]>, 57406c3fb27SDimitry Andric SchedVar<IsCheapLSL, [Ampere1Write_1cyc_1AB]>, 5752a66634dSDimitry Andric SchedVar<NoSchedPred, [Ampere1Write_2cyc_1B_1AB]>]>; 5762a66634dSDimitry Andric 5772a66634dSDimitry Andricdef Ampere1Write_ArithFlagsetting : SchedWriteVariant<[ 5782a66634dSDimitry Andric SchedVar<RegExtendedPred, [Ampere1Write_2cyc_1AB_1A]>, 57906c3fb27SDimitry Andric SchedVar<IsCheapLSL, [Ampere1Write_1cyc_1A]>, 5802a66634dSDimitry Andric SchedVar<NoSchedPred, [Ampere1Write_2cyc_1B_1A]>]>; 5812a66634dSDimitry Andric 5822a66634dSDimitry Andric//===----------------------------------------------------------------------===// 5832a66634dSDimitry Andric// Map the target-defined scheduler read/write resources and latencies for Ampere-1. 5842a66634dSDimitry Andric// This provides a coarse model, which is then specialised below. 5852a66634dSDimitry Andric 5862a66634dSDimitry Andricdef : WriteRes<WriteImm, [Ampere1UnitAB]>; // MOVN, MOVZ 5872a66634dSDimitry Andricdef : WriteRes<WriteI, [Ampere1UnitAB]>; // ALU 5882a66634dSDimitry Andricdef : WriteRes<WriteISReg, [Ampere1UnitB, Ampere1UnitA]> { 5892a66634dSDimitry Andric let Latency = 2; 5902a66634dSDimitry Andric let NumMicroOps = 2; 5912a66634dSDimitry Andric} // ALU of Shifted-Reg 5922a66634dSDimitry Andricdef : WriteRes<WriteIEReg, [Ampere1UnitAB, Ampere1UnitA]> { 5932a66634dSDimitry Andric let Latency = 2; 5942a66634dSDimitry Andric let NumMicroOps = 2; 5952a66634dSDimitry Andric} // ALU of Extended-Reg 5962a66634dSDimitry Andricdef : WriteRes<WriteExtr, [Ampere1UnitB]>; // EXTR shifts a reg pair 5972a66634dSDimitry Andricdef : WriteRes<WriteIS, [Ampere1UnitB]>; // Shift/Scale 5982a66634dSDimitry Andricdef : WriteRes<WriteID32, [Ampere1UnitBS]> { 5992a66634dSDimitry Andric let Latency = 18; 6002a66634dSDimitry Andric} // 32-bit Divide 6012a66634dSDimitry Andricdef : WriteRes<WriteID64, [Ampere1UnitBS]> { 6022a66634dSDimitry Andric let Latency = 34; 6032a66634dSDimitry Andric} // 64-bit Divide 6042a66634dSDimitry Andricdef : WriteRes<WriteIM32, [Ampere1UnitBS]> { 6052a66634dSDimitry Andric let Latency = 3; 6062a66634dSDimitry Andric} // 32-bit Multiply 6072a66634dSDimitry Andricdef : WriteRes<WriteIM64, [Ampere1UnitBS]> { 6082a66634dSDimitry Andric let Latency = 3; 6092a66634dSDimitry Andric} // 32-bit Multiply 6102a66634dSDimitry Andricdef : WriteRes<WriteBr, [Ampere1UnitA]>; 6112a66634dSDimitry Andricdef : WriteRes<WriteBrReg, [Ampere1UnitA, Ampere1UnitA]>; 6122a66634dSDimitry Andricdef : WriteRes<WriteLD, [Ampere1UnitL]> { 6132a66634dSDimitry Andric let Latency = 4; 6142a66634dSDimitry Andric} // Load from base addr plus immediate offset 6152a66634dSDimitry Andricdef : WriteRes<WriteST, [Ampere1UnitS]> { 6162a66634dSDimitry Andric let Latency = 1; 6172a66634dSDimitry Andric} // Store to base addr plus immediate offset 6182a66634dSDimitry Andricdef : WriteRes<WriteSTP, [Ampere1UnitS, Ampere1UnitS]> { 6192a66634dSDimitry Andric let Latency = 1; 6202a66634dSDimitry Andric let NumMicroOps = 2; 6212a66634dSDimitry Andric} // Store a register pair. 6222a66634dSDimitry Andricdef : WriteRes<WriteAdr, [Ampere1UnitAB]>; 6232a66634dSDimitry Andricdef : WriteRes<WriteLDIdx, [Ampere1UnitAB, Ampere1UnitS]> { 6242a66634dSDimitry Andric let Latency = 5; 6252a66634dSDimitry Andric let NumMicroOps = 2; 6262a66634dSDimitry Andric} // Load from a register index (maybe scaled). 6272a66634dSDimitry Andricdef : WriteRes<WriteSTIdx, [Ampere1UnitS, Ampere1UnitS]> { 6282a66634dSDimitry Andric let Latency = 1; 6292a66634dSDimitry Andric let NumMicroOps = 2; 6302a66634dSDimitry Andric} // Store to a register index (maybe scaled). 6312a66634dSDimitry Andricdef : WriteRes<WriteF, [Ampere1UnitXY]> { 6322a66634dSDimitry Andric let Latency = 2; 6332a66634dSDimitry Andric} // General floating-point ops. 6342a66634dSDimitry Andricdef : WriteRes<WriteFCmp, [Ampere1UnitX]> { 6352a66634dSDimitry Andric let Latency = 5; 6362a66634dSDimitry Andric} // Floating-point compare. 6372a66634dSDimitry Andricdef : WriteRes<WriteFCvt, [Ampere1UnitXY]> { 6382a66634dSDimitry Andric let Latency = 6; 6392a66634dSDimitry Andric} // Float conversion. 6402a66634dSDimitry Andricdef : WriteRes<WriteFCopy, [Ampere1UnitXY]> { 6412a66634dSDimitry Andric} // Float-int register copy. 6422a66634dSDimitry Andricdef : WriteRes<WriteFImm, [Ampere1UnitXY]> { 6432a66634dSDimitry Andric let Latency = 2; 6442a66634dSDimitry Andric} // Float-int register copy. 6452a66634dSDimitry Andricdef : WriteRes<WriteFMul, [Ampere1UnitXY]> { 6462a66634dSDimitry Andric let Latency = 5; 6472a66634dSDimitry Andric} // Floating-point multiply. 6482a66634dSDimitry Andricdef : WriteRes<WriteFDiv, [Ampere1UnitXY]> { 6492a66634dSDimitry Andric let Latency = 34; 6502a66634dSDimitry Andric} // Floating-point division. 6512a66634dSDimitry Andricdef : WriteRes<WriteVd, [Ampere1UnitXY]> { 6522a66634dSDimitry Andric let Latency = 3; 6532a66634dSDimitry Andric} // 64bit Vector D ops. 6542a66634dSDimitry Andricdef : WriteRes<WriteVq, [Ampere1UnitXY]> { 6552a66634dSDimitry Andric let Latency = 3; 6562a66634dSDimitry Andric} // 128bit Vector Q ops. 6572a66634dSDimitry Andricdef : WriteRes<WriteVLD, [Ampere1UnitL, Ampere1UnitL]> { 6582a66634dSDimitry Andric let Latency = 5; 6592a66634dSDimitry Andric} // Vector loads. 6602a66634dSDimitry Andricdef : WriteRes<WriteVST, [Ampere1UnitS, Ampere1UnitZ]> { 6612a66634dSDimitry Andric let Latency = 2; 6622a66634dSDimitry Andric} // Vector stores. 6632a66634dSDimitry Andric 6642a66634dSDimitry Andricdef : WriteRes<WriteAtomic, []> { let Unsupported = 1; } 6652a66634dSDimitry Andric 6662a66634dSDimitry Andricdef : WriteRes<WriteSys, []> { let Latency = 1; } 6672a66634dSDimitry Andricdef : WriteRes<WriteBarrier, []> { let Latency = 1; } 6682a66634dSDimitry Andricdef : WriteRes<WriteHint, []> { let Latency = 1; } 6692a66634dSDimitry Andric 6702a66634dSDimitry Andricdef : WriteRes<WriteLDHi, []> { 6712a66634dSDimitry Andric let Latency = 4; 6722a66634dSDimitry Andric} // The second register of a load-pair: LDP,LDPSW,LDNP,LDXP,LDAXP 6732a66634dSDimitry Andric 6742a66634dSDimitry Andric// Forwarding logic. 6752a66634dSDimitry Andricdef : ReadAdvance<ReadI, 0>; 6762a66634dSDimitry Andricdef : ReadAdvance<ReadISReg, 0>; 6772a66634dSDimitry Andricdef : ReadAdvance<ReadIEReg, 0>; 6782a66634dSDimitry Andricdef : ReadAdvance<ReadIM, 0>; 6792a66634dSDimitry Andricdef : ReadAdvance<ReadIMA, 1, [WriteIM32, WriteIM64]>; 6802a66634dSDimitry Andricdef : ReadAdvance<ReadID, 0>; 6812a66634dSDimitry Andricdef : ReadAdvance<ReadExtrHi, 0>; 6822a66634dSDimitry Andricdef : ReadAdvance<ReadST, 0>; 6832a66634dSDimitry Andricdef : ReadAdvance<ReadAdrBase, 0>; 6842a66634dSDimitry Andricdef : ReadAdvance<ReadVLD, 0>; 6852a66634dSDimitry Andric 6862a66634dSDimitry Andric//===----------------------------------------------------------------------===// 6872a66634dSDimitry Andric// Specialising the scheduling model further for Ampere-1. 6882a66634dSDimitry Andric 6892a66634dSDimitry Andricdef : InstRW<[Ampere1Write_1cyc_1AB], (instrs COPY)>; 6902a66634dSDimitry Andric 6912a66634dSDimitry Andric// Branch instructions 6922a66634dSDimitry Andricdef : InstRW<[Ampere1Write_1cyc_1A], (instrs Bcc, BL, RET)>; 6932a66634dSDimitry Andricdef : InstRW<[Ampere1Write_1cyc_1A], 6942a66634dSDimitry Andric (instrs CBZW, CBZX, CBNZW, CBNZX, TBZW, TBZX, TBNZW, TBNZX)>; 6952a66634dSDimitry Andricdef : InstRW<[Ampere1Write_1cyc_2A], (instrs BLR)>; 6962a66634dSDimitry Andric 6972a66634dSDimitry Andric// Cryptography instructions 6982a66634dSDimitry Andric// -- AES encryption/decryption 6992a66634dSDimitry Andricdef : InstRW<[Ampere1Write_2cyc_1XY], (instregex "^AES[DE]")>; 7002a66634dSDimitry Andricdef : InstRW<[Ampere1Write_2cyc_1XY], (instregex "^AESI?MC")>; 7012a66634dSDimitry Andric// -- Polynomial multiplication 7022a66634dSDimitry Andricdef : InstRW<[Ampere1Write_2cyc_1XY], (instregex "^PMUL", "^PMULL")>; 7032a66634dSDimitry Andric// -- SHA-256 hash 7042a66634dSDimitry Andricdef : InstRW<[Ampere1Write_4cyc_1X], (instregex "^SHA256(H|H2)")>; 7052a66634dSDimitry Andric// -- SHA-256 schedule update 7062a66634dSDimitry Andricdef : InstRW<[Ampere1Write_4cyc_1Y], (instregex "^SHA256SU[01]")>; 7072a66634dSDimitry Andric// -- SHA-3 instructions 7082a66634dSDimitry Andricdef : InstRW<[Ampere1Write_2cyc_1XY], 7092a66634dSDimitry Andric (instregex "^BCAX", "^EOR3", "^RAX1", "^XAR")>; 7102a66634dSDimitry Andric// -- SHA-512 hash 7112a66634dSDimitry Andricdef : InstRW<[Ampere1Write_4cyc_1X], (instregex "^SHA512(H|H2)")>; 7122a66634dSDimitry Andric// -- SHA-512 schedule update 7132a66634dSDimitry Andricdef : InstRW<[Ampere1Write_4cyc_1Y], (instregex "^SHA512SU[01]")>; 7142a66634dSDimitry Andric// -- SHA1 choose/majority/parity 7152a66634dSDimitry Andricdef : InstRW<[Ampere1Write_4cyc_1X], (instregex "^SHA1[CMP]")>; 7162a66634dSDimitry Andric// -- SHA1 hash/schedule update 7172a66634dSDimitry Andricdef : InstRW<[Ampere1Write_2cyc_1Y], (instregex "^SHA1SU[01]")>; 7182a66634dSDimitry Andricdef : InstRW<[Ampere1Write_2cyc_1Y], (instregex "^SHA1H")>; 7192a66634dSDimitry Andric 7202a66634dSDimitry Andric// FP and vector load instructions 7212a66634dSDimitry Andric// -- Load 1-element structure to one/all lanes 7222a66634dSDimitry Andric// ---- all lanes 7232a66634dSDimitry Andricdef : InstRW<[Ampere1Write_7cyc_1L_1XY], 7242a66634dSDimitry Andric (instregex "^LD1Rv(8b|4h|2s|16b|8h|4s|2d)")>; 7252a66634dSDimitry Andric// ---- one lane 7262a66634dSDimitry Andricdef : InstRW<[Ampere1Write_7cyc_1L_1XY], 7272a66634dSDimitry Andric (instregex "^LD1i(8|16|32|64)")>; 7282a66634dSDimitry Andric// -- Load 1-element structure to one/all lanes, 1D size 7292a66634dSDimitry Andricdef : InstRW<[Ampere1Write_5cyc_1L], 7302a66634dSDimitry Andric (instregex "^LD1Rv1d")>; 7312a66634dSDimitry Andric// -- Load 1-element structures to 1 register 7322a66634dSDimitry Andricdef : InstRW<[Ampere1Write_5cyc_1L], 7332a66634dSDimitry Andric (instregex "^LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)")>; 7342a66634dSDimitry Andric// -- Load 1-element structures to 2 registers 7352a66634dSDimitry Andricdef : InstRW<[Ampere1Write_5cyc_2L], 7362a66634dSDimitry Andric (instregex "^LD1Twov(8b|4h|2s|1d|16b|8h|4s|2d)")>; 7372a66634dSDimitry Andric// -- Load 1-element structures to 3 registers 7382a66634dSDimitry Andricdef : InstRW<[Ampere1Write_6cyc_3L], 7392a66634dSDimitry Andric (instregex "^LD1Threev(8b|4h|2s|1d|16b|8h|4s|2d)")>; 7402a66634dSDimitry Andric// -- Load 1-element structures to 4 registers 7412a66634dSDimitry Andricdef : InstRW<[Ampere1Write_6cyc_4L], 7422a66634dSDimitry Andric (instregex "^LD1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)")>; 7432a66634dSDimitry Andric// -- Load 2-element structure to all lanes of 2 registers, 1D size 7442a66634dSDimitry Andricdef : InstRW<[Ampere1Write_5cyc_2L], 7452a66634dSDimitry Andric (instregex "^LD2Rv1d")>; 7462a66634dSDimitry Andric// -- Load 2-element structure to all lanes of 2 registers, other sizes 7472a66634dSDimitry Andricdef : InstRW<[Ampere1Write_7cyc_2L_2XY], 7482a66634dSDimitry Andric (instregex "^LD2Rv(8b|4h|2s|16b|8h|4s|2d)")>; 7492a66634dSDimitry Andric// -- Load 2-element structure to one lane of 2 registers 7502a66634dSDimitry Andricdef : InstRW<[Ampere1Write_7cyc_2L_2XY], 7512a66634dSDimitry Andric (instregex "^LD2i(8|16|32|64)")>; 7522a66634dSDimitry Andric// -- Load 2-element structures to 2 registers, 16B/8H/4S/2D size 7532a66634dSDimitry Andricdef : InstRW<[Ampere1Write_7cyc_2L_2XY], 7542a66634dSDimitry Andric (instregex "^LD2Twov(16b|8h|4s|2d)")>; 7552a66634dSDimitry Andric// -- Load 2-element structures to 2 registers, 8B/4H/2S size 7562a66634dSDimitry Andricdef : InstRW<[Ampere1Write_9cyc_2L_3XY], 7572a66634dSDimitry Andric (instregex "^LD2Twov(8b|4h|2s)")>; 7582a66634dSDimitry Andric// -- Load 3-element structure to all lanes of 3 registers, 1D size 7592a66634dSDimitry Andricdef : InstRW<[Ampere1Write_6cyc_3L], 7602a66634dSDimitry Andric (instregex "^LD3Rv1d")>; 7612a66634dSDimitry Andric// -- Load 3-element structure to all lanes of 3 registers, other sizes 7622a66634dSDimitry Andricdef : InstRW<[Ampere1Write_8cyc_3L_3XY], 7632a66634dSDimitry Andric (instregex "^LD3Rv(8b|4h|2s|16b|8h|4s|2d)")>; 7642a66634dSDimitry Andric// -- Load 3-element structure to one lane of 3 registers 7652a66634dSDimitry Andricdef : InstRW<[Ampere1Write_8cyc_3L_3XY], 7662a66634dSDimitry Andric (instregex "^LD3i(8|16|32|64)")>; 7672a66634dSDimitry Andric// -- Load 3-element structures to 3 registers, 16B/8H/4S sizes 7682a66634dSDimitry Andricdef : InstRW<[Ampere1Write_9cyc_3L_3XY], 7692a66634dSDimitry Andric (instregex "^LD3Threev(16b|8h|4s)")>; 7702a66634dSDimitry Andric// -- Load 3-element structures to 3 registers, 2D size 7712a66634dSDimitry Andricdef : InstRW<[Ampere1Write_8cyc_3L_3XY], 7722a66634dSDimitry Andric (instregex "^LD3Threev2d")>; 7732a66634dSDimitry Andric// -- Load 3-element structures to 3 registers, 8B/4H/2S sizes 7742a66634dSDimitry Andricdef : InstRW<[Ampere1Write_10cyc_3L_3XY], 7752a66634dSDimitry Andric (instregex "^LD3Threev(8b|4h|2s)")>; 7762a66634dSDimitry Andric// -- Load 4-element structure to all lanes of 4 registers, 1D size 7772a66634dSDimitry Andricdef : InstRW<[Ampere1Write_6cyc_4L], 7782a66634dSDimitry Andric (instregex "^LD4Rv1d")>; 7792a66634dSDimitry Andric// -- Load 4-element structure to all lanes of 4 registers, other sizes 7802a66634dSDimitry Andricdef : InstRW<[Ampere1Write_8cyc_4L_4XY], 7812a66634dSDimitry Andric (instregex "^LD4Rv(8b|4h|2s|16b|8h|4s|2d)")>; 7822a66634dSDimitry Andric// -- Load 4-element structure to one lane of 4 registers 7832a66634dSDimitry Andricdef : InstRW<[Ampere1Write_6cyc_4L], 7842a66634dSDimitry Andric (instregex "^LD4i(8|16|32|64)")>; 7852a66634dSDimitry Andric// -- Load 4-element structures to 4 registers, 2D size 7862a66634dSDimitry Andricdef : InstRW<[Ampere1Write_9cyc_4L_4XY], 7872a66634dSDimitry Andric (instregex "^LD4Fourv2d")>; 7882a66634dSDimitry Andric// -- Load 4-element structures to 4 registers, 2S size 7892a66634dSDimitry Andricdef : InstRW<[Ampere1Write_12cyc_4L_8XY], 7902a66634dSDimitry Andric (instregex "^LD4Fourv2s")>; 7912a66634dSDimitry Andric// -- Load 4-element structures to 4 registers, other sizes 7922a66634dSDimitry Andricdef : InstRW<[Ampere1Write_11cyc_4L_8XY], 7932a66634dSDimitry Andric (instregex "^LD4Fourv(8b|4h|16b|8h|4s)")>; 7942a66634dSDimitry Andric// -- Load pair, Q-form 7952a66634dSDimitry Andricdef : InstRW<[Ampere1Write_5cyc_2L], (instregex "LDN?PQ")>; 7962a66634dSDimitry Andric// -- Load pair, S/D-form 7972a66634dSDimitry Andricdef : InstRW<[Ampere1Write_5cyc_1L_1BS], (instregex "LDN?P(S|D)")>; 7982a66634dSDimitry Andric// -- Load register 7992a66634dSDimitry Andricdef : InstRW<[Ampere1Write_5cyc_1L], (instregex "LDU?R[BHSDQ]i")>; 8002a66634dSDimitry Andric// -- Load register, sign-extended register 8012a66634dSDimitry Andricdef : InstRW<[Ampere1Write_6cyc_1AB_1L], (instregex "LDR[BHSDQ]ro(W|X)")>; 8022a66634dSDimitry Andric 8032a66634dSDimitry Andric// FP and vector store instructions 8042a66634dSDimitry Andric// -- Store 1-element structure from one lane of 1 register 8052a66634dSDimitry Andricdef : InstRW<[Ampere1Write_4cyc_1XY_1S_1Z], 8062a66634dSDimitry Andric (instregex "^ST1i(8|16|32|64)")>; 8072a66634dSDimitry Andric// -- Store 1-element structures from 1 register 8082a66634dSDimitry Andricdef : InstRW<[Ampere1Write_2cyc_1S_1Z], 8092a66634dSDimitry Andric (instregex "^ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)")>; 8102a66634dSDimitry Andric// -- Store 1-element structures from 2 registers 8112a66634dSDimitry Andricdef : InstRW<[Ampere1Write_3cyc_2S_2Z], 8122a66634dSDimitry Andric (instregex "^ST1Twov(8b|4h|2s|1d|16b|8h|4s|2d)")>; 8132a66634dSDimitry Andric// -- Store 1-element structures from 3 registers 8142a66634dSDimitry Andricdef : InstRW<[Ampere1Write_4cyc_3S_3Z], 8152a66634dSDimitry Andric (instregex "^ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)")>; 8162a66634dSDimitry Andric// -- Store 1-element structures from 4 registers 8172a66634dSDimitry Andricdef : InstRW<[Ampere1Write_5cyc_4S_4Z], 8182a66634dSDimitry Andric (instregex "^ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)")>; 8192a66634dSDimitry Andric// -- Store 2-element structure from one lane of 2 registers 8202a66634dSDimitry Andricdef : InstRW<[Ampere1Write_5cyc_2XY_2S_2Z], 8212a66634dSDimitry Andric (instregex "^ST2i(8|16|32|64)")>; 8222a66634dSDimitry Andric// -- Store 2-element structures from 2 registers, 16B/8H/4S/2D sizes 8232a66634dSDimitry Andricdef : InstRW<[Ampere1Write_5cyc_2XY_2S_2Z], 8242a66634dSDimitry Andric (instregex "^ST2Twov(16b|8h|4s|2d)")>; 8252a66634dSDimitry Andric// -- Store 2-element structures from 2 registers, 8B/4H/2S sizes 8262a66634dSDimitry Andricdef : InstRW<[Ampere1Write_6cyc_2XY_2S_2Z], 8272a66634dSDimitry Andric (instregex "^ST2Twov(8b|4h|2s)")>; 8282a66634dSDimitry Andric// -- Store 3-element structure from one lane of 3 registers 8292a66634dSDimitry Andricdef : InstRW<[Ampere1Write_6cyc_3XY_3S_3Z], 8302a66634dSDimitry Andric (instregex "^ST3i(8|16|32|64)")>; 8312a66634dSDimitry Andric// -- Store 3-element structures from 3 registers 8322a66634dSDimitry Andricdef : InstRW<[Ampere1Write_6cyc_3XY_3S_3Z], 8332a66634dSDimitry Andric (instregex "^ST3Threev(8b|4h|2s|1d|16b|8h|4s|2d)")>; 8342a66634dSDimitry Andric// -- Store 4-element structure from one lane of 4 registers 8352a66634dSDimitry Andricdef : InstRW<[Ampere1Write_7cyc_4XY_4S_4Z], 8362a66634dSDimitry Andric (instregex "^ST4i(8|16|32|64)")>; 8372a66634dSDimitry Andric// -- Store 4-element structures from 4 registers, 16B/8H/4S sizes 8382a66634dSDimitry Andricdef : InstRW<[Ampere1Write_9cyc_8XY_4S_4Z], 8392a66634dSDimitry Andric (instregex "^ST4Fourv(16b|8h|4s)")>; 8402a66634dSDimitry Andric// -- Store 4-element structures from 4 registers, 2D sizes 8412a66634dSDimitry Andricdef : InstRW<[Ampere1Write_7cyc_4XY_4S_4Z], 8422a66634dSDimitry Andric (instregex "^ST4Fourv2d")>; 8432a66634dSDimitry Andric// -- Store 4-element structures from 4 registers, 8B/4H/2S sizes 8442a66634dSDimitry Andricdef : InstRW<[Ampere1Write_9cyc_6XY_4S_4Z], 8452a66634dSDimitry Andric (instregex "^ST4Fourv(8b|4h|2s)")>; 8462a66634dSDimitry Andric// -- Store pair, Q-form 8472a66634dSDimitry Andricdef : InstRW<[Ampere1Write_3cyc_2S_2Z], (instregex "^STN?PQ")>; 8482a66634dSDimitry Andric// -- Store pair, S/D-form 8492a66634dSDimitry Andricdef : InstRW<[Ampere1Write_3cyc_1S_2Z], (instregex "^STN?P[SD]")>; 8502a66634dSDimitry Andric// -- Store register 8512a66634dSDimitry Andricdef : InstRW<[Ampere1Write_2cyc_1S_1Z], (instregex "^STU?R[BHSDQ](ui|i)")>; 8522a66634dSDimitry Andric// -- Store register, sign-extended register offset 8532a66634dSDimitry Andricdef : InstRW<[Ampere1Write_2cyc_1AB_1S_1Z], (instregex "^STR[BHSDQ]ro[XW]")>; 8542a66634dSDimitry Andric 8552a66634dSDimitry Andric// FP data processing, bfloat16 format 8562a66634dSDimitry Andricdef : InstRW<[Ampere1Write_5cyc_1XY], (instrs BFCVT)>; 8572a66634dSDimitry Andricdef : InstRW<[Ampere1Write_7cyc_2XY], (instrs BFCVTN, BFCVTN2)>; 8582a66634dSDimitry Andricdef : InstRW<[Ampere1Write_2cyc_1XY], (instregex "^BFDOTv", "^BF16DOT")>; 8592a66634dSDimitry Andricdef : InstRW<[Ampere1Write_4cyc_2XY], (instrs BFMMLA)>; 8602a66634dSDimitry Andricdef : InstRW<[Ampere1Write_5cyc_1XY], (instregex "^BFMLAL")>; 8612a66634dSDimitry Andric 8622a66634dSDimitry Andric// FP data processing, scalar/vector, half precision 8632a66634dSDimitry Andricdef : InstRW<[Ampere1Write_4cyc_1XY], (instregex "^F(ABD|ABS)v.[fi]16")>; 8642a66634dSDimitry Andricdef : InstRW<[Ampere1Write_4cyc_1XY], 8652a66634dSDimitry Andric (instregex "^F(ADD|ADDP|CADD|NEG|NMUL|SUB)v.[fi]16")>; 8662a66634dSDimitry Andricdef : InstRW<[Ampere1Write_4cyc_1XY], 8672a66634dSDimitry Andric (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)v.[fi]16")>; 8682a66634dSDimitry Andricdef : InstRW<[Ampere1Write_4cyc_1XY], 8692a66634dSDimitry Andric (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)16")>; 8702a66634dSDimitry Andricdef : InstRW<[Ampere1Write_4cyc_1X], 8712a66634dSDimitry Andric (instregex "^FCMPE?H")>; 8722a66634dSDimitry Andricdef : InstRW<[Ampere1Write_10cyc_1A_1BS_1X], 8732a66634dSDimitry Andric (instregex "^FCCMPE?H")>; 8742a66634dSDimitry Andricdef : InstRW<[Ampere1Write_10cyc_1A_1BS_1XY], 8752a66634dSDimitry Andric (instregex "^FCSELH")>; 8762a66634dSDimitry Andricdef : InstRW<[Ampere1Write_4cyc_1XY], (instregex "^FCVT[AMNPZ][SU]v.[if]16")>; 8772a66634dSDimitry Andricdef : InstRW<[Ampere1Write_4cyc_1XY], (instregex "^[SU]CVTFv.[fi]16")>; 8782a66634dSDimitry Andricdef : InstRW<[Ampere1Write_25cyc_1XY], (instregex "^FDIVv.[if]16", "FDIVH")>; 8792a66634dSDimitry Andricdef : InstRW<[Ampere1Write_4cyc_1XY], (instregex "^F(MAX|MIN)(NM)?P?v.[if]16")>; 8802a66634dSDimitry Andricdef : InstRW<[Ampere1Write_8cyc_2XY], (instregex "^F(MAX|MIN)(NM)?Vv4[if]16")>; 8812a66634dSDimitry Andricdef : InstRW<[Ampere1Write_12cyc_3XY], (instregex "^F(MAX|MIN)(NM)?Vv8[if]16")>; 8822a66634dSDimitry Andricdef : InstRW<[Ampere1Write_4cyc_1XY], (instregex "^FMULX?v.[if]16")>; 8832a66634dSDimitry Andricdef : InstRW<[Ampere1Write_4cyc_1XY], (instrs FMULX16)>; 8842a66634dSDimitry Andricdef : InstRW<[Ampere1Write_4cyc_1XY], (instregex "^FN?M(ADD|SUB)[H]rrr")>; 8852a66634dSDimitry Andricdef : InstRW<[Ampere1Write_4cyc_1XY], (instregex "^FML[AS]v.[if]16")>; 8862a66634dSDimitry Andricdef : InstRW<[Ampere1Write_4cyc_1XY], (instregex "^FRECPXv.[if]16")>; 8872a66634dSDimitry Andricdef : InstRW<[Ampere1Write_4cyc_1XY], (instregex "^F(RECP|RSQRT)S16")>; 8882a66634dSDimitry Andricdef : InstRW<[Ampere1Write_4cyc_1XY], (instregex "^FRINT[AIMNPXZ]v.[if]16")>; 8892a66634dSDimitry Andricdef : InstRW<[Ampere1Write_39cyc_1XY], (instregex "^FSQRTv.f16", "^FSQRTHr")>; 8902a66634dSDimitry Andric 8912a66634dSDimitry Andric// FP data processing, scalar/vector, single/double precision 8922a66634dSDimitry Andricdef : InstRW<[Ampere1Write_5cyc_1XY], (instregex "^F(ABD|ABS)v.[fi](32|64)")>; 8932a66634dSDimitry Andricdef : InstRW<[Ampere1Write_5cyc_1XY], 8942a66634dSDimitry Andric (instregex "^F(ADD|ADDP|CADD|NEG|NMUL|SUB)v.[fi](32|64)")>; 8952a66634dSDimitry Andricdef : InstRW<[Ampere1Write_5cyc_1XY], 8962a66634dSDimitry Andric (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)v.[fi](32|64)")>; 8972a66634dSDimitry Andricdef : InstRW<[Ampere1Write_5cyc_1XY], 8982a66634dSDimitry Andric (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)(32|64)")>; 8992a66634dSDimitry Andricdef : InstRW<[Ampere1Write_5cyc_1X], 9002a66634dSDimitry Andric (instregex "^FCMPE?(S|D)")>; 9012a66634dSDimitry Andricdef : InstRW<[Ampere1Write_11cyc_1A_1BS_1X], 9022a66634dSDimitry Andric (instregex "^FCCMPE?(S|D)")>; 9032a66634dSDimitry Andricdef : InstRW<[Ampere1Write_11cyc_1A_1BS_1XY], 9042a66634dSDimitry Andric (instregex "^FCSEL(S|D)")>; 9052a66634dSDimitry Andricdef : InstRW<[Ampere1Write_6cyc_1XY], (instregex "^FCVT[AMNPZ][SU]v.[if](32|64)")>; 9062a66634dSDimitry Andricdef : InstRW<[Ampere1Write_6cyc_1XY], (instregex "^[SU]CVTFv.[fi](32|64)")>; 9072a66634dSDimitry Andricdef : InstRW<[Ampere1Write_34cyc_1XY], (instregex "^FDIVv.[if](64)", "FDIVD")>; 9082a66634dSDimitry Andricdef : InstRW<[Ampere1Write_19cyc_1XY], (instregex "^FDIVv.[if](32)", "FDIVS")>; 9092a66634dSDimitry Andricdef : InstRW<[Ampere1Write_5cyc_1XY], (instregex "^F(MAX|MIN)(NM)?P?v.[if](32|64)")>; 9102a66634dSDimitry Andricdef : InstRW<[Ampere1Write_10cyc_2XY], (instregex "^F(MAX|MIN)(NM)?Vv.[if](32|64)")>; 9112a66634dSDimitry Andricdef : InstRW<[Ampere1Write_6cyc_1XY], (instregex "^FMULX?v.[if](32|64)")>; 9122a66634dSDimitry Andricdef : InstRW<[Ampere1Write_6cyc_1XY], (instrs FMULX32, FMULX64)>; 9132a66634dSDimitry Andricdef : InstRW<[Ampere1Write_5cyc_1XY], (instregex "^FN?M(ADD|SUB)[SD]rrr")>; 9142a66634dSDimitry Andricdef : InstRW<[Ampere1Write_5cyc_1XY], (instregex "^FML[AS]v.[if](32|64)")>; 9152a66634dSDimitry Andricdef : InstRW<[Ampere1Write_5cyc_1XY], (instregex "^FRECPXv.[if](32|64)")>; 9162a66634dSDimitry Andricdef : InstRW<[Ampere1Write_6cyc_1XY], (instregex "^F(RECP|RSQRT)S(32|64)")>; 9172a66634dSDimitry Andricdef : InstRW<[Ampere1Write_6cyc_1XY], (instregex "^FRINT[AIMNPXZ]v.[if](32|64)")>; 9182a66634dSDimitry Andricdef : InstRW<[Ampere1Write_6cyc_1XY], (instregex "^FRINT(32|64)")>; 9192a66634dSDimitry Andricdef : InstRW<[Ampere1Write_62cyc_1XY], (instregex "^FSQRTv.f64", "^FSQRTDr")>; 9202a66634dSDimitry Andricdef : InstRW<[Ampere1Write_32cyc_1XY], (instregex "^FSQRTv.f32", "^FSQRTSr")>; 9212a66634dSDimitry Andric 9222a66634dSDimitry Andric// FP miscellaneous instructions 9232a66634dSDimitry Andricdef : InstRW<[Ampere1Write_10cyc_1XY_1Z], (instregex "^FCVT[AMNPZ][SU][SU][XW][HSD]r")>; 9242a66634dSDimitry Andricdef : InstRW<[Ampere1Write_5cyc_1XY], (instregex "^FCVT[HSD]Hr")>; 9252a66634dSDimitry Andricdef : InstRW<[Ampere1Write_6cyc_1XY], (instregex "^FCVT[HSD][SD]r")>; 9262a66634dSDimitry Andricdef : InstRW<[Ampere1Write_6cyc_1XY], (instregex "^FCVTLv")>; 9272a66634dSDimitry Andricdef : InstRW<[Ampere1Write_8cyc_2XY], (instregex "^FCVT(N|XN)v")>; 9282a66634dSDimitry Andricdef : InstRW<[Ampere1Write_10cyc_1X_1Z], (instrs FJCVTZS)>; 9292a66634dSDimitry Andricdef : InstRW<[Ampere1Write_5cyc_1BS], (instregex "^FMOV[HSD][WX]r")>; 9302a66634dSDimitry Andricdef : InstRW<[Ampere1Write_7cyc_1BS_1XY], (instregex "^FMOVDXHighr")>; 9312a66634dSDimitry Andricdef : InstRW<[Ampere1Write_2cyc_1XY], (instregex "^FMOV[HSD][ri]")>; 9322a66634dSDimitry Andricdef : InstRW<[Ampere1Write_6cyc_1XY_1Z], (instregex "^FMOVXDHighr")>; 9332a66634dSDimitry Andricdef : InstRW<[Ampere1Write_4cyc_1Z], (instregex "^FMOV[WX][HSD]r")>; 9342a66634dSDimitry Andric 9352a66634dSDimitry Andric// Integer arithmetic and logical instructions 9362a66634dSDimitry Andricdef : InstRW<[Ampere1Write_1cyc_1A], 9372a66634dSDimitry Andric (instregex "ADC(W|X)r", "SBC(W|X)r")>; 9382a66634dSDimitry Andricdef : InstRW<[Ampere1Write_Arith], 939*5f757f3fSDimitry Andric (instregex "(ADD|AND|BIC|EON|EOR|ORN|ORR|SUB)(W|X)r[sx]")>; 940*5f757f3fSDimitry Andricdef : InstRW<[Ampere1Write_1cyc_1AB], 941*5f757f3fSDimitry Andric (instregex "(ADD|AND|BIC|EON|EOR|ORN|ORR|SUB)(W|X)r[ri]")>; 9422a66634dSDimitry Andricdef : InstRW<[Ampere1Write_ArithFlagsetting], 943*5f757f3fSDimitry Andric (instregex "(ADD|AND|BIC|SUB)S(W|X)r[sx]")>; 944*5f757f3fSDimitry Andricdef : InstRW<[Ampere1Write_1cyc_1A], 945*5f757f3fSDimitry Andric (instregex "(ADD|AND|BIC|SUB)S(W|X)r[ri]")>; 9462a66634dSDimitry Andricdef : InstRW<[Ampere1Write_1cyc_1A], 9472a66634dSDimitry Andric (instregex "(ADC|SBC)S(W|X)r")>; 9482a66634dSDimitry Andricdef : InstRW<[Ampere1Write_1cyc_1A], (instrs RMIF)>; 9492a66634dSDimitry Andricdef : InstRW<[Ampere1Write_1cyc_1A], 9502a66634dSDimitry Andric (instregex "(CCMN|CCMP)(X|W)")>; 9512a66634dSDimitry Andricdef : InstRW<[Ampere1Write_1cyc_1A], 9522a66634dSDimitry Andric (instregex "(CSEL|CSINC|CSINV|CSNEG)(X|W)")>; 9532a66634dSDimitry Andricdef : InstRW<[Ampere1Write_18cyc_1BS], (instrs SDIVWr, UDIVWr)>; 9542a66634dSDimitry Andricdef : InstRW<[Ampere1Write_34cyc_1BS], (instrs SDIVXr, UDIVXr)>; 9552a66634dSDimitry Andricdef : InstRW<[Ampere1Write_3cyc_1BS], 9562a66634dSDimitry Andric (instregex "(S|U)MULHr")>; 9572a66634dSDimitry Andricdef : InstRW<[Ampere1Write_4cyc_1BS], 9582a66634dSDimitry Andric (instregex "(S|U)?M(ADD|SUB)L?r")>; 9592a66634dSDimitry Andric 9602a66634dSDimitry Andric// Integer load instructions 9612a66634dSDimitry Andricdef : InstRW<[Ampere1Write_4cyc_2L], 9622a66634dSDimitry Andric (instregex "(LDNP|LDP|LDPSW)(X|W)")>; 9632a66634dSDimitry Andricdef : InstRW<[Ampere1Write_4cyc_1L], 9642a66634dSDimitry Andric (instregex "LDR(B|D|H|Q|S)ui")>; 9652a66634dSDimitry Andricdef : InstRW<[Ampere1Write_4cyc_1L], 9662a66634dSDimitry Andric (instregex "LDR(D|Q|W|X)l")>; 9672a66634dSDimitry Andricdef : InstRW<[Ampere1Write_4cyc_1L], 9682a66634dSDimitry Andric (instregex "LDTR(B|H|W|X)i")>; 9692a66634dSDimitry Andricdef : InstRW<[Ampere1Write_4cyc_1L], 9702a66634dSDimitry Andric (instregex "LDTRS(BW|BX|HW|HX|W)i")>; 9712a66634dSDimitry Andricdef : InstRW<[Ampere1Write_4cyc_1L], 9722a66634dSDimitry Andric (instregex "LDUR(BB|HH|X|W)i")>; 9732a66634dSDimitry Andricdef : InstRW<[Ampere1Write_4cyc_1L], 9742a66634dSDimitry Andric (instregex "LDURS(BW|BX|HW|HX|W)i")>; 9752a66634dSDimitry Andricdef : InstRW<[Ampere1Write_5cyc_1AB_1L], 9762a66634dSDimitry Andric (instregex "LDR(HH|SHW|SHX|W|X)ro(W|X)")>; 9772a66634dSDimitry Andricdef : InstRW<[Ampere1Write_1cyc_1L], 9782a66634dSDimitry Andric (instrs PRFMl, PRFUMi, PRFUMi)>; 9792a66634dSDimitry Andricdef : InstRW<[Ampere1Write_2cyc_1AB_1L], 9802a66634dSDimitry Andric (instrs PRFMroW, PRFMroX)>; 9812a66634dSDimitry Andric 9822a66634dSDimitry Andric// Integer miscellaneous instructions 9832a66634dSDimitry Andricdef : InstRW<[Ampere1Write_1cyc_1A], (instrs ADR, ADRP)>; 9842a66634dSDimitry Andricdef : InstRW<[Ampere1Write_1cyc_1B], (instregex "EXTR(W|X)")>; 9852a66634dSDimitry Andricdef : InstRW<[Ampere1Write_1cyc_1B], (instregex "(S|U)?BFM(W|X)")>; 9862a66634dSDimitry Andricdef : InstRW<[Ampere1Write_3cyc_1BS], (instregex "^CRC32C?[BHWX]")>; 9872a66634dSDimitry Andricdef : InstRW<[Ampere1Write_1cyc_1B], (instregex "CLS(W|X)")>; 9882a66634dSDimitry Andricdef : InstRW<[Ampere1Write_1cyc_1A], (instrs SETF8, SETF16)>; 9892a66634dSDimitry Andricdef : InstRW<[Ampere1Write_1cyc_1AB], 9902a66634dSDimitry Andric (instrs MOVKWi, MOVKXi, MOVNWi, MOVNXi, MOVZWi, MOVZXi)>; 9912a66634dSDimitry Andricdef : InstRW<[Ampere1Write_1cyc_1B], 9922a66634dSDimitry Andric (instregex "(RBIT|REV|REV16)(W|X)r", "REV32Xr")>; 9932a66634dSDimitry Andricdef : InstRW<[Ampere1Write_1cyc_1B], 9942a66634dSDimitry Andric (instregex "(ASR|LSL|LSR|ROR)V(W|X)r")>; 9952a66634dSDimitry Andric 9962a66634dSDimitry Andric// Integer store instructions 9972a66634dSDimitry Andricdef : InstRW<[Ampere1Write_1cyc_2S], (instregex "STNP(X|W)i")>; 9982a66634dSDimitry Andricdef : InstRW<[Ampere1Write_2cyc_1B_1S], 9992a66634dSDimitry Andric (instrs STPWi, STPXi)>; 10002a66634dSDimitry Andricdef : InstRW<[Ampere1Write_3cyc_1B_1S_1AB], 10012a66634dSDimitry Andric (instregex "STP(W|X)(pre|post)")>; 10022a66634dSDimitry Andricdef : InstRW<[Ampere1Write_1cyc_1S], 10032a66634dSDimitry Andric (instrs STTRBi, STTRHi, STTRWi, STTRXi)>; 10042a66634dSDimitry Andricdef : InstRW<[Ampere1Write_1cyc_1S], 10052a66634dSDimitry Andric (instregex "STUR(BB|HH|X|W)i", 10062a66634dSDimitry Andric "STR(X|W)ui", 10072a66634dSDimitry Andric "STUR(BB|HH|X|W)i")>; 10082a66634dSDimitry Andricdef : InstRW<[Ampere1Write_1cyc_2S], (instrs STRWroX, STRXroX)>; 10092a66634dSDimitry Andricdef : InstRW<[Ampere1Write_2cyc_1AB_2S], (instrs STRWroW, STRXroW)>; 10102a66634dSDimitry Andric 10112a66634dSDimitry Andric// Pointer authentication 10122a66634dSDimitry Andric//def : InstRW<[Ampere1Write_7cyc_1BS], 10132a66634dSDimitry Andric// (instrs AUTIAZ, AUTIBZ, AUTIASP, AUTIBSP, AUTIA1716, AUTIB1716)>; 10142a66634dSDimitry Andricdef : InstRW<[Ampere1Write_8cyc_1BS_1A], 10152a66634dSDimitry Andric (instregex "BRA(A|AZ|B|BZ)", "RETA(A|B)", "ERETA(A|B)")>; 10162a66634dSDimitry Andricdef : InstRW<[Ampere1Write_8cyc_1BS_2A], 10172a66634dSDimitry Andric (instrs BLRAA, BLRAAZ, BLRAB, BLRABZ)>; 10182a66634dSDimitry Andric//def : InstRW<[Ampere1Write_7cyc_1BS], 10192a66634dSDimitry Andric// (instrs PACIAZ, PACIBZ, PACIASP, PACIBSP, PACIA1716, PACIB1716)>; 10202a66634dSDimitry Andricdef : InstRW<[Ampere1Write_11cyc_1BS_1L], (instregex "^LDRA(A|B)")>; 10212a66634dSDimitry Andricdef : InstRW<[Ampere1Write_7cyc_1BS], (instrs XPACD, XPACI)>; 10222a66634dSDimitry Andric 10232a66634dSDimitry Andric// Vector integer instructions 10242a66634dSDimitry Andric// -- absolute difference 10252a66634dSDimitry Andricdef : InstRW<[Ampere1Write_3cyc_1XY], 10262a66634dSDimitry Andric (instregex "^SABAv", "^SABALv", "^SABDv", "^SABDLv", 10272a66634dSDimitry Andric "^UABAv", "^UABALv", "^UABDv", "^UABDLv")>; 10282a66634dSDimitry Andric// -- arithmetic 10292a66634dSDimitry Andricdef : InstRW<[Ampere1Write_3cyc_1XY], 10302a66634dSDimitry Andric (instregex "^ABSv", "^(ADD|SUB)v", "^SADDLv", "^SADDW", "SHADD", 10312a66634dSDimitry Andric "SHSUB", "^SRHADD", "^URHADD", "SSUBL", "SSUBW", 10322a66634dSDimitry Andric "^UADDLv", "^UADDW", "UHADD", "UHSUB", "USUBL", "USUBW")>; 10332a66634dSDimitry Andric// -- arithmetic, horizontal, 16B 10342a66634dSDimitry Andricdef : InstRW<[Ampere1Write_12cyc_4XY], 10352a66634dSDimitry Andric (instregex "^ADDVv16i8v", "^SADDLVv16i8v", "^UADDLVv16i8v")>; 10362a66634dSDimitry Andricdef : InstRW<[Ampere1Write_12cyc_4XY], 10372a66634dSDimitry Andric (instregex "^[SU](MIN|MAX)Vv16i8v")>; 10382a66634dSDimitry Andric// -- arithmetic, horizontal, 4H/4S 10392a66634dSDimitry Andricdef : InstRW<[Ampere1Write_6cyc_2XY], 10402a66634dSDimitry Andric (instregex "^[SU]?ADDL?V(v8i8|v4i16|v2i32)v")>; 10412a66634dSDimitry Andricdef : InstRW<[Ampere1Write_6cyc_2XY], 10422a66634dSDimitry Andric (instregex "^[SU](MIN|MAX)V(v4i16|v4i32)v")>; 10432a66634dSDimitry Andric// -- arithmetic, horizontal, 8B/8H 10442a66634dSDimitry Andricdef : InstRW<[Ampere1Write_9cyc_3XY], 10452a66634dSDimitry Andric (instregex "^[SU]?ADDL?V(v8i16|v4i32)v")>; 10462a66634dSDimitry Andricdef : InstRW<[Ampere1Write_9cyc_3XY], 10472a66634dSDimitry Andric (instregex "^[SU](MIN|MAX)V(v8i8|v8i16)v")>; 10482a66634dSDimitry Andric// -- arithmetic, narrowing 10492a66634dSDimitry Andricdef : InstRW<[Ampere1Write_5cyc_2XY], (instregex "(ADD|SUB)HNv.*")>; 10502a66634dSDimitry Andricdef : InstRW<[Ampere1Write_5cyc_2XY], (instregex "(RADD|RSUB)HNv.*")>; 10512a66634dSDimitry Andric// -- arithmetic, pairwise 10522a66634dSDimitry Andricdef : InstRW<[Ampere1Write_3cyc_1XY], 10532a66634dSDimitry Andric (instregex "^ADDPv", "^SADALP", "^UADALP", "^SADDLPv", "^UADDLPv")>; 10542a66634dSDimitry Andric// -- arithmetic, saturating 10552a66634dSDimitry Andricdef : InstRW<[Ampere1Write_3cyc_1XY], 10562a66634dSDimitry Andric (instregex "^SQADD", "^SQSUB", "^SUQADD", "^UQADD", "^UQSUB", "^USQADD")>; 10572a66634dSDimitry Andric// -- bit count 10582a66634dSDimitry Andricdef : InstRW<[Ampere1Write_2cyc_1XY], 10592a66634dSDimitry Andric (instregex "^(CLS|CLZ|CNT)v")>; 10602a66634dSDimitry Andric// -- compare 10612a66634dSDimitry Andricdef : InstRW<[Ampere1Write_3cyc_1XY], 10622a66634dSDimitry Andric (instregex "^CMEQv", "^CMGEv", "^CMGTv", "^CMLEv", "^CMLTv", 10632a66634dSDimitry Andric "^CMHIv", "^CMHSv")>; 10642a66634dSDimitry Andric// -- compare non-zero 10652a66634dSDimitry Andricdef : InstRW<[Ampere1Write_2cyc_1XY], (instregex "^CMTSTv")>; 10662a66634dSDimitry Andric// -- dot product 10672a66634dSDimitry Andricdef : InstRW<[Ampere1Write_3cyc_1XY], (instregex "^(S|SU|U|US)DOTv")>; 10682a66634dSDimitry Andric// -- fp reciprocal estimate 10692a66634dSDimitry Andricdef : InstRW<[Ampere1Write_5cyc_1XY], (instregex "^FRECPEv", "^FRSQRTEv")>; 10702a66634dSDimitry Andric// -- integer reciprocal estimate 10712a66634dSDimitry Andricdef : InstRW<[Ampere1Write_5cyc_1XY], (instregex "^URECPEv", "^URSQRTEv")>; 10722a66634dSDimitry Andric// -- logical 10732a66634dSDimitry Andricdef : InstRW<[Ampere1Write_2cyc_1XY], 10742a66634dSDimitry Andric (instregex "^ANDv", "^BICv", "^EORv", "^ORRv", "^ORNv", "^NOTv")>; 10752a66634dSDimitry Andric// -- logical, narrowing 10762a66634dSDimitry Andricdef : InstRW<[Ampere1Write_5cyc_2XY], 10772a66634dSDimitry Andric (instregex "RSHRNv", 10782a66634dSDimitry Andric "SHRNv", "SQSHRNv", "SQSHRUNv", 10792a66634dSDimitry Andric "UQXTNv")>; 10802a66634dSDimitry Andric// -- matrix multiply 10812a66634dSDimitry Andricdef : InstRW<[Ampere1Write_6cyc_2XY], 10822a66634dSDimitry Andric (instrs SMMLA, UMMLA, USMMLA)>; 10832a66634dSDimitry Andric// -- max/min 10842a66634dSDimitry Andricdef : InstRW<[Ampere1Write_3cyc_1XY], 10852a66634dSDimitry Andric (instregex "^SMAXv", "^SMINv", "^UMAXv", "^UMINv")>; 10862a66634dSDimitry Andricdef : InstRW<[Ampere1Write_3cyc_1XY], 10872a66634dSDimitry Andric (instregex "^SMAXPv", "^SMINPv", "^UMAXPv", "^UMINPv")>; 10882a66634dSDimitry Andric// -- move immediate 10892a66634dSDimitry Andricdef : InstRW<[Ampere1Write_2cyc_1XY], (instregex "^MOVIv", "^MVNIv")>; 10902a66634dSDimitry Andric// -- multiply 10912a66634dSDimitry Andricdef : InstRW<[Ampere1Write_3cyc_1XY], 10922a66634dSDimitry Andric (instregex "MULv", "SMULLv", "UMULLv", "SQDMUL(H|L)v", "SQRDMULHv")>; 10932a66634dSDimitry Andric// -- multiply accumulate 10942a66634dSDimitry Andricdef : InstRW<[Ampere1Write_3cyc_1XY], 10952a66634dSDimitry Andric (instregex "MLAv", "MLSv", "(S|U|SQD)(MLAL|MLSL)v", "SQRDML(A|S)Hv")>; 10962a66634dSDimitry Andric// -- negation, saturating 10972a66634dSDimitry Andricdef : InstRW<[Ampere1Write_2cyc_1XY], (instregex "^SQABS", "^SQNEG")>; 10982a66634dSDimitry Andric// -- reverse bits/bytes 10992a66634dSDimitry Andricdef : InstRW<[Ampere1Write_2cyc_1XY], 11002a66634dSDimitry Andric (instregex "^RBITv", "^REV16v", "^REV32v", "^REV64v")>; 11012a66634dSDimitry Andric// -- shift 11022a66634dSDimitry Andricdef : InstRW<[Ampere1Write_3cyc_1XY], (instregex "^[SU]SHL(v16i8|v8i16|v4i32|v2i64)")>; 11032a66634dSDimitry Andric// -- shift and accumulate 11042a66634dSDimitry Andricdef : InstRW<[Ampere1Write_3cyc_1XY], 11052a66634dSDimitry Andric (instregex "SRSRAv", "SSRAv", "URSRAv", "USRAv")>; 11062a66634dSDimitry Andric// -- shift, saturating 11072a66634dSDimitry Andricdef : InstRW<[Ampere1Write_3cyc_1XY], 11082a66634dSDimitry Andric (instregex "^SQRSHLv", "^SQRSHRNv", "^SQRSHRUNv", "^SQSHL", "^SQSHLU", 11092a66634dSDimitry Andric "^SQXTNv", "^SQXTUNv", "^UQSHRNv", "UQRSHRNv", "^UQRSHL", 11102a66634dSDimitry Andric "^UQSHL")>; 11112a66634dSDimitry Andric 11122a66634dSDimitry Andric// Vector miscellaneous instructions 11132a66634dSDimitry Andric// -- duplicate element 11142a66634dSDimitry Andricdef : InstRW<[Ampere1Write_2cyc_1XY], (instregex "^DUPv.+lane")>; 11152a66634dSDimitry Andric// -- duplicate from GPR 11162a66634dSDimitry Andricdef : InstRW<[Ampere1Write_5cyc_1BS], (instregex "^DUPv.+gpr")>; 11172a66634dSDimitry Andric// -- extract narrow 11182a66634dSDimitry Andricdef : InstRW<[Ampere1Write_2cyc_1XY], (instregex "^XTNv")>; 11192a66634dSDimitry Andric// -- insert/extract element 11202a66634dSDimitry Andricdef : InstRW<[Ampere1Write_2cyc_1XY], (instregex "^EXTv", "^INSv.+lane")>; 11212a66634dSDimitry Andric// -- move FP immediate 11222a66634dSDimitry Andricdef : InstRW<[Ampere1Write_2cyc_1XY], (instregex "^FMOVv")>; 11232a66634dSDimitry Andric// -- move element to GPR 11242a66634dSDimitry Andricdef : InstRW<[Ampere1Write_6cyc_1XY_1Z], (instregex "(S|U)MOVv")>; 11252a66634dSDimitry Andric// -- move from GPR to any element 11262a66634dSDimitry Andricdef : InstRW<[Ampere1Write_7cyc_1BS_1XY], (instregex "^INSv.+gpr")>; 11272a66634dSDimitry Andric// -- table lookup 11282a66634dSDimitry Andricdef : InstRW<[Ampere1Write_2cyc_1XY], 11292a66634dSDimitry Andric (instrs TBLv8i8One, TBLv16i8One, TBXv8i8One, TBXv16i8One)>; 11302a66634dSDimitry Andricdef : InstRW<[Ampere1Write_4cyc_2XY], 11312a66634dSDimitry Andric (instrs TBLv8i8Two, TBLv16i8Two, TBXv8i8Two, TBXv16i8Two)>; 11322a66634dSDimitry Andricdef : InstRW<[Ampere1Write_6cyc_3XY], 11332a66634dSDimitry Andric (instrs TBLv8i8Three, TBLv16i8Three, TBXv8i8Three, TBXv16i8Three)>; 11342a66634dSDimitry Andricdef : InstRW<[Ampere1Write_8cyc_4XY], 11352a66634dSDimitry Andric (instrs TBLv8i8Four, TBLv16i8Four, TBXv8i8Four, TBXv16i8Four)>; 11362a66634dSDimitry Andric// -- transpose 11372a66634dSDimitry Andricdef : InstRW<[Ampere1Write_2cyc_1XY], 11382a66634dSDimitry Andric (instregex "^TRN1v", "^TRN2v", "^UZP1v", "^UZP2v")>; 11392a66634dSDimitry Andric// -- zip/unzip 11402a66634dSDimitry Andricdef : InstRW<[Ampere1Write_2cyc_1XY], (instregex "^ZIP1v", "^ZIP2v")>; 11412a66634dSDimitry Andric 11422a66634dSDimitry Andric} // SchedModel = Ampere1Model 1143