1//=- AArch64SchedExynosM3.td - Samsung Exynos M3 Sched Defs --*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the machine model for the Samsung Exynos M3 to support 10// instruction scheduling and other instruction cost heuristics. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// The Exynos-M3 is an advanced superscalar microprocessor with a 6-wide 16// in-order stage for decode and dispatch and a wider issue stage. 17// The execution units and loads and stores are out-of-order. 18 19def ExynosM3Model : SchedMachineModel { 20 let IssueWidth = 6; // Up to 6 uops per cycle. 21 let MicroOpBufferSize = 228; // ROB size. 22 let LoopMicroOpBufferSize = 40; // Based on the instruction queue size. 23 let LoadLatency = 4; // Optimistic load cases. 24 let MispredictPenalty = 16; // Minimum branch misprediction penalty. 25 let CompleteModel = 1; // Use the default model otherwise. 26 27 list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F, 28 PAUnsupported.F, 29 SMEUnsupported.F); 30} 31 32//===----------------------------------------------------------------------===// 33// Define each kind of processor resource and number available on the Exynos-M3, 34// which has 12 pipelines, each with its own queue with out-of-order dispatch. 35 36let SchedModel = ExynosM3Model in { 37 38def M3UnitA : ProcResource<2>; // Simple integer 39def M3UnitC : ProcResource<2>; // Simple and complex integer 40def M3UnitD : ProcResource<1>; // Integer division (inside C0, serialized) 41def M3UnitB : ProcResource<2>; // Branch 42def M3UnitL : ProcResource<2>; // Load 43def M3UnitS : ProcResource<1>; // Store 44def M3PipeF0 : ProcResource<1>; // FP #0 45let Super = M3PipeF0 in { 46 def M3UnitFMAC0 : ProcResource<1>; // FP multiplication 47 def M3UnitFADD0 : ProcResource<1>; // Simple FP 48 def M3UnitFCVT0 : ProcResource<1>; // FP conversion 49 def M3UnitFSQR : ProcResource<2>; // FP square root (serialized) 50 def M3UnitNALU0 : ProcResource<1>; // Simple vector 51 def M3UnitNMSC : ProcResource<1>; // FP and vector miscellanea 52 def M3UnitNSHT0 : ProcResource<1>; // Vector shifting 53 def M3UnitNSHF0 : ProcResource<1>; // Vector shuffling 54} 55def M3PipeF1 : ProcResource<1>; // FP #1 56let Super = M3PipeF1 in { 57 def M3UnitFMAC1 : ProcResource<1>; // FP multiplication 58 def M3UnitFADD1 : ProcResource<1>; // Simple FP 59 def M3UnitFDIV0 : ProcResource<2>; // FP division (serialized) 60 def M3UnitFCVT1 : ProcResource<1>; // FP conversion 61 def M3UnitFST0 : ProcResource<1>; // FP store 62 def M3UnitNALU1 : ProcResource<1>; // Simple vector 63 def M3UnitNCRY0 : ProcResource<1>; // Cryptographic 64 def M3UnitNMUL : ProcResource<1>; // Vector multiplication 65 def M3UnitNSHT1 : ProcResource<1>; // Vector shifting 66 def M3UnitNSHF1 : ProcResource<1>; // Vector shuffling 67} 68def M3PipeF2 : ProcResource<1>; // FP #2 69let Super = M3PipeF2 in { 70 def M3UnitFMAC2 : ProcResource<1>; // FP multiplication 71 def M3UnitFADD2 : ProcResource<1>; // Simple FP 72 def M3UnitFDIV1 : ProcResource<2>; // FP division (serialized) 73 def M3UnitFST1 : ProcResource<1>; // FP store 74 def M3UnitNALU2 : ProcResource<1>; // Simple vector 75 def M3UnitNCRY1 : ProcResource<1>; // Cryptographic 76 def M3UnitNSHT2 : ProcResource<1>; // Vector shifting 77 def M3UnitNSHF2 : ProcResource<1>; // Vector shuffling 78} 79 80 81def M3UnitALU : ProcResGroup<[M3UnitA, 82 M3UnitC]>; 83def M3UnitFMAC : ProcResGroup<[M3UnitFMAC0, 84 M3UnitFMAC1, 85 M3UnitFMAC2]>; 86def M3UnitFADD : ProcResGroup<[M3UnitFADD0, 87 M3UnitFADD1, 88 M3UnitFADD2]>; 89def M3UnitFDIV : ProcResGroup<[M3UnitFDIV0, 90 M3UnitFDIV1]>; 91def M3UnitFCVT : ProcResGroup<[M3UnitFCVT0, 92 M3UnitFCVT1]>; 93def M3UnitFST : ProcResGroup<[M3UnitFST0, 94 M3UnitFST1]>; 95def M3UnitNALU : ProcResGroup<[M3UnitNALU0, 96 M3UnitNALU1, 97 M3UnitNALU2]>; 98def M3UnitNCRY : ProcResGroup<[M3UnitNCRY0, 99 M3UnitNCRY1]>; 100def M3UnitNSHT : ProcResGroup<[M3UnitNSHT0, 101 M3UnitNSHT1, 102 M3UnitNSHT2]>; 103def M3UnitNSHF : ProcResGroup<[M3UnitNSHF0, 104 M3UnitNSHF1, 105 M3UnitNSHF2]>; 106 107//===----------------------------------------------------------------------===// 108// Coarse scheduling model. 109 110def M3WriteZ0 : SchedWriteRes<[]> { let Latency = 0; 111 let NumMicroOps = 1; } 112def M3WriteZ1 : SchedWriteRes<[]> { let Latency = 1; 113 let NumMicroOps = 0; } 114 115def M3WriteA1 : SchedWriteRes<[M3UnitALU]> { let Latency = 1; } 116def M3WriteAA : SchedWriteRes<[M3UnitALU]> { let Latency = 2; 117 let ResourceCycles = [2]; } 118def M3WriteAB : SchedWriteRes<[M3UnitALU, 119 M3UnitC]> { let Latency = 1; 120 let NumMicroOps = 2; } 121def M3WriteAC : SchedWriteRes<[M3UnitALU, 122 M3UnitALU, 123 M3UnitC]> { let Latency = 2; 124 let NumMicroOps = 3; } 125def M3WriteAD : SchedWriteRes<[M3UnitALU, 126 M3UnitC]> { let Latency = 2; 127 let NumMicroOps = 2; } 128def M3WriteC1 : SchedWriteRes<[M3UnitC]> { let Latency = 1; } 129def M3WriteC2 : SchedWriteRes<[M3UnitC]> { let Latency = 2; } 130def M3WriteAU : SchedWriteVariant<[SchedVar<IsCopyIdiomPred, [M3WriteZ0]>, 131 SchedVar<ExynosArithPred, [M3WriteA1]>, 132 SchedVar<ExynosLogicPred, [M3WriteA1]>, 133 SchedVar<NoSchedPred, [M3WriteAA]>]>; 134def M3WriteAV : SchedWriteVariant<[SchedVar<IsCopyIdiomPred, [M3WriteZ0]>, 135 SchedVar<ExynosArithPred, [M3WriteA1]>, 136 SchedVar<NoSchedPred, [M3WriteAA]>]>; 137def M3WriteAW : SchedWriteVariant<[SchedVar<IsZeroIdiomPred, [M3WriteZ0]>, 138 SchedVar<ExynosLogicPred, [M3WriteA1]>, 139 SchedVar<NoSchedPred, [M3WriteAA]>]>; 140def M3WriteAX : SchedWriteVariant<[SchedVar<ExynosArithPred, [M3WriteA1]>, 141 SchedVar<ExynosLogicPred, [M3WriteA1]>, 142 SchedVar<NoSchedPred, [M3WriteAA]>]>; 143def M3WriteAY : SchedWriteVariant<[SchedVar<ExynosRotateRightImmPred, [M3WriteA1]>, 144 SchedVar<NoSchedPred, [M3WriteAA]>]>; 145 146def M3WriteB1 : SchedWriteRes<[M3UnitB]> { let Latency = 1; } 147def M3WriteBX : SchedWriteVariant<[SchedVar<ExynosBranchLinkLRPred, [M3WriteAC]>, 148 SchedVar<NoSchedPred, [M3WriteAB]>]>; 149 150def M3WriteL4 : SchedWriteRes<[M3UnitL]> { let Latency = 4; } 151def M3WriteL5 : SchedWriteRes<[M3UnitL]> { let Latency = 5; } 152def M3WriteLA : SchedWriteRes<[M3UnitL, 153 M3UnitL]> { let Latency = 5; 154 let NumMicroOps = 1; } 155def M3WriteLB : SchedWriteRes<[M3UnitA, 156 M3UnitL]> { let Latency = 5; 157 let NumMicroOps = 2; } 158def M3WriteLC : SchedWriteRes<[M3UnitA, 159 M3UnitL, 160 M3UnitL]> { let Latency = 5; 161 let NumMicroOps = 2; } 162def M3WriteLD : SchedWriteRes<[M3UnitA, 163 M3UnitL]> { let Latency = 4; 164 let NumMicroOps = 2; } 165def M3WriteLE : SchedWriteRes<[M3UnitA, 166 M3UnitL]> { let Latency = 6; 167 let NumMicroOps = 2; } 168def M3WriteLH : SchedWriteRes<[]> { let Latency = 5; 169 let NumMicroOps = 0; } 170def M3WriteLX : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M3WriteL5]>, 171 SchedVar<NoSchedPred, [M3WriteL4]>]>; 172def M3WriteLY : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M3WriteLE]>, 173 SchedVar<NoSchedPred, [M3WriteL5]>]>; 174 175def M3WriteS1 : SchedWriteRes<[M3UnitS]> { let Latency = 1; } 176def M3WriteSA : SchedWriteRes<[M3UnitA, 177 M3UnitS, 178 M3UnitFST]> { let Latency = 3; 179 let NumMicroOps = 2; } 180def M3WriteSB : SchedWriteRes<[M3UnitA, 181 M3UnitS]> { let Latency = 2; 182 let NumMicroOps = 2; } 183def M3WriteSC : SchedWriteRes<[M3UnitA, 184 M3UnitS, 185 M3UnitFST]> { let Latency = 1; 186 let NumMicroOps = 2; } 187def M3WriteSY : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M3WriteSA]>, 188 SchedVar<NoSchedPred, [WriteVST]>]>; 189 190def M3ReadAdrBase : SchedReadVariant<[SchedVar<ExynosScaledIdxPred, [ReadDefault]>, 191 SchedVar<NoSchedPred, [ReadDefault]>]>; 192 193// Branch instructions. 194def : SchedAlias<WriteBr, M3WriteZ0>; 195def : SchedAlias<WriteBrReg, M3WriteC1>; 196 197// Arithmetic and logical integer instructions. 198def : SchedAlias<WriteI, M3WriteA1>; 199def : SchedAlias<WriteISReg, M3WriteA1>; 200def : SchedAlias<WriteIEReg, M3WriteA1>; 201def : SchedAlias<WriteIS, M3WriteA1>; 202 203// Move instructions. 204def : SchedAlias<WriteImm, M3WriteA1>; 205 206// Divide and multiply instructions. 207def : WriteRes<WriteID32, [M3UnitC, 208 M3UnitD]> { let Latency = 12; 209 let ResourceCycles = [1, 12]; } 210def : WriteRes<WriteID64, [M3UnitC, 211 M3UnitD]> { let Latency = 21; 212 let ResourceCycles = [1, 21]; } 213def : WriteRes<WriteIM32, [M3UnitC]> { let Latency = 3; } 214def : WriteRes<WriteIM64, [M3UnitC]> { let Latency = 4; 215 let ResourceCycles = [2]; } 216 217// Miscellaneous instructions. 218def : SchedAlias<WriteExtr, M3WriteAY>; 219 220// Addressing modes. 221def : SchedAlias<WriteAdr, M3WriteZ1>; 222def : SchedAlias<ReadAdrBase, M3ReadAdrBase>; 223 224// Load instructions. 225def : SchedAlias<WriteLD, M3WriteL4>; 226def : WriteRes<WriteLDHi, []> { let Latency = 4; 227 let NumMicroOps = 0; } 228def : SchedAlias<WriteLDIdx, M3WriteLB>; 229 230// Store instructions. 231def : SchedAlias<WriteST, M3WriteS1>; 232def : SchedAlias<WriteSTP, M3WriteS1>; 233def : SchedAlias<WriteSTX, M3WriteS1>; 234def : SchedAlias<WriteSTIdx, M3WriteSB>; 235 236// FP data instructions. 237def : WriteRes<WriteF, [M3UnitFADD]> { let Latency = 2; } 238def : WriteRes<WriteFCmp, [M3UnitNMSC]> { let Latency = 2; } 239def : WriteRes<WriteFDiv, [M3UnitFDIV]> { let Latency = 12; 240 let ResourceCycles = [12]; } 241def : WriteRes<WriteFMul, [M3UnitFMAC]> { let Latency = 4; } 242 243// FP miscellaneous instructions. 244def : WriteRes<WriteFCvt, [M3UnitFCVT]> { let Latency = 3; } 245def : WriteRes<WriteFImm, [M3UnitNALU]> { let Latency = 1; } 246def : WriteRes<WriteFCopy, [M3UnitNALU]> { let Latency = 1; } 247 248// FP load instructions. 249def : SchedAlias<WriteVLD, M3WriteL5>; 250 251// FP store instructions. 252def : WriteRes<WriteVST, [M3UnitS, 253 M3UnitFST]> { let Latency = 1; 254 let NumMicroOps = 1; } 255 256// ASIMD FP instructions. 257def : WriteRes<WriteV, [M3UnitNALU]> { let Latency = 3; } 258 259// Other miscellaneous instructions. 260def : WriteRes<WriteAtomic, []> { let Unsupported = 1; } 261def : WriteRes<WriteBarrier, []> { let Latency = 1; } 262def : WriteRes<WriteHint, []> { let Latency = 1; } 263def : WriteRes<WriteSys, []> { let Latency = 1; } 264 265//===----------------------------------------------------------------------===// 266// Generic fast forwarding. 267 268// TODO: Add FP register forwarding rules. 269 270def : ReadAdvance<ReadI, 0>; 271def : ReadAdvance<ReadISReg, 0>; 272def : ReadAdvance<ReadIEReg, 0>; 273def : ReadAdvance<ReadIM, 0>; 274// TODO: The forwarding for 32 bits actually saves 2 cycles. 275def : ReadAdvance<ReadIMA, 3, [WriteIM32, WriteIM64]>; 276def : ReadAdvance<ReadID, 0>; 277def : ReadAdvance<ReadExtrHi, 0>; 278def : ReadAdvance<ReadAdrBase, 0>; 279def : ReadAdvance<ReadVLD, 0>; 280 281//===----------------------------------------------------------------------===// 282// Finer scheduling model. 283 284def M3WriteNEONA : SchedWriteRes<[M3UnitNSHF, 285 M3UnitFADD]> { let Latency = 3; 286 let NumMicroOps = 2; } 287def M3WriteNEONB : SchedWriteRes<[M3UnitNALU, 288 M3UnitFST]> { let Latency = 10; 289 let NumMicroOps = 2; } 290def M3WriteNEOND : SchedWriteRes<[M3UnitNSHF, 291 M3UnitFST]> { let Latency = 6; 292 let NumMicroOps = 2; } 293def M3WriteNEONH : SchedWriteRes<[M3UnitNALU, 294 M3UnitS]> { let Latency = 5; 295 let NumMicroOps = 2; } 296def M3WriteNEONI : SchedWriteRes<[M3UnitNSHF, 297 M3UnitS]> { let Latency = 5; 298 let NumMicroOps = 2; } 299def M3WriteNEONV : SchedWriteRes<[M3UnitFDIV0, 300 M3UnitFDIV1]> { let Latency = 7; 301 let NumMicroOps = 2; 302 let ResourceCycles = [8, 8]; } 303def M3WriteNEONW : SchedWriteRes<[M3UnitFDIV0, 304 M3UnitFDIV1]> { let Latency = 12; 305 let NumMicroOps = 2; 306 let ResourceCycles = [13, 13]; } 307def M3WriteNEONX : SchedWriteRes<[M3UnitFSQR, 308 M3UnitFSQR]> { let Latency = 18; 309 let NumMicroOps = 2; 310 let ResourceCycles = [19, 19]; } 311def M3WriteNEONY : SchedWriteRes<[M3UnitFSQR, 312 M3UnitFSQR]> { let Latency = 25; 313 let NumMicroOps = 2; 314 let ResourceCycles = [26, 26]; } 315def M3WriteNEONZ : SchedWriteRes<[M3UnitNMSC, 316 M3UnitNMSC]> { let Latency = 5; 317 let NumMicroOps = 2; } 318def M3WriteFADD2 : SchedWriteRes<[M3UnitFADD]> { let Latency = 2; } 319def M3WriteFCVT2 : SchedWriteRes<[M3UnitFCVT]> { let Latency = 2; } 320def M3WriteFCVT3 : SchedWriteRes<[M3UnitFCVT]> { let Latency = 3; } 321def M3WriteFCVT3A : SchedWriteRes<[M3UnitFCVT0]> { let Latency = 3; } 322def M3WriteFCVT4A : SchedWriteRes<[M3UnitFCVT0]> { let Latency = 4; } 323def M3WriteFCVT4 : SchedWriteRes<[M3UnitFCVT]> { let Latency = 4; } 324def M3WriteFDIV10 : SchedWriteRes<[M3UnitFDIV]> { let Latency = 7; 325 let ResourceCycles = [8]; } 326def M3WriteFDIV12 : SchedWriteRes<[M3UnitFDIV]> { let Latency = 12; 327 let ResourceCycles = [13]; } 328def M3WriteFMAC3 : SchedWriteRes<[M3UnitFMAC]> { let Latency = 3; } 329def M3WriteFMAC4 : SchedWriteRes<[M3UnitFMAC]> { let Latency = 4; } 330def M3WriteFMAC5 : SchedWriteRes<[M3UnitFMAC]> { let Latency = 5; } 331def M3WriteFSQR17 : SchedWriteRes<[M3UnitFSQR]> { let Latency = 18; 332 let ResourceCycles = [19]; } 333def M3WriteFSQR25 : SchedWriteRes<[M3UnitFSQR]> { let Latency = 25; 334 let ResourceCycles = [26]; } 335def M3WriteNALU1 : SchedWriteRes<[M3UnitNALU]> { let Latency = 1; } 336def M3WriteNCRY1A : SchedWriteRes<[M3UnitNCRY0]> { let Latency = 1; } 337def M3WriteNCRY3A : SchedWriteRes<[M3UnitNCRY0]> { let Latency = 3; } 338def M3WriteNCRY5A : SchedWriteRes<[M3UnitNCRY]> { let Latency = 5; } 339def M3WriteNMSC1 : SchedWriteRes<[M3UnitNMSC]> { let Latency = 1; } 340def M3WriteNMSC2 : SchedWriteRes<[M3UnitNMSC]> { let Latency = 2; } 341def M3WriteNMSC3 : SchedWriteRes<[M3UnitNMSC]> { let Latency = 3; } 342def M3WriteNMUL3 : SchedWriteRes<[M3UnitNMUL]> { let Latency = 3; } 343def M3WriteNSHF1 : SchedWriteRes<[M3UnitNSHF]> { let Latency = 1; } 344def M3WriteNSHF3 : SchedWriteRes<[M3UnitNSHF]> { let Latency = 3; } 345def M3WriteNSHT1 : SchedWriteRes<[M3UnitNSHT]> { let Latency = 1; } 346def M3WriteNSHT2 : SchedWriteRes<[M3UnitNSHT]> { let Latency = 2; } 347def M3WriteNSHT3 : SchedWriteRes<[M3UnitNSHT]> { let Latency = 3; } 348def M3WriteVLDA : SchedWriteRes<[M3UnitL, 349 M3UnitL]> { let Latency = 5; 350 let NumMicroOps = 2; } 351def M3WriteVLDB : SchedWriteRes<[M3UnitL, 352 M3UnitL, 353 M3UnitL]> { let Latency = 6; 354 let NumMicroOps = 3; } 355def M3WriteVLDC : SchedWriteRes<[M3UnitL, 356 M3UnitL, 357 M3UnitL, 358 M3UnitL]> { let Latency = 6; 359 let NumMicroOps = 4; } 360def M3WriteVLDD : SchedWriteRes<[M3UnitL, 361 M3UnitNALU]> { let Latency = 7; 362 let NumMicroOps = 2; 363 let ResourceCycles = [2, 1]; } 364def M3WriteVLDE : SchedWriteRes<[M3UnitL, 365 M3UnitNALU]> { let Latency = 6; 366 let NumMicroOps = 2; 367 let ResourceCycles = [2, 1]; } 368def M3WriteVLDF : SchedWriteRes<[M3UnitL, 369 M3UnitL]> { let Latency = 10; 370 let NumMicroOps = 2; 371 let ResourceCycles = [5, 5]; } 372def M3WriteVLDG : SchedWriteRes<[M3UnitL, 373 M3UnitNALU, 374 M3UnitNALU]> { let Latency = 7; 375 let NumMicroOps = 3; 376 let ResourceCycles = [2, 1, 1]; } 377def M3WriteVLDH : SchedWriteRes<[M3UnitL, 378 M3UnitNALU, 379 M3UnitNALU]> { let Latency = 6; 380 let NumMicroOps = 3; 381 let ResourceCycles = [2, 1, 1]; } 382def M3WriteVLDI : SchedWriteRes<[M3UnitL, 383 M3UnitL, 384 M3UnitL]> { let Latency = 12; 385 let NumMicroOps = 3; 386 let ResourceCycles = [6, 6, 6]; } 387def M3WriteVLDJ : SchedWriteRes<[M3UnitL, 388 M3UnitNALU, 389 M3UnitNALU, 390 M3UnitNALU]> { let Latency = 7; 391 let NumMicroOps = 4; 392 let ResourceCycles = [2, 1, 1, 1]; } 393def M3WriteVLDK : SchedWriteRes<[M3UnitL, 394 M3UnitNALU, 395 M3UnitNALU, 396 M3UnitNALU, 397 M3UnitNALU]> { let Latency = 9; 398 let NumMicroOps = 5; 399 let ResourceCycles = [4, 1, 1, 1, 1]; } 400def M3WriteVLDL : SchedWriteRes<[M3UnitL, 401 M3UnitNALU, 402 M3UnitNALU, 403 M3UnitL, 404 M3UnitNALU]> { let Latency = 6; 405 let NumMicroOps = 5; 406 let ResourceCycles = [6, 1, 1, 6, 1]; } 407def M3WriteVLDM : SchedWriteRes<[M3UnitL, 408 M3UnitNALU, 409 M3UnitNALU, 410 M3UnitL, 411 M3UnitNALU, 412 M3UnitNALU]> { let Latency = 7; 413 let NumMicroOps = 6; 414 let ResourceCycles = [6, 1, 1, 6, 1, 1]; } 415def M3WriteVLDN : SchedWriteRes<[M3UnitL, 416 M3UnitL, 417 M3UnitL, 418 M3UnitL]> { let Latency = 14; 419 let NumMicroOps = 4; 420 let ResourceCycles = [6, 6, 6, 6]; } 421def M3WriteVSTA : WriteSequence<[WriteVST], 2>; 422def M3WriteVSTB : WriteSequence<[WriteVST], 3>; 423def M3WriteVSTC : WriteSequence<[WriteVST], 4>; 424def M3WriteVSTD : SchedWriteRes<[M3UnitS, 425 M3UnitFST, 426 M3UnitS, 427 M3UnitFST]> { let Latency = 7; 428 let NumMicroOps = 4; 429 let ResourceCycles = [1, 3, 1, 3]; } 430def M3WriteVSTE : SchedWriteRes<[M3UnitS, 431 M3UnitFST, 432 M3UnitS, 433 M3UnitFST, 434 M3UnitS, 435 M3UnitFST]> { let Latency = 8; 436 let NumMicroOps = 6; 437 let ResourceCycles = [1, 3, 1, 3, 1, 3]; } 438def M3WriteVSTF : SchedWriteRes<[M3UnitNALU, 439 M3UnitFST, 440 M3UnitFST, 441 M3UnitS, 442 M3UnitFST, 443 M3UnitS, 444 M3UnitFST]> { let Latency = 15; 445 let NumMicroOps = 7; 446 let ResourceCycles = [1, 3, 3, 1, 3, 1, 3]; } 447def M3WriteVSTG : SchedWriteRes<[M3UnitNALU, 448 M3UnitFST, 449 M3UnitFST, 450 M3UnitS, 451 M3UnitFST, 452 M3UnitS, 453 M3UnitFST, 454 M3UnitS, 455 M3UnitFST]> { let Latency = 16; 456 let NumMicroOps = 9; 457 let ResourceCycles = [1, 3, 3, 1, 3, 1, 3, 1, 3]; } 458def M3WriteVSTH : SchedWriteRes<[M3UnitNALU, 459 M3UnitFST, 460 M3UnitFST, 461 M3UnitS, 462 M3UnitFST]> { let Latency = 14; 463 let NumMicroOps = 5; 464 let ResourceCycles = [1, 3, 3, 1, 3]; } 465def M3WriteVSTI : SchedWriteRes<[M3UnitNALU, 466 M3UnitFST, 467 M3UnitFST, 468 M3UnitS, 469 M3UnitFST, 470 M3UnitS, 471 M3UnitFST, 472 M3UnitS, 473 M3UnitFST]> { let Latency = 17; 474 let NumMicroOps = 9; 475 let ResourceCycles = [1, 3, 3, 1, 3, 1, 3, 1, 3]; } 476 477// Special cases. 478def M3WriteAES : SchedWriteRes<[M3UnitNCRY]> { let Latency = 1; } 479def M3WriteCOPY : SchedWriteVariant<[SchedVar<ExynosFPPred, [M3WriteNALU1]>, 480 SchedVar<NoSchedPred, [M3WriteZ0]>]>; 481def M3WriteMOVI : SchedWriteVariant<[SchedVar<IsZeroFPIdiomPred, [M3WriteZ0]>, 482 SchedVar<NoSchedPred, [M3WriteNALU1]>]>; 483 484// Fast forwarding. 485def M3ReadAES : SchedReadAdvance<1, [M3WriteAES]>; 486def M3ReadFMAC : SchedReadAdvance<1, [M3WriteFMAC4, 487 M3WriteFMAC5]>; 488def M3ReadNMUL : SchedReadAdvance<1, [M3WriteNMUL3]>; 489 490// Branch instructions 491def : InstRW<[M3WriteB1], (instrs Bcc)>; 492def : InstRW<[M3WriteA1], (instrs BL)>; 493def : InstRW<[M3WriteBX], (instrs BLR)>; 494def : InstRW<[M3WriteC1], (instregex "^CBN?Z[WX]")>; 495def : InstRW<[M3WriteAD], (instregex "^TBN?Z[WX]")>; 496 497// Arithmetic and logical integer instructions. 498def : InstRW<[M3WriteAX], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|SUB)[WX]rs$")>; 499def : InstRW<[M3WriteAU], (instrs ORRWrs, ORRXrs)>; 500def : InstRW<[M3WriteAX], (instregex "^(ADD|SUB)S?[WX]rx(64)?$")>; 501def : InstRW<[M3WriteAX], (instregex "^(ADD|AND|BIC|SUB)S[WX]rs$")>; 502def : InstRW<[M3WriteAV], (instrs ADDWri, ADDXri)>; 503def : InstRW<[M3WriteAW], (instrs ORRWri, ORRXri)>; 504 505// Move instructions. 506def : InstRW<[M3WriteCOPY], (instrs COPY)>; 507def : InstRW<[M3WriteZ0], (instrs ADR, ADRP)>; 508def : InstRW<[M3WriteZ0], (instregex "^MOV[NZ][WX]i")>; 509 510// Divide and multiply instructions. 511 512// Miscellaneous instructions. 513 514// Load instructions. 515def : InstRW<[M3WriteLD, 516 WriteLDHi, 517 WriteAdr], (instregex "^LDP(SW|W|X)(post|pre)")>; 518def : InstRW<[M3WriteLB, 519 ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roW")>; 520def : InstRW<[M3WriteLX, 521 ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roX")>; 522def : InstRW<[M3WriteLB, 523 ReadAdrBase], (instrs PRFMroW)>; 524def : InstRW<[M3WriteLX, 525 ReadAdrBase], (instrs PRFMroX)>; 526 527// Store instructions. 528def : InstRW<[M3WriteSB, 529 ReadAdrBase], (instregex "^STR(BB|HH|W|X)roW")>; 530def : InstRW<[WriteST, 531 ReadAdrBase], (instregex "^STR(BB|HH|W|X)roX")>; 532 533// FP data instructions. 534def : InstRW<[M3WriteNSHF1], (instregex "^FABS[DS]r")>; 535def : InstRW<[M3WriteFADD2], (instregex "^F(ADD|SUB)[DS]rr")>; 536def : InstRW<[M3WriteFDIV10], (instrs FDIVSrr)>; 537def : InstRW<[M3WriteFDIV12], (instrs FDIVDrr)>; 538def : InstRW<[M3WriteNMSC1], (instregex "^F(MAX|MIN).+rr")>; 539def : InstRW<[M3WriteFMAC3], (instregex "^FN?MUL[DS]rr")>; 540def : InstRW<[M3WriteFMAC4, 541 M3ReadFMAC], (instregex "^FN?M(ADD|SUB)[DS]rrr")>; 542def : InstRW<[M3WriteNALU1], (instregex "^FNEG[DS]r")>; 543def : InstRW<[M3WriteFCVT3A], (instregex "^FRINT.+r")>; 544def : InstRW<[M3WriteNEONH], (instregex "^FCSEL[DS]rrr")>; 545def : InstRW<[M3WriteFSQR17], (instrs FSQRTSr)>; 546def : InstRW<[M3WriteFSQR25], (instrs FSQRTDr)>; 547 548// FP miscellaneous instructions. 549def : InstRW<[M3WriteFCVT3], (instregex "^FCVT[DHS][DHS]r")>; 550def : InstRW<[M3WriteFCVT4A], (instregex "^[SU]CVTF[SU][XW][DHS]ri")>; 551def : InstRW<[M3WriteFCVT3A], (instregex "^FCVT[AMNPZ][SU]U[XW][DHS]r")>; 552def : InstRW<[M3WriteFCVT3A], (instregex "^FCVTZ[SU][dhs]")>; 553def : InstRW<[M3WriteNALU1], (instregex "^FMOV[DS][ir]")>; 554def : InstRW<[M3WriteFCVT4], (instregex "^[FU](RECP|RSQRT)Ev1")>; 555def : InstRW<[M3WriteNMSC1], (instregex "^FRECPXv1")>; 556def : InstRW<[M3WriteFMAC4, 557 M3ReadFMAC], (instregex "^F(RECP|RSQRT)S(16|32|64)")>; 558def : InstRW<[M3WriteNALU1], (instregex "^FMOV[WX][DS]r")>; 559def : InstRW<[M3WriteNALU1], (instregex "^FMOV[DS][WX]r")>; 560def : InstRW<[M3WriteNEONI], (instregex "^FMOV(DX|XD)Highr")>; 561 562// FP load instructions. 563def : InstRW<[WriteVLD], (instregex "^LDR[DSQ]l")>; 564def : InstRW<[WriteVLD], (instregex "^LDUR[BDHSQ]i")>; 565def : InstRW<[WriteVLD, 566 WriteAdr], (instregex "^LDR[BDHSQ](post|pre)")>; 567def : InstRW<[WriteVLD], (instregex "^LDR[BDHSQ]ui")>; 568def : InstRW<[M3WriteLE, 569 ReadAdrBase], (instregex "^LDR[BDHS]roW")>; 570def : InstRW<[WriteVLD, 571 ReadAdrBase], (instregex "^LDR[BDHS]roX")>; 572def : InstRW<[M3WriteLY, 573 ReadAdrBase], (instregex "^LDRQro[WX]")>; 574def : InstRW<[WriteVLD, 575 M3WriteLH], (instregex "^LDN?P[DS]i")>; 576def : InstRW<[M3WriteLA, 577 M3WriteLH], (instregex "^LDN?PQi")>; 578def : InstRW<[M3WriteLB, 579 M3WriteLH, 580 WriteAdr], (instregex "^LDP[DS](post|pre)")>; 581def : InstRW<[M3WriteLC, 582 M3WriteLH, 583 WriteAdr], (instregex "^LDPQ(post|pre)")>; 584 585// FP store instructions. 586def : InstRW<[WriteVST], (instregex "^STUR[BDHSQ]i")>; 587def : InstRW<[WriteVST, 588 WriteAdr], (instregex "^STR[BDHSQ](post|pre)")>; 589def : InstRW<[WriteVST], (instregex "^STR[BDHSQ]ui")>; 590def : InstRW<[M3WriteSA, 591 ReadAdrBase], (instregex "^STR[BDHS]roW")>; 592def : InstRW<[M3WriteSA, 593 ReadAdrBase], (instregex "^STRQroW")>; 594def : InstRW<[WriteVST, 595 ReadAdrBase], (instregex "^STR[BDHS]roX")>; 596def : InstRW<[M3WriteSY, 597 ReadAdrBase], (instregex "^STRQroX")>; 598def : InstRW<[WriteVST], (instregex "^STN?P[DSQ]i")>; 599def : InstRW<[WriteVST, 600 WriteAdr], (instregex "^STP[DS](post|pre)")>; 601def : InstRW<[M3WriteSC, 602 WriteAdr], (instregex "^STPQ(post|pre)")>; 603 604// ASIMD instructions. 605def : InstRW<[M3WriteNMSC3], (instregex "^[SU]ABAL?v")>; 606def : InstRW<[M3WriteNMSC1], (instregex "^[SU]ABDL?v")>; 607def : InstRW<[M3WriteNMSC1], (instregex "^((SQ)?ABS|SQNEG)v")>; 608def : InstRW<[M3WriteNALU1], (instregex "^(ADD|NEG|SUB)v")>; 609def : InstRW<[M3WriteNMSC3], (instregex "^[SU]?ADDL?Pv")>; 610def : InstRW<[M3WriteNMSC3], (instregex "^[SU]H(ADD|SUB)v")>; 611def : InstRW<[M3WriteNMSC3], (instregex "^[SU](ADD|SUB)[LW]V?v")>; 612def : InstRW<[M3WriteNMSC3], (instregex "^R?(ADD|SUB)HN2?v")>; 613def : InstRW<[M3WriteNMSC3], (instregex "^[SU]Q(ADD|SUB)v")>; 614def : InstRW<[M3WriteNMSC3], (instregex "^(SU|US)QADDv")>; 615def : InstRW<[M3WriteNMSC3], (instregex "^[SU]RHADDv")>; 616def : InstRW<[M3WriteNMSC1], (instregex "^CM(EQ|GE|GT|HI|HS|LE|LT)v")>; 617def : InstRW<[M3WriteNALU1], (instregex "^CMTSTv")>; 618def : InstRW<[M3WriteNALU1], (instregex "^(AND|BIC|EOR|MVNI|NOT|ORN|ORR)v")>; 619def : InstRW<[M3WriteNMSC1], (instregex "^[SU](MIN|MAX)v")>; 620def : InstRW<[M3WriteNMSC2], (instregex "^[SU](MIN|MAX)Pv")>; 621def : InstRW<[M3WriteNMSC3], (instregex "^[SU](MIN|MAX)Vv")>; 622def : InstRW<[M3WriteNMUL3], (instregex "^(MUL|SQR?DMULH)v")>; 623def : InstRW<[M3WriteNMUL3, 624 M3ReadNMUL], (instregex "^ML[AS]v")>; 625def : InstRW<[M3WriteNMUL3], (instregex "^[SU]ML[AS]Lv")>; 626def : InstRW<[M3WriteNMUL3], (instregex "^SQDML[AS]L")>; 627def : InstRW<[M3WriteNMUL3], (instregex "^(S|U|SQD)MULLv")>; 628def : InstRW<[M3WriteNMSC3], (instregex "^[SU]ADALPv")>; 629def : InstRW<[M3WriteNSHT3], (instregex "^[SU]R?SRAv")>; 630def : InstRW<[M3WriteNSHT1], (instregex "^SHL[dv]")>; 631def : InstRW<[M3WriteNSHT1], (instregex "^[SU]SH[LR][dv]")>; 632def : InstRW<[M3WriteNSHT1], (instregex "^S[RS]I[dv]")>; 633def : InstRW<[M3WriteNSHT2], (instregex "^[SU]?SHLLv")>; 634def : InstRW<[M3WriteNSHT3], (instregex "^(([SU]Q)?R)?SHRU?N[bhsv]")>; 635def : InstRW<[M3WriteNSHT3], (instregex "^[SU]RSH[LR][dv]")>; 636def : InstRW<[M3WriteNSHT3], (instregex "^[SU]QR?SHLU?[bdhsv]")>; 637 638// ASIMD FP instructions. 639def : InstRW<[M3WriteNSHF1], (instregex "^FABSv")>; 640def : InstRW<[M3WriteFADD2], (instregex "^F(ABD|ADD|SUB)v")>; 641def : InstRW<[M3WriteNEONA], (instregex "^FADDP")>; 642def : InstRW<[M3WriteNMSC1], (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)v[^1]")>; 643def : InstRW<[M3WriteFCVT3], (instregex "^FCVT(L|N|XN)v")>; 644def : InstRW<[M3WriteFCVT2], (instregex "^FCVT[AMNPZ][SU]v")>; 645def : InstRW<[M3WriteFCVT2], (instregex "^[SU]CVTFv")>; 646def : InstRW<[M3WriteFDIV10], (instrs FDIVv2f32)>; 647def : InstRW<[M3WriteNEONV], (instrs FDIVv4f32)>; 648def : InstRW<[M3WriteNEONW], (instrs FDIVv2f64)>; 649def : InstRW<[M3WriteNMSC1], (instregex "^F(MAX|MIN)(NM)?v")>; 650def : InstRW<[M3WriteNMSC2], (instregex "^F(MAX|MIN)(NM)?Pv")>; 651def : InstRW<[M3WriteNEONZ], (instregex "^F(MAX|MIN)(NM)?Vv")>; 652def : InstRW<[M3WriteFMAC3], (instregex "^FMULX?v.[fi]")>; 653def : InstRW<[M3WriteFMAC4, 654 M3ReadFMAC], (instregex "^FML[AS]v.f")>; 655def : InstRW<[M3WriteFMAC5, 656 M3ReadFMAC], (instregex "^FML[AS]v.i")>; 657def : InstRW<[M3WriteNALU1], (instregex "^FNEGv")>; 658def : InstRW<[M3WriteFCVT3A], (instregex "^FRINT[AIMNPXZ]v")>; 659def : InstRW<[M3WriteFSQR17], (instrs FSQRTv2f32)>; 660def : InstRW<[M3WriteNEONX], (instrs FSQRTv4f32)>; 661def : InstRW<[M3WriteNEONY], (instrs FSQRTv2f64)>; 662 663// ASIMD miscellaneous instructions. 664def : InstRW<[M3WriteNALU1], (instregex "^RBITv")>; 665def : InstRW<[M3WriteNALU1], (instregex "^(BIF|BIT|BSL|BSP)v")>; 666def : InstRW<[M3WriteNEONB], (instregex "^DUPv.+gpr")>; 667def : InstRW<[M3WriteNSHF1], (instregex "^DUPv.+lane")>; 668def : InstRW<[M3WriteNSHF1], (instregex "^EXTv")>; 669def : InstRW<[M3WriteNSHF1], (instregex "^[SU]?Q?XTU?Nv")>; 670def : InstRW<[M3WriteNSHF1], (instregex "^CPY")>; 671def : InstRW<[M3WriteNSHF1], (instregex "^INSv.+lane")>; 672def : InstRW<[M3WriteMOVI], (instregex "^MOVI")>; 673def : InstRW<[M3WriteNALU1], (instregex "^FMOVv")>; 674def : InstRW<[M3WriteFCVT4], (instregex "^[FU](RECP|RSQRT)Ev[248]")>; 675def : InstRW<[M3WriteFMAC4, 676 M3ReadFMAC], (instregex "^F(RECP|RSQRT)Sv")>; 677def : InstRW<[M3WriteNSHF1], (instregex "^REV(16|32|64)v")>; 678def : InstRW<[M3WriteNSHF1], (instregex "^TB[LX]v")>; 679def : InstRW<[M3WriteNEOND], (instregex "^[SU]MOVv")>; 680def : InstRW<[M3WriteNSHF3], (instregex "^INSv.+gpr")>; 681def : InstRW<[M3WriteNSHF1], (instregex "^(TRN|UZP|ZIP)[12]v")>; 682 683// ASIMD load instructions. 684def : InstRW<[M3WriteL5], (instregex "LD1Onev(8b|4h|2s|1d)$")>; 685def : InstRW<[M3WriteL5, 686 M3WriteA1], (instregex "LD1Onev(8b|4h|2s|1d)_POST")>; 687def : InstRW<[M3WriteL5], (instregex "LD1Onev(16b|8h|4s|2d)$")>; 688def : InstRW<[M3WriteL5, 689 M3WriteA1], (instregex "LD1Onev(16b|8h|4s|2d)_POST")>; 690 691def : InstRW<[M3WriteVLDA], (instregex "LD1Twov(8b|4h|2s|1d)$")>; 692def : InstRW<[M3WriteVLDA, 693 M3WriteA1], (instregex "LD1Twov(8b|4h|2s|1d)_POST")>; 694def : InstRW<[M3WriteVLDA], (instregex "LD1Twov(16b|8h|4s|2d)$")>; 695def : InstRW<[M3WriteVLDA, 696 M3WriteA1], (instregex "LD1Twov(16b|8h|4s|2d)_POST")>; 697 698def : InstRW<[M3WriteVLDB], (instregex "LD1Threev(8b|4h|2s|1d)$")>; 699def : InstRW<[M3WriteVLDB, 700 M3WriteA1], (instregex "LD1Threev(8b|4h|2s|1d)_POST")>; 701def : InstRW<[M3WriteVLDB], (instregex "LD1Threev(16b|8h|4s|2d)$")>; 702def : InstRW<[M3WriteVLDB, 703 M3WriteA1], (instregex "LD1Threev(16b|8h|4s|2d)_POST")>; 704 705def : InstRW<[M3WriteVLDC], (instregex "LD1Fourv(8b|4h|2s|1d)$")>; 706def : InstRW<[M3WriteVLDC, 707 M3WriteA1], (instregex "LD1Fourv(8b|4h|2s|1d)_POST")>; 708def : InstRW<[M3WriteVLDC], (instregex "LD1Fourv(16b|8h|4s|2d)$")>; 709def : InstRW<[M3WriteVLDC, 710 M3WriteA1], (instregex "LD1Fourv(16b|8h|4s|2d)_POST")>; 711 712def : InstRW<[M3WriteVLDD], (instregex "LD1i(8|16|32)$")>; 713def : InstRW<[M3WriteVLDD, 714 M3WriteA1], (instregex "LD1i(8|16|32)_POST")>; 715def : InstRW<[M3WriteVLDE], (instregex "LD1i(64)$")>; 716def : InstRW<[M3WriteVLDE, 717 M3WriteA1], (instregex "LD1i(64)_POST")>; 718 719def : InstRW<[M3WriteL5], (instregex "LD1Rv(8b|4h|2s|1d)$")>; 720def : InstRW<[M3WriteL5, 721 M3WriteA1], (instregex "LD1Rv(8b|4h|2s|1d)_POST")>; 722def : InstRW<[M3WriteL5], (instregex "LD1Rv(16b|8h|4s|2d)$")>; 723def : InstRW<[M3WriteL5, 724 M3WriteA1], (instregex "LD1Rv(16b|8h|4s|2d)_POST")>; 725 726def : InstRW<[M3WriteVLDF], (instregex "LD2Twov(8b|4h|2s)$")>; 727def : InstRW<[M3WriteVLDF, 728 M3WriteA1], (instregex "LD2Twov(8b|4h|2s)_POST")>; 729def : InstRW<[M3WriteVLDF], (instregex "LD2Twov(16b|8h|4s|2d)$")>; 730def : InstRW<[M3WriteVLDF, 731 M3WriteA1], (instregex "LD2Twov(16b|8h|4s|2d)_POST")>; 732 733def : InstRW<[M3WriteVLDG], (instregex "LD2i(8|16|32)$")>; 734def : InstRW<[M3WriteVLDG, 735 M3WriteA1], (instregex "LD2i(8|16|32)_POST")>; 736def : InstRW<[M3WriteVLDH], (instregex "LD2i(64)$")>; 737def : InstRW<[M3WriteVLDH, 738 M3WriteA1], (instregex "LD2i(64)_POST")>; 739 740def : InstRW<[M3WriteVLDA], (instregex "LD2Rv(8b|4h|2s|1d)$")>; 741def : InstRW<[M3WriteVLDA, 742 M3WriteA1], (instregex "LD2Rv(8b|4h|2s|1d)_POST")>; 743def : InstRW<[M3WriteVLDA], (instregex "LD2Rv(16b|8h|4s|2d)$")>; 744def : InstRW<[M3WriteVLDA, 745 M3WriteA1], (instregex "LD2Rv(16b|8h|4s|2d)_POST")>; 746 747def : InstRW<[M3WriteVLDI], (instregex "LD3Threev(8b|4h|2s)$")>; 748def : InstRW<[M3WriteVLDI, 749 M3WriteA1], (instregex "LD3Threev(8b|4h|2s)_POST")>; 750def : InstRW<[M3WriteVLDI], (instregex "LD3Threev(16b|8h|4s|2d)$")>; 751def : InstRW<[M3WriteVLDI, 752 M3WriteA1], (instregex "LD3Threev(16b|8h|4s|2d)_POST")>; 753 754def : InstRW<[M3WriteVLDJ], (instregex "LD3i(8|16|32)$")>; 755def : InstRW<[M3WriteVLDJ, 756 M3WriteA1], (instregex "LD3i(8|16|32)_POST")>; 757def : InstRW<[M3WriteVLDL], (instregex "LD3i(64)$")>; 758def : InstRW<[M3WriteVLDL, 759 M3WriteA1], (instregex "LD3i(64)_POST")>; 760 761def : InstRW<[M3WriteVLDB], (instregex "LD3Rv(8b|4h|2s|1d)$")>; 762def : InstRW<[M3WriteVLDB, 763 M3WriteA1], (instregex "LD3Rv(8b|4h|2s|1d)_POST")>; 764def : InstRW<[M3WriteVLDB], (instregex "LD3Rv(16b|8h|4s|2d)$")>; 765def : InstRW<[M3WriteVLDB, 766 M3WriteA1], (instregex "LD3Rv(16b|8h|4s|2d)_POST")>; 767 768def : InstRW<[M3WriteVLDN], (instregex "LD4Fourv(8b|4h|2s)$")>; 769def : InstRW<[M3WriteVLDN, 770 M3WriteA1], (instregex "LD4Fourv(8b|4h|2s)_POST")>; 771def : InstRW<[M3WriteVLDN], (instregex "LD4Fourv(16b|8h|4s|2d)$")>; 772def : InstRW<[M3WriteVLDN, 773 M3WriteA1], (instregex "LD4Fourv(16b|8h|4s|2d)_POST")>; 774 775def : InstRW<[M3WriteVLDK], (instregex "LD4i(8|16|32)$")>; 776def : InstRW<[M3WriteVLDK, 777 M3WriteA1], (instregex "LD4i(8|16|32)_POST")>; 778def : InstRW<[M3WriteVLDM], (instregex "LD4i(64)$")>; 779def : InstRW<[M3WriteVLDM, 780 M3WriteA1], (instregex "LD4i(64)_POST")>; 781 782def : InstRW<[M3WriteVLDC], (instregex "LD4Rv(8b|4h|2s|1d)$")>; 783def : InstRW<[M3WriteVLDC, 784 M3WriteA1], (instregex "LD4Rv(8b|4h|2s|1d)_POST")>; 785def : InstRW<[M3WriteVLDC], (instregex "LD4Rv(16b|8h|4s|2d)$")>; 786def : InstRW<[M3WriteVLDC, 787 M3WriteA1], (instregex "LD4Rv(16b|8h|4s|2d)_POST")>; 788 789// ASIMD store instructions. 790def : InstRW<[WriteVST], (instregex "ST1Onev(8b|4h|2s|1d)$")>; 791def : InstRW<[WriteVST, 792 WriteAdr], (instregex "ST1Onev(8b|4h|2s|1d)_POST")>; 793def : InstRW<[WriteVST], (instregex "ST1Onev(16b|8h|4s|2d)$")>; 794def : InstRW<[WriteVST, 795 WriteAdr], (instregex "ST1Onev(16b|8h|4s|2d)_POST")>; 796 797def : InstRW<[M3WriteVSTA], (instregex "ST1Twov(8b|4h|2s|1d)$")>; 798def : InstRW<[M3WriteVSTA, 799 WriteAdr], (instregex "ST1Twov(8b|4h|2s|1d)_POST")>; 800def : InstRW<[M3WriteVSTA], (instregex "ST1Twov(16b|8h|4s|2d)$")>; 801def : InstRW<[M3WriteVSTA, 802 WriteAdr], (instregex "ST1Twov(16b|8h|4s|2d)_POST")>; 803 804def : InstRW<[M3WriteVSTB], (instregex "ST1Threev(8b|4h|2s|1d)$")>; 805def : InstRW<[M3WriteVSTB, 806 WriteAdr], (instregex "ST1Threev(8b|4h|2s|1d)_POST")>; 807def : InstRW<[M3WriteVSTB], (instregex "ST1Threev(16b|8h|4s|2d)$")>; 808def : InstRW<[M3WriteVSTB, 809 WriteAdr], (instregex "ST1Threev(16b|8h|4s|2d)_POST")>; 810 811def : InstRW<[M3WriteVSTC], (instregex "ST1Fourv(8b|4h|2s|1d)$")>; 812def : InstRW<[M3WriteVSTC, 813 WriteAdr], (instregex "ST1Fourv(8b|4h|2s|1d)_POST")>; 814def : InstRW<[M3WriteVSTC], (instregex "ST1Fourv(16b|8h|4s|2d)$")>; 815def : InstRW<[M3WriteVSTC, 816 WriteAdr], (instregex "ST1Fourv(16b|8h|4s|2d)_POST")>; 817 818def : InstRW<[M3WriteVSTD], (instregex "ST1i(8|16|32|64)$")>; 819def : InstRW<[M3WriteVSTD, 820 WriteAdr], (instregex "ST1i(8|16|32|64)_POST")>; 821 822def : InstRW<[M3WriteVSTD], (instregex "ST2Twov(8b|4h|2s)$")>; 823def : InstRW<[M3WriteVSTD, 824 WriteAdr], (instregex "ST2Twov(8b|4h|2s)_POST")>; 825def : InstRW<[M3WriteVSTE], (instregex "ST2Twov(16b|8h|4s|2d)$")>; 826def : InstRW<[M3WriteVSTE, 827 WriteAdr], (instregex "ST2Twov(16b|8h|4s|2d)_POST")>; 828 829def : InstRW<[M3WriteVSTD], (instregex "ST2i(8|16|32)$")>; 830def : InstRW<[M3WriteVSTD, 831 WriteAdr], (instregex "ST2i(8|16|32)_POST")>; 832def : InstRW<[M3WriteVSTD], (instregex "ST2i(64)$")>; 833def : InstRW<[M3WriteVSTD, 834 WriteAdr], (instregex "ST2i(64)_POST")>; 835 836def : InstRW<[M3WriteVSTF], (instregex "ST3Threev(8b|4h|2s)$")>; 837def : InstRW<[M3WriteVSTF, 838 WriteAdr], (instregex "ST3Threev(8b|4h|2s)_POST")>; 839def : InstRW<[M3WriteVSTG], (instregex "ST3Threev(16b|8h|4s|2d)$")>; 840def : InstRW<[M3WriteVSTG, 841 WriteAdr], (instregex "ST3Threev(16b|8h|4s|2d)_POST")>; 842 843def : InstRW<[M3WriteVSTH], (instregex "ST3i(8|16|32)$")>; 844def : InstRW<[M3WriteVSTH, 845 WriteAdr], (instregex "ST3i(8|16|32)_POST")>; 846def : InstRW<[M3WriteVSTF], (instregex "ST3i(64)$")>; 847def : InstRW<[M3WriteVSTF, 848 WriteAdr], (instregex "ST3i(64)_POST")>; 849 850def : InstRW<[M3WriteVSTF], (instregex "ST4Fourv(8b|4h|2s)$")>; 851def : InstRW<[M3WriteVSTF, 852 WriteAdr], (instregex "ST4Fourv(8b|4h|2s)_POST")>; 853def : InstRW<[M3WriteVSTI], (instregex "ST4Fourv(16b|8h|4s|2d)$")>; 854def : InstRW<[M3WriteVSTI, 855 WriteAdr], (instregex "ST4Fourv(16b|8h|4s|2d)_POST")>; 856 857def : InstRW<[M3WriteVSTF], (instregex "ST4i(8|16|32|64)$")>; 858def : InstRW<[M3WriteVSTF, 859 WriteAdr], (instregex "ST4i(8|16|32|64)_POST")>; 860 861// Cryptography instructions. 862def : InstRW<[M3WriteAES], (instregex "^AES[DE]")>; 863def : InstRW<[M3WriteAES, 864 M3ReadAES], (instregex "^AESI?MC")>; 865 866def : InstRW<[M3WriteNCRY3A], (instregex "^PMULL?v")>; 867 868def : InstRW<[M3WriteNCRY1A], (instregex "^SHA1([CHMP]|SU[01])")>; 869def : InstRW<[M3WriteNCRY1A], (instregex "^SHA256SU0")>; 870def : InstRW<[M3WriteNCRY5A], (instregex "^SHA256(H2?|SU1)")>; 871 872// CRC instructions. 873def : InstRW<[M3WriteC2], (instregex "^CRC32")>; 874 875} // SchedModel = ExynosM3Model 876