10b57cec5SDimitry Andric//==- AArch64SchedFalkorDetails.td - Falkor Scheduling Defs -*- tablegen -*-==// 20b57cec5SDimitry Andric// 30b57cec5SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric// 70b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric// 90b57cec5SDimitry Andric// This file defines the uop and latency details for the machine model for the 100b57cec5SDimitry Andric// Qualcomm Falkor subtarget. 110b57cec5SDimitry Andric// 120b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 130b57cec5SDimitry Andric 140b57cec5SDimitry Andric// Contains all of the Falkor specific SchedWriteRes types. The approach 150b57cec5SDimitry Andric// below is to define a generic SchedWriteRes for every combination of 160b57cec5SDimitry Andric// latency and microOps. The naming conventions is to use a prefix, one field 170b57cec5SDimitry Andric// for latency, and one or more microOp count/type designators. 180b57cec5SDimitry Andric// Prefix: FalkorWr 190b57cec5SDimitry Andric// MicroOp Count/Types: #(B|X|Y|Z|LD|ST|SD|VX|VY|VSD) 200b57cec5SDimitry Andric// Latency: #cyc 210b57cec5SDimitry Andric// 220b57cec5SDimitry Andric// e.g. FalkorWr_1Z_6SD_4VX_6cyc means there are 11 micro-ops to be issued 230b57cec5SDimitry Andric// down one Z pipe, six SD pipes, four VX pipes and the total latency is 240b57cec5SDimitry Andric// six cycles. 250b57cec5SDimitry Andric// 260b57cec5SDimitry Andric// Contains all of the Falkor specific ReadAdvance types for forwarding logic. 270b57cec5SDimitry Andric// 280b57cec5SDimitry Andric// Contains all of the Falkor specific WriteVariant types for immediate zero 290b57cec5SDimitry Andric// and LSLFast. 300b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 310b57cec5SDimitry Andric 320b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 330b57cec5SDimitry Andric// Define 0 micro-op types 340b57cec5SDimitry Andricdef FalkorWr_LdInc_none_2cyc : SchedWriteRes<[]> { 350b57cec5SDimitry Andric let Latency = 2; 360b57cec5SDimitry Andric let NumMicroOps = 0; 370b57cec5SDimitry Andric} 380b57cec5SDimitry Andricdef FalkorWr_StInc_none_2cyc : SchedWriteRes<[]> { 390b57cec5SDimitry Andric let Latency = 2; 400b57cec5SDimitry Andric let NumMicroOps = 0; 410b57cec5SDimitry Andric} 420b57cec5SDimitry Andricdef FalkorWr_none_3cyc : SchedWriteRes<[]> { 430b57cec5SDimitry Andric let Latency = 3; 440b57cec5SDimitry Andric let NumMicroOps = 0; 450b57cec5SDimitry Andric} 460b57cec5SDimitry Andricdef FalkorWr_none_4cyc : SchedWriteRes<[]> { 470b57cec5SDimitry Andric let Latency = 4; 480b57cec5SDimitry Andric let NumMicroOps = 0; 490b57cec5SDimitry Andric} 500b57cec5SDimitry Andric 510b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 520b57cec5SDimitry Andric// Define 1 micro-op types 530b57cec5SDimitry Andric 540b57cec5SDimitry Andricdef FalkorWr_1X_2cyc : SchedWriteRes<[FalkorUnitX]> { let Latency = 2; } 550b57cec5SDimitry Andricdef FalkorWr_IMUL32_1X_2cyc : SchedWriteRes<[FalkorUnitX]> { let Latency = 4; } 560b57cec5SDimitry Andricdef FalkorWr_IMUL64_1X_4cyc : SchedWriteRes<[FalkorUnitX]> { let Latency = 4; } 570b57cec5SDimitry Andricdef FalkorWr_IMUL64_1X_5cyc : SchedWriteRes<[FalkorUnitX]> { let Latency = 5; } 580b57cec5SDimitry Andricdef FalkorWr_1Z_0cyc : SchedWriteRes<[FalkorUnitZ]> { let Latency = 0; } 590b57cec5SDimitry Andricdef FalkorWr_1ZB_0cyc : SchedWriteRes<[FalkorUnitZB]> { let Latency = 0; } 600b57cec5SDimitry Andricdef FalkorWr_1LD_3cyc : SchedWriteRes<[FalkorUnitLD]> { let Latency = 3; } 610b57cec5SDimitry Andricdef FalkorWr_1LD_4cyc : SchedWriteRes<[FalkorUnitLD]> { let Latency = 4; } 620b57cec5SDimitry Andricdef FalkorWr_1XYZ_0cyc : SchedWriteRes<[FalkorUnitXYZ]> { let Latency = 0; } 630b57cec5SDimitry Andricdef FalkorWr_1XYZ_1cyc : SchedWriteRes<[FalkorUnitXYZ]> { let Latency = 1; } 640b57cec5SDimitry Andricdef FalkorWr_1XYZ_2cyc : SchedWriteRes<[FalkorUnitXYZ]> { let Latency = 2; } 650b57cec5SDimitry Andricdef FalkorWr_1XYZB_0cyc : SchedWriteRes<[FalkorUnitXYZB]>{ let Latency = 0; } 660b57cec5SDimitry Andricdef FalkorWr_1XYZB_1cyc : SchedWriteRes<[FalkorUnitXYZB]>{ let Latency = 1; } 670b57cec5SDimitry Andricdef FalkorWr_1none_0cyc : SchedWriteRes<[]> { let Latency = 0; } 680b57cec5SDimitry Andric 690b57cec5SDimitry Andricdef FalkorWr_1VXVY_0cyc : SchedWriteRes<[FalkorUnitVXVY]>{ let Latency = 0; } 700b57cec5SDimitry Andricdef FalkorWr_1VXVY_1cyc : SchedWriteRes<[FalkorUnitVXVY]>{ let Latency = 1; } 710b57cec5SDimitry Andricdef FalkorWr_1VXVY_2cyc : SchedWriteRes<[FalkorUnitVXVY]>{ let Latency = 2; } 720b57cec5SDimitry Andricdef FalkorWr_1VXVY_3cyc : SchedWriteRes<[FalkorUnitVXVY]>{ let Latency = 3; } 730b57cec5SDimitry Andricdef FalkorWr_1VXVY_4cyc : SchedWriteRes<[FalkorUnitVXVY]>{ let Latency = 4; } 740b57cec5SDimitry Andricdef FalkorWr_VMUL32_1VXVY_4cyc : SchedWriteRes<[FalkorUnitVXVY]>{ let Latency = 4; } 750b57cec5SDimitry Andricdef FalkorWr_1VXVY_5cyc : SchedWriteRes<[FalkorUnitVXVY]>{ let Latency = 5; } 760b57cec5SDimitry Andricdef FalkorWr_FMUL32_1VXVY_5cyc : SchedWriteRes<[FalkorUnitVXVY]>{ let Latency = 5; } 770b57cec5SDimitry Andricdef FalkorWr_1VXVY_6cyc : SchedWriteRes<[FalkorUnitVXVY]>{ let Latency = 6; } 780b57cec5SDimitry Andricdef FalkorWr_FMUL64_1VXVY_6cyc : SchedWriteRes<[FalkorUnitVXVY]>{ let Latency = 6; } 790b57cec5SDimitry Andric 800b57cec5SDimitry Andricdef FalkorWr_1LD_0cyc : SchedWriteRes<[FalkorUnitLD]> { let Latency = 0; } 810b57cec5SDimitry Andricdef FalkorWr_1ST_0cyc : SchedWriteRes<[FalkorUnitST]> { let Latency = 0; } 820b57cec5SDimitry Andricdef FalkorWr_1ST_3cyc : SchedWriteRes<[FalkorUnitST]> { let Latency = 3; } 830b57cec5SDimitry Andric 840b57cec5SDimitry Andricdef FalkorWr_1GTOV_0cyc : SchedWriteRes<[FalkorUnitGTOV]>{ let Latency = 0; } 850b57cec5SDimitry Andricdef FalkorWr_1GTOV_1cyc : SchedWriteRes<[FalkorUnitGTOV]>{ let Latency = 1; } 860b57cec5SDimitry Andricdef FalkorWr_1GTOV_4cyc : SchedWriteRes<[FalkorUnitGTOV]>{ let Latency = 4; } 870b57cec5SDimitry Andricdef FalkorWr_1VTOG_1cyc : SchedWriteRes<[FalkorUnitVTOG]>{ let Latency = 1; } 880b57cec5SDimitry Andric 890b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 900b57cec5SDimitry Andric// Define 2 micro-op types 910b57cec5SDimitry Andric 920b57cec5SDimitry Andricdef FalkorWr_2VXVY_0cyc : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY]> { 930b57cec5SDimitry Andric let Latency = 0; 940b57cec5SDimitry Andric let NumMicroOps = 2; 950b57cec5SDimitry Andric} 960b57cec5SDimitry Andricdef FalkorWr_2VXVY_1cyc : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY]> { 970b57cec5SDimitry Andric let Latency = 1; 980b57cec5SDimitry Andric let NumMicroOps = 2; 990b57cec5SDimitry Andric} 1000b57cec5SDimitry Andricdef FalkorWr_2VXVY_2cyc : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY]> { 1010b57cec5SDimitry Andric let Latency = 2; 1020b57cec5SDimitry Andric let NumMicroOps = 2; 1030b57cec5SDimitry Andric} 1040b57cec5SDimitry Andricdef FalkorWr_2VXVY_3cyc : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY]> { 1050b57cec5SDimitry Andric let Latency = 3; 1060b57cec5SDimitry Andric let NumMicroOps = 2; 1070b57cec5SDimitry Andric} 1080b57cec5SDimitry Andricdef FalkorWr_2VXVY_4cyc : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY]> { 1090b57cec5SDimitry Andric let Latency = 4; 1100b57cec5SDimitry Andric let NumMicroOps = 2; 1110b57cec5SDimitry Andric} 1120b57cec5SDimitry Andricdef FalkorWr_VMUL32_2VXVY_4cyc : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY]> { 1130b57cec5SDimitry Andric let Latency = 4; 1140b57cec5SDimitry Andric let NumMicroOps = 2; 1150b57cec5SDimitry Andric} 1160b57cec5SDimitry Andricdef FalkorWr_2VXVY_5cyc : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY]> { 1170b57cec5SDimitry Andric let Latency = 5; 1180b57cec5SDimitry Andric let NumMicroOps = 2; 1190b57cec5SDimitry Andric} 1200b57cec5SDimitry Andricdef FalkorWr_FMUL32_2VXVY_5cyc : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY]> { 1210b57cec5SDimitry Andric let Latency = 5; 1220b57cec5SDimitry Andric let NumMicroOps = 2; 1230b57cec5SDimitry Andric} 1240b57cec5SDimitry Andricdef FalkorWr_2VXVY_6cyc : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY]> { 1250b57cec5SDimitry Andric let Latency = 6; 1260b57cec5SDimitry Andric let NumMicroOps = 2; 1270b57cec5SDimitry Andric} 1280b57cec5SDimitry Andricdef FalkorWr_FMUL64_2VXVY_6cyc : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY]> { 1290b57cec5SDimitry Andric let Latency = 6; 1300b57cec5SDimitry Andric let NumMicroOps = 2; 1310b57cec5SDimitry Andric} 1320b57cec5SDimitry Andric 1330b57cec5SDimitry Andricdef FalkorWr_1LD_1VXVY_4cyc : SchedWriteRes<[FalkorUnitLD, FalkorUnitVXVY]> { 1340b57cec5SDimitry Andric let Latency = 4; 1350b57cec5SDimitry Andric let NumMicroOps = 2; 1360b57cec5SDimitry Andric} 1370b57cec5SDimitry Andricdef FalkorWr_1XYZ_1LD_4cyc : SchedWriteRes<[FalkorUnitXYZ, FalkorUnitLD]> { 1380b57cec5SDimitry Andric let Latency = 4; 1390b57cec5SDimitry Andric let NumMicroOps = 2; 1400b57cec5SDimitry Andric} 1410b57cec5SDimitry Andricdef FalkorWr_2LD_3cyc : SchedWriteRes<[FalkorUnitLD, FalkorUnitLD]> { 1420b57cec5SDimitry Andric let Latency = 3; 1430b57cec5SDimitry Andric let NumMicroOps = 2; 1440b57cec5SDimitry Andric} 1450b57cec5SDimitry Andric 1460b57cec5SDimitry Andricdef FalkorWr_1VX_1VY_5cyc : SchedWriteRes<[FalkorUnitVX, FalkorUnitVY]> { 1470b57cec5SDimitry Andric let Latency = 5; 1480b57cec5SDimitry Andric let NumMicroOps = 2; 1490b57cec5SDimitry Andric} 1500b57cec5SDimitry Andric 1510b57cec5SDimitry Andricdef FalkorWr_1VX_1VY_2cyc : SchedWriteRes<[FalkorUnitVX, FalkorUnitVY]> { 1520b57cec5SDimitry Andric let Latency = 2; 1530b57cec5SDimitry Andric let NumMicroOps = 2; 1540b57cec5SDimitry Andric} 1550b57cec5SDimitry Andric 1560b57cec5SDimitry Andricdef FalkorWr_1VX_1VY_4cyc : SchedWriteRes<[FalkorUnitVX, FalkorUnitVY]> { 1570b57cec5SDimitry Andric let Latency = 4; 1580b57cec5SDimitry Andric let NumMicroOps = 2; 1590b57cec5SDimitry Andric} 1600b57cec5SDimitry Andric 1610b57cec5SDimitry Andricdef FalkorWr_1VX_1VY_10cyc : SchedWriteRes<[FalkorUnitVX, FalkorUnitVY]> { 1620b57cec5SDimitry Andric let Latency = 10; 1630b57cec5SDimitry Andric let NumMicroOps = 2; 1640b57cec5SDimitry Andric} 1650b57cec5SDimitry Andric 1660b57cec5SDimitry Andricdef FalkorWr_1VX_1VY_12cyc : SchedWriteRes<[FalkorUnitVX, FalkorUnitVY]> { 1670b57cec5SDimitry Andric let Latency = 12; 1680b57cec5SDimitry Andric let NumMicroOps = 2; 1690b57cec5SDimitry Andric} 1700b57cec5SDimitry Andric 1710b57cec5SDimitry Andricdef FalkorWr_1VX_1VY_14cyc : SchedWriteRes<[FalkorUnitVX, FalkorUnitVY]> { 1720b57cec5SDimitry Andric let Latency = 14; 1730b57cec5SDimitry Andric let NumMicroOps = 2; 1740b57cec5SDimitry Andric} 1750b57cec5SDimitry Andric 1760b57cec5SDimitry Andricdef FalkorWr_1VX_1VY_21cyc : SchedWriteRes<[FalkorUnitVX, FalkorUnitVY]> { 1770b57cec5SDimitry Andric let Latency = 21; 1780b57cec5SDimitry Andric let NumMicroOps = 2; 1790b57cec5SDimitry Andric} 1800b57cec5SDimitry Andric 1810b57cec5SDimitry Andricdef FalkorWr_1GTOV_1VXVY_2cyc : SchedWriteRes<[FalkorUnitGTOV, FalkorUnitVXVY]> { 1820b57cec5SDimitry Andric let Latency = 2; 1830b57cec5SDimitry Andric let NumMicroOps = 2; 1840b57cec5SDimitry Andric} 1850b57cec5SDimitry Andric 1860b57cec5SDimitry Andricdef FalkorWr_2GTOV_1cyc : SchedWriteRes<[FalkorUnitGTOV, FalkorUnitGTOV]> { 1870b57cec5SDimitry Andric let Latency = 1; 1880b57cec5SDimitry Andric let NumMicroOps = 2; 1890b57cec5SDimitry Andric} 1900b57cec5SDimitry Andric 1910b57cec5SDimitry Andricdef FalkorWr_1XYZ_1ST_4cyc: SchedWriteRes<[FalkorUnitXYZ, FalkorUnitST]> { 1920b57cec5SDimitry Andric let Latency = 4; 1930b57cec5SDimitry Andric let NumMicroOps = 2; 1940b57cec5SDimitry Andric} 1950b57cec5SDimitry Andricdef FalkorWr_1XYZ_1LD_5cyc: SchedWriteRes<[FalkorUnitXYZ, FalkorUnitLD]> { 1960b57cec5SDimitry Andric let Latency = 5; 1970b57cec5SDimitry Andric let NumMicroOps = 2; 1980b57cec5SDimitry Andric} 1990b57cec5SDimitry Andric 2000b57cec5SDimitry Andricdef FalkorWr_2XYZ_2cyc : SchedWriteRes<[FalkorUnitXYZ, FalkorUnitXYZ]> { 2010b57cec5SDimitry Andric let Latency = 2; 2020b57cec5SDimitry Andric let NumMicroOps = 2; 2030b57cec5SDimitry Andric} 2040b57cec5SDimitry Andric 2050b57cec5SDimitry Andricdef FalkorWr_1Z_1XY_0cyc : SchedWriteRes<[FalkorUnitZ, FalkorUnitXY]> { 2060b57cec5SDimitry Andric let Latency = 0; 2070b57cec5SDimitry Andric let NumMicroOps = 2; 2080b57cec5SDimitry Andric} 2090b57cec5SDimitry Andric 2100b57cec5SDimitry Andricdef FalkorWr_1X_1Z_8cyc : SchedWriteRes<[FalkorUnitX, FalkorUnitZ]> { 2110b57cec5SDimitry Andric let Latency = 8; 2120b57cec5SDimitry Andric let NumMicroOps = 2; 2135f757f3fSDimitry Andric let ReleaseAtCycles = [2, 8]; 2140b57cec5SDimitry Andric} 2150b57cec5SDimitry Andric 2160b57cec5SDimitry Andricdef FalkorWr_1X_1Z_11cyc : SchedWriteRes<[FalkorUnitX, FalkorUnitZ]> { 2170b57cec5SDimitry Andric let Latency = 11; 2180b57cec5SDimitry Andric let NumMicroOps = 2; 2195f757f3fSDimitry Andric let ReleaseAtCycles = [2, 11]; 2200b57cec5SDimitry Andric} 2210b57cec5SDimitry Andric 2220b57cec5SDimitry Andricdef FalkorWr_1LD_1Z_3cyc : SchedWriteRes<[FalkorUnitLD, FalkorUnitZ]> { 2230b57cec5SDimitry Andric let Latency = 3; 2240b57cec5SDimitry Andric let NumMicroOps = 2; 2250b57cec5SDimitry Andric} 2260b57cec5SDimitry Andric 2270b57cec5SDimitry Andricdef FalkorWr_1LD_1none_3cyc : SchedWriteRes<[FalkorUnitLD]> { 2280b57cec5SDimitry Andric let Latency = 3; 2290b57cec5SDimitry Andric let NumMicroOps = 2; 2300b57cec5SDimitry Andric} 2310b57cec5SDimitry Andric 2320b57cec5SDimitry Andricdef FalkorWr_1SD_1ST_0cyc: SchedWriteRes<[FalkorUnitSD, FalkorUnitST]> { 2330b57cec5SDimitry Andric let Latency = 0; 2340b57cec5SDimitry Andric let NumMicroOps = 2; 2350b57cec5SDimitry Andric} 2360b57cec5SDimitry Andric 2370b57cec5SDimitry Andricdef FalkorWr_1VSD_1ST_0cyc: SchedWriteRes<[FalkorUnitVSD, FalkorUnitST]> { 2380b57cec5SDimitry Andric let Latency = 0; 2390b57cec5SDimitry Andric let NumMicroOps = 2; 2400b57cec5SDimitry Andric} 2410b57cec5SDimitry Andric 2420b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 2430b57cec5SDimitry Andric// Define 3 micro-op types 2440b57cec5SDimitry Andric 2450b57cec5SDimitry Andricdef FalkorWr_1ST_1SD_1LD_0cyc : SchedWriteRes<[FalkorUnitST, FalkorUnitSD, 2460b57cec5SDimitry Andric FalkorUnitLD]> { 2470b57cec5SDimitry Andric let Latency = 0; 2480b57cec5SDimitry Andric let NumMicroOps = 3; 2490b57cec5SDimitry Andric} 2500b57cec5SDimitry Andric 2510b57cec5SDimitry Andricdef FalkorWr_1ST_1SD_1LD_3cyc : SchedWriteRes<[FalkorUnitST, FalkorUnitSD, 2520b57cec5SDimitry Andric FalkorUnitLD]> { 2530b57cec5SDimitry Andric let Latency = 3; 2540b57cec5SDimitry Andric let NumMicroOps = 3; 2550b57cec5SDimitry Andric} 2560b57cec5SDimitry Andric 2570b57cec5SDimitry Andricdef FalkorWr_3VXVY_3cyc : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY]> { 2580b57cec5SDimitry Andric let Latency = 3; 2590b57cec5SDimitry Andric let NumMicroOps = 3; 2600b57cec5SDimitry Andric} 2610b57cec5SDimitry Andric 2620b57cec5SDimitry Andricdef FalkorWr_3VXVY_4cyc : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY]> { 2630b57cec5SDimitry Andric let Latency = 4; 2640b57cec5SDimitry Andric let NumMicroOps = 3; 2650b57cec5SDimitry Andric} 2660b57cec5SDimitry Andric 2670b57cec5SDimitry Andricdef FalkorWr_3VXVY_5cyc : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY]> { 2680b57cec5SDimitry Andric let Latency = 5; 2690b57cec5SDimitry Andric let NumMicroOps = 3; 2700b57cec5SDimitry Andric} 2710b57cec5SDimitry Andric 2720b57cec5SDimitry Andricdef FalkorWr_3VXVY_6cyc : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY]> { 2730b57cec5SDimitry Andric let Latency = 6; 2740b57cec5SDimitry Andric let NumMicroOps = 3; 2750b57cec5SDimitry Andric} 2760b57cec5SDimitry Andric 2770b57cec5SDimitry Andricdef FalkorWr_1LD_2VXVY_4cyc : SchedWriteRes<[FalkorUnitLD, FalkorUnitVXVY]> { 2780b57cec5SDimitry Andric let Latency = 4; 2790b57cec5SDimitry Andric let NumMicroOps = 3; 2800b57cec5SDimitry Andric} 2810b57cec5SDimitry Andric 2820b57cec5SDimitry Andricdef FalkorWr_2LD_1none_3cyc : SchedWriteRes<[FalkorUnitLD, FalkorUnitLD]> { 2830b57cec5SDimitry Andric let Latency = 3; 2840b57cec5SDimitry Andric let NumMicroOps = 3; 2850b57cec5SDimitry Andric} 2860b57cec5SDimitry Andric 2870b57cec5SDimitry Andricdef FalkorWr_3LD_3cyc : SchedWriteRes<[FalkorUnitLD, FalkorUnitLD, 2880b57cec5SDimitry Andric FalkorUnitLD]> { 2890b57cec5SDimitry Andric let Latency = 3; 2900b57cec5SDimitry Andric let NumMicroOps = 3; 2910b57cec5SDimitry Andric} 2920b57cec5SDimitry Andric 2930b57cec5SDimitry Andricdef FalkorWr_2LD_1Z_3cyc : SchedWriteRes<[FalkorUnitLD, FalkorUnitLD, 2940b57cec5SDimitry Andric FalkorUnitZ]> { 2950b57cec5SDimitry Andric let Latency = 3; 2960b57cec5SDimitry Andric let NumMicroOps = 3; 2970b57cec5SDimitry Andric} 2980b57cec5SDimitry Andric 2990b57cec5SDimitry Andricdef FalkorWr_1XYZ_1SD_1ST_0cyc: SchedWriteRes<[FalkorUnitXYZ, FalkorUnitSD, FalkorUnitST]> { 3000b57cec5SDimitry Andric let Latency = 0; 3010b57cec5SDimitry Andric let NumMicroOps = 3; 3020b57cec5SDimitry Andric} 3030b57cec5SDimitry Andricdef FalkorWr_1XYZ_1VSD_1ST_0cyc: SchedWriteRes<[FalkorUnitXYZ, FalkorUnitVSD, FalkorUnitST]> { 3040b57cec5SDimitry Andric let Latency = 0; 3050b57cec5SDimitry Andric let NumMicroOps = 3; 3060b57cec5SDimitry Andric} 3070b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 3080b57cec5SDimitry Andric// Define 4 micro-op types 3090b57cec5SDimitry Andric 3100b57cec5SDimitry Andricdef FalkorWr_2VX_2VY_14cyc : SchedWriteRes<[FalkorUnitVX, FalkorUnitVY, 3110b57cec5SDimitry Andric FalkorUnitVX, FalkorUnitVY]> { 3120b57cec5SDimitry Andric let Latency = 14; 3130b57cec5SDimitry Andric let NumMicroOps = 4; 3140b57cec5SDimitry Andric} 3150b57cec5SDimitry Andric 3160b57cec5SDimitry Andricdef FalkorWr_2VX_2VY_20cyc : SchedWriteRes<[FalkorUnitVX, FalkorUnitVY, 3170b57cec5SDimitry Andric FalkorUnitVX, FalkorUnitVY]> { 3180b57cec5SDimitry Andric let Latency = 20; 3190b57cec5SDimitry Andric let NumMicroOps = 4; 3200b57cec5SDimitry Andric} 3210b57cec5SDimitry Andric 3220b57cec5SDimitry Andricdef FalkorWr_2VX_2VY_21cyc : SchedWriteRes<[FalkorUnitVX, FalkorUnitVY, 3230b57cec5SDimitry Andric FalkorUnitVX, FalkorUnitVY]> { 3240b57cec5SDimitry Andric let Latency = 21; 3250b57cec5SDimitry Andric let NumMicroOps = 4; 3260b57cec5SDimitry Andric} 3270b57cec5SDimitry Andric 3280b57cec5SDimitry Andricdef FalkorWr_2VX_2VY_24cyc : SchedWriteRes<[FalkorUnitVX, FalkorUnitVY, 3290b57cec5SDimitry Andric FalkorUnitVX, FalkorUnitVY]> { 3300b57cec5SDimitry Andric let Latency = 24; 3310b57cec5SDimitry Andric let NumMicroOps = 4; 3320b57cec5SDimitry Andric} 3330b57cec5SDimitry Andric 3340b57cec5SDimitry Andricdef FalkorWr_4VXVY_2cyc : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY, 3350b57cec5SDimitry Andric FalkorUnitVXVY, FalkorUnitVXVY]> { 3360b57cec5SDimitry Andric let Latency = 2; 3370b57cec5SDimitry Andric let NumMicroOps = 4; 3380b57cec5SDimitry Andric} 3390b57cec5SDimitry Andricdef FalkorWr_4VXVY_3cyc : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY, 3400b57cec5SDimitry Andric FalkorUnitVXVY, FalkorUnitVXVY]> { 3410b57cec5SDimitry Andric let Latency = 3; 3420b57cec5SDimitry Andric let NumMicroOps = 4; 3430b57cec5SDimitry Andric} 3440b57cec5SDimitry Andricdef FalkorWr_4VXVY_4cyc : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY, 3450b57cec5SDimitry Andric FalkorUnitVXVY, FalkorUnitVXVY]> { 3460b57cec5SDimitry Andric let Latency = 4; 3470b57cec5SDimitry Andric let NumMicroOps = 4; 3480b57cec5SDimitry Andric} 3490b57cec5SDimitry Andricdef FalkorWr_4VXVY_6cyc : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY, 3500b57cec5SDimitry Andric FalkorUnitVXVY, FalkorUnitVXVY]> { 3510b57cec5SDimitry Andric let Latency = 6; 3520b57cec5SDimitry Andric let NumMicroOps = 4; 3530b57cec5SDimitry Andric} 3540b57cec5SDimitry Andric 3550b57cec5SDimitry Andricdef FalkorWr_4LD_3cyc : SchedWriteRes<[FalkorUnitLD, FalkorUnitLD, 3560b57cec5SDimitry Andric FalkorUnitLD, FalkorUnitLD]> { 3570b57cec5SDimitry Andric let Latency = 3; 3580b57cec5SDimitry Andric let NumMicroOps = 4; 3590b57cec5SDimitry Andric} 3600b57cec5SDimitry Andric 3610b57cec5SDimitry Andricdef FalkorWr_1LD_3VXVY_4cyc: SchedWriteRes<[FalkorUnitLD, FalkorUnitVXVY, 3620b57cec5SDimitry Andric FalkorUnitVXVY, FalkorUnitVXVY]> { 3630b57cec5SDimitry Andric let Latency = 4; 3640b57cec5SDimitry Andric let NumMicroOps = 4; 3650b57cec5SDimitry Andric} 3660b57cec5SDimitry Andric 3670b57cec5SDimitry Andricdef FalkorWr_2LD_2none_3cyc: SchedWriteRes<[FalkorUnitLD, FalkorUnitLD]> { 3680b57cec5SDimitry Andric let Latency = 3; 3690b57cec5SDimitry Andric let NumMicroOps = 4; 3700b57cec5SDimitry Andric} 3710b57cec5SDimitry Andric 3720b57cec5SDimitry Andricdef FalkorWr_2LD_1ST_1SD_3cyc: SchedWriteRes<[FalkorUnitLD, FalkorUnitST, 3730b57cec5SDimitry Andric FalkorUnitSD, FalkorUnitLD]> { 3740b57cec5SDimitry Andric let Latency = 3; 3750b57cec5SDimitry Andric let NumMicroOps = 4; 3760b57cec5SDimitry Andric} 3770b57cec5SDimitry Andric 3780b57cec5SDimitry Andricdef FalkorWr_2VSD_2ST_0cyc: SchedWriteRes<[FalkorUnitST, FalkorUnitVSD, 3790b57cec5SDimitry Andric FalkorUnitST, FalkorUnitVSD]> { 3800b57cec5SDimitry Andric let Latency = 0; 3810b57cec5SDimitry Andric let NumMicroOps = 4; 3820b57cec5SDimitry Andric} 3830b57cec5SDimitry Andric 3840b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 3850b57cec5SDimitry Andric// Define 5 micro-op types 3860b57cec5SDimitry Andric 3870b57cec5SDimitry Andricdef FalkorWr_1LD_4VXVY_4cyc: SchedWriteRes<[FalkorUnitLD, FalkorUnitVXVY, 3880b57cec5SDimitry Andric FalkorUnitVXVY, FalkorUnitVXVY, 3890b57cec5SDimitry Andric FalkorUnitVXVY]> { 3900b57cec5SDimitry Andric let Latency = 4; 3910b57cec5SDimitry Andric let NumMicroOps = 5; 3920b57cec5SDimitry Andric} 3930b57cec5SDimitry Andricdef FalkorWr_2LD_2VXVY_1none_4cyc: SchedWriteRes<[FalkorUnitLD, FalkorUnitLD, 3940b57cec5SDimitry Andric FalkorUnitVXVY, FalkorUnitVXVY]> { 3950b57cec5SDimitry Andric let Latency = 4; 3960b57cec5SDimitry Andric let NumMicroOps = 5; 3970b57cec5SDimitry Andric} 3980b57cec5SDimitry Andricdef FalkorWr_5VXVY_7cyc : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY, 3990b57cec5SDimitry Andric FalkorUnitVXVY, FalkorUnitVXVY, 4000b57cec5SDimitry Andric FalkorUnitVXVY]> { 4010b57cec5SDimitry Andric let Latency = 7; 4020b57cec5SDimitry Andric let NumMicroOps = 5; 4030b57cec5SDimitry Andric} 4040b57cec5SDimitry Andricdef FalkorWr_1XYZ_2ST_2VSD_0cyc: SchedWriteRes<[FalkorUnitXYZ, FalkorUnitST, 4050b57cec5SDimitry Andric FalkorUnitVSD, FalkorUnitST, 4060b57cec5SDimitry Andric FalkorUnitVSD]> { 4070b57cec5SDimitry Andric let Latency = 0; 4080b57cec5SDimitry Andric let NumMicroOps = 5; 4090b57cec5SDimitry Andric} 4100b57cec5SDimitry Andricdef FalkorWr_1VXVY_2ST_2VSD_0cyc : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitST, 4110b57cec5SDimitry Andric FalkorUnitVSD, FalkorUnitST, 4120b57cec5SDimitry Andric FalkorUnitVSD]> { 4130b57cec5SDimitry Andric let Latency = 0; 4140b57cec5SDimitry Andric let NumMicroOps = 5; 4150b57cec5SDimitry Andric} 4160b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 4170b57cec5SDimitry Andric// Define 6 micro-op types 4180b57cec5SDimitry Andric 4190b57cec5SDimitry Andricdef FalkorWr_2LD_2VXVY_2none_4cyc: SchedWriteRes<[FalkorUnitLD, FalkorUnitLD, 4200b57cec5SDimitry Andric FalkorUnitVXVY, FalkorUnitVXVY]> { 4210b57cec5SDimitry Andric let Latency = 4; 4220b57cec5SDimitry Andric let NumMicroOps = 6; 4230b57cec5SDimitry Andric} 4240b57cec5SDimitry Andric 4250b57cec5SDimitry Andricdef FalkorWr_2XYZ_2ST_2VSD_0cyc: SchedWriteRes<[FalkorUnitXYZ, FalkorUnitST, 4260b57cec5SDimitry Andric FalkorUnitVSD, FalkorUnitXYZ, 4270b57cec5SDimitry Andric FalkorUnitST, FalkorUnitVSD]> { 4280b57cec5SDimitry Andric let Latency = 0; 4290b57cec5SDimitry Andric let NumMicroOps = 6; 4300b57cec5SDimitry Andric} 4310b57cec5SDimitry Andric 4320b57cec5SDimitry Andricdef FalkorWr_2VXVY_2ST_2VSD_0cyc: SchedWriteRes<[FalkorUnitVXVY, FalkorUnitST, 4330b57cec5SDimitry Andric FalkorUnitVSD, FalkorUnitVXVY, 4340b57cec5SDimitry Andric FalkorUnitST, FalkorUnitVSD]> { 4350b57cec5SDimitry Andric let Latency = 0; 4360b57cec5SDimitry Andric let NumMicroOps = 6; 4370b57cec5SDimitry Andric} 4380b57cec5SDimitry Andric 4390b57cec5SDimitry Andricdef FalkorWr_3VSD_3ST_0cyc: SchedWriteRes<[FalkorUnitST, FalkorUnitVSD, 4400b57cec5SDimitry Andric FalkorUnitST, FalkorUnitVSD, 4410b57cec5SDimitry Andric FalkorUnitST, FalkorUnitVSD]> { 4420b57cec5SDimitry Andric let Latency = 0; 4430b57cec5SDimitry Andric let NumMicroOps = 6; 4440b57cec5SDimitry Andric} 4450b57cec5SDimitry Andric 4460b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 4470b57cec5SDimitry Andric// Define 8 micro-op types 4480b57cec5SDimitry Andric 4490b57cec5SDimitry Andricdef FalkorWr_2LD_2VXVY_2LD_2VXVY_4cyc:SchedWriteRes<[FalkorUnitLD, FalkorUnitLD, 4500b57cec5SDimitry Andric FalkorUnitVXVY, FalkorUnitVXVY, 4510b57cec5SDimitry Andric FalkorUnitLD, FalkorUnitLD, 4520b57cec5SDimitry Andric FalkorUnitVXVY, FalkorUnitVXVY]> { 4530b57cec5SDimitry Andric let Latency = 4; 4540b57cec5SDimitry Andric let NumMicroOps = 8; 4550b57cec5SDimitry Andric} 4560b57cec5SDimitry Andric 4570b57cec5SDimitry Andricdef FalkorWr_4VSD_4ST_0cyc: SchedWriteRes<[FalkorUnitST, FalkorUnitVSD, 4580b57cec5SDimitry Andric FalkorUnitST, FalkorUnitVSD, 4590b57cec5SDimitry Andric FalkorUnitST, FalkorUnitVSD, 4600b57cec5SDimitry Andric FalkorUnitST, FalkorUnitVSD]> { 4610b57cec5SDimitry Andric let Latency = 0; 4620b57cec5SDimitry Andric let NumMicroOps = 8; 4630b57cec5SDimitry Andric} 4640b57cec5SDimitry Andric 4650b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 4660b57cec5SDimitry Andric// Define 9 micro-op types 4670b57cec5SDimitry Andric 4680b57cec5SDimitry Andricdef FalkorWr_2LD_2VXVY_2LD_1XYZ_2VXVY_4cyc:SchedWriteRes<[FalkorUnitLD, 4690b57cec5SDimitry Andric FalkorUnitLD, FalkorUnitVXVY, 4700b57cec5SDimitry Andric FalkorUnitVXVY, FalkorUnitLD, 4710b57cec5SDimitry Andric FalkorUnitLD, FalkorUnitXYZ, 4720b57cec5SDimitry Andric FalkorUnitVXVY, FalkorUnitVXVY]> { 4730b57cec5SDimitry Andric let Latency = 4; 4740b57cec5SDimitry Andric let NumMicroOps = 9; 4750b57cec5SDimitry Andric} 4760b57cec5SDimitry Andric 4770b57cec5SDimitry Andricdef FalkorWr_2LD_2VXVY_1XYZ_2LD_2VXVY_4cyc:SchedWriteRes<[FalkorUnitLD, 4780b57cec5SDimitry Andric FalkorUnitLD, FalkorUnitVXVY, 4790b57cec5SDimitry Andric FalkorUnitVXVY, FalkorUnitXYZ, 4800b57cec5SDimitry Andric FalkorUnitLD, FalkorUnitLD, 4810b57cec5SDimitry Andric FalkorUnitVXVY, FalkorUnitVXVY]> { 4820b57cec5SDimitry Andric let Latency = 4; 4830b57cec5SDimitry Andric let NumMicroOps = 9; 4840b57cec5SDimitry Andric} 4850b57cec5SDimitry Andric 4860b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 4870b57cec5SDimitry Andric// Define 10 micro-op types 4880b57cec5SDimitry Andric 4890b57cec5SDimitry Andricdef FalkorWr_2VXVY_4ST_4VSD_0cyc: SchedWriteRes<[FalkorUnitVXVY, FalkorUnitST, 4900b57cec5SDimitry Andric FalkorUnitVSD, FalkorUnitVXVY, 4910b57cec5SDimitry Andric FalkorUnitST, FalkorUnitVSD, 4920b57cec5SDimitry Andric FalkorUnitST, FalkorUnitVSD, 4930b57cec5SDimitry Andric FalkorUnitST, FalkorUnitVSD]> { 4940b57cec5SDimitry Andric let Latency = 0; 4950b57cec5SDimitry Andric let NumMicroOps = 10; 4960b57cec5SDimitry Andric} 4970b57cec5SDimitry Andric 4980b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 4990b57cec5SDimitry Andric// Define 12 micro-op types 5000b57cec5SDimitry Andric 5010b57cec5SDimitry Andricdef FalkorWr_4VXVY_4ST_4VSD_0cyc: SchedWriteRes<[FalkorUnitVXVY, FalkorUnitST, 5020b57cec5SDimitry Andric FalkorUnitVSD, FalkorUnitVXVY, 5030b57cec5SDimitry Andric FalkorUnitST, FalkorUnitVSD, 5040b57cec5SDimitry Andric FalkorUnitVXVY, FalkorUnitST, 5050b57cec5SDimitry Andric FalkorUnitVSD, FalkorUnitVXVY, 5060b57cec5SDimitry Andric FalkorUnitST, FalkorUnitVSD]> { 5070b57cec5SDimitry Andric let Latency = 0; 5080b57cec5SDimitry Andric let NumMicroOps = 12; 5090b57cec5SDimitry Andric} 5100b57cec5SDimitry Andric 5110b57cec5SDimitry Andric// Forwarding logic is modeled for multiply add/accumulate and 5120b57cec5SDimitry Andric// load/store base register increment. 5130b57cec5SDimitry Andric// ----------------------------------------------------------------------------- 5140b57cec5SDimitry Andricdef FalkorReadIMA32 : SchedReadAdvance<3, [FalkorWr_IMUL32_1X_2cyc]>; 5150b57cec5SDimitry Andricdef FalkorReadIMA64 : SchedReadAdvance<4, [FalkorWr_IMUL64_1X_4cyc, FalkorWr_IMUL64_1X_5cyc]>; 5160b57cec5SDimitry Andricdef FalkorReadVMA : SchedReadAdvance<3, [FalkorWr_VMUL32_1VXVY_4cyc, FalkorWr_VMUL32_2VXVY_4cyc]>; 5170b57cec5SDimitry Andricdef FalkorReadFMA32 : SchedReadAdvance<1, [FalkorWr_FMUL32_1VXVY_5cyc, FalkorWr_FMUL32_2VXVY_5cyc]>; 5180b57cec5SDimitry Andricdef FalkorReadFMA64 : SchedReadAdvance<2, [FalkorWr_FMUL64_1VXVY_6cyc, FalkorWr_FMUL64_2VXVY_6cyc]>; 5190b57cec5SDimitry Andric 5200b57cec5SDimitry Andricdef FalkorReadIncLd : SchedReadAdvance<1, [FalkorWr_LdInc_none_2cyc]>; 5210b57cec5SDimitry Andricdef FalkorReadIncSt : SchedReadAdvance<1, [FalkorWr_StInc_none_2cyc]>; 5220b57cec5SDimitry Andric 5230b57cec5SDimitry Andric// SchedPredicates and WriteVariants for Immediate Zero and LSLFast/ASRFast 5240b57cec5SDimitry Andric// ----------------------------------------------------------------------------- 5250b57cec5SDimitry Andricdef FalkorImmZPred : SchedPredicate<[{MI->getOperand(1).isImm() && 5260b57cec5SDimitry Andric MI->getOperand(1).getImm() == 0}]>; 5270b57cec5SDimitry Andricdef FalkorOp1ZrReg : SchedPredicate<[{MI->getOperand(1).getReg() == AArch64::WZR || 5280b57cec5SDimitry Andric 5290b57cec5SDimitry Andric MI->getOperand(1).getReg() == AArch64::XZR}]>; 5300b57cec5SDimitry Andricdef FalkorShiftExtFastPred : SchedPredicate<[{TII->isFalkorShiftExtFast(*MI)}]>; 5310b57cec5SDimitry Andric 5320b57cec5SDimitry Andricdef FalkorWr_FMOV : SchedWriteVariant<[ 5330b57cec5SDimitry Andric SchedVar<FalkorOp1ZrReg, [FalkorWr_1none_0cyc]>, 5340b57cec5SDimitry Andric SchedVar<NoSchedPred, [FalkorWr_1GTOV_1cyc]>]>; 5350b57cec5SDimitry Andric 5360b57cec5SDimitry Andricdef FalkorWr_MOVZ : SchedWriteVariant<[ 5370b57cec5SDimitry Andric SchedVar<FalkorImmZPred, [FalkorWr_1none_0cyc]>, 5380b57cec5SDimitry Andric SchedVar<NoSchedPred, [FalkorWr_1XYZB_0cyc]>]>; // imm fwd 5390b57cec5SDimitry Andric 5400b57cec5SDimitry Andric 5410b57cec5SDimitry Andricdef FalkorWr_ADDSUBsx : SchedWriteVariant<[ 5420b57cec5SDimitry Andric SchedVar<FalkorShiftExtFastPred, [FalkorWr_1XYZ_1cyc]>, 5430b57cec5SDimitry Andric SchedVar<NoSchedPred, [FalkorWr_2XYZ_2cyc]>]>; 5440b57cec5SDimitry Andric 5450b57cec5SDimitry Andricdef FalkorWr_LDRro : SchedWriteVariant<[ 5460b57cec5SDimitry Andric SchedVar<FalkorShiftExtFastPred, [FalkorWr_1LD_3cyc]>, 5470b57cec5SDimitry Andric SchedVar<NoSchedPred, [FalkorWr_1XYZ_1LD_4cyc]>]>; 5480b57cec5SDimitry Andric 5490b57cec5SDimitry Andricdef FalkorWr_LDRSro : SchedWriteVariant<[ 5500b57cec5SDimitry Andric SchedVar<FalkorShiftExtFastPred, [FalkorWr_1LD_4cyc]>, 5510b57cec5SDimitry Andric SchedVar<NoSchedPred, [FalkorWr_1XYZ_1LD_5cyc]>]>; 5520b57cec5SDimitry Andric 5530b57cec5SDimitry Andricdef FalkorWr_ORRi : SchedWriteVariant<[ 5540b57cec5SDimitry Andric SchedVar<FalkorOp1ZrReg, [FalkorWr_1XYZ_0cyc]>, // imm fwd 5550b57cec5SDimitry Andric SchedVar<NoSchedPred, [FalkorWr_1XYZ_1cyc]>]>; 5560b57cec5SDimitry Andric 5570b57cec5SDimitry Andricdef FalkorWr_PRFMro : SchedWriteVariant<[ 5580b57cec5SDimitry Andric SchedVar<FalkorShiftExtFastPred, [FalkorWr_1ST_3cyc]>, 5590b57cec5SDimitry Andric SchedVar<NoSchedPred, [FalkorWr_1XYZ_1ST_4cyc]>]>; 5600b57cec5SDimitry Andric 5610b57cec5SDimitry Andricdef FalkorWr_STRVro : SchedWriteVariant<[ 5620b57cec5SDimitry Andric SchedVar<FalkorShiftExtFastPred, [FalkorWr_1VSD_1ST_0cyc]>, 5630b57cec5SDimitry Andric SchedVar<NoSchedPred, [FalkorWr_1XYZ_1VSD_1ST_0cyc]>]>; 5640b57cec5SDimitry Andric 5650b57cec5SDimitry Andricdef FalkorWr_STRQro : SchedWriteVariant<[ 5660b57cec5SDimitry Andric SchedVar<FalkorShiftExtFastPred, [FalkorWr_1XYZ_2ST_2VSD_0cyc]>, 5670b57cec5SDimitry Andric SchedVar<NoSchedPred, [FalkorWr_2XYZ_2ST_2VSD_0cyc]>]>; 5680b57cec5SDimitry Andric 5690b57cec5SDimitry Andricdef FalkorWr_STRro : SchedWriteVariant<[ 5700b57cec5SDimitry Andric SchedVar<FalkorShiftExtFastPred, [FalkorWr_1SD_1ST_0cyc]>, 5710b57cec5SDimitry Andric SchedVar<NoSchedPred, [FalkorWr_1XYZ_1SD_1ST_0cyc]>]>; 5720b57cec5SDimitry Andric 5730b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 5740b57cec5SDimitry Andric// Specialize the coarse model by associating instruction groups with the 5750b57cec5SDimitry Andric// subtarget-defined types. As the modeled is refined, this will override most 5760b57cec5SDimitry Andric// of the earlier mappings. 5770b57cec5SDimitry Andric 5780b57cec5SDimitry Andric// Miscellaneous 5790b57cec5SDimitry Andric// ----------------------------------------------------------------------------- 5800b57cec5SDimitry Andric 5810b57cec5SDimitry Andric// FIXME: This could be better modeled by looking at the regclasses of the operands. 5820b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1XYZ_1cyc], (instrs COPY)>; 5830b57cec5SDimitry Andric 5840b57cec5SDimitry Andric// SIMD Floating-point Instructions 5850b57cec5SDimitry Andric// ----------------------------------------------------------------------------- 5860b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^(FABS|FNEG)v2f32$")>; 5870b57cec5SDimitry Andric 5880b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^(F(MAX|MIN)(NM)?P?|FAC(GE|GT))(v2f32|v2i32p)$")>; 5890b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^FAC(GE|GT)(32|64)$")>; 5900b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^FCM(EQ|GE|GT)(32|64|v2f32|v2i32)$")>; 5910b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^FCM(EQ|LE|GE|GT|LT)(v1i32|v1i64|v2i32)rz$")>; 5920b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^FRINT(A|I|M|N|P|X|Z)v2f32$")>; 5930b57cec5SDimitry Andric 5940b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^F(MAX|MIN)(NM)?Vv4i32v$")>; 5950b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(FABD|FADD|FSUB)v2f32$")>; 5960b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^FADDP(v2i32p|v2i64p|v2f32)$")>; 5970b57cec5SDimitry Andric 5980b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_4cyc], (instregex "^FCVT(N|M|P|Z|A)(S|U)(v1i32|v1i64|v2f32)$")>; 5990b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_4cyc], (instrs FCVTXNv1i64)>; 6000b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_4cyc], (instregex "^FCVTZ(S|U)v2i32(_shift)?$")>; 6010b57cec5SDimitry Andric 6020b57cec5SDimitry Andricdef : InstRW<[FalkorWr_FMUL32_1VXVY_5cyc], 6030b57cec5SDimitry Andric (instregex "^(FMUL|FMULX)(v2f32|(v1i32_indexed|v2i32_indexed))$")>; 6040b57cec5SDimitry Andricdef : InstRW<[FalkorWr_FMUL32_1VXVY_5cyc], 6050b57cec5SDimitry Andric (instrs FMULX32)>; 6060b57cec5SDimitry Andric 6070b57cec5SDimitry Andricdef : InstRW<[FalkorWr_FMUL64_1VXVY_6cyc], 6080b57cec5SDimitry Andric (instregex "^(FMUL|FMULX)v1i64_indexed$")>; 6090b57cec5SDimitry Andricdef : InstRW<[FalkorWr_FMUL64_1VXVY_6cyc], 6100b57cec5SDimitry Andric (instrs FMULX64)>; 6110b57cec5SDimitry Andric 6120b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VXVY_1cyc], (instregex "^(FABS|FNEG)(v2f64|v4f32)$")>; 6130b57cec5SDimitry Andric 6140b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^(F(MAX|MIN)(NM)?P?|FAC(GE|GT)|FCM(EQ|GE|GT))(v2f64|v4f32|v2i64p)$")>; 6150b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^FCM(EQ|LE|GE|GT|LT)(v2i64|v4i32)rz$")>; 6160b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VXVY_2cyc], (instrs FCVTLv4i16, FCVTLv2i32)>; 6170b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^FRINT(A|I|M|N|P|X|Z)(v2f64|v4f32)$")>; 6180b57cec5SDimitry Andric 6190b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VX_1VY_10cyc],(instrs FDIVv2f32)>; 6200b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VX_1VY_12cyc],(instrs FSQRTv2f32)>; 6210b57cec5SDimitry Andric 6220b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VXVY_3cyc], (instregex "^(FABD|FADD(P)?|FSUB)(v2f64|v4f32)$")>; 6230b57cec5SDimitry Andric 6240b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VXVY_4cyc], (instregex "^FCVT(N|M|P|Z|A)(S|U)(v2f64|v4f32)$")>; 6250b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VXVY_4cyc], (instrs FCVTLv8i16, FCVTLv4i32)>; 6260b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VXVY_4cyc], (instregex "^FCVTZ(S|U)(v2i64|v4i32)(_shift)?$")>; 6270b57cec5SDimitry Andric 6280b57cec5SDimitry Andricdef : InstRW<[FalkorWr_FMUL32_2VXVY_5cyc], 6290b57cec5SDimitry Andric (instregex "^(FMUL|FMULX)(v2f64|v4f32|v4i32_indexed)$")>; 6300b57cec5SDimitry Andric 6310b57cec5SDimitry Andricdef : InstRW<[FalkorWr_FMUL64_2VXVY_6cyc], 6320b57cec5SDimitry Andric (instregex "^(FMUL|FMULX)v2i64_indexed$")>; 6330b57cec5SDimitry Andric 6340b57cec5SDimitry Andricdef : InstRW<[FalkorWr_3VXVY_4cyc], (instrs FCVTNv4i16, FCVTNv2i32, FCVTXNv2f32)>; 6350b57cec5SDimitry Andricdef : InstRW<[FalkorWr_3VXVY_5cyc], (instrs FCVTNv8i16, FCVTNv4i32, FCVTXNv4f32)>; 6360b57cec5SDimitry Andric 6370b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VX_2VY_14cyc],(instrs FDIVv2f64)>; 6380b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VX_2VY_20cyc],(instrs FDIVv4f32)>; 6390b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VX_2VY_21cyc],(instrs FSQRTv2f64)>; 6400b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VX_2VY_24cyc],(instrs FSQRTv4f32)>; 6410b57cec5SDimitry Andric 6420b57cec5SDimitry Andricdef : InstRW<[FalkorWr_VMUL32_1VXVY_4cyc, FalkorReadVMA], 6430b57cec5SDimitry Andric (instregex "^ML(A|S)(v8i8|v4i16|v2i32)(_indexed)?$")>; 6440b57cec5SDimitry Andricdef : InstRW<[FalkorWr_VMUL32_2VXVY_4cyc, FalkorReadVMA], 6450b57cec5SDimitry Andric (instregex "^ML(A|S)(v16i8|v8i16|v4i32|v2i64)(_indexed)?$")>; 6460b57cec5SDimitry Andric 6470b57cec5SDimitry Andricdef : InstRW<[FalkorWr_FMUL32_1VXVY_5cyc, FalkorReadFMA32], 6480b57cec5SDimitry Andric (instregex "^FML(A|S)(v2f32|(v1i32_indexed|v2i32_indexed))$")>; 6490b57cec5SDimitry Andricdef : InstRW<[FalkorWr_FMUL64_1VXVY_6cyc, FalkorReadFMA64], 6500b57cec5SDimitry Andric (instregex "^FML(A|S)v1i64_indexed$")>; 6510b57cec5SDimitry Andricdef : InstRW<[FalkorWr_FMUL32_2VXVY_5cyc, FalkorReadFMA32], 6520b57cec5SDimitry Andric (instregex "^FML(A|S)(v4f32|v4i32_indexed)$")>; 6530b57cec5SDimitry Andricdef : InstRW<[FalkorWr_FMUL64_2VXVY_6cyc, FalkorReadFMA64], 6540b57cec5SDimitry Andric (instregex "^FML(A|S)(v2f64|v2i64_indexed)$")>; 6550b57cec5SDimitry Andric 6560b57cec5SDimitry Andric// SIMD Integer Instructions 6570b57cec5SDimitry Andric// ----------------------------------------------------------------------------- 6580b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^ADD(v1i64|v2i32|v4i16|v8i8)$")>; 6590b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_1cyc], (instrs ADDPv2i64p)>; 6600b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^(AND|ORR|ORN|BIC|EOR)v8i8$")>; 6610b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^(BIC|ORR)(v2i32|v4i16)$")>; 6620b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^NEG(v1i64|v2i32|v4i16|v8i8)$")>; 6630b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^SUB(v1i64|v2i32|v4i16|v8i8)$")>; 6640b57cec5SDimitry Andric 6650b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^(S|U)(ADDLP|HADD|HSUB|SHL)(v2i32|v4i16|v8i8)(_v.*)?$")>; 6660b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^(S|U)SHLv1i64$")>; 6670b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^(S|U)SHR(v2i32|v4i16|v8i8)_shift$")>; 6680b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^(S|U)SHRd$")>; 6690b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^((S|U)?(MAX|MIN)P?|ABS|ADDP|CM(EQ|GE|HS|GT|HI))(v1i64|v2i32|v4i16|v8i8)$")>; 6700b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^CM(EQ|GE|HS|GT|HI)(v1i64|v2i32|v4i16|v8i8)$")>; 6710b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^CM(EQ|LE|GE|GT|LT)(v1i64|v2i32|v4i16|v8i8)rz$")>; 6720b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^CMTST(v1i64|v2i32|v4i16|v8i8)$")>; 6730b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_2cyc], (instrs PMULv8i8)>; 6740b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^SHL(v2i32|v4i16|v8i8)_shift$")>; 6750b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^SHLd$")>; 6760b57cec5SDimitry Andric 6770b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^SQNEG(v2i32|v4i16|v8i8)$")>; 6780b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S|U)R?SRA(d|(v2i32|v4i16|v8i8)_shift)$")>; 6790b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S|U)(ABD|ADALP)(v8i8|v4i16|v2i32)(_v.*)?$")>; 6800b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S|U)ADDLVv4i16v$")>; 6810b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S|U)QADD(v1i8|v1i16|v2i16|v1i32|v1i64|v2i32|v4i16|v8i8)$")>; 6820b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S|U)QSHLU?(d|s|h|b|(v8i8|v4i16|v2i32)_shift)$")>; 6830b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S|U)(QSHL|RSHL|QRSHL)(v1i8|v1i16|v1i32|v1i64|v2i32|v4i16|v8i8)$")>; 6840b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(SQR?SHRN|UQR?SHRN|SQR?SHRUN)(s|h|b)$")>; 6850b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S|U)QSUB(v1i8|v1i16|v2i16|v1i32|v1i64|v2i32|v4i16|v8i8)$")>; 6860b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S|U)RHADD(v2i32|v4i16|v8i8)$")>; 6870b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S|U)RSHR(v2i32|v4i16|v8i8)_shift$")>; 6880b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S|U)RSHRd$")>; 6890b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^R?SHRN(v2i32|v4i16|v8i8)_shift$")>; 6900b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(SU|US)QADD(v1i8|v1i16|v2i16|v1i32|v1i64|v2i32|v4i16|v8i8)$")>; 6910b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S|U)?(MAX|MIN)V(v4i16v|v4i32v)$")>; 6920b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_3cyc], (instrs ADDVv4i16v)>; 6930b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^S(L|R)I(d|(v8i8|v4i16|v2i32)_shift)$")>; 6940b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^SQABS(v1i8|v1i16|v1i32|v1i64|v2i32|v4i16|v8i8)$")>; 6950b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^SQNEG(v1i8|v1i16|v1i32|v1i64)$")>; 6960b57cec5SDimitry Andric 6970b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_4cyc], (instregex "^(S|U)ADDLVv8i8v$")>; 6980b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_4cyc], (instregex "^(S|U)?(MAX|MIN)V(v8i8v|v8i16v)$")>; 6990b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_4cyc], (instrs ADDVv8i8v)>; 7000b57cec5SDimitry Andricdef : InstRW<[FalkorWr_VMUL32_1VXVY_4cyc], 7010b57cec5SDimitry Andric (instregex "^MUL(v2i32|v4i16|v8i8)(_indexed)?$")>; 7020b57cec5SDimitry Andricdef : InstRW<[FalkorWr_VMUL32_1VXVY_4cyc], 7030b57cec5SDimitry Andric (instregex "^SQR?DMULH(v8i8|v4i16|v1i32|v2i32|v1i16)(_indexed)?$")>; 7040b57cec5SDimitry Andricdef : InstRW<[FalkorWr_VMUL32_1VXVY_4cyc], 7050b57cec5SDimitry Andric (instregex "^SQDMULL(i16|i32)$")>; 7060b57cec5SDimitry Andricdef : InstRW<[FalkorWr_VMUL32_1VXVY_4cyc, FalkorReadVMA], 7070b57cec5SDimitry Andric (instregex "^SQRDML(A|S)H(i16|i32|v8i8|v4i16|v1i32|v2i32|v1i16)(_indexed)?$")>; 7080b57cec5SDimitry Andric 7090b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_5cyc], (instregex "^(S|U)?(MAX|MIN)Vv16i8v$")>; 7100b57cec5SDimitry Andric 7110b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VXVY_3cyc], (instrs ADDVv4i32v)>; 7120b57cec5SDimitry Andric 7130b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VXVY_4cyc], (instrs ADDVv8i16v)>; 7140b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VXVY_4cyc], (instregex "^(ADD|SUB)HNv.*$")>; 7150b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VXVY_4cyc], (instregex "^(S|U)ABA(v2i32|v4i16|v8i8)$")>; 7160b57cec5SDimitry Andric 7170b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VXVY_5cyc], (instrs ADDVv16i8v)>; 7180b57cec5SDimitry Andric 7190b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VXVY_6cyc], (instregex "^(SQR?SHRN|UQR?SHRN|SQR?SHRUN)(v8i8|v16i8|v4i16|v8i16|v2i32|v4i32)_shift?$")>; 7200b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VXVY_6cyc], (instregex "^R(ADD|SUB)HNv.*$")>; 7210b57cec5SDimitry Andric 7220b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VXVY_1cyc], (instregex "^ADD(v16i8|v8i16|v4i32|v2i64)$")>; 7230b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VXVY_1cyc], (instrs ADDPv2i64)>; // sz==11 7240b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VXVY_1cyc], (instregex "^(AND|ORR|ORN|BIC|EOR)v16i8$")>; 7250b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VXVY_1cyc], (instregex "^(BIC|ORR)(v8i16|v4i32)$")>; 7260b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VXVY_1cyc], (instregex "^(NEG|SUB)(v16i8|v8i16|v4i32|v2i64)$")>; 7270b57cec5SDimitry Andric 7280b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^(S|U)ADDLv.*$")>; 7290b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^(S|U)(ADDLP|HADD|HSUB|SHL)(v16i8|v2i64|v4i32|v8i16)(_v.*)?$")>; 7300b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^(S|U)SHLL(v16i8|v8i16|v4i32|v8i8|v4i16|v2i32)(_shift)?$")>; 7310b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^(S|U)SHR(v16i8|v8i16|v4i32|v2i64)_shift$")>; 7320b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^(S|U)SUBLv.*$")>; 7330b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^((S|U)?(MAX|MIN)P?|ABS)(v16i8|v2i64|v4i32|v8i16)$")>; 7340b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^ADDP(v4i32|v8i16|v16i8)$")>; // sz!=11 7350b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^CM(EQ|GE|HS|GT|HI)(v16i8|v2i64|v4i32|v8i16)$")>; 7360b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^CM(EQ|LE|GE|GT|LT)(v16i8|v2i64|v4i32|v8i16)rz$")>; 7370b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^(CMTST|PMUL)(v16i8|v2i64|v4i32|v8i16)$")>; 7380b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^PMULL(v8i8|v16i8)$")>; 7390b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^SHL(v16i8|v8i16|v4i32|v2i64)_shift$")>; 7400b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^SHLL(v16i8|v8i16|v4i32|v8i8|v4i16|v2i32)(_shift)?$")>; 7410b57cec5SDimitry Andric 7420b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VXVY_3cyc], (instregex "^(S|U)R?SRA(v2i64|v4i32|v8i16|v16i8)_shift$")>; 7430b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VXVY_3cyc], (instregex "^(S|U)ABD(v16i8|v8i16|v4i32|v2i64)$")>; 7440b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VXVY_3cyc], (instregex "^(S|U)ABDLv.*$")>; 7450b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VXVY_3cyc], (instregex "^(S|U)(ADALP|QADD)(v16i8|v8i16|v4i32|v2i64)(_v.*)?$")>; 7460b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VXVY_3cyc], (instregex "^(S|U)QSHLU?(v2i64|v4i32|v8i16|v16i8)_shift$")>; 7470b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VXVY_3cyc], (instregex "^(S|U)(QSHL|RSHL|QRSHL|QSUB|RHADD)(v16i8|v8i16|v4i32|v2i64)$")>; 7480b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VXVY_3cyc], (instregex "^(S|U)RSHR(v2i64|v4i32|v8i16|v16i8)_shift$")>; 7490b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VXVY_3cyc], (instregex "^R?SHRN(v2i64|v4i32|v8i16|v16i8)_shift$")>; 7500b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VXVY_3cyc], (instregex "^(SU|US)QADD(v16i8|v8i16|v4i32|v2i64)$")>; 7510b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VXVY_3cyc], (instregex "^PMULL(v1i64|v2i64)$")>; 7520b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VXVY_3cyc], (instregex "^S(L|R)I(v16i8|v8i16|v4i32|v2i64)_shift$")>; 7530b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VXVY_3cyc], (instregex "^SQ(ABS|NEG)(v16i8|v8i16|v4i32|v2i64)$")>; 7540b57cec5SDimitry Andric 7550b57cec5SDimitry Andricdef : InstRW<[FalkorWr_VMUL32_2VXVY_4cyc], 7560b57cec5SDimitry Andric (instregex "^(MUL|SQR?DMULH)(v16i8|v8i16|v4i32)(_indexed)?$")>; 7570b57cec5SDimitry Andricdef : InstRW<[FalkorWr_VMUL32_2VXVY_4cyc], 7580b57cec5SDimitry Andric (instregex "^SQDMULLv.*$")>; 7590b57cec5SDimitry Andricdef : InstRW<[FalkorWr_VMUL32_2VXVY_4cyc, FalkorReadVMA], 7600b57cec5SDimitry Andric (instregex "^SQRDML(A|S)H(v16i8|v8i16|v4i32)(_indexed)?$")>; 7610b57cec5SDimitry Andric 7620b57cec5SDimitry Andricdef : InstRW<[FalkorWr_3VXVY_3cyc], (instregex "^(S|U)ADDLVv4i32v$")>; 7630b57cec5SDimitry Andric 7640b57cec5SDimitry Andricdef : InstRW<[FalkorWr_3VXVY_5cyc], (instregex "^(S|U)ADDLVv8i16v$")>; 7650b57cec5SDimitry Andric 7660b57cec5SDimitry Andricdef : InstRW<[FalkorWr_3VXVY_6cyc], (instregex "^(S|U)ADDLVv16i8v$")>; 7670b57cec5SDimitry Andric 7680b57cec5SDimitry Andricdef : InstRW<[FalkorWr_4VXVY_2cyc], (instregex "^(S|U)(ADD|SUB)Wv.*$")>; 7690b57cec5SDimitry Andric 7700b57cec5SDimitry Andricdef : InstRW<[FalkorWr_4VXVY_3cyc], (instregex "^(S|U)ABALv.*$")>; 7710b57cec5SDimitry Andric 7720b57cec5SDimitry Andricdef : InstRW<[FalkorWr_4VXVY_4cyc], (instregex "^(S|U)ABA(v16i8|v8i16|v4i32)$")>; 7730b57cec5SDimitry Andric 7740b57cec5SDimitry Andricdef : InstRW<[FalkorWr_VMUL32_1VXVY_4cyc, FalkorReadVMA], 7750b57cec5SDimitry Andric (instregex "^SQD(MLAL|MLSL)(i16|i32|v1i32_indexed|v1i64_indexed)$")>; 7760b57cec5SDimitry Andricdef : InstRW<[FalkorWr_VMUL32_2VXVY_4cyc, FalkorReadVMA], 7770b57cec5SDimitry Andric (instregex "^SQD(MLAL|MLSL)v[248].*$")>; 7780b57cec5SDimitry Andric 7790b57cec5SDimitry Andric// SIMD Load Instructions 7800b57cec5SDimitry Andric// ----------------------------------------------------------------------------- 7810b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1LD_3cyc, FalkorReadIncLd], (instregex "^LD1(i64|Onev(8b|4h|2s|1d|16b|8h|4s|2d))$")>; 7820b57cec5SDimitry Andricdef : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_1LD_3cyc, FalkorReadIncLd], 7830b57cec5SDimitry Andric (instregex "^LD1(i64|Onev(8b|4h|2s|1d|16b|8h|4s|2d))_POST$")>; 7840b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1LD_3cyc, FalkorReadIncLd], (instregex "^LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 7850b57cec5SDimitry Andricdef : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_1LD_3cyc, FalkorReadIncLd], 7860b57cec5SDimitry Andric (instregex "^LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 7870b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1LD_3cyc, FalkorReadIncLd], (instrs LD2i64)>; 7880b57cec5SDimitry Andricdef : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_1LD_3cyc, FalkorReadIncLd], 7890b57cec5SDimitry Andric (instrs LD2i64_POST)>; 7900b57cec5SDimitry Andric 7910b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1LD_1VXVY_4cyc, FalkorReadIncLd], (instregex "^LD1i(8|16|32)$")>; 7920b57cec5SDimitry Andricdef : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_1LD_1VXVY_4cyc, FalkorReadIncLd], 7930b57cec5SDimitry Andric (instregex "^LD1i(8|16|32)_POST$")>; 7940b57cec5SDimitry Andric 7950b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1LD_1none_3cyc, FalkorReadIncLd], (instregex "^LD1Twov(8b|4h|2s|1d)$")>; 7960b57cec5SDimitry Andricdef : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_1LD_1none_3cyc, FalkorReadIncLd], 7970b57cec5SDimitry Andric (instregex "^LD1Twov(8b|4h|2s|1d)_POST$")>; 7980b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1LD_1none_3cyc, FalkorReadIncLd], (instregex "^LD2Twov(8b|4h|2s)$")>; 7990b57cec5SDimitry Andricdef : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_1LD_1none_3cyc, FalkorReadIncLd], 8000b57cec5SDimitry Andric (instregex "^LD2Twov(8b|4h|2s)_POST$")>; 8010b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1LD_1none_3cyc, FalkorReadIncLd], (instregex "^LD2Rv(8b|4h|2s|1d)$")>; 8020b57cec5SDimitry Andricdef : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_1LD_1none_3cyc, FalkorReadIncLd], 8030b57cec5SDimitry Andric (instregex "^LD2Rv(8b|4h|2s|1d)_POST$")>; 8040b57cec5SDimitry Andric 8050b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2LD_3cyc, FalkorReadIncLd], (instregex "^LD1Twov(16b|8h|4s|2d)$")>; 8060b57cec5SDimitry Andricdef : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_2LD_3cyc, FalkorReadIncLd], 8070b57cec5SDimitry Andric (instregex "^LD1Twov(16b|8h|4s|2d)_POST$")>; 8080b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2LD_3cyc, FalkorReadIncLd], (instregex "^LD2Twov(16b|8h|4s|2d)$")>; 8090b57cec5SDimitry Andricdef : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_2LD_3cyc, FalkorReadIncLd], 8100b57cec5SDimitry Andric (instregex "^LD2Twov(16b|8h|4s|2d)_POST$")>; 8110b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2LD_3cyc, FalkorReadIncLd], (instregex "^LD2Rv(16b|8h|4s|2d)$")>; 8120b57cec5SDimitry Andricdef : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_2LD_3cyc, FalkorReadIncLd], 8130b57cec5SDimitry Andric (instregex "^LD2Rv(16b|8h|4s|2d)_POST$")>; 8140b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2LD_3cyc, FalkorReadIncLd], (instrs LD3i64)>; 8150b57cec5SDimitry Andricdef : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_2LD_3cyc, FalkorReadIncLd], 8160b57cec5SDimitry Andric (instrs LD3i64_POST)>; 8170b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2LD_3cyc, FalkorReadIncLd], (instrs LD4i64)>; 8180b57cec5SDimitry Andricdef : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_2LD_3cyc, FalkorReadIncLd], 8190b57cec5SDimitry Andric (instrs LD4i64_POST)>; 8200b57cec5SDimitry Andric 8210b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1LD_2VXVY_4cyc, FalkorReadIncLd], (instregex "^LD2i(8|16|32)$")>; 8220b57cec5SDimitry Andricdef : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_1LD_2VXVY_4cyc, FalkorReadIncLd], 8230b57cec5SDimitry Andric (instregex "^LD2i(8|16|32)_POST$")>; 8240b57cec5SDimitry Andric 8250b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2LD_1none_3cyc, FalkorReadIncLd], (instregex "^LD1Threev(8b|4h|2s|1d)$")>; 8260b57cec5SDimitry Andricdef : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_2LD_1none_3cyc, FalkorReadIncLd], 8270b57cec5SDimitry Andric (instregex "^LD1Threev(8b|4h|2s|1d)_POST$")>; 8280b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2LD_1none_3cyc, FalkorReadIncLd], (instregex "^LD3Rv(8b|4h|2s|1d)$")>; 8290b57cec5SDimitry Andricdef : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_2LD_1none_3cyc, FalkorReadIncLd], 8300b57cec5SDimitry Andric (instregex "^LD3Rv(8b|4h|2s|1d)_POST$")>; 8310b57cec5SDimitry Andric 8320b57cec5SDimitry Andricdef : InstRW<[FalkorWr_3LD_3cyc, FalkorReadIncLd], (instregex "^LD1Threev(16b|8h|4s|2d)$")>; 8330b57cec5SDimitry Andricdef : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_3LD_3cyc, FalkorReadIncLd], 8340b57cec5SDimitry Andric (instregex "^LD1Threev(16b|8h|4s|2d)_POST$")>; 8350b57cec5SDimitry Andricdef : InstRW<[FalkorWr_3LD_3cyc, FalkorReadIncLd], (instrs LD3Threev2d)>; 8360b57cec5SDimitry Andricdef : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_3LD_3cyc, FalkorReadIncLd], 8370b57cec5SDimitry Andric (instrs LD3Threev2d_POST)>; 8380b57cec5SDimitry Andricdef : InstRW<[FalkorWr_3LD_3cyc, FalkorReadIncLd], (instregex "^LD3Rv(16b|8h|4s|2d)$")>; 8390b57cec5SDimitry Andricdef : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_3LD_3cyc, FalkorReadIncLd], 8400b57cec5SDimitry Andric (instregex "^LD3Rv(16b|8h|4s|2d)_POST$")>; 8410b57cec5SDimitry Andric 8420b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1LD_3VXVY_4cyc, FalkorReadIncLd], (instregex "^LD3i(8|16|32)$")>; 8430b57cec5SDimitry Andricdef : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_1LD_3VXVY_4cyc, FalkorReadIncLd], 8440b57cec5SDimitry Andric (instregex "^LD3i(8|16|32)_POST$")>; 8450b57cec5SDimitry Andric 8460b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2LD_2none_3cyc, FalkorReadIncLd], (instregex "^LD1Fourv(8b|4h|2s|1d)$")>; 8470b57cec5SDimitry Andricdef : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_2LD_2none_3cyc, FalkorReadIncLd], 8480b57cec5SDimitry Andric (instregex "^LD1Fourv(8b|4h|2s|1d)_POST$")>; 8490b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2LD_2none_3cyc, FalkorReadIncLd], (instregex "^LD4Rv(8b|4h|2s|1d)$")>; 8500b57cec5SDimitry Andricdef : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_2LD_2none_3cyc, FalkorReadIncLd], 8510b57cec5SDimitry Andric (instregex "^LD4Rv(8b|4h|2s|1d)_POST$")>; 8520b57cec5SDimitry Andric 8530b57cec5SDimitry Andricdef : InstRW<[FalkorWr_4LD_3cyc, FalkorReadIncLd], (instregex "^LD1Fourv(16b|8h|4s|2d)$")>; 8540b57cec5SDimitry Andricdef : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_4LD_3cyc, FalkorReadIncLd], 8550b57cec5SDimitry Andric (instregex "^LD1Fourv(16b|8h|4s|2d)_POST$")>; 8560b57cec5SDimitry Andricdef : InstRW<[FalkorWr_4LD_3cyc, FalkorReadIncLd], (instrs LD4Fourv2d)>; 8570b57cec5SDimitry Andricdef : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_4LD_3cyc, FalkorReadIncLd], 8580b57cec5SDimitry Andric (instrs LD4Fourv2d_POST)>; 8590b57cec5SDimitry Andricdef : InstRW<[FalkorWr_4LD_3cyc, FalkorReadIncLd], (instregex "^LD4Rv(16b|8h|4s|2d)$")>; 8600b57cec5SDimitry Andricdef : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_4LD_3cyc, FalkorReadIncLd], 8610b57cec5SDimitry Andric (instregex "^LD4Rv(16b|8h|4s|2d)_POST$")>; 8620b57cec5SDimitry Andric 8630b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1LD_4VXVY_4cyc, FalkorReadIncLd], (instregex "^LD4i(8|16|32)$")>; 8640b57cec5SDimitry Andricdef : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_1LD_4VXVY_4cyc, FalkorReadIncLd], 8650b57cec5SDimitry Andric (instregex "^LD4i(8|16|32)_POST$")>; 8660b57cec5SDimitry Andric 8670b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2LD_2VXVY_1none_4cyc, FalkorReadIncLd], 8680b57cec5SDimitry Andric (instregex "^LD3Threev(8b|4h|2s)$")>; 8690b57cec5SDimitry Andricdef : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_2LD_2VXVY_1none_4cyc, FalkorReadIncLd], 8700b57cec5SDimitry Andric (instregex "^LD3Threev(8b|4h|2s)_POST$")>; 8710b57cec5SDimitry Andric 8720b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2LD_2VXVY_2none_4cyc, FalkorReadIncLd], 8730b57cec5SDimitry Andric (instregex "^LD4Fourv(8b|4h|2s)$")>; 8740b57cec5SDimitry Andricdef : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_2LD_2VXVY_2none_4cyc, FalkorReadIncLd], 8750b57cec5SDimitry Andric (instregex "^LD4Fourv(8b|4h|2s)_POST$")>; 8760b57cec5SDimitry Andric 8770b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2LD_2VXVY_2LD_2VXVY_4cyc, FalkorReadIncLd], 8780b57cec5SDimitry Andric (instregex "^LD3Threev(16b|8h|4s)$")>; 8790b57cec5SDimitry Andric 8800b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2LD_2VXVY_2LD_2VXVY_4cyc, FalkorReadIncLd], 8810b57cec5SDimitry Andric (instregex "^LD4Fourv(16b|8h|4s)$")>; 8820b57cec5SDimitry Andric 8830b57cec5SDimitry Andricdef : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_2LD_2VXVY_1XYZ_2LD_2VXVY_4cyc, FalkorReadIncLd], 8840b57cec5SDimitry Andric (instregex "^LD3Threev(16b|8h|4s)_POST$")>; 8850b57cec5SDimitry Andric 8860b57cec5SDimitry Andricdef : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_2LD_2VXVY_2LD_1XYZ_2VXVY_4cyc, FalkorReadIncLd], 8870b57cec5SDimitry Andric (instregex "^LD4Fourv(16b|8h|4s)_POST$")>; 8880b57cec5SDimitry Andric 8890b57cec5SDimitry Andric// Arithmetic and Logical Instructions 8900b57cec5SDimitry Andric// ----------------------------------------------------------------------------- 8910b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^(CCMN|CCMP)(W|X)(r|i)$")>; 8920b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^ADC(S)?(W|X)r$")>; 8930b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^ADD(S)?(W|X)r(r|i)$")>; 8940b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^(CSEL|CSINC|CSINV|CSNEG)(W|X)r$")>; 8950b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^AND(S)?(W|X)r(i|r|s)$")>; 8960b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^BIC(S)?(W|X)r(r|s)$")>; 8970b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^EON(W|X)r(r|s)$")>; 8980b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^EOR(W|X)r(i|r|s)$")>; 8990b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^ORN(W|X)r(r|s)$")>; 9000b57cec5SDimitry Andricdef : InstRW<[FalkorWr_ORRi], (instregex "^ORR(W|X)ri$")>; 9010b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^ORR(W|X)r(r|s)$")>; 9020b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^SBC(S)?(W|X)r$")>; 9030b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^SUB(S)?(W|X)r(r|i)$")>; 9040b57cec5SDimitry Andricdef : InstRW<[FalkorWr_ADDSUBsx], (instregex "^ADD(S)?(W|X)r(s|x|x64)$")>; 9050b57cec5SDimitry Andricdef : InstRW<[FalkorWr_ADDSUBsx], (instregex "^SUB(S)?(W|X)r(s|x|x64)$")>; 9060b57cec5SDimitry Andric 9070b57cec5SDimitry Andric// SIMD Miscellaneous Instructions 9080b57cec5SDimitry Andric// ----------------------------------------------------------------------------- 9090b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1GTOV_1cyc], (instregex "^DUP(v8i8|v4i16|v2i32)(gpr|lane)$")>; 9100b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^DUP(v16i8|v8i16)(gpr|lane)$")>; 91104eeddc0SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^DUP(i8|i16|i32|i64)$")>; 9120b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1GTOV_1cyc], (instregex "^INSv(i8|i16)(gpr|lane)$")>; 9130b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VTOG_1cyc], (instregex "^(S|U)MOVv.*$")>; 9145ffd83dbSDimitry Andricdef : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^(BIF|BIT|BSL|BSP)v8i8$")>; 9150b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_1cyc], (instrs EXTv8i8)>; 9160b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_0cyc], (instregex "(MOVI|MVNI)(D|v8b_ns|v2i32|v4i16|v2s_msl)$")>; // imm fwd 9170b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_1cyc], (instrs TBLv8i8One)>; 9180b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_1cyc], (instrs NOTv8i8)>; 9190b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^REV(16|32|64)v.*$")>; 9200b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^(TRN1|TRN2|ZIP1|UZP1|UZP2|ZIP2|XTN)(v2i32|v2i64|v4i16|v4i32|v8i8|v8i16|v16i8)$")>; 9210b57cec5SDimitry Andric 9220b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^(CLS|CLZ|CNT|RBIT)(v2i32|v4i16|v8i8)$")>; 9230b57cec5SDimitry Andric 9240b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "(S|U)QXTU?Nv.*$")>; 9250b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_3cyc], (instrs FRECPEv1i32, FRECPEv1i64, FRSQRTEv1i32, FRSQRTEv1i64, FRECPEv2f32, FRSQRTEv2f32)>; 9260b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_3cyc], (instrs FRECPXv1i32, FRECPXv1i64)>; 9270b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_3cyc], (instrs URECPEv2i32, URSQRTEv2i32)>; 9280b57cec5SDimitry Andric 9290b57cec5SDimitry Andricdef : InstRW<[FalkorWr_FMUL32_1VXVY_5cyc], 9300b57cec5SDimitry Andric (instrs FRECPS32, FRSQRTS32, FRECPSv2f32, FRSQRTSv2f32)>; 9310b57cec5SDimitry Andric 9320b57cec5SDimitry Andricdef : InstRW<[FalkorWr_FMUL64_1VXVY_6cyc], 9330b57cec5SDimitry Andric (instrs FRECPS64, FRSQRTS64)>; 9340b57cec5SDimitry Andric 9350b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1GTOV_1VXVY_2cyc], 9360b57cec5SDimitry Andric (instregex "^INSv(i32|i64)(gpr|lane)$")>; 9370b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2GTOV_1cyc], (instregex "^DUP(v4i32|v2i64)(gpr|lane)$")>; 9385ffd83dbSDimitry Andricdef : InstRW<[FalkorWr_2VXVY_1cyc], (instregex "^(BIF|BIT|BSL|BSP)v16i8$")>; 9390b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VXVY_1cyc], (instrs EXTv16i8)>; 9400b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VXVY_0cyc], (instregex "(MOVI|MVNI)(v2d_ns|v16b_ns|v4i32|v8i16|v4s_msl)$")>; // imm fwd 9410b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VXVY_1cyc], (instrs NOTv16i8)>; 9420b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VXVY_1cyc], (instrs TBLv16i8One)>; 9430b57cec5SDimitry Andric 9440b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^(CLS|CLZ|CNT|RBIT)(v4i32|v8i16|v16i8)$")>; 9450b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VXVY_3cyc], (instrs FRECPEv2f64, FRECPEv4f32, FRSQRTEv2f64, FRSQRTEv4f32)>; 9460b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VXVY_3cyc], (instrs URECPEv4i32, URSQRTEv4i32)>; 9470b57cec5SDimitry Andric 9480b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VXVY_4cyc], (instrs TBLv8i8Two)>; 9490b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VXVY_4cyc], (instregex "^TBX(v8|v16)i8One$")>; 9500b57cec5SDimitry Andric 9510b57cec5SDimitry Andricdef : InstRW<[FalkorWr_FMUL32_2VXVY_5cyc], 9520b57cec5SDimitry Andric (instrs FRECPSv4f32, FRSQRTSv4f32)>; 9530b57cec5SDimitry Andric 9540b57cec5SDimitry Andricdef : InstRW<[FalkorWr_FMUL64_2VXVY_6cyc], 9550b57cec5SDimitry Andric (instrs FRECPSv2f64, FRSQRTSv2f64)>; 9560b57cec5SDimitry Andric 9570b57cec5SDimitry Andricdef : InstRW<[FalkorWr_3VXVY_5cyc], (instregex "^TBL(v8i8Three|v16i8Two)$")>; 9580b57cec5SDimitry Andricdef : InstRW<[FalkorWr_3VXVY_5cyc], (instregex "^TBX(v8i8Two|v16i8Two)$")>; 9590b57cec5SDimitry Andric 9600b57cec5SDimitry Andricdef : InstRW<[FalkorWr_4VXVY_6cyc], (instregex "^TBL(v8i8Four|v16i8Three)$")>; 9610b57cec5SDimitry Andricdef : InstRW<[FalkorWr_4VXVY_6cyc], (instregex "^TBX(v8i8Three|v16i8Three)$")>; 9620b57cec5SDimitry Andric 9630b57cec5SDimitry Andricdef : InstRW<[FalkorWr_5VXVY_7cyc], (instrs TBLv16i8Four)>; 9640b57cec5SDimitry Andricdef : InstRW<[FalkorWr_5VXVY_7cyc], (instregex "^TBX(v8i8Four|v16i8Four)$")>; 9650b57cec5SDimitry Andric 9660b57cec5SDimitry Andric// SIMD Store Instructions 9670b57cec5SDimitry Andric// ----------------------------------------------------------------------------- 9680b57cec5SDimitry Andric 9690b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VSD_1ST_0cyc, ReadDefault, FalkorReadIncSt], 9700b57cec5SDimitry Andric (instregex "^STR(Q|D|S|H|B)ui$")>; 9710b57cec5SDimitry Andricdef : InstRW<[FalkorWr_StInc_none_2cyc, FalkorWr_1VSD_1ST_0cyc, ReadDefault, FalkorReadIncSt], 9720b57cec5SDimitry Andric (instregex "^STR(Q|D|S|H|B)(post|pre)$")>; 9730b57cec5SDimitry Andricdef : InstRW<[FalkorWr_STRVro, ReadDefault, FalkorReadIncSt], 9740b57cec5SDimitry Andric (instregex "^STR(D|S|H|B)ro(W|X)$")>; 9750b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VSD_2ST_0cyc, ReadDefault, ReadDefault, FalkorReadIncSt], 9760b57cec5SDimitry Andric (instregex "^STPQi$")>; 9770b57cec5SDimitry Andricdef : InstRW<[FalkorWr_StInc_none_2cyc, FalkorWr_2VSD_2ST_0cyc, ReadDefault, ReadDefault, FalkorReadIncSt], 9780b57cec5SDimitry Andric (instregex "^STPQ(post|pre)$")>; 9790b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VSD_1ST_0cyc, ReadDefault, ReadDefault, FalkorReadIncSt], 9800b57cec5SDimitry Andric (instregex "^STP(D|S)(i)$")>; 9810b57cec5SDimitry Andricdef : InstRW<[FalkorWr_StInc_none_2cyc, FalkorWr_1VSD_1ST_0cyc, ReadDefault, ReadDefault, FalkorReadIncSt], 9820b57cec5SDimitry Andric (instregex "^STP(D|S)(post|pre)$")>; 9830b57cec5SDimitry Andricdef : InstRW<[FalkorWr_STRQro, ReadDefault, FalkorReadIncSt], 9840b57cec5SDimitry Andric (instregex "^STRQro(W|X)$")>; 9850b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VSD_1ST_0cyc, ReadDefault, FalkorReadIncSt], 9860b57cec5SDimitry Andric (instregex "^STUR(Q|D|S|B|H)i$")>; 9870b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VSD_1ST_0cyc, ReadDefault, ReadDefault, FalkorReadIncSt], 9880b57cec5SDimitry Andric (instrs STNPDi, STNPSi)>; 9890b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VSD_2ST_0cyc, ReadDefault, ReadDefault, FalkorReadIncSt], 9900b57cec5SDimitry Andric (instrs STNPQi)>; 9910b57cec5SDimitry Andric 9920b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VSD_1ST_0cyc, ReadDefault, FalkorReadIncSt], 9930b57cec5SDimitry Andric (instregex "^ST1(One(v8b|v4h|v2s|v1d)|(i8|i16|i32|i64)|One(v16b|v8h|v4s|v2d)|Two(v8b|v4h|v2s|v1d))$")>; 9940b57cec5SDimitry Andricdef : InstRW<[FalkorWr_StInc_none_2cyc, FalkorWr_1VSD_1ST_0cyc, ReadDefault, FalkorReadIncSt], 9950b57cec5SDimitry Andric (instregex "^ST1(One(v8b|v4h|v2s|v1d)_POST|(i8|i16|i32|i64)_POST)$")>; 9960b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VSD_1ST_0cyc, ReadDefault, FalkorReadIncSt], 9970b57cec5SDimitry Andric (instregex "^ST2(Two(v8b|v4h|v2s)|(i8|i16|i32|i64))$")>; 9980b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1XYZ_1cyc, FalkorWr_1VSD_1ST_0cyc, ReadDefault, FalkorReadIncSt], 9990b57cec5SDimitry Andric (instregex "^ST1(One(v16b|v8h|v4s|v2d)|Two(v8b|v4h|v2s|v1d))_POST$")>; 10000b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1XYZ_1cyc, FalkorWr_1VSD_1ST_0cyc, ReadDefault, FalkorReadIncSt], 10010b57cec5SDimitry Andric (instregex "^ST2(Two(v8b|v4h|v2s)|(i8|i16|i32|i64))_POST$")>; 10020b57cec5SDimitry Andric 10030b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VSD_2ST_0cyc, ReadDefault, FalkorReadIncSt], 10040b57cec5SDimitry Andric (instregex "^ST1(Two(v16b|v8h|v4s|v2d)|(Three|Four)(v8b|v4h|v2s|v1d))$")>; 10050b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VSD_2ST_0cyc, ReadDefault, FalkorReadIncSt], 10060b57cec5SDimitry Andric (instregex "^ST2Two(v16b|v8h|v4s|v2d)$")>; 10070b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VSD_2ST_0cyc, ReadDefault, FalkorReadIncSt], 10080b57cec5SDimitry Andric (instregex "^ST3(i8|i16|i32|i64)$")>; 10090b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VSD_2ST_0cyc, ReadDefault, FalkorReadIncSt], 10100b57cec5SDimitry Andric (instregex "^ST4(i8|i16|i32|i64)$")>; 10110b57cec5SDimitry Andric// FIXME: This is overly conservative in the imm POST case (no XYZ used in that case). 10120b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1XYZ_1cyc, FalkorWr_2VSD_2ST_0cyc, ReadDefault, FalkorReadIncSt], 10130b57cec5SDimitry Andric (instregex "^ST1(Two(v16b|v8h|v4s|v2d)|(Three|Four)(v8b|v4h|v2s|v1d))_POST$")>; 10140b57cec5SDimitry Andric// FIXME: This is overly conservative in the imm POST case (no XYZ used in that case). 10150b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1XYZ_1cyc, FalkorWr_2VSD_2ST_0cyc, ReadDefault, FalkorReadIncSt], 10160b57cec5SDimitry Andric (instregex "^ST2Two(v16b|v8h|v4s|v2d)_POST$")>; 10170b57cec5SDimitry Andric// FIXME: This is overly conservative in the imm POST case (no XYZ used in that case). 10180b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1XYZ_1cyc, FalkorWr_2VSD_2ST_0cyc, ReadDefault, FalkorReadIncSt], 10190b57cec5SDimitry Andric (instregex "^ST3(i8|i16|i32|i64)_POST$")>; 10200b57cec5SDimitry Andric// FIXME: This is overly conservative in the imm POST case (no XYZ used in that case). 10210b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1XYZ_1cyc, FalkorWr_2VSD_2ST_0cyc, ReadDefault, FalkorReadIncSt], 10220b57cec5SDimitry Andric (instregex "^ST4(i8|i16|i32|i64)_POST$")>; 10230b57cec5SDimitry Andric 10240b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_2ST_2VSD_0cyc, ReadDefault, FalkorReadIncSt], 10250b57cec5SDimitry Andric (instregex "^ST3Three(v8b|v4h|v2s)$")>; 10260b57cec5SDimitry Andric// FIXME: This is overly conservative in the imm POST case (no XYZ used in that case). 10270b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1XYZ_1cyc, FalkorWr_1VXVY_2ST_2VSD_0cyc, ReadDefault, FalkorReadIncSt], 10280b57cec5SDimitry Andric (instregex "^ST3Three(v8b|v4h|v2s)_POST$")>; 10290b57cec5SDimitry Andric 10300b57cec5SDimitry Andricdef : InstRW<[FalkorWr_3VSD_3ST_0cyc, ReadDefault, FalkorReadIncSt], 10310b57cec5SDimitry Andric (instregex "^ST1Three(v16b|v8h|v4s|v2d)$")>; 10320b57cec5SDimitry Andricdef : InstRW<[FalkorWr_3VSD_3ST_0cyc, ReadDefault, FalkorReadIncSt], 10330b57cec5SDimitry Andric (instrs ST3Threev2d)>; 10340b57cec5SDimitry Andric// FIXME: This is overly conservative in the imm POST case (no XYZ used in that case). 10350b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1XYZ_1cyc, FalkorWr_3VSD_3ST_0cyc, ReadDefault, FalkorReadIncSt], 10360b57cec5SDimitry Andric (instregex "^ST1Three(v16b|v8h|v4s|v2d)_POST$")>; 10370b57cec5SDimitry Andric// FIXME: This is overly conservative in the imm POST case (no XYZ used in that case). 10380b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1XYZ_1cyc, FalkorWr_3VSD_3ST_0cyc, ReadDefault, FalkorReadIncSt], 10390b57cec5SDimitry Andric (instrs ST3Threev2d_POST)>; 10400b57cec5SDimitry Andric 10410b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VXVY_2ST_2VSD_0cyc, ReadDefault, FalkorReadIncSt], 10420b57cec5SDimitry Andric (instregex "^ST4Four(v8b|v4h|v2s)$")>; 10430b57cec5SDimitry Andric// FIXME: This is overly conservative in the imm POST case (no XYZ used in that case). 10440b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1XYZ_1cyc, FalkorWr_2VXVY_2ST_2VSD_0cyc, ReadDefault, FalkorReadIncSt], 10450b57cec5SDimitry Andric (instregex "^ST4Four(v8b|v4h|v2s)_POST$")>; 10460b57cec5SDimitry Andric 10470b57cec5SDimitry Andricdef : InstRW<[FalkorWr_4VSD_4ST_0cyc, ReadDefault, FalkorReadIncSt], 10480b57cec5SDimitry Andric (instregex "^ST1Four(v16b|v8h|v4s|v2d)$")>; 10490b57cec5SDimitry Andricdef : InstRW<[FalkorWr_4VSD_4ST_0cyc, ReadDefault, FalkorReadIncSt], 10500b57cec5SDimitry Andric (instrs ST4Fourv2d)>; 10510b57cec5SDimitry Andric// FIXME: This is overly conservative in the imm POST case (no XYZ used in that case). 10520b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1XYZ_1cyc, FalkorWr_4VSD_4ST_0cyc, ReadDefault, FalkorReadIncSt], 10530b57cec5SDimitry Andric (instregex "^ST1Four(v16b|v8h|v4s|v2d)_POST$")>; 10540b57cec5SDimitry Andric// FIXME: This is overly conservative in the imm POST case (no XYZ used in that case). 10550b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1XYZ_1cyc, FalkorWr_4VSD_4ST_0cyc, ReadDefault, FalkorReadIncSt], 10560b57cec5SDimitry Andric (instrs ST4Fourv2d_POST)>; 10570b57cec5SDimitry Andric 10580b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VXVY_4ST_4VSD_0cyc, ReadDefault, FalkorReadIncSt], 10590b57cec5SDimitry Andric (instregex "^ST3Three(v16b|v8h|v4s)$")>; 10600b57cec5SDimitry Andric// FIXME: This is overly conservative in the imm POST case (no XYZ used in that case). 10610b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1XYZ_1cyc, FalkorWr_2VXVY_4ST_4VSD_0cyc, ReadDefault, FalkorReadIncSt], 10620b57cec5SDimitry Andric (instregex "^ST3Three(v16b|v8h|v4s)_POST$")>; 10630b57cec5SDimitry Andric 10640b57cec5SDimitry Andricdef : InstRW<[FalkorWr_4VXVY_4ST_4VSD_0cyc, ReadDefault, FalkorReadIncSt], 10650b57cec5SDimitry Andric (instregex "^ST4Four(v16b|v8h|v4s)$")>; 10660b57cec5SDimitry Andric// FIXME: This is overly conservative in the imm POST case (no XYZ used in that case). 10670b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1XYZ_1cyc, FalkorWr_4VXVY_4ST_4VSD_0cyc, ReadDefault, FalkorReadIncSt], 10680b57cec5SDimitry Andric (instregex "^ST4Four(v16b|v8h|v4s)_POST$")>; 10690b57cec5SDimitry Andric 10700b57cec5SDimitry Andric// Branch Instructions 10710b57cec5SDimitry Andric// ----------------------------------------------------------------------------- 10720b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1none_0cyc], (instrs B, TCRETURNdi)>; 10730b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1Z_0cyc], (instregex "^(BR|RET|(CBZ|CBNZ|TBZ|TBNZ)(W|X))$")>; 10740b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1Z_0cyc], (instrs RET_ReallyLR, TCRETURNri)>; 10750b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1ZB_0cyc], (instrs Bcc)>; 10760b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1XYZB_0cyc], (instrs BL)>; 10770b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1Z_1XY_0cyc], (instrs BLR)>; 10780b57cec5SDimitry Andric 10790b57cec5SDimitry Andric// Cryptography Extensions 10800b57cec5SDimitry Andric// ----------------------------------------------------------------------------- 10810b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_1cyc], (instrs SHA1Hrr)>; 10820b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_2cyc], (instrs AESIMCrr, AESMCrr)>; 10830b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VXVY_3cyc], (instrs AESDrr, AESErr)>; 10840b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VXVY_2cyc], (instrs SHA1SU0rrr, SHA1SU1rr, SHA256SU0rr)>; 10850b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VX_1VY_4cyc], (instregex "^SHA1(C|M|P)rrr$")>; 10860b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VX_1VY_5cyc], (instrs SHA256H2rrr, SHA256Hrrr)>; 10870b57cec5SDimitry Andricdef : InstRW<[FalkorWr_4VXVY_3cyc], (instrs SHA256SU1rrr)>; 10880b57cec5SDimitry Andric 10890b57cec5SDimitry Andric// FP Load Instructions 10900b57cec5SDimitry Andric// ----------------------------------------------------------------------------- 10910b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1LD_3cyc, FalkorReadIncLd], 10920b57cec5SDimitry Andric (instregex "^LDR((Q|D|S|H|B)ui|(Q|D|S)l)$")>; 10930b57cec5SDimitry Andricdef : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_1LD_3cyc, FalkorReadIncLd], 10940b57cec5SDimitry Andric (instregex "^LDR(Q|D|S|H|B)(post|pre)$")>; 10950b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1LD_3cyc, FalkorReadIncLd], 10960b57cec5SDimitry Andric (instregex "^LDUR(Q|D|S|H|B)i$")>; 10970b57cec5SDimitry Andricdef : InstRW<[FalkorWr_LDRro, FalkorReadIncLd], 10980b57cec5SDimitry Andric (instregex "^LDR(Q|D|H|S|B)ro(W|X)$")>; 10990b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2LD_3cyc, FalkorWr_none_3cyc, FalkorReadIncLd], 11000b57cec5SDimitry Andric (instrs LDNPQi)>; 11010b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2LD_3cyc, FalkorWr_none_3cyc, FalkorReadIncLd], 11020b57cec5SDimitry Andric (instrs LDPQi)>; 11030b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1LD_1none_3cyc, FalkorWr_none_3cyc, FalkorReadIncLd], 11040b57cec5SDimitry Andric (instregex "LDNP(D|S)i$")>; 11050b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1LD_1none_3cyc, FalkorWr_none_3cyc, FalkorReadIncLd], 11060b57cec5SDimitry Andric (instregex "LDP(D|S)i$")>; 11070b57cec5SDimitry Andricdef : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_1LD_1none_3cyc, FalkorWr_none_3cyc, FalkorReadIncLd], 11080b57cec5SDimitry Andric (instregex "LDP(D|S)(pre|post)$")>; 11090b57cec5SDimitry Andricdef : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_2LD_3cyc, FalkorWr_none_3cyc, FalkorReadIncLd], 11100b57cec5SDimitry Andric (instregex "^LDPQ(pre|post)$")>; 11110b57cec5SDimitry Andric 11120b57cec5SDimitry Andric// FP Data Processing Instructions 11130b57cec5SDimitry Andric// ----------------------------------------------------------------------------- 11140b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^FCCMP(E)?(S|D)rr$")>; 11150b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^FCMP(E)?(S|D)r(r|i)$")>; 11160b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VTOG_1cyc], (instregex "^FCVT(A|M|N|P|Z)(S|U)U(W|X)(S|D)r$")>; 11170b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^(FABS|FNEG)(S|D)r$")>; 11180b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^FCSEL(S|D)rrr$")>; 11190b57cec5SDimitry Andric 11200b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^F(MAX|MIN)(NM)?(S|D)rr$")>; 11210b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^F(MAX|MIN)(NM)?Pv2i(32|64)p$")>; 11220b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_2cyc], (instrs FCVTSHr, FCVTDHr)>; 11230b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^FRINT(A|I|M|N|P|X|Z)(S|D)r$")>; 11240b57cec5SDimitry Andric 11250b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^FABD(32|64)$")>; 11260b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(FADD|FSUB)(S|D)rr$")>; 11270b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_3cyc], (instrs FCVTHSr, FCVTHDr)>; 11280b57cec5SDimitry Andric 11290b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_4cyc], (instrs FCVTSDr, FCVTDSr)>; 11300b57cec5SDimitry Andric 11310b57cec5SDimitry Andricdef : InstRW<[FalkorWr_FMUL32_1VXVY_5cyc], 11320b57cec5SDimitry Andric (instregex "^F(N)?MULSrr$")>; 11330b57cec5SDimitry Andric 11340b57cec5SDimitry Andricdef : InstRW<[FalkorWr_FMUL64_1VXVY_6cyc], 11350b57cec5SDimitry Andric (instregex "^F(N)?MULDrr$")>; 11360b57cec5SDimitry Andric 11370b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VX_1VY_10cyc],(instrs FDIVSrr)>; 11380b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VX_1VY_14cyc],(instrs FDIVDrr)>; 11390b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VX_1VY_12cyc],(instrs FSQRTSr)>; 11400b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VX_1VY_21cyc],(instrs FSQRTDr)>; 11410b57cec5SDimitry Andric 11420b57cec5SDimitry Andricdef : InstRW<[FalkorWr_FMUL32_1VXVY_5cyc, ReadDefault, ReadDefault, FalkorReadFMA32], 11430b57cec5SDimitry Andric (instregex "^F(N)?M(ADD|SUB)Srrr$")>; 11440b57cec5SDimitry Andricdef : InstRW<[FalkorWr_FMUL64_1VXVY_6cyc, ReadDefault, ReadDefault, FalkorReadFMA64], 11450b57cec5SDimitry Andric (instregex "^F(N)?M(ADD|SUB)Drrr$")>; 11460b57cec5SDimitry Andric 11470b57cec5SDimitry Andric// FP Miscellaneous Instructions 11480b57cec5SDimitry Andric// ----------------------------------------------------------------------------- 11490b57cec5SDimitry Andricdef : InstRW<[FalkorWr_FMOV], (instregex "^FMOV(WS|XD|XDHigh)r$")>; 11500b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1GTOV_0cyc], (instregex "^FMOV(S|D)i$")>; // imm fwd 11510b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VTOG_1cyc], (instregex "^FCVTZ(S|U)S(W|X)(D|S)ri$")>; 11520b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VTOG_1cyc], (instregex "^FCVTZ(S|U)(d|s)$")>; 11530b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VTOG_1cyc], (instregex "^FMOV(SW|DX|DXHigh)r$")>; 11540b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_0cyc], (instregex "^FMOV(Sr|Dr|v.*_ns)$")>; // imm fwd 11550b57cec5SDimitry Andric// FIXME: We are currently generating movi v0.2d, #0 for these, which is worse than fmov wzr/xzr 11560b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VXVY_0cyc], (instrs FMOVD0, FMOVS0)>; // imm fwd 11570b57cec5SDimitry Andric 11580b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1GTOV_4cyc], (instregex "^(S|U)CVTF(S|U)(W|X)(D|S)ri$")>; 11590b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1VXVY_4cyc], (instregex "^(S|U)CVTF(v1i32|v2i32|v1i64|v2f32|d|s)(_shift)?")>; 11600b57cec5SDimitry Andric 11610b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2VXVY_4cyc], (instregex "^(S|U)CVTF(v2i64|v4i32|v2f64|v4f32)(_shift)?")>; 11620b57cec5SDimitry Andric 11630b57cec5SDimitry Andric// Load Instructions 11640b57cec5SDimitry Andric// ----------------------------------------------------------------------------- 11650b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1ST_0cyc], (instrs PRFMui, PRFMl)>; 11660b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1ST_0cyc], (instrs PRFUMi)>; 11670b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1LD_3cyc, FalkorWr_none_3cyc, FalkorReadIncLd], 11680b57cec5SDimitry Andric (instregex "^LDNP(W|X)i$")>; 11690b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1LD_3cyc, FalkorWr_none_3cyc, FalkorReadIncLd], 11700b57cec5SDimitry Andric (instregex "^LDP(W|X)i$")>; 11710b57cec5SDimitry Andricdef : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_1LD_3cyc, FalkorWr_none_3cyc, FalkorReadIncLd], 11720b57cec5SDimitry Andric (instregex "^LDP(W|X)(post|pre)$")>; 11730b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1LD_3cyc, FalkorReadIncLd], 11740b57cec5SDimitry Andric (instregex "^LDR(BB|HH|W|X)ui$")>; 11750b57cec5SDimitry Andricdef : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_1LD_3cyc, FalkorReadIncLd], 11760b57cec5SDimitry Andric (instregex "^LDR(BB|HH|W|X)(post|pre)$")>; 11770b57cec5SDimitry Andricdef : InstRW<[FalkorWr_LDRro, FalkorReadIncLd], 11780b57cec5SDimitry Andric (instregex "^LDR(BB|HH|W|X)ro(W|X)$")>; 11790b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1LD_3cyc, FalkorReadIncLd], 11800b57cec5SDimitry Andric (instregex "^LDR(W|X)l$")>; 11810b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1LD_3cyc, FalkorReadIncLd], 11820b57cec5SDimitry Andric (instregex "^LDTR(B|H|W|X)i$")>; 11830b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1LD_3cyc, FalkorReadIncLd], 11840b57cec5SDimitry Andric (instregex "^LDUR(BB|HH|W|X)i$")>; 11850b57cec5SDimitry Andricdef : InstRW<[FalkorWr_PRFMro], (instregex "^PRFMro(W|X)$")>; 11860b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1LD_4cyc, FalkorWr_none_4cyc, FalkorReadIncLd], 11870b57cec5SDimitry Andric (instrs LDPSWi)>; 11880b57cec5SDimitry Andricdef : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_1LD_4cyc, FalkorWr_none_4cyc, FalkorReadIncLd], 11890b57cec5SDimitry Andric (instregex "^LDPSW(post|pre)$")>; 11900b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1LD_4cyc, FalkorReadIncLd], 11910b57cec5SDimitry Andric (instregex "^LDRS(BW|BX|HW|HX|W)ui$")>; 11920b57cec5SDimitry Andricdef : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_1LD_4cyc, FalkorReadIncLd], 11930b57cec5SDimitry Andric (instregex "^LDRS(BW|BX|HW|HX|W)(post|pre)$")>; 11940b57cec5SDimitry Andricdef : InstRW<[FalkorWr_LDRSro, FalkorReadIncLd], 11950b57cec5SDimitry Andric (instregex "^LDRS(BW|BX|HW|HX|W)ro(W|X)$")>; 11960b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1LD_4cyc, FalkorReadIncLd], 11970b57cec5SDimitry Andric (instrs LDRSWl)>; 11980b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1LD_4cyc, FalkorReadIncLd], 11990b57cec5SDimitry Andric (instregex "^LDTRS(BW|BX|HW|HX|W)i$")>; 12000b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1LD_4cyc, FalkorReadIncLd], 12010b57cec5SDimitry Andric (instregex "^LDURS(BW|BX|HW|HX|W)i$")>; 12020b57cec5SDimitry Andric 12030b57cec5SDimitry Andric// Miscellaneous Data-Processing Instructions 12040b57cec5SDimitry Andric// ----------------------------------------------------------------------------- 12050b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^(S|U)?BFM(W|X)ri$")>; 12060b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1X_2cyc], (instregex "^CRC32.*$")>; 12070b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1XYZ_2cyc], (instregex "^(CLS|CLZ|RBIT|REV|REV16|REV32)(W|X)r$")>; 12080b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2XYZ_2cyc], (instregex "^EXTR(W|X)rri$")>; 12090b57cec5SDimitry Andric 12100b57cec5SDimitry Andric// Divide and Multiply Instructions 12110b57cec5SDimitry Andric// ----------------------------------------------------------------------------- 12120b57cec5SDimitry Andricdef : InstRW<[FalkorWr_IMUL64_1X_4cyc, ReadDefault, ReadDefault, FalkorReadIMA64], 12130b57cec5SDimitry Andric (instregex "^(S|U)M(ADD|SUB)Lrrr$")>; 12140b57cec5SDimitry Andricdef : InstRW<[FalkorWr_IMUL32_1X_2cyc, ReadDefault, ReadDefault, FalkorReadIMA32], 12150b57cec5SDimitry Andric (instregex "^M(ADD|SUB)Wrrr$")>; 12160b57cec5SDimitry Andric 12170b57cec5SDimitry Andricdef : InstRW<[FalkorWr_IMUL64_1X_5cyc], (instregex "^(S|U)MULHrr$")>; 12180b57cec5SDimitry Andricdef : InstRW<[FalkorWr_IMUL64_1X_5cyc, ReadDefault, ReadDefault, FalkorReadIMA64], 12190b57cec5SDimitry Andric (instregex "^M(ADD|SUB)Xrrr$")>; 12200b57cec5SDimitry Andric 12210b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1X_1Z_8cyc], (instregex "^(S|U)DIVWr$")>; 12220b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1X_1Z_11cyc], (instregex "^(S|U)DIVXr$")>; 12230b57cec5SDimitry Andric 12240b57cec5SDimitry Andricdef : InstRW<[FalkorWr_VMUL32_2VXVY_4cyc], 12250b57cec5SDimitry Andric (instregex "^(S|U)MULLv.*$")>; 12260b57cec5SDimitry Andricdef : InstRW<[FalkorWr_VMUL32_2VXVY_4cyc, FalkorReadVMA], 12270b57cec5SDimitry Andric (instregex "^(S|U)(MLAL|MLSL)v.*$")>; 12280b57cec5SDimitry Andric 12290b57cec5SDimitry Andric// Move and Shift Instructions 12300b57cec5SDimitry Andric// ----------------------------------------------------------------------------- 12310b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^(LSLV|LSRV|ASRV|RORV)(W|X)r$")>; 12320b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1XYZ_0cyc], (instregex "^MOVK(W|X)i$")>; // imm fwd 12330b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1XYZB_0cyc], (instregex "^ADRP?$")>; // imm fwd 12340b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1XYZB_0cyc], (instregex "^MOVN(W|X)i$")>; // imm fwd 12350b57cec5SDimitry Andricdef : InstRW<[FalkorWr_MOVZ], (instregex "^MOVZ(W|X)i$")>; 12360b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1XYZ_0cyc], (instrs MOVi32imm, MOVi64imm)>; // imm fwd (approximation) 12370b57cec5SDimitry Andricdef : InstRW<[WriteSequence<[FalkorWr_1XYZ_1cyc, FalkorWr_1XYZ_1cyc]>], 12380b57cec5SDimitry Andric (instrs MOVaddr, MOVaddrBA, MOVaddrCP, MOVaddrEXT, MOVaddrJT, MOVaddrTLS)>; 12390b57cec5SDimitry Andricdef : InstRW<[WriteSequence<[FalkorWr_1LD_3cyc, FalkorWr_1XYZ_1cyc]>], 12400b57cec5SDimitry Andric (instrs LOADgot)>; 12410b57cec5SDimitry Andric 12420b57cec5SDimitry Andric// Other Instructions 12430b57cec5SDimitry Andric// ----------------------------------------------------------------------------- 12440b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1LD_0cyc], (instrs CLREX, DMB, DSB)>; 12450b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1none_0cyc], (instrs BRK, DCPS1, DCPS2, DCPS3, HINT, HLT, HVC, ISB, SMC, SVC)>; 12460b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1ST_0cyc], (instrs SYSxt, SYSLxt)>; 12470b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1Z_0cyc], (instrs MSRpstateImm1, MSRpstateImm4)>; 12480b57cec5SDimitry Andric 12490b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1LD_3cyc, FalkorReadIncLd], 12500b57cec5SDimitry Andric (instregex "^(LDAR(B|H|W|X)|LDAXR(B|H|W|X)|LDXR(B|H|W|X))$")>; 12510b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1LD_3cyc, FalkorWr_none_3cyc, FalkorReadIncLd], 12520b57cec5SDimitry Andric (instregex "^(LDAXP(W|X)|LDXP(W|X))$")>; 12530b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1LD_3cyc], (instrs MRS, MOVbaseTLS)>; 12540b57cec5SDimitry Andric 12550b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1LD_1Z_3cyc], (instrs DRPS)>; 12560b57cec5SDimitry Andric 12570b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1SD_1ST_0cyc], (instrs MSR)>; 12580b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1SD_1ST_0cyc, ReadDefault, ReadDefault, FalkorReadIncSt], 12590b57cec5SDimitry Andric (instrs STNPWi, STNPXi)>; 12600b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2LD_1Z_3cyc], (instrs ERET)>; 12610b57cec5SDimitry Andric 1262bdd1243dSDimitry Andric 1263bdd1243dSDimitry Andricdef : InstRW<[FalkorWr_1ST_1SD_1LD_3cyc], (instregex "^LDCLR(A|AL|L)?(B|H)?$")>; 12640b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1ST_1SD_1LD_0cyc, ReadDefault, FalkorReadIncSt], 12650b57cec5SDimitry Andric (instregex "^STLR(B|H|W|X)$")>; 12660b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1ST_1SD_1LD_0cyc, ReadDefault, ReadDefault, FalkorReadIncSt], 12670b57cec5SDimitry Andric (instregex "^STXP(W|X)$")>; 12680b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1ST_1SD_1LD_0cyc, ReadDefault, ReadDefault, FalkorReadIncSt], 12690b57cec5SDimitry Andric (instregex "^STXR(B|H|W|X)$")>; 12700b57cec5SDimitry Andric 12710b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2LD_1ST_1SD_3cyc, ReadDefault, ReadDefault, ReadDefault, FalkorReadIncSt], 12720b57cec5SDimitry Andric (instregex "^STLXP(W|X)$")>; 12730b57cec5SDimitry Andricdef : InstRW<[FalkorWr_2LD_1ST_1SD_3cyc, ReadDefault, ReadDefault, FalkorReadIncSt], 12740b57cec5SDimitry Andric (instregex "^STLXR(B|H|W|X)$")>; 12750b57cec5SDimitry Andric 12760b57cec5SDimitry Andric// Store Instructions 12770b57cec5SDimitry Andric// ----------------------------------------------------------------------------- 12780b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1SD_1ST_0cyc, ReadDefault, ReadDefault, FalkorReadIncSt], 12790b57cec5SDimitry Andric (instregex "^STP(W|X)i$")>; 12800b57cec5SDimitry Andricdef : InstRW<[FalkorWr_StInc_none_2cyc, FalkorWr_1SD_1ST_0cyc, ReadDefault, ReadDefault, FalkorReadIncSt], 12810b57cec5SDimitry Andric (instregex "^STP(W|X)(post|pre)$")>; 12820b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1SD_1ST_0cyc, ReadDefault, FalkorReadIncSt], 12830b57cec5SDimitry Andric (instregex "^STR(BB|HH|W|X)ui$")>; 12840b57cec5SDimitry Andricdef : InstRW<[FalkorWr_StInc_none_2cyc, FalkorWr_1SD_1ST_0cyc, ReadDefault, FalkorReadIncSt], 12850b57cec5SDimitry Andric (instregex "^STR(BB|HH|W|X)(post|pre)$")>; 12860b57cec5SDimitry Andricdef : InstRW<[FalkorWr_STRro, ReadDefault, FalkorReadIncSt], 12870b57cec5SDimitry Andric (instregex "^STR(BB|HH|W|X)ro(W|X)$")>; 12880b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1SD_1ST_0cyc, ReadDefault, FalkorReadIncSt], 12890b57cec5SDimitry Andric (instregex "^STTR(B|H|W|X)i$")>; 12900b57cec5SDimitry Andricdef : InstRW<[FalkorWr_1SD_1ST_0cyc, ReadDefault, FalkorReadIncSt], 12910b57cec5SDimitry Andric (instregex "^STUR(BB|HH|W|X)i$")>; 12920b57cec5SDimitry Andric 1293