106c3fb27SDimitry Andric//=- AArch64SchedNeoverseV1.td - NeoverseV1 Scheduling Model -*- tablegen -*-=// 206c3fb27SDimitry Andric// 306c3fb27SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 406c3fb27SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 506c3fb27SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 606c3fb27SDimitry Andric// 706c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 806c3fb27SDimitry Andric// 906c3fb27SDimitry Andric// This file defines the scheduling model for the Arm Neoverse V1 processors. 1006c3fb27SDimitry Andric// 1106c3fb27SDimitry Andric// References: 1206c3fb27SDimitry Andric// - "Arm Neoverse V1 Software Optimization Guide" 1306c3fb27SDimitry Andric// - "Arm Neoverse V1 Platform: Unleashing a new performance tier for Arm-based computing" 1406c3fb27SDimitry Andric// https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/neoverse-v1-platform-a-new-performance-tier-for-arm 1506c3fb27SDimitry Andric// - "Neoverse V1" 1606c3fb27SDimitry Andric// https://en.wikichip.org/wiki/arm_holdings/microarchitectures/neoverse_v1 1706c3fb27SDimitry Andric 1806c3fb27SDimitry Andric// 1906c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 2006c3fb27SDimitry Andric 2106c3fb27SDimitry Andricdef NeoverseV1Model : SchedMachineModel { 2206c3fb27SDimitry Andric let IssueWidth = 15; // Maximum micro-ops dispatch rate. 2306c3fb27SDimitry Andric let MicroOpBufferSize = 256; // Micro-op re-order buffer. 2406c3fb27SDimitry Andric let LoadLatency = 4; // Optimistic load latency. 2506c3fb27SDimitry Andric let MispredictPenalty = 11; // Cycles cost of branch mispredicted. 2606c3fb27SDimitry Andric let LoopMicroOpBufferSize = 16; // NOTE: Copied from Cortex-A57. 2706c3fb27SDimitry Andric let CompleteModel = 1; 2806c3fb27SDimitry Andric 2906c3fb27SDimitry Andric list<Predicate> UnsupportedFeatures = !listconcat(SVE2Unsupported.F, 3006c3fb27SDimitry Andric SMEUnsupported.F, 31*4c2d3b02SDimitry Andric [HasMTE, HasCPA, 32*4c2d3b02SDimitry Andric HasCSSC]); 3306c3fb27SDimitry Andric} 3406c3fb27SDimitry Andric 3506c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 3606c3fb27SDimitry Andric// Define each kind of processor resource and number available on Neoverse V1. 3706c3fb27SDimitry Andric// Instructions are first fetched and then decoded into internal macro-ops 3806c3fb27SDimitry Andric// (MOPs). From there, the MOPs proceed through register renaming and dispatch 3906c3fb27SDimitry Andric// stages. A MOP can be split into one or more micro-ops further down the 4006c3fb27SDimitry Andric// pipeline, after the decode stage. Once dispatched, micro-ops wait for their 4106c3fb27SDimitry Andric// operands and issue out-of-order to one of the issue pipelines. Each issue 4206c3fb27SDimitry Andric// pipeline can accept one micro-op per cycle. 4306c3fb27SDimitry Andric 4406c3fb27SDimitry Andriclet SchedModel = NeoverseV1Model in { 4506c3fb27SDimitry Andric 4606c3fb27SDimitry Andric// Define the issue ports. 4706c3fb27SDimitry Andricdef V1UnitB : ProcResource<2>; // Branch 0/1 4806c3fb27SDimitry Andricdef V1UnitS : ProcResource<2>; // Integer single cycle 0/1 4906c3fb27SDimitry Andricdef V1UnitM0 : ProcResource<1>; // Integer multicycle 0 5006c3fb27SDimitry Andricdef V1UnitM1 : ProcResource<1>; // Integer multicycle 1 5106c3fb27SDimitry Andricdef V1UnitL01 : ProcResource<2>; // Load/Store 0/1 5206c3fb27SDimitry Andricdef V1UnitL2 : ProcResource<1>; // Load 2 5306c3fb27SDimitry Andricdef V1UnitD : ProcResource<2>; // Store data 0/1 5406c3fb27SDimitry Andricdef V1UnitV0 : ProcResource<1>; // FP/ASIMD 0 5506c3fb27SDimitry Andricdef V1UnitV1 : ProcResource<1>; // FP/ASIMD 1 5606c3fb27SDimitry Andricdef V1UnitV2 : ProcResource<1>; // FP/ASIMD 2 5706c3fb27SDimitry Andricdef V1UnitV3 : ProcResource<1>; // FP/ASIMD 3 5806c3fb27SDimitry Andric 5906c3fb27SDimitry Andricdef V1UnitI : ProcResGroup<[V1UnitS, 6006c3fb27SDimitry Andric V1UnitM0, V1UnitM1]>; // Integer units 6106c3fb27SDimitry Andricdef V1UnitJ : ProcResGroup<[V1UnitS, V1UnitM0]>; // Integer 0-2 units 6206c3fb27SDimitry Andricdef V1UnitM : ProcResGroup<[V1UnitM0, V1UnitM1]>; // Integer multicycle units 6306c3fb27SDimitry Andricdef V1UnitL : ProcResGroup<[V1UnitL01, V1UnitL2]>; // Load units 6406c3fb27SDimitry Andricdef V1UnitV : ProcResGroup<[V1UnitV0, V1UnitV1, 6506c3fb27SDimitry Andric V1UnitV2, V1UnitV3]>; // FP/ASIMD units 6606c3fb27SDimitry Andricdef V1UnitV01 : ProcResGroup<[V1UnitV0, V1UnitV1]>; // FP/ASIMD 0/1 units 6706c3fb27SDimitry Andricdef V1UnitV02 : ProcResGroup<[V1UnitV0, V1UnitV2]>; // FP/ASIMD 0/2 units 6806c3fb27SDimitry Andricdef V1UnitV13 : ProcResGroup<[V1UnitV1, V1UnitV3]>; // FP/ASIMD 1/3 units 6906c3fb27SDimitry Andric 7006c3fb27SDimitry Andric// Define commonly used read types. 7106c3fb27SDimitry Andric 7206c3fb27SDimitry Andric// No generic forwarding is provided for these types. 7306c3fb27SDimitry Andricdef : ReadAdvance<ReadI, 0>; 7406c3fb27SDimitry Andricdef : ReadAdvance<ReadISReg, 0>; 7506c3fb27SDimitry Andricdef : ReadAdvance<ReadIEReg, 0>; 7606c3fb27SDimitry Andricdef : ReadAdvance<ReadIM, 0>; 7706c3fb27SDimitry Andricdef : ReadAdvance<ReadIMA, 0>; 7806c3fb27SDimitry Andricdef : ReadAdvance<ReadID, 0>; 7906c3fb27SDimitry Andricdef : ReadAdvance<ReadExtrHi, 0>; 8006c3fb27SDimitry Andricdef : ReadAdvance<ReadAdrBase, 0>; 8106c3fb27SDimitry Andricdef : ReadAdvance<ReadST, 0>; 8206c3fb27SDimitry Andricdef : ReadAdvance<ReadVLD, 0>; 8306c3fb27SDimitry Andric 8406c3fb27SDimitry Andricdef : WriteRes<WriteAtomic, []> { let Unsupported = 1; } 8506c3fb27SDimitry Andricdef : WriteRes<WriteBarrier, []> { let Latency = 1; } 8606c3fb27SDimitry Andricdef : WriteRes<WriteHint, []> { let Latency = 1; } 8706c3fb27SDimitry Andric 8806c3fb27SDimitry Andric 8906c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 9006c3fb27SDimitry Andric// Define generic 0 micro-op types 9106c3fb27SDimitry Andric 9206c3fb27SDimitry Andriclet Latency = 0, NumMicroOps = 0 in 9306c3fb27SDimitry Andricdef V1Write_0c_0Z : SchedWriteRes<[]>; 9406c3fb27SDimitry Andric 9506c3fb27SDimitry Andric 9606c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 9706c3fb27SDimitry Andric// Define generic 1 micro-op types 9806c3fb27SDimitry Andric 9906c3fb27SDimitry Andricdef V1Write_1c_1B : SchedWriteRes<[V1UnitB]> { let Latency = 1; } 10006c3fb27SDimitry Andricdef V1Write_1c_1I : SchedWriteRes<[V1UnitI]> { let Latency = 1; } 10106c3fb27SDimitry Andricdef V1Write_1c_1J : SchedWriteRes<[V1UnitJ]> { let Latency = 1; } 10206c3fb27SDimitry Andricdef V1Write_4c_1L : SchedWriteRes<[V1UnitL]> { let Latency = 4; } 10306c3fb27SDimitry Andricdef V1Write_6c_1L : SchedWriteRes<[V1UnitL]> { let Latency = 6; } 10406c3fb27SDimitry Andricdef V1Write_1c_1L01 : SchedWriteRes<[V1UnitL01]> { let Latency = 1; } 10506c3fb27SDimitry Andricdef V1Write_4c_1L01 : SchedWriteRes<[V1UnitL01]> { let Latency = 4; } 10606c3fb27SDimitry Andricdef V1Write_6c_1L01 : SchedWriteRes<[V1UnitL01]> { let Latency = 6; } 10706c3fb27SDimitry Andricdef V1Write_2c_1M : SchedWriteRes<[V1UnitM]> { let Latency = 2; } 10806c3fb27SDimitry Andricdef V1Write_3c_1M : SchedWriteRes<[V1UnitM]> { let Latency = 3; } 10906c3fb27SDimitry Andricdef V1Write_4c_1M : SchedWriteRes<[V1UnitM]> { let Latency = 4; } 11006c3fb27SDimitry Andricdef V1Write_1c_1M0 : SchedWriteRes<[V1UnitM0]> { let Latency = 1; } 11106c3fb27SDimitry Andricdef V1Write_2c_1M0 : SchedWriteRes<[V1UnitM0]> { let Latency = 2; } 11206c3fb27SDimitry Andricdef V1Write_3c_1M0 : SchedWriteRes<[V1UnitM0]> { let Latency = 3; } 11306c3fb27SDimitry Andricdef V1Write_5c_1M0 : SchedWriteRes<[V1UnitM0]> { let Latency = 5; } 11406c3fb27SDimitry Andricdef V1Write_12c5_1M0 : SchedWriteRes<[V1UnitM0]> { let Latency = 12; 1155f757f3fSDimitry Andric let ReleaseAtCycles = [5]; } 11606c3fb27SDimitry Andricdef V1Write_20c5_1M0 : SchedWriteRes<[V1UnitM0]> { let Latency = 20; 1175f757f3fSDimitry Andric let ReleaseAtCycles = [5]; } 11806c3fb27SDimitry Andricdef V1Write_2c_1V : SchedWriteRes<[V1UnitV]> { let Latency = 2; } 11906c3fb27SDimitry Andricdef V1Write_3c_1V : SchedWriteRes<[V1UnitV]> { let Latency = 3; } 12006c3fb27SDimitry Andricdef V1Write_4c_1V : SchedWriteRes<[V1UnitV]> { let Latency = 4; } 12106c3fb27SDimitry Andricdef V1Write_5c_1V : SchedWriteRes<[V1UnitV]> { let Latency = 5; } 12206c3fb27SDimitry Andricdef V1Write_2c_1V0 : SchedWriteRes<[V1UnitV0]> { let Latency = 2; } 12306c3fb27SDimitry Andricdef V1Write_3c_1V0 : SchedWriteRes<[V1UnitV0]> { let Latency = 3; } 12406c3fb27SDimitry Andricdef V1Write_4c_1V0 : SchedWriteRes<[V1UnitV0]> { let Latency = 4; } 12506c3fb27SDimitry Andricdef V1Write_6c_1V0 : SchedWriteRes<[V1UnitV0]> { let Latency = 6; } 12606c3fb27SDimitry Andricdef V1Write_10c7_1V0 : SchedWriteRes<[V1UnitV0]> { let Latency = 10; 1275f757f3fSDimitry Andric let ReleaseAtCycles = [7]; } 12806c3fb27SDimitry Andricdef V1Write_12c7_1V0 : SchedWriteRes<[V1UnitV0]> { let Latency = 12; 1295f757f3fSDimitry Andric let ReleaseAtCycles = [7]; } 13006c3fb27SDimitry Andricdef V1Write_13c10_1V0 : SchedWriteRes<[V1UnitV0]> { let Latency = 13; 1315f757f3fSDimitry Andric let ReleaseAtCycles = [10]; } 13206c3fb27SDimitry Andricdef V1Write_15c7_1V0 : SchedWriteRes<[V1UnitV0]> { let Latency = 15; 1335f757f3fSDimitry Andric let ReleaseAtCycles = [7]; } 13406c3fb27SDimitry Andricdef V1Write_16c7_1V0 : SchedWriteRes<[V1UnitV0]> { let Latency = 16; 1355f757f3fSDimitry Andric let ReleaseAtCycles = [7]; } 13606c3fb27SDimitry Andricdef V1Write_20c7_1V0 : SchedWriteRes<[V1UnitV0]> { let Latency = 20; 1375f757f3fSDimitry Andric let ReleaseAtCycles = [7]; } 13806c3fb27SDimitry Andricdef V1Write_2c_1V01 : SchedWriteRes<[V1UnitV01]> { let Latency = 2; } 13906c3fb27SDimitry Andricdef V1Write_3c_1V01 : SchedWriteRes<[V1UnitV01]> { let Latency = 3; } 14006c3fb27SDimitry Andricdef V1Write_4c_1V01 : SchedWriteRes<[V1UnitV01]> { let Latency = 4; } 14106c3fb27SDimitry Andricdef V1Write_5c_1V01 : SchedWriteRes<[V1UnitV01]> { let Latency = 5; } 14206c3fb27SDimitry Andricdef V1Write_3c_1V02 : SchedWriteRes<[V1UnitV02]> { let Latency = 3; } 14306c3fb27SDimitry Andricdef V1Write_4c_1V02 : SchedWriteRes<[V1UnitV02]> { let Latency = 4; } 14406c3fb27SDimitry Andricdef V1Write_7c7_1V02 : SchedWriteRes<[V1UnitV02]> { let Latency = 7; 1455f757f3fSDimitry Andric let ReleaseAtCycles = [7]; } 14606c3fb27SDimitry Andricdef V1Write_10c7_1V02 : SchedWriteRes<[V1UnitV02]> { let Latency = 10; 1475f757f3fSDimitry Andric let ReleaseAtCycles = [7]; } 14806c3fb27SDimitry Andricdef V1Write_13c5_1V02 : SchedWriteRes<[V1UnitV02]> { let Latency = 13; 1495f757f3fSDimitry Andric let ReleaseAtCycles = [5]; } 15006c3fb27SDimitry Andricdef V1Write_13c11_1V02 : SchedWriteRes<[V1UnitV02]> { let Latency = 13; 1515f757f3fSDimitry Andric let ReleaseAtCycles = [11]; } 15206c3fb27SDimitry Andricdef V1Write_15c7_1V02 : SchedWriteRes<[V1UnitV02]> { let Latency = 15; 1535f757f3fSDimitry Andric let ReleaseAtCycles = [7]; } 15406c3fb27SDimitry Andricdef V1Write_16c7_1V02 : SchedWriteRes<[V1UnitV02]> { let Latency = 16; 1555f757f3fSDimitry Andric let ReleaseAtCycles = [7]; } 15606c3fb27SDimitry Andricdef V1Write_2c_1V1 : SchedWriteRes<[V1UnitV1]> { let Latency = 2; } 15706c3fb27SDimitry Andricdef V1Write_3c_1V1 : SchedWriteRes<[V1UnitV1]> { let Latency = 3; } 15806c3fb27SDimitry Andricdef V1Write_4c_1V1 : SchedWriteRes<[V1UnitV1]> { let Latency = 4; } 15906c3fb27SDimitry Andricdef V1Write_2c_1V13 : SchedWriteRes<[V1UnitV13]> { let Latency = 2; } 16006c3fb27SDimitry Andricdef V1Write_4c_1V13 : SchedWriteRes<[V1UnitV13]> { let Latency = 4; } 16106c3fb27SDimitry Andric 16206c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 16306c3fb27SDimitry Andric// Define generic 2 micro-op types 16406c3fb27SDimitry Andric 16506c3fb27SDimitry Andriclet Latency = 1, NumMicroOps = 2 in 16606c3fb27SDimitry Andricdef V1Write_1c_1B_1S : SchedWriteRes<[V1UnitB, V1UnitS]>; 16706c3fb27SDimitry Andriclet Latency = 6, NumMicroOps = 2 in 16806c3fb27SDimitry Andricdef V1Write_6c_1B_1M0 : SchedWriteRes<[V1UnitB, V1UnitM0]>; 16906c3fb27SDimitry Andriclet Latency = 3, NumMicroOps = 2 in 17006c3fb27SDimitry Andricdef V1Write_3c_1I_1M : SchedWriteRes<[V1UnitI, V1UnitM]>; 17106c3fb27SDimitry Andriclet Latency = 5, NumMicroOps = 2 in 17206c3fb27SDimitry Andricdef V1Write_5c_1I_1L : SchedWriteRes<[V1UnitI, V1UnitL]>; 17306c3fb27SDimitry Andriclet Latency = 7, NumMicroOps = 2 in 17406c3fb27SDimitry Andricdef V1Write_7c_1I_1L : SchedWriteRes<[V1UnitI, V1UnitL]>; 17506c3fb27SDimitry Andriclet Latency = 6, NumMicroOps = 2 in 17606c3fb27SDimitry Andricdef V1Write_6c_2L : SchedWriteRes<[V1UnitL, V1UnitL]>; 17706c3fb27SDimitry Andriclet Latency = 6, NumMicroOps = 2 in 17806c3fb27SDimitry Andricdef V1Write_6c_1L_1M : SchedWriteRes<[V1UnitL, V1UnitM]>; 17906c3fb27SDimitry Andriclet Latency = 8, NumMicroOps = 2 in 18006c3fb27SDimitry Andricdef V1Write_8c_1L_1V : SchedWriteRes<[V1UnitL, V1UnitV]>; 18106c3fb27SDimitry Andriclet Latency = 9, NumMicroOps = 2 in 18206c3fb27SDimitry Andricdef V1Write_9c_1L_1V : SchedWriteRes<[V1UnitL, V1UnitV]>; 18306c3fb27SDimitry Andriclet Latency = 11, NumMicroOps = 2 in 18406c3fb27SDimitry Andricdef V1Write_11c_1L_1V : SchedWriteRes<[V1UnitL, V1UnitV]>; 18506c3fb27SDimitry Andriclet Latency = 1, NumMicroOps = 2 in 18606c3fb27SDimitry Andricdef V1Write_1c_1L01_1D : SchedWriteRes<[V1UnitL01, V1UnitD]>; 18706c3fb27SDimitry Andriclet Latency = 6, NumMicroOps = 2 in 18806c3fb27SDimitry Andricdef V1Write_6c_1L01_1S : SchedWriteRes<[V1UnitL01, V1UnitS]>; 18906c3fb27SDimitry Andriclet Latency = 7, NumMicroOps = 2 in 19006c3fb27SDimitry Andricdef V1Write_7c_1L01_1S : SchedWriteRes<[V1UnitL01, V1UnitS]>; 19106c3fb27SDimitry Andriclet Latency = 2, NumMicroOps = 2 in 19206c3fb27SDimitry Andricdef V1Write_2c_1L01_1V : SchedWriteRes<[V1UnitL01, V1UnitV]>; 19306c3fb27SDimitry Andriclet Latency = 4, NumMicroOps = 2 in 19406c3fb27SDimitry Andricdef V1Write_4c_1L01_1V : SchedWriteRes<[V1UnitL01, V1UnitV]>; 19506c3fb27SDimitry Andriclet Latency = 6, NumMicroOps = 2 in 19606c3fb27SDimitry Andricdef V1Write_6c_1L01_1V : SchedWriteRes<[V1UnitL01, V1UnitV]>; 19706c3fb27SDimitry Andriclet Latency = 2, NumMicroOps = 2 in 19806c3fb27SDimitry Andricdef V1Write_2c_1L01_1V01 : SchedWriteRes<[V1UnitL01, V1UnitV01]>; 19906c3fb27SDimitry Andriclet Latency = 4, NumMicroOps = 2 in 20006c3fb27SDimitry Andricdef V1Write_4c_1L01_1V01 : SchedWriteRes<[V1UnitL01, V1UnitV01]>; 20106c3fb27SDimitry Andriclet Latency = 2, NumMicroOps = 2 in 20206c3fb27SDimitry Andricdef V1Write_2c_2M0 : SchedWriteRes<[V1UnitM0, V1UnitM0]>; 20306c3fb27SDimitry Andriclet Latency = 3, NumMicroOps = 2 in 20406c3fb27SDimitry Andricdef V1Write_3c_2M0 : SchedWriteRes<[V1UnitM0, V1UnitM0]>; 20506c3fb27SDimitry Andriclet Latency = 9, NumMicroOps = 2 in 20606c3fb27SDimitry Andricdef V1Write_9c_1M0_1L : SchedWriteRes<[V1UnitM0, V1UnitL]>; 20706c3fb27SDimitry Andriclet Latency = 5, NumMicroOps = 2 in 20806c3fb27SDimitry Andricdef V1Write_5c_1M0_1V : SchedWriteRes<[V1UnitM0, V1UnitV]>; 20906c3fb27SDimitry Andriclet Latency = 4, NumMicroOps = 2 in 21006c3fb27SDimitry Andricdef V1Write_4c_1M0_1V0 : SchedWriteRes<[V1UnitM0, V1UnitV0]>; 21106c3fb27SDimitry Andriclet Latency = 7, NumMicroOps = 2 in 21206c3fb27SDimitry Andricdef V1Write_7c_1M0_1V0 : SchedWriteRes<[V1UnitM0, V1UnitV1]>; 21306c3fb27SDimitry Andriclet Latency = 5, NumMicroOps = 2 in 21406c3fb27SDimitry Andricdef V1Write_5c_1M0_1V01 : SchedWriteRes<[V1UnitM0, V1UnitV01]>; 21506c3fb27SDimitry Andriclet Latency = 6, NumMicroOps = 2 in 21606c3fb27SDimitry Andricdef V1Write_6c_1M0_1V1 : SchedWriteRes<[V1UnitM0, V1UnitV1]>; 21706c3fb27SDimitry Andriclet Latency = 9, NumMicroOps = 2 in 21806c3fb27SDimitry Andricdef V1Write_9c_1M0_1V1 : SchedWriteRes<[V1UnitM0, V1UnitV1]>; 21906c3fb27SDimitry Andriclet Latency = 4, NumMicroOps = 2 in 22006c3fb27SDimitry Andricdef V1Write_4c_2V : SchedWriteRes<[V1UnitV, V1UnitV]>; 22106c3fb27SDimitry Andriclet Latency = 8, NumMicroOps = 2 in 22206c3fb27SDimitry Andricdef V1Write_8c_1V_1V01 : SchedWriteRes<[V1UnitV, V1UnitV01]>; 22306c3fb27SDimitry Andriclet Latency = 4, NumMicroOps = 2 in 22406c3fb27SDimitry Andricdef V1Write_4c_2V0 : SchedWriteRes<[V1UnitV0, V1UnitV0]>; 22506c3fb27SDimitry Andriclet Latency = 5, NumMicroOps = 2 in 22606c3fb27SDimitry Andricdef V1Write_5c_2V0 : SchedWriteRes<[V1UnitV0, V1UnitV0]>; 22706c3fb27SDimitry Andriclet Latency = 2, NumMicroOps = 2 in 22806c3fb27SDimitry Andricdef V1Write_2c_2V01 : SchedWriteRes<[V1UnitV01, V1UnitV01]>; 22906c3fb27SDimitry Andriclet Latency = 4, NumMicroOps = 2 in 23006c3fb27SDimitry Andricdef V1Write_4c_2V01 : SchedWriteRes<[V1UnitV01, V1UnitV01]>; 23106c3fb27SDimitry Andriclet Latency = 4, NumMicroOps = 2 in 23206c3fb27SDimitry Andricdef V1Write_4c_2V02 : SchedWriteRes<[V1UnitV02, V1UnitV02]>; 23306c3fb27SDimitry Andriclet Latency = 6, NumMicroOps = 2 in 23406c3fb27SDimitry Andricdef V1Write_6c_2V02 : SchedWriteRes<[V1UnitV02, V1UnitV02]>; 23506c3fb27SDimitry Andriclet Latency = 4, NumMicroOps = 2 in 23606c3fb27SDimitry Andricdef V1Write_4c_1V13_1V : SchedWriteRes<[V1UnitV13, V1UnitV]>; 23706c3fb27SDimitry Andriclet Latency = 4, NumMicroOps = 2 in 23806c3fb27SDimitry Andricdef V1Write_4c_2V13 : SchedWriteRes<[V1UnitV13, V1UnitV13]>; 23906c3fb27SDimitry Andric 24006c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 24106c3fb27SDimitry Andric// Define generic 3 micro-op types 24206c3fb27SDimitry Andric 24306c3fb27SDimitry Andriclet Latency = 2, NumMicroOps = 3 in 24406c3fb27SDimitry Andricdef V1Write_2c_1I_1L01_1V01 : SchedWriteRes<[V1UnitI, V1UnitL01, V1UnitV01]>; 24506c3fb27SDimitry Andriclet Latency = 7, NumMicroOps = 3 in 24606c3fb27SDimitry Andricdef V1Write_7c_2M0_1V01 : SchedWriteRes<[V1UnitM0, V1UnitM0, V1UnitV01]>; 24706c3fb27SDimitry Andriclet Latency = 8, NumMicroOps = 3 in 24806c3fb27SDimitry Andricdef V1Write_8c_1L_2V : SchedWriteRes<[V1UnitL, V1UnitV, V1UnitV]>; 24906c3fb27SDimitry Andriclet Latency = 6, NumMicroOps = 3 in 25006c3fb27SDimitry Andricdef V1Write_6c_3L : SchedWriteRes<[V1UnitL, V1UnitL, V1UnitL]>; 25106c3fb27SDimitry Andriclet Latency = 2, NumMicroOps = 3 in 25206c3fb27SDimitry Andricdef V1Write_2c_1L01_1S_1V : SchedWriteRes<[V1UnitL01, V1UnitS, V1UnitV]>; 25306c3fb27SDimitry Andriclet Latency = 4, NumMicroOps = 3 in 25406c3fb27SDimitry Andricdef V1Write_4c_1L01_1S_1V : SchedWriteRes<[V1UnitL01, V1UnitS, V1UnitV]>; 25506c3fb27SDimitry Andriclet Latency = 2, NumMicroOps = 3 in 25606c3fb27SDimitry Andricdef V1Write_2c_2L01_1V01 : SchedWriteRes<[V1UnitL01, V1UnitL01, V1UnitV01]>; 25706c3fb27SDimitry Andriclet Latency = 6, NumMicroOps = 3 in 25806c3fb27SDimitry Andricdef V1Write_6c_3V : SchedWriteRes<[V1UnitV, V1UnitV, V1UnitV]>; 25906c3fb27SDimitry Andriclet Latency = 4, NumMicroOps = 3 in 26006c3fb27SDimitry Andricdef V1Write_4c_3V01 : SchedWriteRes<[V1UnitV01, V1UnitV01, V1UnitV01]>; 26106c3fb27SDimitry Andriclet Latency = 6, NumMicroOps = 3 in 26206c3fb27SDimitry Andricdef V1Write_6c_3V01 : SchedWriteRes<[V1UnitV01, V1UnitV01, V1UnitV01]>; 26306c3fb27SDimitry Andriclet Latency = 8, NumMicroOps = 3 in 26406c3fb27SDimitry Andricdef V1Write_8c_3V01 : SchedWriteRes<[V1UnitV01, V1UnitV01, V1UnitV01]>; 26506c3fb27SDimitry Andric 26606c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 26706c3fb27SDimitry Andric// Define generic 4 micro-op types 26806c3fb27SDimitry Andric 26906c3fb27SDimitry Andriclet Latency = 8, NumMicroOps = 4 in 27006c3fb27SDimitry Andricdef V1Write_8c_2M0_2V0 : SchedWriteRes<[V1UnitM0, V1UnitM0, 27106c3fb27SDimitry Andric V1UnitV0, V1UnitV0]>; 27206c3fb27SDimitry Andriclet Latency = 7, NumMicroOps = 4 in 27306c3fb27SDimitry Andricdef V1Write_7c_4L : SchedWriteRes<[V1UnitL, V1UnitL, V1UnitL, V1UnitL]>; 27406c3fb27SDimitry Andriclet Latency = 8, NumMicroOps = 4 in 27506c3fb27SDimitry Andricdef V1Write_8c_2L_2V : SchedWriteRes<[V1UnitL, V1UnitL, 27606c3fb27SDimitry Andric V1UnitV, V1UnitV]>; 27706c3fb27SDimitry Andriclet Latency = 9, NumMicroOps = 4 in 27806c3fb27SDimitry Andricdef V1Write_9c_2L_2V : SchedWriteRes<[V1UnitL, V1UnitL, 27906c3fb27SDimitry Andric V1UnitV, V1UnitV]>; 28006c3fb27SDimitry Andriclet Latency = 11, NumMicroOps = 4 in 28106c3fb27SDimitry Andricdef V1Write_11c_2L_2V : SchedWriteRes<[V1UnitL, V1UnitL, 28206c3fb27SDimitry Andric V1UnitV, V1UnitV]>; 28306c3fb27SDimitry Andriclet Latency = 10, NumMicroOps = 4 in 28406c3fb27SDimitry Andricdef V1Write_10c_2L01_2V : SchedWriteRes<[V1UnitL01, V1UnitL01, 28506c3fb27SDimitry Andric V1UnitV, V1UnitV]>; 28606c3fb27SDimitry Andriclet Latency = 2, NumMicroOps = 4 in 28706c3fb27SDimitry Andricdef V1Write_2c_2L01_2V01 : SchedWriteRes<[V1UnitL01, V1UnitL01, 28806c3fb27SDimitry Andric V1UnitV01, V1UnitV01]>; 28906c3fb27SDimitry Andriclet Latency = 4, NumMicroOps = 4 in 29006c3fb27SDimitry Andricdef V1Write_4c_2L01_2V01 : SchedWriteRes<[V1UnitL01, V1UnitL01, 29106c3fb27SDimitry Andric V1UnitV01, V1UnitV01]>; 29206c3fb27SDimitry Andriclet Latency = 8, NumMicroOps = 4 in 29306c3fb27SDimitry Andricdef V1Write_8c_2L01_2V01 : SchedWriteRes<[V1UnitL01, V1UnitL01, 29406c3fb27SDimitry Andric V1UnitV01, V1UnitV01]>; 29506c3fb27SDimitry Andriclet Latency = 9, NumMicroOps = 4 in 29606c3fb27SDimitry Andricdef V1Write_9c_2L01_2V01 : SchedWriteRes<[V1UnitL01, V1UnitL01, 29706c3fb27SDimitry Andric V1UnitV01, V1UnitV01]>; 29806c3fb27SDimitry Andriclet Latency = 10, NumMicroOps = 4 in 29906c3fb27SDimitry Andricdef V1Write_10c_2L01_2V01 : SchedWriteRes<[V1UnitL01, V1UnitL01, 30006c3fb27SDimitry Andric V1UnitV01, V1UnitV01]>; 30106c3fb27SDimitry Andriclet Latency = 10, NumMicroOps = 4 in 30206c3fb27SDimitry Andricdef V1Write_10c_1V_1V01_2V1 : SchedWriteRes<[V1UnitV, V1UnitV01, 30306c3fb27SDimitry Andric V1UnitV1, V1UnitV1]>; 30406c3fb27SDimitry Andriclet Latency = 12, NumMicroOps = 4 in 30506c3fb27SDimitry Andricdef V1Write_12c_1V_1V01_2V1 : SchedWriteRes<[V1UnitV, V1UnitV01, 30606c3fb27SDimitry Andric V1UnitV1, V1UnitV1]>; 30706c3fb27SDimitry Andriclet Latency = 6, NumMicroOps = 4 in 30806c3fb27SDimitry Andricdef V1Write_6c_4V0 : SchedWriteRes<[V1UnitV0, V1UnitV0, 30906c3fb27SDimitry Andric V1UnitV0, V1UnitV0]>; 31006c3fb27SDimitry Andriclet Latency = 12, NumMicroOps = 4 in 31106c3fb27SDimitry Andricdef V1Write_12c_4V01 : SchedWriteRes<[V1UnitV01, V1UnitV01, 31206c3fb27SDimitry Andric V1UnitV01, V1UnitV01]>; 31306c3fb27SDimitry Andriclet Latency = 6, NumMicroOps = 4 in 31406c3fb27SDimitry Andricdef V1Write_6c_4V02 : SchedWriteRes<[V1UnitV02, V1UnitV02]>; 31506c3fb27SDimitry Andric 31606c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 31706c3fb27SDimitry Andric// Define generic 5 micro-op types 31806c3fb27SDimitry Andric 31906c3fb27SDimitry Andriclet Latency = 8, NumMicroOps = 5 in 32006c3fb27SDimitry Andricdef V1Write_8c_2L_3V : SchedWriteRes<[V1UnitL, V1UnitL, 32106c3fb27SDimitry Andric V1UnitV, V1UnitV, V1UnitV]>; 32206c3fb27SDimitry Andriclet Latency = 14, NumMicroOps = 5 in 32306c3fb27SDimitry Andricdef V1Write_14c_1V_1V0_2V1_1V13 : SchedWriteRes<[V1UnitV, 32406c3fb27SDimitry Andric V1UnitV0, 32506c3fb27SDimitry Andric V1UnitV1, V1UnitV1, 32606c3fb27SDimitry Andric V1UnitV13]>; 32706c3fb27SDimitry Andriclet Latency = 9, NumMicroOps = 5 in 32806c3fb27SDimitry Andricdef V1Write_9c_1V_4V01 : SchedWriteRes<[V1UnitV, 32906c3fb27SDimitry Andric V1UnitV01, V1UnitV01, 33006c3fb27SDimitry Andric V1UnitV01, V1UnitV01]>; 33106c3fb27SDimitry Andriclet Latency = 6, NumMicroOps = 5 in 33206c3fb27SDimitry Andricdef V1Write_6c_5V01 : SchedWriteRes<[V1UnitV01, V1UnitV01, 33306c3fb27SDimitry Andric V1UnitV01, V1UnitV01, V1UnitV01]>; 33406c3fb27SDimitry Andric 33506c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 33606c3fb27SDimitry Andric// Define generic 6 micro-op types 33706c3fb27SDimitry Andric 33806c3fb27SDimitry Andriclet Latency = 6, NumMicroOps = 6 in 33906c3fb27SDimitry Andricdef V1Write_6c_3L_3V : SchedWriteRes<[V1UnitL, V1UnitL, V1UnitL, 34006c3fb27SDimitry Andric V1UnitV, V1UnitV, V1UnitV]>; 34106c3fb27SDimitry Andriclet Latency = 8, NumMicroOps = 6 in 34206c3fb27SDimitry Andricdef V1Write_8c_3L_3V : SchedWriteRes<[V1UnitL, V1UnitL, V1UnitL, 34306c3fb27SDimitry Andric V1UnitV, V1UnitV, V1UnitV]>; 34406c3fb27SDimitry Andriclet Latency = 2, NumMicroOps = 6 in 34506c3fb27SDimitry Andricdef V1Write_2c_3L01_3V01 : SchedWriteRes<[V1UnitL01, V1UnitL01, V1UnitL01, 34606c3fb27SDimitry Andric V1UnitV01, V1UnitV01, V1UnitV01]>; 34706c3fb27SDimitry Andriclet Latency = 5, NumMicroOps = 6 in 34806c3fb27SDimitry Andricdef V1Write_5c_3L01_3V01 : SchedWriteRes<[V1UnitL01, V1UnitL01, V1UnitL01, 34906c3fb27SDimitry Andric V1UnitV01, V1UnitV01, V1UnitV01]>; 35006c3fb27SDimitry Andriclet Latency = 6, NumMicroOps = 6 in 35106c3fb27SDimitry Andricdef V1Write_6c_3L01_3V01 : SchedWriteRes<[V1UnitL01, V1UnitL01, V1UnitL01, 35206c3fb27SDimitry Andric V1UnitV01, V1UnitV01, V1UnitV01]>; 35306c3fb27SDimitry Andriclet Latency = 11, NumMicroOps = 6 in 35406c3fb27SDimitry Andricdef V1Write_11c_3L01_3V01 : SchedWriteRes<[V1UnitL01, V1UnitL01, V1UnitL01, 35506c3fb27SDimitry Andric V1UnitV01, V1UnitV01, V1UnitV01]>; 35606c3fb27SDimitry Andriclet Latency = 11, NumMicroOps = 6 in 35706c3fb27SDimitry Andricdef V1Write_11c_1V_5V01 : SchedWriteRes<[V1UnitV, 35806c3fb27SDimitry Andric V1UnitV01, V1UnitV01, 35906c3fb27SDimitry Andric V1UnitV01, V1UnitV01, V1UnitV01]>; 36006c3fb27SDimitry Andriclet Latency = 13, NumMicroOps = 6 in 36106c3fb27SDimitry Andricdef V1Write_13c_6V01 : SchedWriteRes<[V1UnitV01, V1UnitV01, V1UnitV01, 36206c3fb27SDimitry Andric V1UnitV01, V1UnitV01, V1UnitV01]>; 36306c3fb27SDimitry Andric 36406c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 36506c3fb27SDimitry Andric// Define generic 7 micro-op types 36606c3fb27SDimitry Andric 36706c3fb27SDimitry Andriclet Latency = 8, NumMicroOps = 7 in 36806c3fb27SDimitry Andricdef V1Write_8c_3L_4V : SchedWriteRes<[V1UnitL, V1UnitL, V1UnitL, 36906c3fb27SDimitry Andric V1UnitV, V1UnitV, V1UnitV, V1UnitV]>; 37006c3fb27SDimitry Andriclet Latency = 8, NumMicroOps = 7 in 37106c3fb27SDimitry Andricdef V1Write_13c_3L01_1S_3V01 : SchedWriteRes<[V1UnitL01, V1UnitL01, V1UnitL01, 37206c3fb27SDimitry Andric V1UnitS, 37306c3fb27SDimitry Andric V1UnitV01, V1UnitV01, V1UnitV01]>; 37406c3fb27SDimitry Andric 37506c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 37606c3fb27SDimitry Andric// Define generic 8 micro-op types 37706c3fb27SDimitry Andric 37806c3fb27SDimitry Andriclet Latency = 9, NumMicroOps = 8 in 37906c3fb27SDimitry Andricdef V1Write_9c_4L_4V : SchedWriteRes<[V1UnitL, V1UnitL, 38006c3fb27SDimitry Andric V1UnitL, V1UnitL, 38106c3fb27SDimitry Andric V1UnitV, V1UnitV, 38206c3fb27SDimitry Andric V1UnitV, V1UnitV]>; 38306c3fb27SDimitry Andriclet Latency = 2, NumMicroOps = 8 in 38406c3fb27SDimitry Andricdef V1Write_2c_4L01_4V01 : SchedWriteRes<[V1UnitL01, V1UnitL01, 38506c3fb27SDimitry Andric V1UnitL01, V1UnitL01, 38606c3fb27SDimitry Andric V1UnitV01, V1UnitV01, 38706c3fb27SDimitry Andric V1UnitV01, V1UnitV01]>; 38806c3fb27SDimitry Andriclet Latency = 4, NumMicroOps = 8 in 38906c3fb27SDimitry Andricdef V1Write_4c_4L01_4V01 : SchedWriteRes<[V1UnitL01, V1UnitL01, 39006c3fb27SDimitry Andric V1UnitL01, V1UnitL01, 39106c3fb27SDimitry Andric V1UnitV01, V1UnitV01, 39206c3fb27SDimitry Andric V1UnitV01, V1UnitV01]>; 39306c3fb27SDimitry Andriclet Latency = 12, NumMicroOps = 8 in 39406c3fb27SDimitry Andricdef V1Write_12c_4L01_4V01 : SchedWriteRes<[V1UnitL01, V1UnitL01, 39506c3fb27SDimitry Andric V1UnitL01, V1UnitL01, 39606c3fb27SDimitry Andric V1UnitV01, V1UnitV01, 39706c3fb27SDimitry Andric V1UnitV01, V1UnitV01]>; 39806c3fb27SDimitry Andric 39906c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 40006c3fb27SDimitry Andric// Define generic 10 micro-op types 40106c3fb27SDimitry Andric 40206c3fb27SDimitry Andriclet Latency = 13, NumMicroOps = 10 in 40306c3fb27SDimitry Andricdef V1Write_13c_4L01_2S_4V01 : SchedWriteRes<[V1UnitL01, V1UnitL01, 40406c3fb27SDimitry Andric V1UnitL01, V1UnitL01, 40506c3fb27SDimitry Andric V1UnitS, V1UnitS, 40606c3fb27SDimitry Andric V1UnitV01, V1UnitV01, 40706c3fb27SDimitry Andric V1UnitV01, V1UnitV01]>; 40806c3fb27SDimitry Andriclet Latency = 7, NumMicroOps = 10 in 40906c3fb27SDimitry Andricdef V1Write_7c_5L01_5V : SchedWriteRes<[V1UnitL01, V1UnitL01, 41006c3fb27SDimitry Andric V1UnitL01, V1UnitL01, V1UnitL01, 41106c3fb27SDimitry Andric V1UnitV, V1UnitV, 41206c3fb27SDimitry Andric V1UnitV, V1UnitV, V1UnitV]>; 41306c3fb27SDimitry Andriclet Latency = 11, NumMicroOps = 10 in 41406c3fb27SDimitry Andricdef V1Write_11c_10V0 : SchedWriteRes<[V1UnitV0, 41506c3fb27SDimitry Andric V1UnitV0, V1UnitV0, V1UnitV0, 41606c3fb27SDimitry Andric V1UnitV0, V1UnitV0, V1UnitV0, 41706c3fb27SDimitry Andric V1UnitV0, V1UnitV0, V1UnitV0]>; 41806c3fb27SDimitry Andric 41906c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 42006c3fb27SDimitry Andric// Define generic 12 micro-op types 42106c3fb27SDimitry Andric 42206c3fb27SDimitry Andriclet Latency = 7, NumMicroOps = 12 in 42306c3fb27SDimitry Andricdef V1Write_7c_6L01_6V01 : SchedWriteRes<[V1UnitL01, V1UnitL01, V1UnitL01, 42406c3fb27SDimitry Andric V1UnitL01, V1UnitL01, V1UnitL01, 42506c3fb27SDimitry Andric V1UnitV01, V1UnitV01, V1UnitV01, 42606c3fb27SDimitry Andric V1UnitV01, V1UnitV01, V1UnitV01]>; 42706c3fb27SDimitry Andric 42806c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 42906c3fb27SDimitry Andric// Define generic 15 micro-op types 43006c3fb27SDimitry Andric 43106c3fb27SDimitry Andriclet Latency = 7, NumMicroOps = 15 in 43206c3fb27SDimitry Andricdef V1Write_7c_5L01_5S_5V : SchedWriteRes<[V1UnitL01, V1UnitL01, 43306c3fb27SDimitry Andric V1UnitL01, V1UnitL01, V1UnitL01, 43406c3fb27SDimitry Andric V1UnitS, V1UnitS, 43506c3fb27SDimitry Andric V1UnitS, V1UnitS, V1UnitS, 43606c3fb27SDimitry Andric V1UnitV, V1UnitV, 43706c3fb27SDimitry Andric V1UnitV, V1UnitV, V1UnitV]>; 43806c3fb27SDimitry Andric 43906c3fb27SDimitry Andric 44006c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 44106c3fb27SDimitry Andric// Define generic 18 micro-op types 44206c3fb27SDimitry Andric 44306c3fb27SDimitry Andriclet Latency = 19, NumMicroOps = 18 in 44406c3fb27SDimitry Andricdef V1Write_11c_9L01_9V : SchedWriteRes<[V1UnitL01, V1UnitL01, V1UnitL01, 44506c3fb27SDimitry Andric V1UnitL01, V1UnitL01, V1UnitL01, 44606c3fb27SDimitry Andric V1UnitL01, V1UnitL01, V1UnitL01, 44706c3fb27SDimitry Andric V1UnitV, V1UnitV, V1UnitV, 44806c3fb27SDimitry Andric V1UnitV, V1UnitV, V1UnitV, 44906c3fb27SDimitry Andric V1UnitV, V1UnitV, V1UnitV]>; 45006c3fb27SDimitry Andriclet Latency = 19, NumMicroOps = 18 in 45106c3fb27SDimitry Andricdef V1Write_19c_18V0 : SchedWriteRes<[V1UnitV0, V1UnitV0, V1UnitV0, 45206c3fb27SDimitry Andric V1UnitV0, V1UnitV0, V1UnitV0, 45306c3fb27SDimitry Andric V1UnitV0, V1UnitV0, V1UnitV0, 45406c3fb27SDimitry Andric V1UnitV0, V1UnitV0, V1UnitV0, 45506c3fb27SDimitry Andric V1UnitV0, V1UnitV0, V1UnitV0, 45606c3fb27SDimitry Andric V1UnitV0, V1UnitV0, V1UnitV0]>; 45706c3fb27SDimitry Andric 45806c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 45906c3fb27SDimitry Andric// Define generic 27 micro-op types 46006c3fb27SDimitry Andric 46106c3fb27SDimitry Andriclet Latency = 11, NumMicroOps = 27 in 46206c3fb27SDimitry Andricdef V1Write_11c_9L01_9S_9V : SchedWriteRes<[V1UnitL01, V1UnitL01, V1UnitL01, 46306c3fb27SDimitry Andric V1UnitL01, V1UnitL01, V1UnitL01, 46406c3fb27SDimitry Andric V1UnitL01, V1UnitL01, V1UnitL01, 46506c3fb27SDimitry Andric V1UnitS, V1UnitS, V1UnitS, 46606c3fb27SDimitry Andric V1UnitS, V1UnitS, V1UnitS, 46706c3fb27SDimitry Andric V1UnitS, V1UnitS, V1UnitS, 46806c3fb27SDimitry Andric V1UnitV, V1UnitV, V1UnitV, 46906c3fb27SDimitry Andric V1UnitV, V1UnitV, V1UnitV, 47006c3fb27SDimitry Andric V1UnitV, V1UnitV, V1UnitV]>; 47106c3fb27SDimitry Andric 47206c3fb27SDimitry Andric 47306c3fb27SDimitry Andric// Miscellaneous Instructions 47406c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 47506c3fb27SDimitry Andric 47606c3fb27SDimitry Andric// COPY 47706c3fb27SDimitry Andricdef : InstRW<[V1Write_1c_1I], (instrs COPY)>; 47806c3fb27SDimitry Andric 47906c3fb27SDimitry Andric// MSR 48006c3fb27SDimitry Andricdef : WriteRes<WriteSys, []> { let Latency = 1; } 48106c3fb27SDimitry Andric 48206c3fb27SDimitry Andric 48306c3fb27SDimitry Andric// Branch Instructions 48406c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 48506c3fb27SDimitry Andric 48606c3fb27SDimitry Andric// Branch, immed 48706c3fb27SDimitry Andric// Compare and branch 48806c3fb27SDimitry Andricdef : SchedAlias<WriteBr, V1Write_1c_1B>; 48906c3fb27SDimitry Andric 49006c3fb27SDimitry Andric// Branch, register 49106c3fb27SDimitry Andricdef : SchedAlias<WriteBrReg, V1Write_1c_1B>; 49206c3fb27SDimitry Andric 49306c3fb27SDimitry Andric// Branch and link, immed 49406c3fb27SDimitry Andric// Branch and link, register 49506c3fb27SDimitry Andricdef : InstRW<[V1Write_1c_1B_1S], (instrs BL, BLR)>; 49606c3fb27SDimitry Andric 49706c3fb27SDimitry Andric// Compare and branch 49806c3fb27SDimitry Andricdef : InstRW<[V1Write_1c_1B], (instregex "^[CT]BN?Z[XW]$")>; 49906c3fb27SDimitry Andric 50006c3fb27SDimitry Andric 50106c3fb27SDimitry Andric// Arithmetic and Logical Instructions 50206c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 50306c3fb27SDimitry Andric 50406c3fb27SDimitry Andric// ALU, basic 50506c3fb27SDimitry Andric// Conditional compare 50606c3fb27SDimitry Andric// Conditional select 50706c3fb27SDimitry Andric// Logical, basic 50806c3fb27SDimitry Andric// Address generation 50906c3fb27SDimitry Andric// Count leading 51006c3fb27SDimitry Andric// Reverse bits/bytes 51106c3fb27SDimitry Andric// Move immediate 51206c3fb27SDimitry Andricdef : SchedAlias<WriteI, V1Write_1c_1I>; 51306c3fb27SDimitry Andric 51406c3fb27SDimitry Andric// ALU, basic, flagset 51506c3fb27SDimitry Andricdef : InstRW<[V1Write_1c_1J], 51606c3fb27SDimitry Andric (instregex "^(ADD|SUB)S[WX]r[ir]$", 51706c3fb27SDimitry Andric "^(ADC|SBC)S[WX]r$", 51806c3fb27SDimitry Andric "^ANDS[WX]ri$", 51906c3fb27SDimitry Andric "^(AND|BIC)S[WX]rr$")>; 52006c3fb27SDimitry Andric 52106c3fb27SDimitry Andric// ALU, extend and shift 52206c3fb27SDimitry Andricdef : SchedAlias<WriteIEReg, V1Write_2c_1M>; 52306c3fb27SDimitry Andric 52406c3fb27SDimitry Andric// Arithmetic, LSL shift, shift <= 4 52506c3fb27SDimitry Andric// Arithmetic, LSR/ASR/ROR shift or LSL shift > 4 52606c3fb27SDimitry Andricdef V1WriteISReg : SchedWriteVariant< 52706c3fb27SDimitry Andric [SchedVar<IsCheapLSL, [V1Write_1c_1I]>, 52806c3fb27SDimitry Andric SchedVar<NoSchedPred, [V1Write_2c_1M]>]>; 52906c3fb27SDimitry Andricdef : SchedAlias<WriteISReg, V1WriteISReg>; 53006c3fb27SDimitry Andric 53106c3fb27SDimitry Andric// Arithmetic, flagset, LSL shift, shift <= 4 53206c3fb27SDimitry Andric// Arithmetic, flagset, LSR/ASR/ROR shift or LSL shift > 4 53306c3fb27SDimitry Andricdef V1WriteISRegS : SchedWriteVariant< 53406c3fb27SDimitry Andric [SchedVar<IsCheapLSL, [V1Write_1c_1J]>, 53506c3fb27SDimitry Andric SchedVar<NoSchedPred, [V1Write_2c_1M]>]>; 53606c3fb27SDimitry Andricdef : InstRW<[V1WriteISRegS], 53706c3fb27SDimitry Andric (instregex "^(ADD|SUB)S(([WX]r[sx])|Xrx64)$")>; 53806c3fb27SDimitry Andric 53906c3fb27SDimitry Andric// Logical, shift, no flagset 54006c3fb27SDimitry Andricdef : InstRW<[V1Write_1c_1I], (instregex "^(AND|BIC|EON|EOR|ORN|ORR)[WX]rs$")>; 54106c3fb27SDimitry Andric 54206c3fb27SDimitry Andric// Logical, shift, flagset 54306c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1M], (instregex "^(AND|BIC)S[WX]rs$")>; 54406c3fb27SDimitry Andric 54506c3fb27SDimitry Andric// Flag manipulation instructions 54606c3fb27SDimitry Andricdef : InstRW<[V1Write_1c_1J], (instrs SETF8, SETF16, RMIF, CFINV)>; 54706c3fb27SDimitry Andric 54806c3fb27SDimitry Andric 54906c3fb27SDimitry Andric// Divide and multiply instructions 55006c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 55106c3fb27SDimitry Andric 55206c3fb27SDimitry Andric// Divide 55306c3fb27SDimitry Andricdef : SchedAlias<WriteID32, V1Write_12c5_1M0>; 55406c3fb27SDimitry Andricdef : SchedAlias<WriteID64, V1Write_20c5_1M0>; 55506c3fb27SDimitry Andric 55606c3fb27SDimitry Andric// Multiply 55706c3fb27SDimitry Andric// Multiply accumulate 55806c3fb27SDimitry Andric// Multiply accumulate, long 55906c3fb27SDimitry Andric// Multiply long 56006c3fb27SDimitry Andricdef V1WriteIM : SchedWriteVariant< 56106c3fb27SDimitry Andric [SchedVar<NeoverseMULIdiomPred, [V1Write_2c_1M]>, 56206c3fb27SDimitry Andric SchedVar<NoSchedPred, [V1Write_2c_1M0]>]>; 56306c3fb27SDimitry Andricdef : SchedAlias<WriteIM32, V1WriteIM>; 56406c3fb27SDimitry Andricdef : SchedAlias<WriteIM64, V1WriteIM>; 56506c3fb27SDimitry Andric 56606c3fb27SDimitry Andric// Multiply high 56706c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1M, ReadIM, ReadIM], (instrs SMULHrr, UMULHrr)>; 56806c3fb27SDimitry Andric 56906c3fb27SDimitry Andric 57006c3fb27SDimitry Andric// Pointer Authentication Instructions (v8.3 PAC) 57106c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 57206c3fb27SDimitry Andric 57306c3fb27SDimitry Andric// Authenticate data address 57406c3fb27SDimitry Andric// Authenticate instruction address 57506c3fb27SDimitry Andric// Compute pointer authentication code for data address 57606c3fb27SDimitry Andric// Compute pointer authentication code, using generic key 57706c3fb27SDimitry Andric// Compute pointer authentication code for instruction address 57806c3fb27SDimitry Andricdef : InstRW<[V1Write_5c_1M0], (instregex "^AUT", 57906c3fb27SDimitry Andric "^PAC")>; 58006c3fb27SDimitry Andric 58106c3fb27SDimitry Andric// Branch and link, register, with pointer authentication 58206c3fb27SDimitry Andric// Branch, register, with pointer authentication 58306c3fb27SDimitry Andric// Branch, return, with pointer authentication 58406c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_1B_1M0], (instregex "^BL?RA[AB]Z?$", 58506c3fb27SDimitry Andric "^E?RETA[AB]$")>; 58606c3fb27SDimitry Andric 58706c3fb27SDimitry Andric// Load register, with pointer authentication 58806c3fb27SDimitry Andricdef : InstRW<[V1Write_9c_1M0_1L], (instregex "^LDRA[AB](indexed|writeback)")>; 58906c3fb27SDimitry Andric 59006c3fb27SDimitry Andric// Strip pointer authentication code 59106c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1M0], (instrs XPACD, XPACI, XPACLRI)>; 59206c3fb27SDimitry Andric 59306c3fb27SDimitry Andric 59406c3fb27SDimitry Andric// Miscellaneous data-processing instructions 59506c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 59606c3fb27SDimitry Andric 59706c3fb27SDimitry Andric// Bitfield extract, one reg 59806c3fb27SDimitry Andric// Bitfield extract, two regs 59906c3fb27SDimitry Andricdef V1WriteExtr : SchedWriteVariant< 60006c3fb27SDimitry Andric [SchedVar<IsRORImmIdiomPred, [V1Write_1c_1I]>, 60106c3fb27SDimitry Andric SchedVar<NoSchedPred, [V1Write_3c_1I_1M]>]>; 60206c3fb27SDimitry Andricdef : SchedAlias<WriteExtr, V1WriteExtr>; 60306c3fb27SDimitry Andric 60406c3fb27SDimitry Andric// Bitfield move, basic 60506c3fb27SDimitry Andric// Variable shift 60606c3fb27SDimitry Andricdef : SchedAlias<WriteIS, V1Write_1c_1I>; 60706c3fb27SDimitry Andric 60806c3fb27SDimitry Andric// Bitfield move, insert 60906c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1M], (instregex "^BFM[WX]ri$")>; 61006c3fb27SDimitry Andric 61106c3fb27SDimitry Andric// Move immediate 61206c3fb27SDimitry Andricdef : SchedAlias<WriteImm, V1Write_1c_1I>; 61306c3fb27SDimitry Andric 61406c3fb27SDimitry Andric 61506c3fb27SDimitry Andric// Load instructions 61606c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 61706c3fb27SDimitry Andric 61806c3fb27SDimitry Andric// Load register, immed offset 61906c3fb27SDimitry Andricdef : SchedAlias<WriteLD, V1Write_4c_1L>; 62006c3fb27SDimitry Andric 62106c3fb27SDimitry Andric// Load register, immed offset, index 62206c3fb27SDimitry Andricdef : SchedAlias<WriteLDIdx, V1Write_4c_1L>; 62306c3fb27SDimitry Andricdef : SchedAlias<WriteAdr, V1Write_1c_1I>; 62406c3fb27SDimitry Andric 62506c3fb27SDimitry Andric// Load pair, immed offset 62606c3fb27SDimitry Andricdef : SchedAlias<WriteLDHi, V1Write_4c_1L>; 62706c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_1L, V1Write_0c_0Z], (instrs LDPWi, LDNPWi)>; 6285f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V1Write_4c_1L, V1Write_0c_0Z], 62906c3fb27SDimitry Andric (instrs LDPWpost, LDPWpre)>; 63006c3fb27SDimitry Andric 63106c3fb27SDimitry Andric// Load pair, signed immed offset, signed words 63206c3fb27SDimitry Andricdef : InstRW<[V1Write_5c_1I_1L, V1Write_0c_0Z], (instrs LDPSWi)>; 63306c3fb27SDimitry Andric 63406c3fb27SDimitry Andric// Load pair, immed post or pre-index, signed words 6355f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V1Write_5c_1I_1L, V1Write_0c_0Z], 63606c3fb27SDimitry Andric (instrs LDPSWpost, LDPSWpre)>; 63706c3fb27SDimitry Andric 63806c3fb27SDimitry Andric 63906c3fb27SDimitry Andric// Store instructions 64006c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 64106c3fb27SDimitry Andric 64206c3fb27SDimitry Andric// Store register, immed offset 64306c3fb27SDimitry Andricdef : SchedAlias<WriteST, V1Write_1c_1L01_1D>; 64406c3fb27SDimitry Andric 64506c3fb27SDimitry Andric// Store register, immed offset, index 64606c3fb27SDimitry Andricdef : SchedAlias<WriteSTIdx, V1Write_1c_1L01_1D>; 64706c3fb27SDimitry Andric 64806c3fb27SDimitry Andric// Store pair, immed offset 64906c3fb27SDimitry Andricdef : SchedAlias<WriteSTP, V1Write_1c_1L01_1D>; 65006c3fb27SDimitry Andric 65106c3fb27SDimitry Andric 65206c3fb27SDimitry Andric// FP data processing instructions 65306c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 65406c3fb27SDimitry Andric 65506c3fb27SDimitry Andric// FP absolute value 65606c3fb27SDimitry Andric// FP arithmetic 65706c3fb27SDimitry Andric// FP min/max 65806c3fb27SDimitry Andric// FP negate 65906c3fb27SDimitry Andricdef : SchedAlias<WriteF, V1Write_2c_1V>; 66006c3fb27SDimitry Andric 66106c3fb27SDimitry Andric// FP compare 66206c3fb27SDimitry Andricdef : SchedAlias<WriteFCmp, V1Write_2c_1V0>; 66306c3fb27SDimitry Andric 66406c3fb27SDimitry Andric// FP divide 66506c3fb27SDimitry Andric// FP square root 66606c3fb27SDimitry Andricdef : SchedAlias<WriteFDiv, V1Write_10c7_1V02>; 66706c3fb27SDimitry Andric 66806c3fb27SDimitry Andric// FP divide, H-form 66906c3fb27SDimitry Andric// FP square root, H-form 67006c3fb27SDimitry Andricdef : InstRW<[V1Write_7c7_1V02], (instrs FDIVHrr, FSQRTHr)>; 67106c3fb27SDimitry Andric 67206c3fb27SDimitry Andric// FP divide, S-form 67306c3fb27SDimitry Andric// FP square root, S-form 67406c3fb27SDimitry Andricdef : InstRW<[V1Write_10c7_1V02], (instrs FDIVSrr, FSQRTSr)>; 67506c3fb27SDimitry Andric 67606c3fb27SDimitry Andric// FP divide, D-form 67706c3fb27SDimitry Andricdef : InstRW<[V1Write_15c7_1V02], (instrs FDIVDrr)>; 67806c3fb27SDimitry Andric 67906c3fb27SDimitry Andric// FP square root, D-form 68006c3fb27SDimitry Andricdef : InstRW<[V1Write_16c7_1V02], (instrs FSQRTDr)>; 68106c3fb27SDimitry Andric 68206c3fb27SDimitry Andric// FP multiply 68306c3fb27SDimitry Andricdef : SchedAlias<WriteFMul, V1Write_3c_1V>; 68406c3fb27SDimitry Andric 68506c3fb27SDimitry Andric// FP multiply accumulate 68606c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_1V], (instregex "^FN?M(ADD|SUB)[HSD]rrr$")>; 68706c3fb27SDimitry Andric 68806c3fb27SDimitry Andric// FP round to integral 68906c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1V02], (instregex "^FRINT[AIMNPXZ][HSD]r$", 69006c3fb27SDimitry Andric "^FRINT(32|64)[XZ][SD]r$")>; 69106c3fb27SDimitry Andric 69206c3fb27SDimitry Andric// FP select 69306c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1V01], (instregex "^FCSEL[HSD]rrr$")>; 69406c3fb27SDimitry Andric 69506c3fb27SDimitry Andric 69606c3fb27SDimitry Andric// FP miscellaneous instructions 69706c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 69806c3fb27SDimitry Andric 69906c3fb27SDimitry Andric// FP convert, from gen to vec reg 70006c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1M0], (instregex "^[SU]CVTF[SU][WX][HSD]ri$")>; 70106c3fb27SDimitry Andric 70206c3fb27SDimitry Andric// FP convert, from vec to gen reg 70306c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1V0], (instregex "^FCVT[AMNPZ][SU][SU][WX][HSD]r$")>; 70406c3fb27SDimitry Andric 70506c3fb27SDimitry Andric// FP convert, Javascript from vec to gen reg 70606c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1V0], (instrs FJCVTZS)>; 70706c3fb27SDimitry Andric 70806c3fb27SDimitry Andric// FP convert, from vec to vec reg 70906c3fb27SDimitry Andricdef : SchedAlias<WriteFCvt, V1Write_3c_1V02>; 71006c3fb27SDimitry Andric 71106c3fb27SDimitry Andric// FP move, immed 71206c3fb27SDimitry Andricdef : SchedAlias<WriteFImm, V1Write_2c_1V>; 71306c3fb27SDimitry Andric 71406c3fb27SDimitry Andric// FP move, register 71506c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1V], (instrs FMOVHr, FMOVSr, FMOVDr)>; 71606c3fb27SDimitry Andric 71706c3fb27SDimitry Andric// FP transfer, from gen to low half of vec reg 71806c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1M0], (instrs FMOVWHr, FMOVXHr, FMOVWSr, FMOVXDr)>; 71906c3fb27SDimitry Andric 72006c3fb27SDimitry Andric// FP transfer, from gen to high half of vec reg 72106c3fb27SDimitry Andricdef : InstRW<[V1Write_5c_1M0_1V], (instrs FMOVXDHighr)>; 72206c3fb27SDimitry Andric 72306c3fb27SDimitry Andric// FP transfer, from vec to gen reg 72406c3fb27SDimitry Andricdef : SchedAlias<WriteFCopy, V1Write_2c_1V1>; 72506c3fb27SDimitry Andric 72606c3fb27SDimitry Andric 72706c3fb27SDimitry Andric// FP load instructions 72806c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 72906c3fb27SDimitry Andric 73006c3fb27SDimitry Andric// Load vector reg, literal, S/D/Q forms 73106c3fb27SDimitry Andric// Load vector reg, unscaled immed 73206c3fb27SDimitry Andric// Load vector reg, unsigned immed 73306c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_1L, ReadAdrBase], (instregex "^LDR[SDQ]l$", 73406c3fb27SDimitry Andric "^LDUR[BHSDQ]i$", 73506c3fb27SDimitry Andric "^LDR[BHSDQ]ui$")>; 73606c3fb27SDimitry Andric 73706c3fb27SDimitry Andric// Load vector reg, immed post-index 73806c3fb27SDimitry Andric// Load vector reg, immed pre-index 7395f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V1Write_6c_1L], 74006c3fb27SDimitry Andric (instregex "^LDR[BHSDQ](post|pre)$")>; 74106c3fb27SDimitry Andric 74206c3fb27SDimitry Andric// Load vector reg, register offset, basic 74306c3fb27SDimitry Andric// Load vector reg, register offset, scale, S/D-form 74406c3fb27SDimitry Andric// Load vector reg, register offset, extend 74506c3fb27SDimitry Andric// Load vector reg, register offset, extend, scale, S/D-form 74606c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_1L, ReadAdrBase], (instregex "^LDR[BSD]ro[WX]$")>; 74706c3fb27SDimitry Andric 74806c3fb27SDimitry Andric// Load vector reg, register offset, scale, H/Q-form 74906c3fb27SDimitry Andric// Load vector reg, register offset, extend, scale, H/Q-form 75006c3fb27SDimitry Andricdef : InstRW<[V1Write_7c_1I_1L, ReadAdrBase], (instregex "^LDR[HQ]ro[WX]$")>; 75106c3fb27SDimitry Andric 75206c3fb27SDimitry Andric// Load vector pair, immed offset, S/D-form 75306c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_1L, V1Write_0c_0Z], (instregex "^LDN?P[SD]i$")>; 75406c3fb27SDimitry Andric 75506c3fb27SDimitry Andric// Load vector pair, immed offset, Q-form 75606c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_1L, WriteLDHi], (instrs LDPQi, LDNPQi)>; 75706c3fb27SDimitry Andric 75806c3fb27SDimitry Andric// Load vector pair, immed post-index, S/D-form 75906c3fb27SDimitry Andric// Load vector pair, immed pre-index, S/D-form 7605f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V1Write_6c_1L, V1Write_0c_0Z], 76106c3fb27SDimitry Andric (instregex "^LDP[SD](pre|post)$")>; 76206c3fb27SDimitry Andric 76306c3fb27SDimitry Andric// Load vector pair, immed post-index, Q-form 76406c3fb27SDimitry Andric// Load vector pair, immed pre-index, Q-form 7655f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V1Write_6c_1L, WriteLDHi], 76606c3fb27SDimitry Andric (instrs LDPQpost, LDPQpre)>; 76706c3fb27SDimitry Andric 76806c3fb27SDimitry Andric 76906c3fb27SDimitry Andric// FP store instructions 77006c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 77106c3fb27SDimitry Andric 77206c3fb27SDimitry Andric// Store vector reg, unscaled immed, B/H/S/D/Q-form 77306c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1L01_1V01], (instregex "^STUR[BHSDQ]i$")>; 77406c3fb27SDimitry Andric 77506c3fb27SDimitry Andric// Store vector reg, immed post-index, B/H/S/D/Q-form 77606c3fb27SDimitry Andric// Store vector reg, immed pre-index, B/H/S/D/Q-form 7775f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V1Write_2c_1L01_1V01], 77806c3fb27SDimitry Andric (instregex "^STR[BHSDQ](pre|post)$")>; 77906c3fb27SDimitry Andric 78006c3fb27SDimitry Andric// Store vector reg, unsigned immed, B/H/S/D/Q-form 78106c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1L01_1V01], (instregex "^STR[BHSDQ]ui$")>; 78206c3fb27SDimitry Andric 78306c3fb27SDimitry Andric// Store vector reg, register offset, basic, B/S/D-form 78406c3fb27SDimitry Andric// Store vector reg, register offset, scale, B/S/D-form 78506c3fb27SDimitry Andric// Store vector reg, register offset, extend, B/S/D-form 78606c3fb27SDimitry Andric// Store vector reg, register offset, extend, scale, B/S/D-form 78706c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1L01_1V01, ReadAdrBase], 78806c3fb27SDimitry Andric (instregex "^STR[BSD]ro[WX]$")>; 78906c3fb27SDimitry Andric 79006c3fb27SDimitry Andric// Store vector reg, register offset, basic, H/Q-form 79106c3fb27SDimitry Andric// Store vector reg, register offset, scale, H/Q-form 79206c3fb27SDimitry Andric// Store vector reg, register offset, extend, H/Q-form 79306c3fb27SDimitry Andric// Store vector reg, register offset, extend, scale, H/Q-form 79406c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1I_1L01_1V01, ReadAdrBase], 79506c3fb27SDimitry Andric (instregex "^STR[HQ]ro[WX]$")>; 79606c3fb27SDimitry Andric 79706c3fb27SDimitry Andric// Store vector pair, immed offset, S/D/Q-form 79806c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1L01_1V01], (instregex "^STN?P[SDQ]i$")>; 79906c3fb27SDimitry Andric 80006c3fb27SDimitry Andric// Store vector pair, immed post-index, S/D-form 80106c3fb27SDimitry Andric// Store vector pair, immed pre-index, S/D-form 8025f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V1Write_2c_1L01_1V01], 80306c3fb27SDimitry Andric (instregex "^STP[SD](pre|post)$")>; 80406c3fb27SDimitry Andric 80506c3fb27SDimitry Andric// Store vector pair, immed post-index, Q-form 80606c3fb27SDimitry Andric// Store vector pair, immed pre-index, Q-form 8075f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V1Write_2c_2L01_1V01], (instrs STPQpre, STPQpost)>; 80806c3fb27SDimitry Andric 80906c3fb27SDimitry Andric 81006c3fb27SDimitry Andric// ASIMD integer instructions 81106c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 81206c3fb27SDimitry Andric 81306c3fb27SDimitry Andric// ASIMD absolute diff 81406c3fb27SDimitry Andric// ASIMD absolute diff long 81506c3fb27SDimitry Andric// ASIMD arith, basic 81606c3fb27SDimitry Andric// ASIMD arith, complex 81706c3fb27SDimitry Andric// ASIMD arith, pair-wise 81806c3fb27SDimitry Andric// ASIMD compare 81906c3fb27SDimitry Andric// ASIMD logical 82006c3fb27SDimitry Andric// ASIMD max/min, basic and pair-wise 82106c3fb27SDimitry Andricdef : SchedAlias<WriteVd, V1Write_2c_1V>; 82206c3fb27SDimitry Andricdef : SchedAlias<WriteVq, V1Write_2c_1V>; 82306c3fb27SDimitry Andric 82406c3fb27SDimitry Andric// ASIMD absolute diff accum 82506c3fb27SDimitry Andric// ASIMD absolute diff accum long 82606c3fb27SDimitry Andric// ASIMD pairwise add and accumulate long 82706c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_1V13], (instregex "^[SU]ABAL?v", "^[SU]ADALPv")>; 82806c3fb27SDimitry Andric 82906c3fb27SDimitry Andric// ASIMD arith, reduce, 4H/4S 83006c3fb27SDimitry Andric// ASIMD max/min, reduce, 4H/4S 83106c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1V13], (instregex "^(ADD|[SU]ADDL)Vv4(i16|i32)v$", 83206c3fb27SDimitry Andric "^[SU](MAX|MIN)Vv4(i16|i32)v$")>; 83306c3fb27SDimitry Andric 83406c3fb27SDimitry Andric// ASIMD arith, reduce, 8B/8H 83506c3fb27SDimitry Andric// ASIMD max/min, reduce, 8B/8H 83606c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_1V13_1V], (instregex "^(ADD|[SU]ADDL)Vv8(i8|i16)v$", 83706c3fb27SDimitry Andric "^[SU](MAX|MIN)Vv8(i8|i16)v$")>; 83806c3fb27SDimitry Andric 83906c3fb27SDimitry Andric// ASIMD arith, reduce, 16B 84006c3fb27SDimitry Andric// ASIMD max/min, reduce, 16B 84106c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_2V13], (instregex "^(ADD|[SU]ADDL)Vv16i8v$", 84206c3fb27SDimitry Andric "[SU](MAX|MIN)Vv16i8v$")>; 84306c3fb27SDimitry Andric 84406c3fb27SDimitry Andric// ASIMD dot product 84506c3fb27SDimitry Andric// ASIMD dot product using signed and unsigned integers 84606c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1V], (instregex "^([SU]|SU|US)DOT(lane)?v(8|16)i8$")>; 84706c3fb27SDimitry Andric 84806c3fb27SDimitry Andric// ASIMD matrix multiply- accumulate 84906c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1V], (instrs SMMLA, UMMLA, USMMLA)>; 85006c3fb27SDimitry Andric 85106c3fb27SDimitry Andric// ASIMD multiply 85206c3fb27SDimitry Andric// ASIMD multiply accumulate 85306c3fb27SDimitry Andric// ASIMD multiply accumulate long 85406c3fb27SDimitry Andric// ASIMD multiply accumulate high 85506c3fb27SDimitry Andric// ASIMD multiply accumulate saturating long 85606c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_1V02], 85706c3fb27SDimitry Andric (instregex "^MUL(v[148]i16|v[124]i32)$", 85806c3fb27SDimitry Andric "^SQR?DMULH(v[48]i16|v[24]i32)$", 85906c3fb27SDimitry Andric "^ML[AS](v[148]i16|v[124]i32)$", 86006c3fb27SDimitry Andric "^[SU]ML[AS]Lv", 86106c3fb27SDimitry Andric "^SQRDML[AS]H(v[148]i16|v[124]i32)$", 86206c3fb27SDimitry Andric "^SQDML[AS]Lv")>; 86306c3fb27SDimitry Andric 86406c3fb27SDimitry Andric// ASIMD multiply/multiply long (8x8) polynomial 86506c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1V01], (instregex "^PMULL?v(8|16)i8$")>; 86606c3fb27SDimitry Andric 86706c3fb27SDimitry Andric// ASIMD multiply long 86806c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1V02], (instregex "^([SU]|SQD)MULLv")>; 86906c3fb27SDimitry Andric 87006c3fb27SDimitry Andric// ASIMD shift accumulate 87106c3fb27SDimitry Andric// ASIMD shift by immed, complex 87206c3fb27SDimitry Andric// ASIMD shift by register, complex 87306c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_1V13], 87406c3fb27SDimitry Andric (instregex "^[SU]R?SRAv", 87506c3fb27SDimitry Andric "^RSHRNv", "^SQRSHRU?Nv", "^(SQSHLU?|UQSHL)[bhsd]$", 87606c3fb27SDimitry Andric "^(SQSHLU?|UQSHL)(v8i8|v16i8|v4i16|v8i16|v2i32|v4i32|v2i64)_shift$", 87706c3fb27SDimitry Andric "^SQSHU?RNv", "^[SU]RSHRv", "^UQR?SHRNv", 87806c3fb27SDimitry Andric "^[SU]Q?RSHLv", "^[SU]QSHLv")>; 87906c3fb27SDimitry Andric 88006c3fb27SDimitry Andric// ASIMD shift by immed, basic 88106c3fb27SDimitry Andric// ASIMD shift by immed and insert, basic 88206c3fb27SDimitry Andric// ASIMD shift by register, basic 88306c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1V13], (instregex "^SHLL?v", "^SHRNv", "^[SU]SHLLv", 88406c3fb27SDimitry Andric "^[SU]SHRv", "^S[LR]Iv", "^[SU]SHLv")>; 88506c3fb27SDimitry Andric 88606c3fb27SDimitry Andric 88706c3fb27SDimitry Andric// ASIMD FP instructions 88806c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 88906c3fb27SDimitry Andric 89006c3fb27SDimitry Andric// ASIMD FP absolute value/difference 89106c3fb27SDimitry Andric// ASIMD FP arith, normal 89206c3fb27SDimitry Andric// ASIMD FP compare 89306c3fb27SDimitry Andric// ASIMD FP complex add 89406c3fb27SDimitry Andric// ASIMD FP max/min, normal 89506c3fb27SDimitry Andric// ASIMD FP max/min, pairwise 89606c3fb27SDimitry Andric// ASIMD FP negate 89706c3fb27SDimitry Andric// Covered by "SchedAlias (WriteV[dq]...)" above 89806c3fb27SDimitry Andric 89906c3fb27SDimitry Andric// ASIMD FP complex multiply add 90006c3fb27SDimitry Andric// ASIMD FP multiply accumulate 90106c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_1V], (instregex "^FCADD(v[48]f16|v[24]f32|v2f64)$", 90206c3fb27SDimitry Andric "^FML[AS]v")>; 90306c3fb27SDimitry Andric 90406c3fb27SDimitry Andric// ASIMD FP convert, long (F16 to F32) 90506c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_2V02], (instregex "^FCVTLv[48]i16$")>; 90606c3fb27SDimitry Andric 90706c3fb27SDimitry Andric// ASIMD FP convert, long (F32 to F64) 90806c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1V02], (instregex "^FCVTLv[24]i32$")>; 90906c3fb27SDimitry Andric 91006c3fb27SDimitry Andric// ASIMD FP convert, narrow (F32 to F16) 91106c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_2V02], (instregex "^FCVTNv[48]i16$")>; 91206c3fb27SDimitry Andric 91306c3fb27SDimitry Andric// ASIMD FP convert, narrow (F64 to F32) 91406c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1V02], (instregex "^FCVTNv[24]i32$", 91506c3fb27SDimitry Andric "^FCVTXN(v[24]f32|v1i64)$")>; 91606c3fb27SDimitry Andric 91706c3fb27SDimitry Andric// ASIMD FP convert, other, D-form F32 and Q-form F64 91806c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1V02], (instregex "^[FSU]CVT[AMNPZ][SU]v2f(32|64)$", 91906c3fb27SDimitry Andric "^[SU]CVTFv2f(32|64)$")>; 92006c3fb27SDimitry Andric 92106c3fb27SDimitry Andric// ASIMD FP convert, other, D-form F16 and Q-form F32 92206c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_2V02], (instregex "^[FSU]CVT[AMNPZ][SU]v4f(16|32)$", 92306c3fb27SDimitry Andric "^[SU]CVTFv4f(16|32)$")>; 92406c3fb27SDimitry Andric 92506c3fb27SDimitry Andric// ASIMD FP convert, other, Q-form F16 92606c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_4V02], (instregex "^[FSU]CVT[AMNPZ][SU]v8f16$", 92706c3fb27SDimitry Andric "^[SU]CVTFv8f16$")>; 92806c3fb27SDimitry Andric 92906c3fb27SDimitry Andric// ASIMD FP divide, D-form, F16 93006c3fb27SDimitry Andric// ASIMD FP square root, D-form, F16 93106c3fb27SDimitry Andricdef : InstRW<[V1Write_7c7_1V02], (instrs FDIVv4f16, FSQRTv4f16)>; 93206c3fb27SDimitry Andric 93306c3fb27SDimitry Andric// ASIMD FP divide, F32 93406c3fb27SDimitry Andric// ASIMD FP square root, F32 93506c3fb27SDimitry Andricdef : InstRW<[V1Write_10c7_1V02], (instrs FDIVv2f32, FDIVv4f32, 93606c3fb27SDimitry Andric FSQRTv2f32, FSQRTv4f32)>; 93706c3fb27SDimitry Andric 93806c3fb27SDimitry Andric// ASIMD FP divide, Q-form, F16 93906c3fb27SDimitry Andricdef : InstRW<[V1Write_13c5_1V02], (instrs FDIVv8f16)>; 94006c3fb27SDimitry Andric 94106c3fb27SDimitry Andric// ASIMD FP divide, Q-form, F64 94206c3fb27SDimitry Andricdef : InstRW<[V1Write_15c7_1V02], (instrs FDIVv2f64)>; 94306c3fb27SDimitry Andric 94406c3fb27SDimitry Andric// ASIMD FP square root, Q-form, F16 94506c3fb27SDimitry Andricdef : InstRW<[V1Write_13c11_1V02], (instrs FSQRTv8f16)>; 94606c3fb27SDimitry Andric 94706c3fb27SDimitry Andric// ASIMD FP square root, Q-form, F64 94806c3fb27SDimitry Andricdef : InstRW<[V1Write_16c7_1V02], (instrs FSQRTv2f64)>; 94906c3fb27SDimitry Andric 95006c3fb27SDimitry Andric// ASIMD FP max/min, reduce, F32 and D-form F16 95106c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_2V], (instregex "^F(MAX|MIN)(NM)?Vv4(i16|i32)v$")>; 95206c3fb27SDimitry Andric 95306c3fb27SDimitry Andric// ASIMD FP max/min, reduce, Q-form F16 95406c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_3V], (instregex "^F(MAX|MIN)(NM)?Vv8i16v$")>; 95506c3fb27SDimitry Andric 95606c3fb27SDimitry Andric// ASIMD FP multiply 95706c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1V], (instregex "^FMULX?v")>; 95806c3fb27SDimitry Andric 95906c3fb27SDimitry Andric// ASIMD FP multiply accumulate long 96006c3fb27SDimitry Andricdef : InstRW<[V1Write_5c_1V], (instregex "^FML[AS]L2?v")>; 96106c3fb27SDimitry Andric 96206c3fb27SDimitry Andric// ASIMD FP round, D-form F32 and Q-form F64 96306c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1V02], (instregex "^FRINT[AIMNPXZ]v2f(32|64)$")>; 96406c3fb27SDimitry Andric 96506c3fb27SDimitry Andric// ASIMD FP round, D-form F16 and Q-form F32 96606c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_2V02], (instregex "^FRINT[AIMNPXZ]v4f(16|32)$")>; 96706c3fb27SDimitry Andric 96806c3fb27SDimitry Andric// ASIMD FP round, Q-form F16 96906c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_4V02], (instregex "^FRINT[AIMNPXZ]v8f16$")>; 97006c3fb27SDimitry Andric 97106c3fb27SDimitry Andric 97206c3fb27SDimitry Andric// ASIMD BF instructions 97306c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 97406c3fb27SDimitry Andric 97506c3fb27SDimitry Andric// ASIMD convert, F32 to BF16 97606c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_1V02], (instrs BFCVTN, BFCVTN2)>; 97706c3fb27SDimitry Andric 97806c3fb27SDimitry Andric// ASIMD dot product 97906c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_1V], (instregex "^BF(DOT|16DOTlane)v[48]bf16$")>; 98006c3fb27SDimitry Andric 98106c3fb27SDimitry Andric// ASIMD matrix multiply accumulate 98206c3fb27SDimitry Andricdef : InstRW<[V1Write_5c_1V], (instrs BFMMLA)>; 98306c3fb27SDimitry Andric 98406c3fb27SDimitry Andric// ASIMD multiply accumulate long 98506c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_1V], (instregex "^BFMLAL[BT](Idx)?$")>; 98606c3fb27SDimitry Andric 98706c3fb27SDimitry Andric// Scalar convert, F32 to BF16 98806c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1V02], (instrs BFCVT)>; 98906c3fb27SDimitry Andric 99006c3fb27SDimitry Andric 99106c3fb27SDimitry Andric// ASIMD miscellaneous instructions 99206c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 99306c3fb27SDimitry Andric 99406c3fb27SDimitry Andric// ASIMD bit reverse 99506c3fb27SDimitry Andric// ASIMD bitwise insert 99606c3fb27SDimitry Andric// ASIMD count 99706c3fb27SDimitry Andric// ASIMD duplicate, element 99806c3fb27SDimitry Andric// ASIMD extract 99906c3fb27SDimitry Andric// ASIMD extract narrow 100006c3fb27SDimitry Andric// ASIMD insert, element to element 100106c3fb27SDimitry Andric// ASIMD move, FP immed 100206c3fb27SDimitry Andric// ASIMD move, integer immed 100306c3fb27SDimitry Andric// ASIMD reverse 100406c3fb27SDimitry Andric// ASIMD table lookup, 1 or 2 table regs 100506c3fb27SDimitry Andric// ASIMD table lookup extension, 1 table reg 100606c3fb27SDimitry Andric// ASIMD transfer, element to gen reg 100706c3fb27SDimitry Andric// ASIMD transpose 100806c3fb27SDimitry Andric// ASIMD unzip/zip 100906c3fb27SDimitry Andric// Covered by "SchedAlias (WriteV[dq]...)" above 101006c3fb27SDimitry Andric 101106c3fb27SDimitry Andric// ASIMD duplicate, gen reg 101206c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1M0], 101306c3fb27SDimitry Andric (instregex "^DUP((v16|v8)i8|(v8|v4)i16|(v4|v2)i32|v2i64)gpr$")>; 101406c3fb27SDimitry Andric 101506c3fb27SDimitry Andric// ASIMD extract narrow, saturating 101606c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_1V13], (instregex "^[SU]QXTNv", "^SQXTUNv")>; 101706c3fb27SDimitry Andric 101806c3fb27SDimitry Andric// ASIMD reciprocal and square root estimate, D-form U32 101906c3fb27SDimitry Andric// ASIMD reciprocal and square root estimate, D-form F32 and F64 102006c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1V02], (instrs URECPEv2i32, 102106c3fb27SDimitry Andric URSQRTEv2i32, 102206c3fb27SDimitry Andric FRECPEv1i32, FRECPEv2f32, FRECPEv1i64, 102306c3fb27SDimitry Andric FRSQRTEv1i32, FRSQRTEv2f32, FRSQRTEv1i64)>; 102406c3fb27SDimitry Andric 102506c3fb27SDimitry Andric// ASIMD reciprocal and square root estimate, Q-form U32 102606c3fb27SDimitry Andric// ASIMD reciprocal and square root estimate, D-form F16 and Q-form F32 and F64 102706c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_1V02], (instrs URECPEv4i32, 102806c3fb27SDimitry Andric URSQRTEv4i32, 102906c3fb27SDimitry Andric FRECPEv1f16, FRECPEv4f16, 103006c3fb27SDimitry Andric FRECPEv4f32, FRECPEv2f64, 103106c3fb27SDimitry Andric FRSQRTEv1f16, FRSQRTEv4f16, 103206c3fb27SDimitry Andric FRSQRTEv4f32, FRSQRTEv2f64)>; 103306c3fb27SDimitry Andric 103406c3fb27SDimitry Andric// ASIMD reciprocal and square root estimate, Q-form F16 103506c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_2V02], (instrs FRECPEv8f16, 103606c3fb27SDimitry Andric FRSQRTEv8f16)>; 103706c3fb27SDimitry Andric 103806c3fb27SDimitry Andric// ASIMD reciprocal exponent 103906c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1V02], (instrs FRECPXv1f16, FRECPXv1i32, FRECPXv1i64)>; 104006c3fb27SDimitry Andric 104106c3fb27SDimitry Andric// ASIMD reciprocal step 104206c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_1V], (instregex "^FRECPS(16|32|64)$", "^FRECPSv", 104306c3fb27SDimitry Andric "^FRSQRTS(16|32|64)$", "^FRSQRTSv")>; 104406c3fb27SDimitry Andric 104506c3fb27SDimitry Andric// ASIMD table lookup, 1 or 2 table regs 104606c3fb27SDimitry Andric// ASIMD table lookup extension, 1 table reg 104706c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_2V01], (instregex "^TBLv(8|16)i8(One|Two)$", 104806c3fb27SDimitry Andric "^TBXv(8|16)i8One$")>; 104906c3fb27SDimitry Andric 105006c3fb27SDimitry Andric// ASIMD table lookup, 3 table regs 105106c3fb27SDimitry Andric// ASIMD table lookup extension, 2 table reg 105206c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_2V01], (instrs TBLv8i8Three, TBLv16i8Three, 105306c3fb27SDimitry Andric TBXv8i8Two, TBXv16i8Two)>; 105406c3fb27SDimitry Andric 105506c3fb27SDimitry Andric// ASIMD table lookup, 4 table regs 105606c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_3V01], (instrs TBLv8i8Four, TBLv16i8Four)>; 105706c3fb27SDimitry Andric 105806c3fb27SDimitry Andric// ASIMD table lookup extension, 3 table reg 105906c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_3V01], (instrs TBXv8i8Three, TBXv16i8Three)>; 106006c3fb27SDimitry Andric 106106c3fb27SDimitry Andric// ASIMD table lookup extension, 4 table reg 106206c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_5V01], (instrs TBXv8i8Four, TBXv16i8Four)>; 106306c3fb27SDimitry Andric 106406c3fb27SDimitry Andric// ASIMD transfer, element to gen reg 106506c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1V], (instregex "^SMOVvi(((8|16)to(32|64))|32to64)$", 106606c3fb27SDimitry Andric "^UMOVvi(8|16|32|64)$")>; 106706c3fb27SDimitry Andric 106806c3fb27SDimitry Andric// ASIMD transfer, gen reg to element 106906c3fb27SDimitry Andricdef : InstRW<[V1Write_5c_1M0_1V], (instregex "^INSvi(8|16|32|64)gpr$")>; 107006c3fb27SDimitry Andric 107106c3fb27SDimitry Andric 107206c3fb27SDimitry Andric// ASIMD load instructions 107306c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 107406c3fb27SDimitry Andric 107506c3fb27SDimitry Andric// ASIMD load, 1 element, multiple, 1 reg 107606c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_1L], 107706c3fb27SDimitry Andric (instregex "^LD1Onev(8b|16b|4h|8h|2s|4s|1d|2d)$")>; 10785f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V1Write_6c_1L], 107906c3fb27SDimitry Andric (instregex "^LD1Onev(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>; 108006c3fb27SDimitry Andric 108106c3fb27SDimitry Andric// ASIMD load, 1 element, multiple, 2 reg 108206c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_2L], 108306c3fb27SDimitry Andric (instregex "^LD1Twov(8b|16b|4h|8h|2s|4s|1d|2d)$")>; 10845f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V1Write_6c_2L], 108506c3fb27SDimitry Andric (instregex "^LD1Twov(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>; 108606c3fb27SDimitry Andric 108706c3fb27SDimitry Andric// ASIMD load, 1 element, multiple, 3 reg 108806c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_3L], 108906c3fb27SDimitry Andric (instregex "^LD1Threev(8b|16b|4h|8h|2s|4s|1d|2d)$")>; 10905f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V1Write_6c_3L], 109106c3fb27SDimitry Andric (instregex "^LD1Threev(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>; 109206c3fb27SDimitry Andric 109306c3fb27SDimitry Andric// ASIMD load, 1 element, multiple, 4 reg, D-form 109406c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_2L], 109506c3fb27SDimitry Andric (instregex "^LD1Fourv(8b|4h|2s|1d)$")>; 10965f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V1Write_6c_2L], 109706c3fb27SDimitry Andric (instregex "^LD1Fourv(8b|4h|2s|1d)_POST$")>; 109806c3fb27SDimitry Andric 109906c3fb27SDimitry Andric// ASIMD load, 1 element, multiple, 4 reg, Q-form 110006c3fb27SDimitry Andricdef : InstRW<[V1Write_7c_4L], 110106c3fb27SDimitry Andric (instregex "^LD1Fourv(16b|8h|4s|2d)$")>; 11025f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V1Write_7c_4L], 110306c3fb27SDimitry Andric (instregex "^LD1Fourv(16b|8h|4s|2d)_POST$")>; 110406c3fb27SDimitry Andric 110506c3fb27SDimitry Andric// ASIMD load, 1 element, one lane 110606c3fb27SDimitry Andric// ASIMD load, 1 element, all lanes 110706c3fb27SDimitry Andricdef : InstRW<[V1Write_8c_1L_1V], 110806c3fb27SDimitry Andric (instregex "^LD1(i|Rv)(8|16|32|64)$", 110906c3fb27SDimitry Andric "^LD1Rv(8b|16b|4h|8h|2s|4s|1d|2d)$")>; 11105f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V1Write_8c_1L_1V], 111106c3fb27SDimitry Andric (instregex "^LD1i(8|16|32|64)_POST$", 111206c3fb27SDimitry Andric "^LD1Rv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>; 111306c3fb27SDimitry Andric 111406c3fb27SDimitry Andric// ASIMD load, 2 element, multiple, D-form 111506c3fb27SDimitry Andricdef : InstRW<[V1Write_8c_1L_2V], 111606c3fb27SDimitry Andric (instregex "^LD2Twov(8b|4h|2s)$")>; 11175f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V1Write_8c_1L_2V], 111806c3fb27SDimitry Andric (instregex "^LD2Twov(8b|4h|2s)_POST$")>; 111906c3fb27SDimitry Andric 112006c3fb27SDimitry Andric// ASIMD load, 2 element, multiple, Q-form 112106c3fb27SDimitry Andricdef : InstRW<[V1Write_8c_2L_2V], 112206c3fb27SDimitry Andric (instregex "^LD2Twov(16b|8h|4s|2d)$")>; 11235f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V1Write_8c_2L_2V], 112406c3fb27SDimitry Andric (instregex "^LD2Twov(16b|8h|4s|2d)_POST$")>; 112506c3fb27SDimitry Andric 112606c3fb27SDimitry Andric// ASIMD load, 2 element, one lane 112706c3fb27SDimitry Andric// ASIMD load, 2 element, all lanes 112806c3fb27SDimitry Andricdef : InstRW<[V1Write_8c_1L_2V], 112906c3fb27SDimitry Andric (instregex "^LD2i(8|16|32|64)$", 113006c3fb27SDimitry Andric "^LD2Rv(8b|16b|4h|8h|2s|4s|1d|2d)$")>; 11315f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V1Write_8c_1L_2V], 113206c3fb27SDimitry Andric (instregex "^LD2i(8|16|32|64)_POST$", 113306c3fb27SDimitry Andric "^LD2Rv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>; 113406c3fb27SDimitry Andric 113506c3fb27SDimitry Andric// ASIMD load, 3 element, multiple, D-form 113606c3fb27SDimitry Andric// ASIMD load, 3 element, one lane 113706c3fb27SDimitry Andric// ASIMD load, 3 element, all lanes 113806c3fb27SDimitry Andricdef : InstRW<[V1Write_8c_2L_3V], 113906c3fb27SDimitry Andric (instregex "^LD3Threev(8b|4h|2s)$", 114006c3fb27SDimitry Andric "^LD3i(8|16|32|64)$", 114106c3fb27SDimitry Andric "^LD3Rv(8b|16b|4h|8h|2s|4s|1d|2d)$")>; 11425f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V1Write_8c_2L_3V], 114306c3fb27SDimitry Andric (instregex "^LD3Threev(8b|4h|2s)_POST$", 114406c3fb27SDimitry Andric "^LD3i(8|16|32|64)_POST$", 114506c3fb27SDimitry Andric "^LD3Rv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>; 114606c3fb27SDimitry Andric 114706c3fb27SDimitry Andric// ASIMD load, 3 element, multiple, Q-form 114806c3fb27SDimitry Andricdef : InstRW<[V1Write_8c_3L_3V], 114906c3fb27SDimitry Andric (instregex "^LD3Threev(16b|8h|4s|2d)$")>; 11505f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V1Write_8c_3L_3V], 115106c3fb27SDimitry Andric (instregex "^LD3Threev(16b|8h|4s|2d)_POST$")>; 115206c3fb27SDimitry Andric 115306c3fb27SDimitry Andric// ASIMD load, 4 element, multiple, D-form 115406c3fb27SDimitry Andric// ASIMD load, 4 element, one lane 115506c3fb27SDimitry Andric// ASIMD load, 4 element, all lanes 115606c3fb27SDimitry Andricdef : InstRW<[V1Write_8c_3L_4V], 115706c3fb27SDimitry Andric (instregex "^LD4Fourv(8b|4h|2s)$", 115806c3fb27SDimitry Andric "^LD4i(8|16|32|64)$", 115906c3fb27SDimitry Andric "^LD4Rv(8b|16b|4h|8h|2s|4s|1d|2d)$")>; 11605f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V1Write_8c_3L_4V], 116106c3fb27SDimitry Andric (instregex "^LD4Fourv(8b|4h|2s)_POST$", 116206c3fb27SDimitry Andric "^LD4i(8|16|32|64)_POST$", 116306c3fb27SDimitry Andric "^LD4Rv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>; 116406c3fb27SDimitry Andric 116506c3fb27SDimitry Andric// ASIMD load, 4 element, multiple, Q-form 116606c3fb27SDimitry Andricdef : InstRW<[V1Write_9c_4L_4V], 116706c3fb27SDimitry Andric (instregex "^LD4Fourv(16b|8h|4s|2d)$")>; 11685f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V1Write_9c_4L_4V], 116906c3fb27SDimitry Andric (instregex "^LD4Fourv(16b|8h|4s|2d)_POST$")>; 117006c3fb27SDimitry Andric 117106c3fb27SDimitry Andric 117206c3fb27SDimitry Andric// ASIMD store instructions 117306c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 117406c3fb27SDimitry Andric 117506c3fb27SDimitry Andric// ASIMD store, 1 element, multiple, 1 reg 117606c3fb27SDimitry Andric// ASIMD store, 1 element, multiple, 2 reg, D-form 117706c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1L01_1V01], 117806c3fb27SDimitry Andric (instregex "^ST1Onev(8b|16b|4h|8h|2s|4s|1d|2d)$", 117906c3fb27SDimitry Andric "^ST1Twov(8b|4h|2s|1d)$")>; 11805f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V1Write_2c_1L01_1V01], 118106c3fb27SDimitry Andric (instregex "^ST1Onev(8b|16b|4h|8h|2s|4s|1d|2d)_POST$", 118206c3fb27SDimitry Andric "^ST1Twov(8b|4h|2s|1d)_POST$")>; 118306c3fb27SDimitry Andric 118406c3fb27SDimitry Andric// ASIMD store, 1 element, multiple, 2 reg, Q-form 118506c3fb27SDimitry Andric// ASIMD store, 1 element, multiple, 3 reg, D-form 118606c3fb27SDimitry Andric// ASIMD store, 1 element, multiple, 4 reg, D-form 118706c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_2L01_2V01], 118806c3fb27SDimitry Andric (instregex "^ST1Twov(16b|8h|4s|2d)$", 118906c3fb27SDimitry Andric "^ST1Threev(8b|4h|2s|1d)$", 119006c3fb27SDimitry Andric "^ST1Fourv(8b|4h|2s|1d)$")>; 11915f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V1Write_2c_2L01_2V01], 119206c3fb27SDimitry Andric (instregex "^ST1Twov(16b|8h|4s|2d)_POST$", 119306c3fb27SDimitry Andric "^ST1Threev(8b|4h|2s|1d)_POST$", 119406c3fb27SDimitry Andric "^ST1Fourv(8b|4h|2s|1d)_POST$")>; 119506c3fb27SDimitry Andric 119606c3fb27SDimitry Andric// ASIMD store, 1 element, multiple, 3 reg, Q-form 119706c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_3L01_3V01], 119806c3fb27SDimitry Andric (instregex "^ST1Threev(16b|8h|4s|2d)$")>; 11995f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V1Write_2c_3L01_3V01], 120006c3fb27SDimitry Andric (instregex "^ST1Threev(16b|8h|4s|2d)_POST$")>; 120106c3fb27SDimitry Andric 120206c3fb27SDimitry Andric// ASIMD store, 1 element, multiple, 4 reg, Q-form 120306c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_4L01_4V01], 120406c3fb27SDimitry Andric (instregex "^ST1Fourv(16b|8h|4s|2d)$")>; 12055f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V1Write_2c_4L01_4V01], 120606c3fb27SDimitry Andric (instregex "^ST1Fourv(16b|8h|4s|2d)_POST$")>; 120706c3fb27SDimitry Andric 120806c3fb27SDimitry Andric// ASIMD store, 1 element, one lane 120906c3fb27SDimitry Andric// ASIMD store, 2 element, multiple, D-form 121006c3fb27SDimitry Andric// ASIMD store, 2 element, one lane 121106c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_1L01_1V01], 121206c3fb27SDimitry Andric (instregex "^ST1i(8|16|32|64)$", 121306c3fb27SDimitry Andric "^ST2Twov(8b|4h|2s)$", 121406c3fb27SDimitry Andric "^ST2i(8|16|32|64)$")>; 12155f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V1Write_4c_1L01_1V01], 121606c3fb27SDimitry Andric (instregex "^ST1i(8|16|32|64)_POST$", 121706c3fb27SDimitry Andric "^ST2Twov(8b|4h|2s)_POST$", 121806c3fb27SDimitry Andric "^ST2i(8|16|32|64)_POST$")>; 121906c3fb27SDimitry Andric 122006c3fb27SDimitry Andric// ASIMD store, 2 element, multiple, Q-form 122106c3fb27SDimitry Andric// ASIMD store, 3 element, multiple, D-form 122206c3fb27SDimitry Andric// ASIMD store, 3 element, one lane 122306c3fb27SDimitry Andric// ASIMD store, 4 element, one lane, D 122406c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_2L01_2V01], 122506c3fb27SDimitry Andric (instregex "^ST2Twov(16b|8h|4s|2d)$", 122606c3fb27SDimitry Andric "^ST3Threev(8b|4h|2s)$", 122706c3fb27SDimitry Andric "^ST3i(8|16|32|64)$", 122806c3fb27SDimitry Andric "^ST4i64$")>; 12295f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V1Write_4c_2L01_2V01], 123006c3fb27SDimitry Andric (instregex "^ST2Twov(16b|8h|4s|2d)_POST$", 123106c3fb27SDimitry Andric "^ST3Threev(8b|4h|2s)_POST$", 123206c3fb27SDimitry Andric "^ST3i(8|16|32|64)_POST$", 123306c3fb27SDimitry Andric "^ST4i64_POST$")>; 123406c3fb27SDimitry Andric 123506c3fb27SDimitry Andric// ASIMD store, 3 element, multiple, Q-form 123606c3fb27SDimitry Andricdef : InstRW<[V1Write_5c_3L01_3V01], 123706c3fb27SDimitry Andric (instregex "^ST3Threev(16b|8h|4s|2d)$")>; 12385f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V1Write_5c_3L01_3V01], 123906c3fb27SDimitry Andric (instregex "^ST3Threev(16b|8h|4s|2d)_POST$")>; 124006c3fb27SDimitry Andric 124106c3fb27SDimitry Andric// ASIMD store, 4 element, multiple, D-form 124206c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_3L01_3V01], 124306c3fb27SDimitry Andric (instregex "^ST4Fourv(8b|4h|2s)$")>; 12445f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V1Write_6c_3L01_3V01], 124506c3fb27SDimitry Andric (instregex "^ST4Fourv(8b|4h|2s)_POST$")>; 124606c3fb27SDimitry Andric 124706c3fb27SDimitry Andric// ASIMD store, 4 element, multiple, Q-form, B/H/S 124806c3fb27SDimitry Andricdef : InstRW<[V1Write_7c_6L01_6V01], 124906c3fb27SDimitry Andric (instregex "^ST4Fourv(16b|8h|4s)$")>; 12505f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V1Write_7c_6L01_6V01], 125106c3fb27SDimitry Andric (instregex "^ST4Fourv(16b|8h|4s)_POST$")>; 125206c3fb27SDimitry Andric 125306c3fb27SDimitry Andric// ASIMD store, 4 element, multiple, Q-form, D 125406c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_4L01_4V01], 125506c3fb27SDimitry Andric (instrs ST4Fourv2d)>; 12565f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V1Write_4c_4L01_4V01], 125706c3fb27SDimitry Andric (instrs ST4Fourv2d_POST)>; 125806c3fb27SDimitry Andric 125906c3fb27SDimitry Andric// ASIMD store, 4 element, one lane, B/H/S 126006c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_3L_3V], 126106c3fb27SDimitry Andric (instregex "^ST4i(8|16|32)$")>; 12625f757f3fSDimitry Andricdef : InstRW<[WriteAdr, V1Write_6c_3L_3V], 126306c3fb27SDimitry Andric (instregex "^ST4i(8|16|32)_POST$")>; 126406c3fb27SDimitry Andric 126506c3fb27SDimitry Andric 126606c3fb27SDimitry Andric// Cryptography extensions 126706c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 126806c3fb27SDimitry Andric 126906c3fb27SDimitry Andric// Crypto polynomial (64x64) multiply long 127006c3fb27SDimitry Andric// Covered by "SchedAlias (WriteV[dq]...)" above 127106c3fb27SDimitry Andric 127206c3fb27SDimitry Andric// Crypto AES ops 127306c3fb27SDimitry Andricdef V1WriteVC : WriteSequence<[V1Write_2c_1V]>; 127406c3fb27SDimitry Andricdef V1ReadVC : SchedReadAdvance<2, [V1WriteVC]>; 127506c3fb27SDimitry Andricdef : InstRW<[V1WriteVC], (instrs AESDrr, AESErr)>; 127606c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1V, V1ReadVC], (instrs AESMCrr, AESIMCrr)>; 127706c3fb27SDimitry Andric 127806c3fb27SDimitry Andric// Crypto SHA1 hash acceleration op 127906c3fb27SDimitry Andric// Crypto SHA1 schedule acceleration ops 128006c3fb27SDimitry Andric// Crypto SHA256 schedule acceleration ops 128106c3fb27SDimitry Andric// Crypto SHA512 hash acceleration ops 128206c3fb27SDimitry Andric// Crypto SM3 ops 128306c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1V0], (instregex "^SHA1(H|SU[01])rr$", 128406c3fb27SDimitry Andric "^SHA256SU[01]rr$", 128506c3fb27SDimitry Andric "^SHA512(H2?|SU[01])$", 128606c3fb27SDimitry Andric "^SM3(PARTW(1|2SM3SS1)|TT[12][AB])$")>; 128706c3fb27SDimitry Andric 128806c3fb27SDimitry Andric// Crypto SHA1 hash acceleration ops 128906c3fb27SDimitry Andric// Crypto SHA256 hash acceleration ops 129006c3fb27SDimitry Andric// Crypto SM4 ops 129106c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_1V0], (instregex "^SHA1[CMP]rrr$", 129206c3fb27SDimitry Andric "^SHA256H2?rrr$", 129306c3fb27SDimitry Andric "^SM4E(KEY)?$")>; 129406c3fb27SDimitry Andric 129506c3fb27SDimitry Andric// Crypto SHA3 ops 129606c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1V0], (instrs BCAX, EOR3, RAX1, XAR)>; 129706c3fb27SDimitry Andric 129806c3fb27SDimitry Andric 129906c3fb27SDimitry Andric// CRC instruction 130006c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 130106c3fb27SDimitry Andric 130206c3fb27SDimitry Andric// CRC checksum ops 130306c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1M0], (instregex "^CRC32C?[BHWX]rr$")>; 130406c3fb27SDimitry Andric 130506c3fb27SDimitry Andric 130606c3fb27SDimitry Andric// SVE Predicate instructions 130706c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 130806c3fb27SDimitry Andric 130906c3fb27SDimitry Andric// Loop control, based on predicate 131006c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1M0], (instregex "^BRK[AB]_PP[mz]P$")>; 131106c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1M0], (instrs BRKN_PPzP, BRKPA_PPzPP, BRKPB_PPzPP)>; 131206c3fb27SDimitry Andric 131306c3fb27SDimitry Andric// Loop control, based on predicate and flag setting 131406c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_2M0], (instrs BRKAS_PPzP, BRKBS_PPzP, BRKNS_PPzP, 131506c3fb27SDimitry Andric BRKPAS_PPzPP, BRKPBS_PPzPP)>; 131606c3fb27SDimitry Andric 131706c3fb27SDimitry Andric// Loop control, based on GPR 131806c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_2M0], (instregex "^WHILE(LE|LO|LS|LT)_P(WW|XX)_[BHSD]$")>; 131906c3fb27SDimitry Andric 132006c3fb27SDimitry Andric// Loop terminate 132106c3fb27SDimitry Andricdef : InstRW<[V1Write_1c_1M0], (instregex "^CTERM(EQ|NE)_(WW|XX)$")>; 132206c3fb27SDimitry Andric 132306c3fb27SDimitry Andric// Predicate counting scalar 132406c3fb27SDimitry Andric// Predicate counting scalar, active predicate 132506c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1M0], (instrs ADDPL_XXI, ADDVL_XXI, RDVLI_XI)>; 132606c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1M0], (instregex "^(CNT|([SU]Q)?(DEC|INC))[BHWD]_XPiI$", 132706c3fb27SDimitry Andric "^SQ(DEC|INC)[BHWD]_XPiWdI$", 132806c3fb27SDimitry Andric "^UQ(DEC|INC)[BHWD]_WPiI$", 132906c3fb27SDimitry Andric "^CNTP_XPP_[BHSD]$", 133006c3fb27SDimitry Andric "^([SU]Q)?(DEC|INC)P_XP_[BHSD]$", 133106c3fb27SDimitry Andric "^UQ(DEC|INC)P_WP_[BHSD]$", 133206c3fb27SDimitry Andric "^[SU]Q(DEC|INC)P_XPWd_[BHSD]$")>; 133306c3fb27SDimitry Andric 133406c3fb27SDimitry Andric// Predicate counting vector, active predicate 133506c3fb27SDimitry Andricdef : InstRW<[V1Write_7c_2M0_1V01], (instregex "^([SU]Q)?(DEC|INC)P_ZP_[HSD]$")>; 133606c3fb27SDimitry Andric 133706c3fb27SDimitry Andric// Predicate logical 133806c3fb27SDimitry Andricdef : InstRW<[V1Write_1c_1M0], 133906c3fb27SDimitry Andric (instregex "^(AND|BIC|EOR|NAND|NOR|ORN|ORR)_PPzPP$")>; 134006c3fb27SDimitry Andric 134106c3fb27SDimitry Andric// Predicate logical, flag setting 134206c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_2M0], 134306c3fb27SDimitry Andric (instregex "^(AND|BIC|EOR|NAND|NOR|ORN|ORR)S_PPzPP$")>; 134406c3fb27SDimitry Andric 134506c3fb27SDimitry Andric// Predicate reverse 134606c3fb27SDimitry Andric// Predicate set/initialize/find next 134706c3fb27SDimitry Andric// Predicate transpose 134806c3fb27SDimitry Andric// Predicate unpack and widen 134906c3fb27SDimitry Andric// Predicate zip/unzip 135006c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1M0], (instregex "^REV_PP_[BHSD]$", 135106c3fb27SDimitry Andric "^PFALSE$", "^PFIRST_B$", 135206c3fb27SDimitry Andric "^PNEXT_[BHSD]$", "^PTRUE_[BHSD]$", 135306c3fb27SDimitry Andric "^TRN[12]_PPP_[BHSDQ]$", 135406c3fb27SDimitry Andric "^(ZIP|UZP)[12]_PPP_[BHSDQ]$")>; 135506c3fb27SDimitry Andric 135606c3fb27SDimitry Andric// Predicate set/initialize/find next 135706c3fb27SDimitry Andric// Predicate unpack and widen 135806c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1M0], (instrs PTEST_PP, 135906c3fb27SDimitry Andric PUNPKHI_PP, PUNPKLO_PP)>; 136006c3fb27SDimitry Andric 136106c3fb27SDimitry Andric// Predicate select 136206c3fb27SDimitry Andricdef : InstRW<[V1Write_1c_1M0], (instrs SEL_PPPP)>; 136306c3fb27SDimitry Andric 136406c3fb27SDimitry Andric// Predicate set/initialize, set flags 136506c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_2M0], (instregex "^PTRUES_[BHSD]$")>; 136606c3fb27SDimitry Andric 136706c3fb27SDimitry Andric 136806c3fb27SDimitry Andric 136906c3fb27SDimitry Andric// SVE integer instructions 137006c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 137106c3fb27SDimitry Andric 137206c3fb27SDimitry Andric// Arithmetic, basic 137306c3fb27SDimitry Andric// Logical 137406c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1V01], 137506c3fb27SDimitry Andric (instregex "^(ABS|CNOT|NEG)_ZPmZ_[BHSD]$", 137606c3fb27SDimitry Andric "^(ADD|SUB)_Z(I|P[mZ]Z|ZZ)_[BHSD]$", 137706c3fb27SDimitry Andric "^ADR_[SU]XTW_ZZZ_D_[0123]$", 137806c3fb27SDimitry Andric "^ADR_LSL_ZZZ_[SD]_[0123]$", 137906c3fb27SDimitry Andric "^[SU]ABD_ZP[mZ]Z_[BHSD]$", 138006c3fb27SDimitry Andric "^[SU](MAX|MIN)_Z(I|P[mZ]Z)_[BHSD]$", 138106c3fb27SDimitry Andric "^[SU]Q(ADD|SUB)_Z(I|ZZ)_[BHSD]$", 138206c3fb27SDimitry Andric "^SUBR_Z(I|P[mZ]Z)_[BHSD]$", 138306c3fb27SDimitry Andric "^(AND|EOR|ORR)_ZI$", 138406c3fb27SDimitry Andric "^(AND|BIC|EOR|EOR(BT|TB)?|ORR)_ZZZ$", 138506c3fb27SDimitry Andric "^EOR(BT|TB)_ZZZ_[BHSD]$", 138606c3fb27SDimitry Andric "^(AND|BIC|EOR|NOT|ORR)_ZPmZ_[BHSD]$")>; 138706c3fb27SDimitry Andric 138806c3fb27SDimitry Andric// Arithmetic, shift 138906c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1V1], 139006c3fb27SDimitry Andric (instregex "^(ASR|LSL|LSR)_WIDE_Z(Pm|Z)Z_[BHS]", 139106c3fb27SDimitry Andric "^(ASR|LSL|LSR)_ZPm[IZ]_[BHSD]", 139206c3fb27SDimitry Andric "^(ASR|LSL|LSR)_ZZI_[BHSD]", 139306c3fb27SDimitry Andric "^(ASR|LSL|LSR)_ZPZ[IZ]_[BHSD]", 139406c3fb27SDimitry Andric "^(ASRR|LSLR|LSRR)_ZPmZ_[BHSD]")>; 139506c3fb27SDimitry Andric 139606c3fb27SDimitry Andric// Arithmetic, shift right for divide 139706c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_1V1], (instregex "^ASRD_ZP[mZ]I_[BHSD]$")>; 139806c3fb27SDimitry Andric 139906c3fb27SDimitry Andric// Count/reverse bits 140006c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1V01], (instregex "^(CLS|CLZ|CNT|RBIT)_ZPmZ_[BHSD]$")>; 140106c3fb27SDimitry Andric 140206c3fb27SDimitry Andric// Broadcast logical bitmask immediate to vector 140306c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1V01], (instrs DUPM_ZI)>; 140406c3fb27SDimitry Andric 140506c3fb27SDimitry Andric// Compare and set flags 140606c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_1M0_1V0], 140706c3fb27SDimitry Andric (instregex "^CMP(EQ|GE|GT|HI|HS|LE|LO|LS|LT|NE)_PPzZ[IZ]_[BHSD]$", 140806c3fb27SDimitry Andric "^CMP(EQ|GE|GT|HI|HS|LE|LO|LS|LT|NE)_WIDE_PPzZZ_[BHS]$")>; 140906c3fb27SDimitry Andric 141006c3fb27SDimitry Andric// Conditional extract operations, scalar form 141106c3fb27SDimitry Andricdef : InstRW<[V1Write_9c_1M0_1V1], (instregex "^CLAST[AB]_RPZ_[BHSD]$")>; 141206c3fb27SDimitry Andric 141306c3fb27SDimitry Andric// Conditional extract operations, SIMD&FP scalar and vector forms 141406c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1V1], (instregex "^CLAST[AB]_[VZ]PZ_[BHSD]$", 141506c3fb27SDimitry Andric "^COMPACT_ZPZ_[SD]$", 141606c3fb27SDimitry Andric "^SPLICE_ZPZZ?_[BHSD]$")>; 141706c3fb27SDimitry Andric 141806c3fb27SDimitry Andric// Convert to floating point, 64b to float or convert to double 141906c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1V0], (instregex "^[SU]CVTF_ZPmZ_Dto[HSD]", 142006c3fb27SDimitry Andric "^[SU]CVTF_ZPmZ_StoD")>; 142106c3fb27SDimitry Andric 142206c3fb27SDimitry Andric// Convert to floating point, 32b to single or half 142306c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_2V0], (instregex "^[SU]CVTF_ZPmZ_Sto[HS]$")>; 142406c3fb27SDimitry Andric 142506c3fb27SDimitry Andric// Convert to floating point, 16b to half 142606c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_4V0], (instregex "^[SU]CVTF_ZPmZ_HtoH$")>; 142706c3fb27SDimitry Andric 142806c3fb27SDimitry Andric// Copy, scalar 142906c3fb27SDimitry Andricdef : InstRW<[V1Write_5c_1M0_1V01], (instregex "^CPY_ZPmR_[BHSD]$")>; 143006c3fb27SDimitry Andric 143106c3fb27SDimitry Andric// Copy, scalar SIMD&FP or imm 143206c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1V01], (instregex "^CPY_ZP([mz]I|mV)_[BHSD]$")>; 143306c3fb27SDimitry Andric 143406c3fb27SDimitry Andric// Divides, 32 bit 143506c3fb27SDimitry Andricdef : InstRW<[V1Write_12c7_1V0], (instregex "^[SU]DIVR?_ZPmZ_S$")>; 143606c3fb27SDimitry Andric 143706c3fb27SDimitry Andric// Divides, 64 bit 143806c3fb27SDimitry Andricdef : InstRW<[V1Write_20c7_1V0], (instregex "^[SU]DIVR?_ZPmZ_D$")>; 143906c3fb27SDimitry Andric 144006c3fb27SDimitry Andric// Dot product, 8 bit 144106c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1V01], (instregex "^[SU]DOT_ZZZI?_S$")>; 144206c3fb27SDimitry Andric 144306c3fb27SDimitry Andric// Dot product, 8 bit, using signed and unsigned integers 144406c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1V], (instrs SUDOT_ZZZI, USDOT_ZZZ, USDOT_ZZZI)>; 144506c3fb27SDimitry Andric 144606c3fb27SDimitry Andric// Dot product, 16 bit 144706c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_1V01], (instregex "^[SU]DOT_ZZZI?_D$")>; 144806c3fb27SDimitry Andric 144906c3fb27SDimitry Andric// Duplicate, immediate and indexed form 145006c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1V01], (instregex "^DUP_ZI_[BHSD]$", 145106c3fb27SDimitry Andric "^DUP_ZZI_[BHSDQ]$")>; 145206c3fb27SDimitry Andric 145306c3fb27SDimitry Andric// Duplicate, scalar form 145406c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1M0], (instregex "^DUP_ZR_[BHSD]$")>; 145506c3fb27SDimitry Andric 145606c3fb27SDimitry Andric// Extend, sign or zero 145706c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1V1], (instregex "^[SU]XTB_ZPmZ_[HSD]$", 145806c3fb27SDimitry Andric "^[SU]XTH_ZPmZ_[SD]$", 145906c3fb27SDimitry Andric "^[SU]XTW_ZPmZ_[D]$")>; 146006c3fb27SDimitry Andric 146106c3fb27SDimitry Andric// Extract 146206c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1V01], (instrs EXT_ZZI)>; 146306c3fb27SDimitry Andric 146406c3fb27SDimitry Andric// Extract/insert operation, SIMD and FP scalar form 146506c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1V1], (instregex "^LAST[AB]_VPZ_[BHSD]$", 146606c3fb27SDimitry Andric "^INSR_ZV_[BHSD]$")>; 146706c3fb27SDimitry Andric 146806c3fb27SDimitry Andric// Extract/insert operation, scalar 146906c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_1M0_1V1], (instregex "^LAST[AB]_RPZ_[BHSD]$", 147006c3fb27SDimitry Andric "^INSR_ZR_[BHSD]$")>; 147106c3fb27SDimitry Andric 147206c3fb27SDimitry Andric// Horizontal operations, B, H, S form, imm, imm 147306c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_1V0], (instregex "^INDEX_II_[BHS]$")>; 147406c3fb27SDimitry Andric 147506c3fb27SDimitry Andric// Horizontal operations, B, H, S form, scalar, imm / scalar / imm, scalar 147606c3fb27SDimitry Andricdef : InstRW<[V1Write_7c_1M0_1V0], (instregex "^INDEX_(IR|RI|RR)_[BHS]$")>; 147706c3fb27SDimitry Andric 147806c3fb27SDimitry Andric// Horizontal operations, D form, imm, imm 147906c3fb27SDimitry Andricdef : InstRW<[V1Write_5c_2V0], (instrs INDEX_II_D)>; 148006c3fb27SDimitry Andric 148106c3fb27SDimitry Andric// Horizontal operations, D form, scalar, imm / scalar / imm, scalar 148206c3fb27SDimitry Andricdef : InstRW<[V1Write_8c_2M0_2V0], (instregex "^INDEX_(IR|RI|RR)_D$")>; 148306c3fb27SDimitry Andric 148406c3fb27SDimitry Andric// Move prefix 148506c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1V01], (instregex "^MOVPRFX_ZP[mz]Z_[BHSD]$", 148606c3fb27SDimitry Andric "^MOVPRFX_ZZ$")>; 148706c3fb27SDimitry Andric 148806c3fb27SDimitry Andric// Matrix multiply-accumulate 148906c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1V01], (instrs SMMLA_ZZZ, UMMLA_ZZZ, USMMLA_ZZZ)>; 149006c3fb27SDimitry Andric 149106c3fb27SDimitry Andric// Multiply, B, H, S element size 149206c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_1V0], (instregex "^MUL_(ZI|ZPmZ)_[BHS]$", 149306c3fb27SDimitry Andric "^[SU]MULH_(ZPmZ|ZZZ)_[BHS]$")>; 149406c3fb27SDimitry Andric 149506c3fb27SDimitry Andric// Multiply, D element size 149606c3fb27SDimitry Andric// Multiply accumulate, D element size 149706c3fb27SDimitry Andricdef : InstRW<[V1Write_5c_2V0], (instregex "^MUL_(ZI|ZPmZ)_D$", 149806c3fb27SDimitry Andric "^[SU]MULH_ZPmZ_D$", 149906c3fb27SDimitry Andric "^(MLA|MLS|MAD|MSB)_ZPmZZ_D$")>; 150006c3fb27SDimitry Andric 150106c3fb27SDimitry Andric// Multiply accumulate, B, H, S element size 150206c3fb27SDimitry Andric// NOTE: This is not specified in the SOG. 150306c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_1V0], (instregex "^(ML[AS]|MAD|MSB)_ZPmZZ_[BHS]")>; 150406c3fb27SDimitry Andric 150506c3fb27SDimitry Andric// Predicate counting vector 150606c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1V0], (instregex "^([SU]Q)?(DEC|INC)[HWD]_ZPiI$")>; 150706c3fb27SDimitry Andric 150806c3fb27SDimitry Andric// Reduction, arithmetic, B form 150906c3fb27SDimitry Andricdef : InstRW<[V1Write_14c_1V_1V0_2V1_1V13], 151006c3fb27SDimitry Andric (instregex "^[SU](ADD|MAX|MIN)V_VPZ_B")>; 151106c3fb27SDimitry Andric 151206c3fb27SDimitry Andric// Reduction, arithmetic, H form 151306c3fb27SDimitry Andricdef : InstRW<[V1Write_12c_1V_1V01_2V1], 151406c3fb27SDimitry Andric (instregex "^[SU](ADD|MAX|MIN)V_VPZ_H")>; 151506c3fb27SDimitry Andric 151606c3fb27SDimitry Andric// Reduction, arithmetic, S form 151706c3fb27SDimitry Andricdef : InstRW<[V1Write_10c_1V_1V01_2V1], 151806c3fb27SDimitry Andric (instregex "^[SU](ADD|MAX|MIN)V_VPZ_S")>; 151906c3fb27SDimitry Andric 152006c3fb27SDimitry Andric// Reduction, arithmetic, D form 152106c3fb27SDimitry Andricdef : InstRW<[V1Write_8c_1V_1V01], 152206c3fb27SDimitry Andric (instregex "^[SU](ADD|MAX|MIN)V_VPZ_D")>; 152306c3fb27SDimitry Andric 152406c3fb27SDimitry Andric// Reduction, logical 152506c3fb27SDimitry Andricdef : InstRW<[V1Write_12c_4V01], (instregex "^(AND|EOR|OR)V_VPZ_[BHSD]$")>; 152606c3fb27SDimitry Andric 152706c3fb27SDimitry Andric// Reverse, vector 152806c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1V01], (instregex "^REV_ZZ_[BHSD]$", 152906c3fb27SDimitry Andric "^REVB_ZPmZ_[HSD]$", 153006c3fb27SDimitry Andric "^REVH_ZPmZ_[SD]$", 153106c3fb27SDimitry Andric "^REVW_ZPmZ_D$")>; 153206c3fb27SDimitry Andric 153306c3fb27SDimitry Andric// Select, vector form 153406c3fb27SDimitry Andric// Table lookup 153506c3fb27SDimitry Andric// Table lookup extension 153606c3fb27SDimitry Andric// Transpose, vector form 153706c3fb27SDimitry Andric// Unpack and extend 153806c3fb27SDimitry Andric// Zip/unzip 153906c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1V01], (instregex "^SEL_ZPZZ_[BHSD]$", 154006c3fb27SDimitry Andric "^TB[LX]_ZZZ_[BHSD]$", 154106c3fb27SDimitry Andric "^TRN[12]_ZZZ_[BHSDQ]$", 154206c3fb27SDimitry Andric "^[SU]UNPK(HI|LO)_ZZ_[HSD]$", 154306c3fb27SDimitry Andric "^(UZP|ZIP)[12]_ZZZ_[BHSDQ]$")>; 154406c3fb27SDimitry Andric 154506c3fb27SDimitry Andric 154606c3fb27SDimitry Andric// SVE floating-point instructions 154706c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 154806c3fb27SDimitry Andric 154906c3fb27SDimitry Andric// Floating point absolute value/difference 155006c3fb27SDimitry Andric// Floating point arithmetic 155106c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1V01], (instregex "^FAB[SD]_ZPmZ_[HSD]$", 155206c3fb27SDimitry Andric "^F(ADD|SUB)_(ZPm[IZ]|ZZZ)_[HSD]$", 155306c3fb27SDimitry Andric "^FADDP_ZPmZZ_[HSD]$", 155406c3fb27SDimitry Andric "^FNEG_ZPmZ_[HSD]$", 155506c3fb27SDimitry Andric "^FSUBR_ZPm[IZ]_[HSD]$")>; 155606c3fb27SDimitry Andric 155706c3fb27SDimitry Andric// Floating point associative add, F16 155806c3fb27SDimitry Andricdef : InstRW<[V1Write_19c_18V0], (instrs FADDA_VPZ_H)>; 155906c3fb27SDimitry Andric 156006c3fb27SDimitry Andric// Floating point associative add, F32 156106c3fb27SDimitry Andricdef : InstRW<[V1Write_11c_10V0], (instrs FADDA_VPZ_S)>; 156206c3fb27SDimitry Andric 156306c3fb27SDimitry Andric// Floating point associative add, F64 156406c3fb27SDimitry Andricdef : InstRW<[V1Write_8c_3V01], (instrs FADDA_VPZ_D)>; 156506c3fb27SDimitry Andric 156606c3fb27SDimitry Andric// Floating point compare 156706c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1V0], (instregex "^FAC(GE|GT)_PPzZZ_[HSD]$", 156806c3fb27SDimitry Andric "^FCM(EQ|GE|GT|NE|UO)_PPzZZ_[HSD]$", 156906c3fb27SDimitry Andric "^FCM(EQ|GE|GT|LE|LT|NE)_PPzZ0_[HSD]$")>; 157006c3fb27SDimitry Andric 157106c3fb27SDimitry Andric// Floating point complex add 157206c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1V01], (instregex "^FCADD_ZPmZ_[HSD]$")>; 157306c3fb27SDimitry Andric 157406c3fb27SDimitry Andric// Floating point complex multiply add 157506c3fb27SDimitry Andricdef : InstRW<[V1Write_5c_1V01], (instregex "^FCMLA_ZPmZZ_[HSD]$", 157606c3fb27SDimitry Andric "^FCMLA_ZZZI_[HS]$")>; 157706c3fb27SDimitry Andric 157806c3fb27SDimitry Andric// Floating point convert, long or narrow (F16 to F32 or F32 to F16) 157906c3fb27SDimitry Andric// Floating point convert to integer, F32 158006c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_2V0], (instregex "^FCVT_ZPmZ_(HtoS|StoH)$", 158106c3fb27SDimitry Andric "^FCVTZ[SU]_ZPmZ_(HtoS|StoS)$")>; 158206c3fb27SDimitry Andric 158306c3fb27SDimitry Andric// Floating point convert, long or narrow (F16 to F64, F32 to F64, F64 to F32 or F64 to F16) 158406c3fb27SDimitry Andric// Floating point convert to integer, F64 158506c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1V0], (instregex "^FCVT_ZPmZ_(HtoD|StoD|DtoS|DtoH)$", 158606c3fb27SDimitry Andric "^FCVTZ[SU]_ZPmZ_(HtoD|StoD|DtoS|DtoD)$")>; 158706c3fb27SDimitry Andric 158806c3fb27SDimitry Andric// Floating point convert to integer, F16 158906c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_4V0], (instregex "^FCVTZ[SU]_ZPmZ_HtoH$")>; 159006c3fb27SDimitry Andric 159106c3fb27SDimitry Andric// Floating point copy 159206c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1V01], (instregex "^FCPY_ZPmI_[HSD]$", 159306c3fb27SDimitry Andric "^FDUP_ZI_[HSD]$")>; 159406c3fb27SDimitry Andric 159506c3fb27SDimitry Andric// Floating point divide, F16 159606c3fb27SDimitry Andricdef : InstRW<[V1Write_13c10_1V0], (instregex "^FDIVR?_ZPmZ_H$")>; 159706c3fb27SDimitry Andric 159806c3fb27SDimitry Andric// Floating point divide, F32 159906c3fb27SDimitry Andricdef : InstRW<[V1Write_10c7_1V0], (instregex "^FDIVR?_ZPmZ_S$")>; 160006c3fb27SDimitry Andric 160106c3fb27SDimitry Andric// Floating point divide, F64 160206c3fb27SDimitry Andricdef : InstRW<[V1Write_15c7_1V0], (instregex "^FDIVR?_ZPmZ_D$")>; 160306c3fb27SDimitry Andric 160406c3fb27SDimitry Andric// Floating point min/max 160506c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1V01], (instregex "^F(MAX|MIN)(NM)?_ZPm[IZ]_[HSD]$")>; 160606c3fb27SDimitry Andric 160706c3fb27SDimitry Andric// Floating point multiply 160806c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1V01], (instregex "^F(SCALE|MULX)_ZPmZ_[HSD]$", 160906c3fb27SDimitry Andric "^FMUL_(ZPm[IZ]|ZZZI?)_[HSD]$")>; 161006c3fb27SDimitry Andric 161106c3fb27SDimitry Andric// Floating point multiply accumulate 161206c3fb27SDimitry Andric// Floating point reciprocal step 161306c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_1V01], (instregex "^F(N?M(AD|SB)|N?ML[AS])_ZPmZZ_[HSD]$", 161406c3fb27SDimitry Andric "^FML[AS]_ZZZI_[HSD]$", 161506c3fb27SDimitry Andric "^F(RECPS|RSQRTS)_ZZZ_[HSD]$")>; 161606c3fb27SDimitry Andric 161706c3fb27SDimitry Andric// Floating point reciprocal estimate, F16 161806c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_4V0], (instrs FRECPE_ZZ_H, FRSQRTE_ZZ_H)>; 161906c3fb27SDimitry Andric 162006c3fb27SDimitry Andric// Floating point reciprocal estimate, F32 162106c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_2V0], (instrs FRECPE_ZZ_S, FRSQRTE_ZZ_S)>; 162206c3fb27SDimitry Andric 162306c3fb27SDimitry Andric// Floating point reciprocal estimate, F64 162406c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1V0], (instrs FRECPE_ZZ_D, FRSQRTE_ZZ_D)>; 162506c3fb27SDimitry Andric 162606c3fb27SDimitry Andric// Floating point reciprocal exponent 162706c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1V0], (instregex "^FRECPX_ZPmZ_[HSD]$")>; 162806c3fb27SDimitry Andric 162906c3fb27SDimitry Andric// Floating point reduction, F16 163006c3fb27SDimitry Andricdef : InstRW<[V1Write_13c_6V01], (instregex "^F(ADD|((MAX|MIN)(NM)?))V_VPZ_H$")>; 163106c3fb27SDimitry Andric 163206c3fb27SDimitry Andric// Floating point reduction, F32 163306c3fb27SDimitry Andricdef : InstRW<[V1Write_11c_1V_5V01], (instregex "^F(ADD|((MAX|MIN)(NM)?))V_VPZ_S$")>; 163406c3fb27SDimitry Andric 163506c3fb27SDimitry Andric// Floating point reduction, F64 163606c3fb27SDimitry Andricdef : InstRW<[V1Write_9c_1V_4V01], (instregex "^F(ADD|((MAX|MIN)(NM)?))V_VPZ_D$")>; 163706c3fb27SDimitry Andric 163806c3fb27SDimitry Andric// Floating point round to integral, F16 163906c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_1V0], (instregex "^FRINT[AIMNPXZ]_ZPmZ_H$")>; 164006c3fb27SDimitry Andric 164106c3fb27SDimitry Andric// Floating point round to integral, F32 164206c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_1V0], (instregex "^FRINT[AIMNPXZ]_ZPmZ_S$")>; 164306c3fb27SDimitry Andric 164406c3fb27SDimitry Andric// Floating point round to integral, F64 164506c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1V0], (instregex "^FRINT[AIMNPXZ]_ZPmZ_D$")>; 164606c3fb27SDimitry Andric 164706c3fb27SDimitry Andric// Floating point square root, F16 164806c3fb27SDimitry Andricdef : InstRW<[V1Write_13c10_1V0], (instrs FSQRT_ZPmZ_H)>; 164906c3fb27SDimitry Andric 165006c3fb27SDimitry Andric// Floating point square root, F32 165106c3fb27SDimitry Andricdef : InstRW<[V1Write_10c7_1V0], (instrs FSQRT_ZPmZ_S)>; 165206c3fb27SDimitry Andric 165306c3fb27SDimitry Andric// Floating point square root, F64 165406c3fb27SDimitry Andricdef : InstRW<[V1Write_16c7_1V0], (instrs FSQRT_ZPmZ_D)>; 165506c3fb27SDimitry Andric 165606c3fb27SDimitry Andric// Floating point trigonometric 165706c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1V01], (instregex "^FEXPA_ZZ_[HSD]$", 165806c3fb27SDimitry Andric "^FTMAD_ZZI_[HSD]$", 165906c3fb27SDimitry Andric "^FTS(MUL|SEL)_ZZZ_[HSD]$")>; 166006c3fb27SDimitry Andric 166106c3fb27SDimitry Andric 166206c3fb27SDimitry Andric// SVE BFloat16 (BF16) instructions 166306c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 166406c3fb27SDimitry Andric 166506c3fb27SDimitry Andric// Convert, F32 to BF16 166606c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_1V0], (instrs BFCVT_ZPmZ, BFCVTNT_ZPmZ)>; 166706c3fb27SDimitry Andric 166806c3fb27SDimitry Andric// Dot product 166906c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_1V01], (instrs BFDOT_ZZI, BFDOT_ZZZ)>; 167006c3fb27SDimitry Andric 167106c3fb27SDimitry Andric// Matrix multiply accumulate 167206c3fb27SDimitry Andricdef : InstRW<[V1Write_5c_1V01], (instrs BFMMLA_ZZZ)>; 167306c3fb27SDimitry Andric 167406c3fb27SDimitry Andric// Multiply accumulate long 167506c3fb27SDimitry Andricdef : InstRW<[V1Write_5c_1V01], (instregex "^BFMLAL[BT]_ZZZ(I)?$")>; 167606c3fb27SDimitry Andric 167706c3fb27SDimitry Andric 167806c3fb27SDimitry Andric// SVE Load instructions 167906c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 168006c3fb27SDimitry Andric 168106c3fb27SDimitry Andric// Load vector 168206c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_1L01], (instrs LDR_ZXI)>; 168306c3fb27SDimitry Andric 168406c3fb27SDimitry Andric// Load predicate 168506c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_1L_1M], (instrs LDR_PXI)>; 168606c3fb27SDimitry Andric 168706c3fb27SDimitry Andric// Contiguous load, scalar + imm 168806c3fb27SDimitry Andric// Contiguous load, scalar + scalar 168906c3fb27SDimitry Andric// Contiguous load broadcast, scalar + imm 169006c3fb27SDimitry Andric// Contiguous load broadcast, scalar + scalar 16915f757f3fSDimitry Andricdef : InstRW<[V1Write_6c_1L01], (instregex "^LD1[BHWD]_IMM$", 16925f757f3fSDimitry Andric "^LD1S?B_[HSD]_IMM$", 16935f757f3fSDimitry Andric "^LD1S?H_[SD]_IMM$", 16945f757f3fSDimitry Andric "^LD1S?W_D_IMM$", 169506c3fb27SDimitry Andric "^LD1[BWD]$", 169606c3fb27SDimitry Andric "^LD1S?B_[HSD]$", 169706c3fb27SDimitry Andric "^LD1S?W_D$", 169806c3fb27SDimitry Andric "^LD1R[BHWD]_IMM$", 169906c3fb27SDimitry Andric "^LD1RSW_IMM$", 170006c3fb27SDimitry Andric "^LD1RS?B_[HSD]_IMM$", 170106c3fb27SDimitry Andric "^LD1RS?H_[SD]_IMM$", 170206c3fb27SDimitry Andric "^LD1RS?W_D_IMM$", 170306c3fb27SDimitry Andric "^LD1RQ_[BHWD]_IMM$", 170406c3fb27SDimitry Andric "^LD1RQ_[BWD]$")>; 170506c3fb27SDimitry Andricdef : InstRW<[V1Write_7c_1L01_1S], (instregex "^LD1H$", 170606c3fb27SDimitry Andric "^LD1S?H_[SD]$", 170706c3fb27SDimitry Andric "^LD1RQ_H$")>; 170806c3fb27SDimitry Andric 170906c3fb27SDimitry Andric// Non temporal load, scalar + imm 171006c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_1L01], (instregex "^LDNT1[BHWD]_ZRI$")>; 171106c3fb27SDimitry Andric 171206c3fb27SDimitry Andric// Non temporal load, scalar + scalar 171306c3fb27SDimitry Andricdef : InstRW<[V1Write_7c_1L01_1S], (instrs LDNT1H_ZRR)>; 171406c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_1L01_1S], (instregex "^LDNT1[BWD]_ZRR$")>; 171506c3fb27SDimitry Andric 171606c3fb27SDimitry Andric// Contiguous first faulting load, scalar + scalar 171706c3fb27SDimitry Andricdef : InstRW<[V1Write_7c_1L01_1S], (instregex "^LDFF1H_REAL$", 171806c3fb27SDimitry Andric "^LDFF1S?H_[SD]_REAL$")>; 171906c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_1L01_1S], (instregex "^LDFF1[BWD]_REAL$", 172006c3fb27SDimitry Andric "^LDFF1S?B_[HSD]_REAL$", 172106c3fb27SDimitry Andric "^LDFF1S?W_D_REAL$")>; 172206c3fb27SDimitry Andric 172306c3fb27SDimitry Andric// Contiguous non faulting load, scalar + imm 172406c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_1L01], (instregex "^LDNF1[BHWD]_IMM_REAL$", 172506c3fb27SDimitry Andric "^LDNF1S?B_[HSD]_IMM_REAL$", 172606c3fb27SDimitry Andric "^LDNF1S?H_[SD]_IMM_REAL$", 172706c3fb27SDimitry Andric "^LDNF1S?W_D_IMM_REAL$")>; 172806c3fb27SDimitry Andric 172906c3fb27SDimitry Andric// Contiguous Load two structures to two vectors, scalar + imm 173006c3fb27SDimitry Andricdef : InstRW<[V1Write_8c_2L01_2V01], (instregex "^LD2[BHWD]_IMM$")>; 173106c3fb27SDimitry Andric 173206c3fb27SDimitry Andric// Contiguous Load two structures to two vectors, scalar + scalar 173306c3fb27SDimitry Andricdef : InstRW<[V1Write_10c_2L01_2V01], (instrs LD2H)>; 173406c3fb27SDimitry Andricdef : InstRW<[V1Write_9c_2L01_2V01], (instregex "^LD2[BWD]$")>; 173506c3fb27SDimitry Andric 173606c3fb27SDimitry Andric// Contiguous Load three structures to three vectors, scalar + imm 173706c3fb27SDimitry Andricdef : InstRW<[V1Write_11c_3L01_3V01], (instregex "^LD3[BHWD]_IMM$")>; 173806c3fb27SDimitry Andric 173906c3fb27SDimitry Andric// Contiguous Load three structures to three vectors, scalar + scalar 174006c3fb27SDimitry Andricdef : InstRW<[V1Write_13c_3L01_1S_3V01], (instregex "^LD3[BHWD]$")>; 174106c3fb27SDimitry Andric 174206c3fb27SDimitry Andric// Contiguous Load four structures to four vectors, scalar + imm 174306c3fb27SDimitry Andricdef : InstRW<[V1Write_12c_4L01_4V01], (instregex "^LD4[BHWD]_IMM$")>; 174406c3fb27SDimitry Andric 174506c3fb27SDimitry Andric// Contiguous Load four structures to four vectors, scalar + scalar 174606c3fb27SDimitry Andricdef : InstRW<[V1Write_13c_4L01_2S_4V01], (instregex "^LD4[BHWD]$")>; 174706c3fb27SDimitry Andric 174806c3fb27SDimitry Andric// Gather load, vector + imm, 32-bit element size 174906c3fb27SDimitry Andricdef : InstRW<[V1Write_11c_1L_1V], (instregex "^GLD(FF)?1S?[BH]_S_IMM_REAL$", 175006c3fb27SDimitry Andric "^GLD(FF)?1W_IMM_REAL$")>; 175106c3fb27SDimitry Andric 175206c3fb27SDimitry Andric// Gather load, vector + imm, 64-bit element size 175306c3fb27SDimitry Andricdef : InstRW<[V1Write_9c_2L_2V], 175406c3fb27SDimitry Andric (instregex "^GLD(FF)?1S?[BHW]_D_IMM_REAL$", 175506c3fb27SDimitry Andric "^GLD(FF)?1S?[BHW]_D_([SU]XTW_)?(SCALED_)?REAL$", 175606c3fb27SDimitry Andric "^GLD(FF)?1D_IMM_REAL$", 175706c3fb27SDimitry Andric "^GLD(FF)?1D_([SU]XTW_)?(SCALED_)?REAL$")>; 175806c3fb27SDimitry Andric 175906c3fb27SDimitry Andric// Gather load, 32-bit scaled offset 176006c3fb27SDimitry Andricdef : InstRW<[V1Write_11c_2L_2V], 176106c3fb27SDimitry Andric (instregex "^GLD(FF)?1S?[HW]_S_[SU]XTW_SCALED_REAL$", 176206c3fb27SDimitry Andric "^GLD(FF)?1W_[SU]XTW_SCALED_REAL")>; 176306c3fb27SDimitry Andric 176406c3fb27SDimitry Andric// Gather load, 32-bit unpacked unscaled offset 176506c3fb27SDimitry Andricdef : InstRW<[V1Write_9c_1L_1V], 176606c3fb27SDimitry Andric (instregex "^GLD(FF)?1S?[BH]_S_[SU]XTW_REAL$", 176706c3fb27SDimitry Andric "^GLD(FF)?1W_[SU]XTW_REAL$")>; 176806c3fb27SDimitry Andric 176906c3fb27SDimitry Andric// Prefetch 177006c3fb27SDimitry Andric// NOTE: This is not specified in the SOG. 177106c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_1L01], (instregex "^PRF[BHWD]")>; 177206c3fb27SDimitry Andric 177306c3fb27SDimitry Andric 177406c3fb27SDimitry Andric// SVE Store instructions 177506c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 177606c3fb27SDimitry Andric 177706c3fb27SDimitry Andric// Store from predicate reg 177806c3fb27SDimitry Andricdef : InstRW<[V1Write_1c_1L01], (instrs STR_PXI)>; 177906c3fb27SDimitry Andric 178006c3fb27SDimitry Andric// Store from vector reg 178106c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1L01_1V], (instrs STR_ZXI)>; 178206c3fb27SDimitry Andric 178306c3fb27SDimitry Andric// Contiguous store, scalar + imm 178406c3fb27SDimitry Andric// Contiguous store, scalar + scalar 178506c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1L01_1V], (instregex "^ST1[BHWD]_IMM$", 178606c3fb27SDimitry Andric "^ST1B_[HSD]_IMM$", 178706c3fb27SDimitry Andric "^ST1H_[SD]_IMM$", 178806c3fb27SDimitry Andric "^ST1W_D_IMM$", 178906c3fb27SDimitry Andric "^ST1[BWD]$", 179006c3fb27SDimitry Andric "^ST1B_[HSD]$", 179106c3fb27SDimitry Andric "^ST1W_D$")>; 179206c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1L01_1S_1V], (instregex "^ST1H(_[SD])?$")>; 179306c3fb27SDimitry Andric 179406c3fb27SDimitry Andric// Contiguous store two structures from two vectors, scalar + imm 179506c3fb27SDimitry Andric// Contiguous store two structures from two vectors, scalar + scalar 179606c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_1L01_1V], (instregex "^ST2[BHWD]_IMM$", 179706c3fb27SDimitry Andric "^ST2[BWD]$")>; 179806c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_1L01_1S_1V], (instrs ST2H)>; 179906c3fb27SDimitry Andric 180006c3fb27SDimitry Andric// Contiguous store three structures from three vectors, scalar + imm 180106c3fb27SDimitry Andricdef : InstRW<[V1Write_7c_5L01_5V], (instregex "^ST3[BHWD]_IMM$")>; 180206c3fb27SDimitry Andric 180306c3fb27SDimitry Andric// Contiguous store three structures from three vectors, scalar + scalar 180406c3fb27SDimitry Andricdef : InstRW<[V1Write_7c_5L01_5S_5V], (instregex "^ST3[BHWD]$")>; 180506c3fb27SDimitry Andric 180606c3fb27SDimitry Andric// Contiguous store four structures from four vectors, scalar + imm 180706c3fb27SDimitry Andricdef : InstRW<[V1Write_11c_9L01_9V], (instregex "^ST4[BHWD]_IMM$")>; 180806c3fb27SDimitry Andric 180906c3fb27SDimitry Andric// Contiguous store four structures from four vectors, scalar + scalar 181006c3fb27SDimitry Andricdef : InstRW<[V1Write_11c_9L01_9S_9V], (instregex "^ST4[BHWD]$")>; 181106c3fb27SDimitry Andric 181206c3fb27SDimitry Andric// Non temporal store, scalar + imm 181306c3fb27SDimitry Andric// Non temporal store, scalar + scalar 181406c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1L01_1V], (instregex "^STNT1[BHWD]_ZRI$", 181506c3fb27SDimitry Andric "^STNT1[BWD]_ZRR$")>; 181606c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1L01_1S_1V], (instrs STNT1H_ZRR)>; 181706c3fb27SDimitry Andric 181806c3fb27SDimitry Andric// Scatter store vector + imm 32-bit element size 181906c3fb27SDimitry Andric// Scatter store, 32-bit scaled offset 182006c3fb27SDimitry Andric// Scatter store, 32-bit unscaled offset 182106c3fb27SDimitry Andricdef : InstRW<[V1Write_10c_2L01_2V], (instregex "^SST1[BH]_S_IMM$", 182206c3fb27SDimitry Andric "^SST1W_IMM$", 182306c3fb27SDimitry Andric "^SST1(H_S|W)_[SU]XTW_SCALED$", 182406c3fb27SDimitry Andric "^SST1[BH]_S_[SU]XTW$", 182506c3fb27SDimitry Andric "^SST1W_[SU]XTW$")>; 182606c3fb27SDimitry Andric 182706c3fb27SDimitry Andric// Scatter store, 32-bit unpacked unscaled offset 182806c3fb27SDimitry Andric// Scatter store, 32-bit unpacked scaled offset 182906c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_1L01_1V], (instregex "^SST1[BHW]_D_[SU]XTW$", 183006c3fb27SDimitry Andric "^SST1D_[SU]XTW$", 183106c3fb27SDimitry Andric "^SST1[HW]_D_[SU]XTW_SCALED$", 183206c3fb27SDimitry Andric "^SST1D_[SU]XTW_SCALED$")>; 183306c3fb27SDimitry Andric 183406c3fb27SDimitry Andric// Scatter store vector + imm 64-bit element size 183506c3fb27SDimitry Andric// Scatter store, 64-bit scaled offset 183606c3fb27SDimitry Andric// Scatter store, 64-bit unscaled offset 183706c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_1L01_1V], (instregex "^SST1[BHW]_D_IMM$", 183806c3fb27SDimitry Andric "^SST1D_IMM$", 183906c3fb27SDimitry Andric "^SST1[HW]_D_SCALED$", 184006c3fb27SDimitry Andric "^SST1D_SCALED$", 184106c3fb27SDimitry Andric "^SST1[BHW]_D$", 184206c3fb27SDimitry Andric "^SST1D$")>; 184306c3fb27SDimitry Andric 184406c3fb27SDimitry Andric 184506c3fb27SDimitry Andric// SVE Miscellaneous instructions 184606c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 184706c3fb27SDimitry Andric 184806c3fb27SDimitry Andric// Read first fault register, unpredicated 184906c3fb27SDimitry Andric// Set first fault register 185006c3fb27SDimitry Andric// Write to first fault register 185106c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1M0], (instrs RDFFR_P_REAL, 185206c3fb27SDimitry Andric SETFFR, 185306c3fb27SDimitry Andric WRFFR)>; 185406c3fb27SDimitry Andric 185506c3fb27SDimitry Andric// Read first fault register, predicated 185606c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_2M0], (instrs RDFFR_PPz_REAL)>; 185706c3fb27SDimitry Andric 185806c3fb27SDimitry Andric// Read first fault register and set flags 185906c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_1M], (instrs RDFFRS_PPz)>; 186006c3fb27SDimitry Andric 186106c3fb27SDimitry Andric 186206c3fb27SDimitry Andric} 1863