1*06c3fb27SDimitry Andric//=- AArch64SchedNeoverseV1.td - NeoverseV1 Scheduling Model -*- tablegen -*-=// 2*06c3fb27SDimitry Andric// 3*06c3fb27SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*06c3fb27SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 5*06c3fb27SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*06c3fb27SDimitry Andric// 7*06c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 8*06c3fb27SDimitry Andric// 9*06c3fb27SDimitry Andric// This file defines the scheduling model for the Arm Neoverse V1 processors. 10*06c3fb27SDimitry Andric// 11*06c3fb27SDimitry Andric// References: 12*06c3fb27SDimitry Andric// - "Arm Neoverse V1 Software Optimization Guide" 13*06c3fb27SDimitry Andric// - "Arm Neoverse V1 Platform: Unleashing a new performance tier for Arm-based computing" 14*06c3fb27SDimitry Andric// https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/neoverse-v1-platform-a-new-performance-tier-for-arm 15*06c3fb27SDimitry Andric// - "Neoverse V1" 16*06c3fb27SDimitry Andric// https://en.wikichip.org/wiki/arm_holdings/microarchitectures/neoverse_v1 17*06c3fb27SDimitry Andric 18*06c3fb27SDimitry Andric// 19*06c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 20*06c3fb27SDimitry Andric 21*06c3fb27SDimitry Andricdef NeoverseV1Model : SchedMachineModel { 22*06c3fb27SDimitry Andric let IssueWidth = 15; // Maximum micro-ops dispatch rate. 23*06c3fb27SDimitry Andric let MicroOpBufferSize = 256; // Micro-op re-order buffer. 24*06c3fb27SDimitry Andric let LoadLatency = 4; // Optimistic load latency. 25*06c3fb27SDimitry Andric let MispredictPenalty = 11; // Cycles cost of branch mispredicted. 26*06c3fb27SDimitry Andric let LoopMicroOpBufferSize = 16; // NOTE: Copied from Cortex-A57. 27*06c3fb27SDimitry Andric let CompleteModel = 1; 28*06c3fb27SDimitry Andric 29*06c3fb27SDimitry Andric list<Predicate> UnsupportedFeatures = !listconcat(SVE2Unsupported.F, 30*06c3fb27SDimitry Andric SMEUnsupported.F, 31*06c3fb27SDimitry Andric [HasMTE]); 32*06c3fb27SDimitry Andric} 33*06c3fb27SDimitry Andric 34*06c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 35*06c3fb27SDimitry Andric// Define each kind of processor resource and number available on Neoverse V1. 36*06c3fb27SDimitry Andric// Instructions are first fetched and then decoded into internal macro-ops 37*06c3fb27SDimitry Andric// (MOPs). From there, the MOPs proceed through register renaming and dispatch 38*06c3fb27SDimitry Andric// stages. A MOP can be split into one or more micro-ops further down the 39*06c3fb27SDimitry Andric// pipeline, after the decode stage. Once dispatched, micro-ops wait for their 40*06c3fb27SDimitry Andric// operands and issue out-of-order to one of the issue pipelines. Each issue 41*06c3fb27SDimitry Andric// pipeline can accept one micro-op per cycle. 42*06c3fb27SDimitry Andric 43*06c3fb27SDimitry Andriclet SchedModel = NeoverseV1Model in { 44*06c3fb27SDimitry Andric 45*06c3fb27SDimitry Andric// Define the issue ports. 46*06c3fb27SDimitry Andricdef V1UnitB : ProcResource<2>; // Branch 0/1 47*06c3fb27SDimitry Andricdef V1UnitS : ProcResource<2>; // Integer single cycle 0/1 48*06c3fb27SDimitry Andricdef V1UnitM0 : ProcResource<1>; // Integer multicycle 0 49*06c3fb27SDimitry Andricdef V1UnitM1 : ProcResource<1>; // Integer multicycle 1 50*06c3fb27SDimitry Andricdef V1UnitL01 : ProcResource<2>; // Load/Store 0/1 51*06c3fb27SDimitry Andricdef V1UnitL2 : ProcResource<1>; // Load 2 52*06c3fb27SDimitry Andricdef V1UnitD : ProcResource<2>; // Store data 0/1 53*06c3fb27SDimitry Andricdef V1UnitV0 : ProcResource<1>; // FP/ASIMD 0 54*06c3fb27SDimitry Andricdef V1UnitV1 : ProcResource<1>; // FP/ASIMD 1 55*06c3fb27SDimitry Andricdef V1UnitV2 : ProcResource<1>; // FP/ASIMD 2 56*06c3fb27SDimitry Andricdef V1UnitV3 : ProcResource<1>; // FP/ASIMD 3 57*06c3fb27SDimitry Andric 58*06c3fb27SDimitry Andricdef V1UnitI : ProcResGroup<[V1UnitS, 59*06c3fb27SDimitry Andric V1UnitM0, V1UnitM1]>; // Integer units 60*06c3fb27SDimitry Andricdef V1UnitJ : ProcResGroup<[V1UnitS, V1UnitM0]>; // Integer 0-2 units 61*06c3fb27SDimitry Andricdef V1UnitM : ProcResGroup<[V1UnitM0, V1UnitM1]>; // Integer multicycle units 62*06c3fb27SDimitry Andricdef V1UnitL : ProcResGroup<[V1UnitL01, V1UnitL2]>; // Load units 63*06c3fb27SDimitry Andricdef V1UnitV : ProcResGroup<[V1UnitV0, V1UnitV1, 64*06c3fb27SDimitry Andric V1UnitV2, V1UnitV3]>; // FP/ASIMD units 65*06c3fb27SDimitry Andricdef V1UnitV01 : ProcResGroup<[V1UnitV0, V1UnitV1]>; // FP/ASIMD 0/1 units 66*06c3fb27SDimitry Andricdef V1UnitV02 : ProcResGroup<[V1UnitV0, V1UnitV2]>; // FP/ASIMD 0/2 units 67*06c3fb27SDimitry Andricdef V1UnitV13 : ProcResGroup<[V1UnitV1, V1UnitV3]>; // FP/ASIMD 1/3 units 68*06c3fb27SDimitry Andric 69*06c3fb27SDimitry Andric// Define commonly used read types. 70*06c3fb27SDimitry Andric 71*06c3fb27SDimitry Andric// No generic forwarding is provided for these types. 72*06c3fb27SDimitry Andricdef : ReadAdvance<ReadI, 0>; 73*06c3fb27SDimitry Andricdef : ReadAdvance<ReadISReg, 0>; 74*06c3fb27SDimitry Andricdef : ReadAdvance<ReadIEReg, 0>; 75*06c3fb27SDimitry Andricdef : ReadAdvance<ReadIM, 0>; 76*06c3fb27SDimitry Andricdef : ReadAdvance<ReadIMA, 0>; 77*06c3fb27SDimitry Andricdef : ReadAdvance<ReadID, 0>; 78*06c3fb27SDimitry Andricdef : ReadAdvance<ReadExtrHi, 0>; 79*06c3fb27SDimitry Andricdef : ReadAdvance<ReadAdrBase, 0>; 80*06c3fb27SDimitry Andricdef : ReadAdvance<ReadST, 0>; 81*06c3fb27SDimitry Andricdef : ReadAdvance<ReadVLD, 0>; 82*06c3fb27SDimitry Andric 83*06c3fb27SDimitry Andricdef : WriteRes<WriteAtomic, []> { let Unsupported = 1; } 84*06c3fb27SDimitry Andricdef : WriteRes<WriteBarrier, []> { let Latency = 1; } 85*06c3fb27SDimitry Andricdef : WriteRes<WriteHint, []> { let Latency = 1; } 86*06c3fb27SDimitry Andric 87*06c3fb27SDimitry Andric 88*06c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 89*06c3fb27SDimitry Andric// Define generic 0 micro-op types 90*06c3fb27SDimitry Andric 91*06c3fb27SDimitry Andriclet Latency = 0, NumMicroOps = 0 in 92*06c3fb27SDimitry Andricdef V1Write_0c_0Z : SchedWriteRes<[]>; 93*06c3fb27SDimitry Andric 94*06c3fb27SDimitry Andric 95*06c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 96*06c3fb27SDimitry Andric// Define generic 1 micro-op types 97*06c3fb27SDimitry Andric 98*06c3fb27SDimitry Andricdef V1Write_1c_1B : SchedWriteRes<[V1UnitB]> { let Latency = 1; } 99*06c3fb27SDimitry Andricdef V1Write_1c_1I : SchedWriteRes<[V1UnitI]> { let Latency = 1; } 100*06c3fb27SDimitry Andricdef V1Write_1c_1J : SchedWriteRes<[V1UnitJ]> { let Latency = 1; } 101*06c3fb27SDimitry Andricdef V1Write_4c_1L : SchedWriteRes<[V1UnitL]> { let Latency = 4; } 102*06c3fb27SDimitry Andricdef V1Write_6c_1L : SchedWriteRes<[V1UnitL]> { let Latency = 6; } 103*06c3fb27SDimitry Andricdef V1Write_1c_1L01 : SchedWriteRes<[V1UnitL01]> { let Latency = 1; } 104*06c3fb27SDimitry Andricdef V1Write_4c_1L01 : SchedWriteRes<[V1UnitL01]> { let Latency = 4; } 105*06c3fb27SDimitry Andricdef V1Write_6c_1L01 : SchedWriteRes<[V1UnitL01]> { let Latency = 6; } 106*06c3fb27SDimitry Andricdef V1Write_2c_1M : SchedWriteRes<[V1UnitM]> { let Latency = 2; } 107*06c3fb27SDimitry Andricdef V1Write_3c_1M : SchedWriteRes<[V1UnitM]> { let Latency = 3; } 108*06c3fb27SDimitry Andricdef V1Write_4c_1M : SchedWriteRes<[V1UnitM]> { let Latency = 4; } 109*06c3fb27SDimitry Andricdef V1Write_1c_1M0 : SchedWriteRes<[V1UnitM0]> { let Latency = 1; } 110*06c3fb27SDimitry Andricdef V1Write_2c_1M0 : SchedWriteRes<[V1UnitM0]> { let Latency = 2; } 111*06c3fb27SDimitry Andricdef V1Write_3c_1M0 : SchedWriteRes<[V1UnitM0]> { let Latency = 3; } 112*06c3fb27SDimitry Andricdef V1Write_5c_1M0 : SchedWriteRes<[V1UnitM0]> { let Latency = 5; } 113*06c3fb27SDimitry Andricdef V1Write_12c5_1M0 : SchedWriteRes<[V1UnitM0]> { let Latency = 12; 114*06c3fb27SDimitry Andric let ResourceCycles = [5]; } 115*06c3fb27SDimitry Andricdef V1Write_20c5_1M0 : SchedWriteRes<[V1UnitM0]> { let Latency = 20; 116*06c3fb27SDimitry Andric let ResourceCycles = [5]; } 117*06c3fb27SDimitry Andricdef V1Write_2c_1V : SchedWriteRes<[V1UnitV]> { let Latency = 2; } 118*06c3fb27SDimitry Andricdef V1Write_3c_1V : SchedWriteRes<[V1UnitV]> { let Latency = 3; } 119*06c3fb27SDimitry Andricdef V1Write_4c_1V : SchedWriteRes<[V1UnitV]> { let Latency = 4; } 120*06c3fb27SDimitry Andricdef V1Write_5c_1V : SchedWriteRes<[V1UnitV]> { let Latency = 5; } 121*06c3fb27SDimitry Andricdef V1Write_2c_1V0 : SchedWriteRes<[V1UnitV0]> { let Latency = 2; } 122*06c3fb27SDimitry Andricdef V1Write_3c_1V0 : SchedWriteRes<[V1UnitV0]> { let Latency = 3; } 123*06c3fb27SDimitry Andricdef V1Write_4c_1V0 : SchedWriteRes<[V1UnitV0]> { let Latency = 4; } 124*06c3fb27SDimitry Andricdef V1Write_6c_1V0 : SchedWriteRes<[V1UnitV0]> { let Latency = 6; } 125*06c3fb27SDimitry Andricdef V1Write_10c7_1V0 : SchedWriteRes<[V1UnitV0]> { let Latency = 10; 126*06c3fb27SDimitry Andric let ResourceCycles = [7]; } 127*06c3fb27SDimitry Andricdef V1Write_12c7_1V0 : SchedWriteRes<[V1UnitV0]> { let Latency = 12; 128*06c3fb27SDimitry Andric let ResourceCycles = [7]; } 129*06c3fb27SDimitry Andricdef V1Write_13c10_1V0 : SchedWriteRes<[V1UnitV0]> { let Latency = 13; 130*06c3fb27SDimitry Andric let ResourceCycles = [10]; } 131*06c3fb27SDimitry Andricdef V1Write_15c7_1V0 : SchedWriteRes<[V1UnitV0]> { let Latency = 15; 132*06c3fb27SDimitry Andric let ResourceCycles = [7]; } 133*06c3fb27SDimitry Andricdef V1Write_16c7_1V0 : SchedWriteRes<[V1UnitV0]> { let Latency = 16; 134*06c3fb27SDimitry Andric let ResourceCycles = [7]; } 135*06c3fb27SDimitry Andricdef V1Write_20c7_1V0 : SchedWriteRes<[V1UnitV0]> { let Latency = 20; 136*06c3fb27SDimitry Andric let ResourceCycles = [7]; } 137*06c3fb27SDimitry Andricdef V1Write_2c_1V01 : SchedWriteRes<[V1UnitV01]> { let Latency = 2; } 138*06c3fb27SDimitry Andricdef V1Write_3c_1V01 : SchedWriteRes<[V1UnitV01]> { let Latency = 3; } 139*06c3fb27SDimitry Andricdef V1Write_4c_1V01 : SchedWriteRes<[V1UnitV01]> { let Latency = 4; } 140*06c3fb27SDimitry Andricdef V1Write_5c_1V01 : SchedWriteRes<[V1UnitV01]> { let Latency = 5; } 141*06c3fb27SDimitry Andricdef V1Write_3c_1V02 : SchedWriteRes<[V1UnitV02]> { let Latency = 3; } 142*06c3fb27SDimitry Andricdef V1Write_4c_1V02 : SchedWriteRes<[V1UnitV02]> { let Latency = 4; } 143*06c3fb27SDimitry Andricdef V1Write_7c7_1V02 : SchedWriteRes<[V1UnitV02]> { let Latency = 7; 144*06c3fb27SDimitry Andric let ResourceCycles = [7]; } 145*06c3fb27SDimitry Andricdef V1Write_10c7_1V02 : SchedWriteRes<[V1UnitV02]> { let Latency = 10; 146*06c3fb27SDimitry Andric let ResourceCycles = [7]; } 147*06c3fb27SDimitry Andricdef V1Write_13c5_1V02 : SchedWriteRes<[V1UnitV02]> { let Latency = 13; 148*06c3fb27SDimitry Andric let ResourceCycles = [5]; } 149*06c3fb27SDimitry Andricdef V1Write_13c11_1V02 : SchedWriteRes<[V1UnitV02]> { let Latency = 13; 150*06c3fb27SDimitry Andric let ResourceCycles = [11]; } 151*06c3fb27SDimitry Andricdef V1Write_15c7_1V02 : SchedWriteRes<[V1UnitV02]> { let Latency = 15; 152*06c3fb27SDimitry Andric let ResourceCycles = [7]; } 153*06c3fb27SDimitry Andricdef V1Write_16c7_1V02 : SchedWriteRes<[V1UnitV02]> { let Latency = 16; 154*06c3fb27SDimitry Andric let ResourceCycles = [7]; } 155*06c3fb27SDimitry Andricdef V1Write_2c_1V1 : SchedWriteRes<[V1UnitV1]> { let Latency = 2; } 156*06c3fb27SDimitry Andricdef V1Write_3c_1V1 : SchedWriteRes<[V1UnitV1]> { let Latency = 3; } 157*06c3fb27SDimitry Andricdef V1Write_4c_1V1 : SchedWriteRes<[V1UnitV1]> { let Latency = 4; } 158*06c3fb27SDimitry Andricdef V1Write_2c_1V13 : SchedWriteRes<[V1UnitV13]> { let Latency = 2; } 159*06c3fb27SDimitry Andricdef V1Write_4c_1V13 : SchedWriteRes<[V1UnitV13]> { let Latency = 4; } 160*06c3fb27SDimitry Andric 161*06c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 162*06c3fb27SDimitry Andric// Define generic 2 micro-op types 163*06c3fb27SDimitry Andric 164*06c3fb27SDimitry Andriclet Latency = 1, NumMicroOps = 2 in 165*06c3fb27SDimitry Andricdef V1Write_1c_1B_1S : SchedWriteRes<[V1UnitB, V1UnitS]>; 166*06c3fb27SDimitry Andriclet Latency = 6, NumMicroOps = 2 in 167*06c3fb27SDimitry Andricdef V1Write_6c_1B_1M0 : SchedWriteRes<[V1UnitB, V1UnitM0]>; 168*06c3fb27SDimitry Andriclet Latency = 3, NumMicroOps = 2 in 169*06c3fb27SDimitry Andricdef V1Write_3c_1I_1M : SchedWriteRes<[V1UnitI, V1UnitM]>; 170*06c3fb27SDimitry Andriclet Latency = 5, NumMicroOps = 2 in 171*06c3fb27SDimitry Andricdef V1Write_5c_1I_1L : SchedWriteRes<[V1UnitI, V1UnitL]>; 172*06c3fb27SDimitry Andriclet Latency = 7, NumMicroOps = 2 in 173*06c3fb27SDimitry Andricdef V1Write_7c_1I_1L : SchedWriteRes<[V1UnitI, V1UnitL]>; 174*06c3fb27SDimitry Andriclet Latency = 6, NumMicroOps = 2 in 175*06c3fb27SDimitry Andricdef V1Write_6c_2L : SchedWriteRes<[V1UnitL, V1UnitL]>; 176*06c3fb27SDimitry Andriclet Latency = 6, NumMicroOps = 2 in 177*06c3fb27SDimitry Andricdef V1Write_6c_1L_1M : SchedWriteRes<[V1UnitL, V1UnitM]>; 178*06c3fb27SDimitry Andriclet Latency = 8, NumMicroOps = 2 in 179*06c3fb27SDimitry Andricdef V1Write_8c_1L_1V : SchedWriteRes<[V1UnitL, V1UnitV]>; 180*06c3fb27SDimitry Andriclet Latency = 9, NumMicroOps = 2 in 181*06c3fb27SDimitry Andricdef V1Write_9c_1L_1V : SchedWriteRes<[V1UnitL, V1UnitV]>; 182*06c3fb27SDimitry Andriclet Latency = 11, NumMicroOps = 2 in 183*06c3fb27SDimitry Andricdef V1Write_11c_1L_1V : SchedWriteRes<[V1UnitL, V1UnitV]>; 184*06c3fb27SDimitry Andriclet Latency = 1, NumMicroOps = 2 in 185*06c3fb27SDimitry Andricdef V1Write_1c_1L01_1D : SchedWriteRes<[V1UnitL01, V1UnitD]>; 186*06c3fb27SDimitry Andriclet Latency = 6, NumMicroOps = 2 in 187*06c3fb27SDimitry Andricdef V1Write_6c_1L01_1S : SchedWriteRes<[V1UnitL01, V1UnitS]>; 188*06c3fb27SDimitry Andriclet Latency = 7, NumMicroOps = 2 in 189*06c3fb27SDimitry Andricdef V1Write_7c_1L01_1S : SchedWriteRes<[V1UnitL01, V1UnitS]>; 190*06c3fb27SDimitry Andriclet Latency = 2, NumMicroOps = 2 in 191*06c3fb27SDimitry Andricdef V1Write_2c_1L01_1V : SchedWriteRes<[V1UnitL01, V1UnitV]>; 192*06c3fb27SDimitry Andriclet Latency = 4, NumMicroOps = 2 in 193*06c3fb27SDimitry Andricdef V1Write_4c_1L01_1V : SchedWriteRes<[V1UnitL01, V1UnitV]>; 194*06c3fb27SDimitry Andriclet Latency = 6, NumMicroOps = 2 in 195*06c3fb27SDimitry Andricdef V1Write_6c_1L01_1V : SchedWriteRes<[V1UnitL01, V1UnitV]>; 196*06c3fb27SDimitry Andriclet Latency = 2, NumMicroOps = 2 in 197*06c3fb27SDimitry Andricdef V1Write_2c_1L01_1V01 : SchedWriteRes<[V1UnitL01, V1UnitV01]>; 198*06c3fb27SDimitry Andriclet Latency = 4, NumMicroOps = 2 in 199*06c3fb27SDimitry Andricdef V1Write_4c_1L01_1V01 : SchedWriteRes<[V1UnitL01, V1UnitV01]>; 200*06c3fb27SDimitry Andriclet Latency = 2, NumMicroOps = 2 in 201*06c3fb27SDimitry Andricdef V1Write_2c_2M0 : SchedWriteRes<[V1UnitM0, V1UnitM0]>; 202*06c3fb27SDimitry Andriclet Latency = 3, NumMicroOps = 2 in 203*06c3fb27SDimitry Andricdef V1Write_3c_2M0 : SchedWriteRes<[V1UnitM0, V1UnitM0]>; 204*06c3fb27SDimitry Andriclet Latency = 9, NumMicroOps = 2 in 205*06c3fb27SDimitry Andricdef V1Write_9c_1M0_1L : SchedWriteRes<[V1UnitM0, V1UnitL]>; 206*06c3fb27SDimitry Andriclet Latency = 5, NumMicroOps = 2 in 207*06c3fb27SDimitry Andricdef V1Write_5c_1M0_1V : SchedWriteRes<[V1UnitM0, V1UnitV]>; 208*06c3fb27SDimitry Andriclet Latency = 4, NumMicroOps = 2 in 209*06c3fb27SDimitry Andricdef V1Write_4c_1M0_1V0 : SchedWriteRes<[V1UnitM0, V1UnitV0]>; 210*06c3fb27SDimitry Andriclet Latency = 7, NumMicroOps = 2 in 211*06c3fb27SDimitry Andricdef V1Write_7c_1M0_1V0 : SchedWriteRes<[V1UnitM0, V1UnitV1]>; 212*06c3fb27SDimitry Andriclet Latency = 5, NumMicroOps = 2 in 213*06c3fb27SDimitry Andricdef V1Write_5c_1M0_1V01 : SchedWriteRes<[V1UnitM0, V1UnitV01]>; 214*06c3fb27SDimitry Andriclet Latency = 6, NumMicroOps = 2 in 215*06c3fb27SDimitry Andricdef V1Write_6c_1M0_1V1 : SchedWriteRes<[V1UnitM0, V1UnitV1]>; 216*06c3fb27SDimitry Andriclet Latency = 9, NumMicroOps = 2 in 217*06c3fb27SDimitry Andricdef V1Write_9c_1M0_1V1 : SchedWriteRes<[V1UnitM0, V1UnitV1]>; 218*06c3fb27SDimitry Andriclet Latency = 4, NumMicroOps = 2 in 219*06c3fb27SDimitry Andricdef V1Write_4c_2V : SchedWriteRes<[V1UnitV, V1UnitV]>; 220*06c3fb27SDimitry Andriclet Latency = 8, NumMicroOps = 2 in 221*06c3fb27SDimitry Andricdef V1Write_8c_1V_1V01 : SchedWriteRes<[V1UnitV, V1UnitV01]>; 222*06c3fb27SDimitry Andriclet Latency = 4, NumMicroOps = 2 in 223*06c3fb27SDimitry Andricdef V1Write_4c_2V0 : SchedWriteRes<[V1UnitV0, V1UnitV0]>; 224*06c3fb27SDimitry Andriclet Latency = 5, NumMicroOps = 2 in 225*06c3fb27SDimitry Andricdef V1Write_5c_2V0 : SchedWriteRes<[V1UnitV0, V1UnitV0]>; 226*06c3fb27SDimitry Andriclet Latency = 2, NumMicroOps = 2 in 227*06c3fb27SDimitry Andricdef V1Write_2c_2V01 : SchedWriteRes<[V1UnitV01, V1UnitV01]>; 228*06c3fb27SDimitry Andriclet Latency = 4, NumMicroOps = 2 in 229*06c3fb27SDimitry Andricdef V1Write_4c_2V01 : SchedWriteRes<[V1UnitV01, V1UnitV01]>; 230*06c3fb27SDimitry Andriclet Latency = 4, NumMicroOps = 2 in 231*06c3fb27SDimitry Andricdef V1Write_4c_2V02 : SchedWriteRes<[V1UnitV02, V1UnitV02]>; 232*06c3fb27SDimitry Andriclet Latency = 6, NumMicroOps = 2 in 233*06c3fb27SDimitry Andricdef V1Write_6c_2V02 : SchedWriteRes<[V1UnitV02, V1UnitV02]>; 234*06c3fb27SDimitry Andriclet Latency = 4, NumMicroOps = 2 in 235*06c3fb27SDimitry Andricdef V1Write_4c_1V13_1V : SchedWriteRes<[V1UnitV13, V1UnitV]>; 236*06c3fb27SDimitry Andriclet Latency = 4, NumMicroOps = 2 in 237*06c3fb27SDimitry Andricdef V1Write_4c_2V13 : SchedWriteRes<[V1UnitV13, V1UnitV13]>; 238*06c3fb27SDimitry Andric 239*06c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 240*06c3fb27SDimitry Andric// Define generic 3 micro-op types 241*06c3fb27SDimitry Andric 242*06c3fb27SDimitry Andriclet Latency = 2, NumMicroOps = 3 in 243*06c3fb27SDimitry Andricdef V1Write_2c_1I_1L01_1V01 : SchedWriteRes<[V1UnitI, V1UnitL01, V1UnitV01]>; 244*06c3fb27SDimitry Andriclet Latency = 7, NumMicroOps = 3 in 245*06c3fb27SDimitry Andricdef V1Write_7c_2M0_1V01 : SchedWriteRes<[V1UnitM0, V1UnitM0, V1UnitV01]>; 246*06c3fb27SDimitry Andriclet Latency = 8, NumMicroOps = 3 in 247*06c3fb27SDimitry Andricdef V1Write_8c_1L_2V : SchedWriteRes<[V1UnitL, V1UnitV, V1UnitV]>; 248*06c3fb27SDimitry Andriclet Latency = 6, NumMicroOps = 3 in 249*06c3fb27SDimitry Andricdef V1Write_6c_3L : SchedWriteRes<[V1UnitL, V1UnitL, V1UnitL]>; 250*06c3fb27SDimitry Andriclet Latency = 2, NumMicroOps = 3 in 251*06c3fb27SDimitry Andricdef V1Write_2c_1L01_1S_1V : SchedWriteRes<[V1UnitL01, V1UnitS, V1UnitV]>; 252*06c3fb27SDimitry Andriclet Latency = 4, NumMicroOps = 3 in 253*06c3fb27SDimitry Andricdef V1Write_4c_1L01_1S_1V : SchedWriteRes<[V1UnitL01, V1UnitS, V1UnitV]>; 254*06c3fb27SDimitry Andriclet Latency = 2, NumMicroOps = 3 in 255*06c3fb27SDimitry Andricdef V1Write_2c_2L01_1V01 : SchedWriteRes<[V1UnitL01, V1UnitL01, V1UnitV01]>; 256*06c3fb27SDimitry Andriclet Latency = 6, NumMicroOps = 3 in 257*06c3fb27SDimitry Andricdef V1Write_6c_3V : SchedWriteRes<[V1UnitV, V1UnitV, V1UnitV]>; 258*06c3fb27SDimitry Andriclet Latency = 4, NumMicroOps = 3 in 259*06c3fb27SDimitry Andricdef V1Write_4c_3V01 : SchedWriteRes<[V1UnitV01, V1UnitV01, V1UnitV01]>; 260*06c3fb27SDimitry Andriclet Latency = 6, NumMicroOps = 3 in 261*06c3fb27SDimitry Andricdef V1Write_6c_3V01 : SchedWriteRes<[V1UnitV01, V1UnitV01, V1UnitV01]>; 262*06c3fb27SDimitry Andriclet Latency = 8, NumMicroOps = 3 in 263*06c3fb27SDimitry Andricdef V1Write_8c_3V01 : SchedWriteRes<[V1UnitV01, V1UnitV01, V1UnitV01]>; 264*06c3fb27SDimitry Andric 265*06c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 266*06c3fb27SDimitry Andric// Define generic 4 micro-op types 267*06c3fb27SDimitry Andric 268*06c3fb27SDimitry Andriclet Latency = 8, NumMicroOps = 4 in 269*06c3fb27SDimitry Andricdef V1Write_8c_2M0_2V0 : SchedWriteRes<[V1UnitM0, V1UnitM0, 270*06c3fb27SDimitry Andric V1UnitV0, V1UnitV0]>; 271*06c3fb27SDimitry Andriclet Latency = 7, NumMicroOps = 4 in 272*06c3fb27SDimitry Andricdef V1Write_7c_4L : SchedWriteRes<[V1UnitL, V1UnitL, V1UnitL, V1UnitL]>; 273*06c3fb27SDimitry Andriclet Latency = 8, NumMicroOps = 4 in 274*06c3fb27SDimitry Andricdef V1Write_8c_2L_2V : SchedWriteRes<[V1UnitL, V1UnitL, 275*06c3fb27SDimitry Andric V1UnitV, V1UnitV]>; 276*06c3fb27SDimitry Andriclet Latency = 9, NumMicroOps = 4 in 277*06c3fb27SDimitry Andricdef V1Write_9c_2L_2V : SchedWriteRes<[V1UnitL, V1UnitL, 278*06c3fb27SDimitry Andric V1UnitV, V1UnitV]>; 279*06c3fb27SDimitry Andriclet Latency = 11, NumMicroOps = 4 in 280*06c3fb27SDimitry Andricdef V1Write_11c_2L_2V : SchedWriteRes<[V1UnitL, V1UnitL, 281*06c3fb27SDimitry Andric V1UnitV, V1UnitV]>; 282*06c3fb27SDimitry Andriclet Latency = 10, NumMicroOps = 4 in 283*06c3fb27SDimitry Andricdef V1Write_10c_2L01_2V : SchedWriteRes<[V1UnitL01, V1UnitL01, 284*06c3fb27SDimitry Andric V1UnitV, V1UnitV]>; 285*06c3fb27SDimitry Andriclet Latency = 2, NumMicroOps = 4 in 286*06c3fb27SDimitry Andricdef V1Write_2c_2L01_2V01 : SchedWriteRes<[V1UnitL01, V1UnitL01, 287*06c3fb27SDimitry Andric V1UnitV01, V1UnitV01]>; 288*06c3fb27SDimitry Andriclet Latency = 4, NumMicroOps = 4 in 289*06c3fb27SDimitry Andricdef V1Write_4c_2L01_2V01 : SchedWriteRes<[V1UnitL01, V1UnitL01, 290*06c3fb27SDimitry Andric V1UnitV01, V1UnitV01]>; 291*06c3fb27SDimitry Andriclet Latency = 8, NumMicroOps = 4 in 292*06c3fb27SDimitry Andricdef V1Write_8c_2L01_2V01 : SchedWriteRes<[V1UnitL01, V1UnitL01, 293*06c3fb27SDimitry Andric V1UnitV01, V1UnitV01]>; 294*06c3fb27SDimitry Andriclet Latency = 9, NumMicroOps = 4 in 295*06c3fb27SDimitry Andricdef V1Write_9c_2L01_2V01 : SchedWriteRes<[V1UnitL01, V1UnitL01, 296*06c3fb27SDimitry Andric V1UnitV01, V1UnitV01]>; 297*06c3fb27SDimitry Andriclet Latency = 10, NumMicroOps = 4 in 298*06c3fb27SDimitry Andricdef V1Write_10c_2L01_2V01 : SchedWriteRes<[V1UnitL01, V1UnitL01, 299*06c3fb27SDimitry Andric V1UnitV01, V1UnitV01]>; 300*06c3fb27SDimitry Andriclet Latency = 10, NumMicroOps = 4 in 301*06c3fb27SDimitry Andricdef V1Write_10c_1V_1V01_2V1 : SchedWriteRes<[V1UnitV, V1UnitV01, 302*06c3fb27SDimitry Andric V1UnitV1, V1UnitV1]>; 303*06c3fb27SDimitry Andriclet Latency = 12, NumMicroOps = 4 in 304*06c3fb27SDimitry Andricdef V1Write_12c_1V_1V01_2V1 : SchedWriteRes<[V1UnitV, V1UnitV01, 305*06c3fb27SDimitry Andric V1UnitV1, V1UnitV1]>; 306*06c3fb27SDimitry Andriclet Latency = 6, NumMicroOps = 4 in 307*06c3fb27SDimitry Andricdef V1Write_6c_4V0 : SchedWriteRes<[V1UnitV0, V1UnitV0, 308*06c3fb27SDimitry Andric V1UnitV0, V1UnitV0]>; 309*06c3fb27SDimitry Andriclet Latency = 12, NumMicroOps = 4 in 310*06c3fb27SDimitry Andricdef V1Write_12c_4V01 : SchedWriteRes<[V1UnitV01, V1UnitV01, 311*06c3fb27SDimitry Andric V1UnitV01, V1UnitV01]>; 312*06c3fb27SDimitry Andriclet Latency = 6, NumMicroOps = 4 in 313*06c3fb27SDimitry Andricdef V1Write_6c_4V02 : SchedWriteRes<[V1UnitV02, V1UnitV02]>; 314*06c3fb27SDimitry Andric 315*06c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 316*06c3fb27SDimitry Andric// Define generic 5 micro-op types 317*06c3fb27SDimitry Andric 318*06c3fb27SDimitry Andriclet Latency = 8, NumMicroOps = 5 in 319*06c3fb27SDimitry Andricdef V1Write_8c_2L_3V : SchedWriteRes<[V1UnitL, V1UnitL, 320*06c3fb27SDimitry Andric V1UnitV, V1UnitV, V1UnitV]>; 321*06c3fb27SDimitry Andriclet Latency = 14, NumMicroOps = 5 in 322*06c3fb27SDimitry Andricdef V1Write_14c_1V_1V0_2V1_1V13 : SchedWriteRes<[V1UnitV, 323*06c3fb27SDimitry Andric V1UnitV0, 324*06c3fb27SDimitry Andric V1UnitV1, V1UnitV1, 325*06c3fb27SDimitry Andric V1UnitV13]>; 326*06c3fb27SDimitry Andriclet Latency = 9, NumMicroOps = 5 in 327*06c3fb27SDimitry Andricdef V1Write_9c_1V_4V01 : SchedWriteRes<[V1UnitV, 328*06c3fb27SDimitry Andric V1UnitV01, V1UnitV01, 329*06c3fb27SDimitry Andric V1UnitV01, V1UnitV01]>; 330*06c3fb27SDimitry Andriclet Latency = 6, NumMicroOps = 5 in 331*06c3fb27SDimitry Andricdef V1Write_6c_5V01 : SchedWriteRes<[V1UnitV01, V1UnitV01, 332*06c3fb27SDimitry Andric V1UnitV01, V1UnitV01, V1UnitV01]>; 333*06c3fb27SDimitry Andric 334*06c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 335*06c3fb27SDimitry Andric// Define generic 6 micro-op types 336*06c3fb27SDimitry Andric 337*06c3fb27SDimitry Andriclet Latency = 6, NumMicroOps = 6 in 338*06c3fb27SDimitry Andricdef V1Write_6c_3L_3V : SchedWriteRes<[V1UnitL, V1UnitL, V1UnitL, 339*06c3fb27SDimitry Andric V1UnitV, V1UnitV, V1UnitV]>; 340*06c3fb27SDimitry Andriclet Latency = 8, NumMicroOps = 6 in 341*06c3fb27SDimitry Andricdef V1Write_8c_3L_3V : SchedWriteRes<[V1UnitL, V1UnitL, V1UnitL, 342*06c3fb27SDimitry Andric V1UnitV, V1UnitV, V1UnitV]>; 343*06c3fb27SDimitry Andriclet Latency = 2, NumMicroOps = 6 in 344*06c3fb27SDimitry Andricdef V1Write_2c_3L01_3V01 : SchedWriteRes<[V1UnitL01, V1UnitL01, V1UnitL01, 345*06c3fb27SDimitry Andric V1UnitV01, V1UnitV01, V1UnitV01]>; 346*06c3fb27SDimitry Andriclet Latency = 5, NumMicroOps = 6 in 347*06c3fb27SDimitry Andricdef V1Write_5c_3L01_3V01 : SchedWriteRes<[V1UnitL01, V1UnitL01, V1UnitL01, 348*06c3fb27SDimitry Andric V1UnitV01, V1UnitV01, V1UnitV01]>; 349*06c3fb27SDimitry Andriclet Latency = 6, NumMicroOps = 6 in 350*06c3fb27SDimitry Andricdef V1Write_6c_3L01_3V01 : SchedWriteRes<[V1UnitL01, V1UnitL01, V1UnitL01, 351*06c3fb27SDimitry Andric V1UnitV01, V1UnitV01, V1UnitV01]>; 352*06c3fb27SDimitry Andriclet Latency = 11, NumMicroOps = 6 in 353*06c3fb27SDimitry Andricdef V1Write_11c_3L01_3V01 : SchedWriteRes<[V1UnitL01, V1UnitL01, V1UnitL01, 354*06c3fb27SDimitry Andric V1UnitV01, V1UnitV01, V1UnitV01]>; 355*06c3fb27SDimitry Andriclet Latency = 11, NumMicroOps = 6 in 356*06c3fb27SDimitry Andricdef V1Write_11c_1V_5V01 : SchedWriteRes<[V1UnitV, 357*06c3fb27SDimitry Andric V1UnitV01, V1UnitV01, 358*06c3fb27SDimitry Andric V1UnitV01, V1UnitV01, V1UnitV01]>; 359*06c3fb27SDimitry Andriclet Latency = 13, NumMicroOps = 6 in 360*06c3fb27SDimitry Andricdef V1Write_13c_6V01 : SchedWriteRes<[V1UnitV01, V1UnitV01, V1UnitV01, 361*06c3fb27SDimitry Andric V1UnitV01, V1UnitV01, V1UnitV01]>; 362*06c3fb27SDimitry Andric 363*06c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 364*06c3fb27SDimitry Andric// Define generic 7 micro-op types 365*06c3fb27SDimitry Andric 366*06c3fb27SDimitry Andriclet Latency = 8, NumMicroOps = 7 in 367*06c3fb27SDimitry Andricdef V1Write_8c_3L_4V : SchedWriteRes<[V1UnitL, V1UnitL, V1UnitL, 368*06c3fb27SDimitry Andric V1UnitV, V1UnitV, V1UnitV, V1UnitV]>; 369*06c3fb27SDimitry Andriclet Latency = 8, NumMicroOps = 7 in 370*06c3fb27SDimitry Andricdef V1Write_13c_3L01_1S_3V01 : SchedWriteRes<[V1UnitL01, V1UnitL01, V1UnitL01, 371*06c3fb27SDimitry Andric V1UnitS, 372*06c3fb27SDimitry Andric V1UnitV01, V1UnitV01, V1UnitV01]>; 373*06c3fb27SDimitry Andric 374*06c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 375*06c3fb27SDimitry Andric// Define generic 8 micro-op types 376*06c3fb27SDimitry Andric 377*06c3fb27SDimitry Andriclet Latency = 9, NumMicroOps = 8 in 378*06c3fb27SDimitry Andricdef V1Write_9c_4L_4V : SchedWriteRes<[V1UnitL, V1UnitL, 379*06c3fb27SDimitry Andric V1UnitL, V1UnitL, 380*06c3fb27SDimitry Andric V1UnitV, V1UnitV, 381*06c3fb27SDimitry Andric V1UnitV, V1UnitV]>; 382*06c3fb27SDimitry Andriclet Latency = 2, NumMicroOps = 8 in 383*06c3fb27SDimitry Andricdef V1Write_2c_4L01_4V01 : SchedWriteRes<[V1UnitL01, V1UnitL01, 384*06c3fb27SDimitry Andric V1UnitL01, V1UnitL01, 385*06c3fb27SDimitry Andric V1UnitV01, V1UnitV01, 386*06c3fb27SDimitry Andric V1UnitV01, V1UnitV01]>; 387*06c3fb27SDimitry Andriclet Latency = 4, NumMicroOps = 8 in 388*06c3fb27SDimitry Andricdef V1Write_4c_4L01_4V01 : SchedWriteRes<[V1UnitL01, V1UnitL01, 389*06c3fb27SDimitry Andric V1UnitL01, V1UnitL01, 390*06c3fb27SDimitry Andric V1UnitV01, V1UnitV01, 391*06c3fb27SDimitry Andric V1UnitV01, V1UnitV01]>; 392*06c3fb27SDimitry Andriclet Latency = 12, NumMicroOps = 8 in 393*06c3fb27SDimitry Andricdef V1Write_12c_4L01_4V01 : SchedWriteRes<[V1UnitL01, V1UnitL01, 394*06c3fb27SDimitry Andric V1UnitL01, V1UnitL01, 395*06c3fb27SDimitry Andric V1UnitV01, V1UnitV01, 396*06c3fb27SDimitry Andric V1UnitV01, V1UnitV01]>; 397*06c3fb27SDimitry Andric 398*06c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 399*06c3fb27SDimitry Andric// Define generic 10 micro-op types 400*06c3fb27SDimitry Andric 401*06c3fb27SDimitry Andriclet Latency = 13, NumMicroOps = 10 in 402*06c3fb27SDimitry Andricdef V1Write_13c_4L01_2S_4V01 : SchedWriteRes<[V1UnitL01, V1UnitL01, 403*06c3fb27SDimitry Andric V1UnitL01, V1UnitL01, 404*06c3fb27SDimitry Andric V1UnitS, V1UnitS, 405*06c3fb27SDimitry Andric V1UnitV01, V1UnitV01, 406*06c3fb27SDimitry Andric V1UnitV01, V1UnitV01]>; 407*06c3fb27SDimitry Andriclet Latency = 7, NumMicroOps = 10 in 408*06c3fb27SDimitry Andricdef V1Write_7c_5L01_5V : SchedWriteRes<[V1UnitL01, V1UnitL01, 409*06c3fb27SDimitry Andric V1UnitL01, V1UnitL01, V1UnitL01, 410*06c3fb27SDimitry Andric V1UnitV, V1UnitV, 411*06c3fb27SDimitry Andric V1UnitV, V1UnitV, V1UnitV]>; 412*06c3fb27SDimitry Andriclet Latency = 11, NumMicroOps = 10 in 413*06c3fb27SDimitry Andricdef V1Write_11c_10V0 : SchedWriteRes<[V1UnitV0, 414*06c3fb27SDimitry Andric V1UnitV0, V1UnitV0, V1UnitV0, 415*06c3fb27SDimitry Andric V1UnitV0, V1UnitV0, V1UnitV0, 416*06c3fb27SDimitry Andric V1UnitV0, V1UnitV0, V1UnitV0]>; 417*06c3fb27SDimitry Andric 418*06c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 419*06c3fb27SDimitry Andric// Define generic 12 micro-op types 420*06c3fb27SDimitry Andric 421*06c3fb27SDimitry Andriclet Latency = 7, NumMicroOps = 12 in 422*06c3fb27SDimitry Andricdef V1Write_7c_6L01_6V01 : SchedWriteRes<[V1UnitL01, V1UnitL01, V1UnitL01, 423*06c3fb27SDimitry Andric V1UnitL01, V1UnitL01, V1UnitL01, 424*06c3fb27SDimitry Andric V1UnitV01, V1UnitV01, V1UnitV01, 425*06c3fb27SDimitry Andric V1UnitV01, V1UnitV01, V1UnitV01]>; 426*06c3fb27SDimitry Andric 427*06c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 428*06c3fb27SDimitry Andric// Define generic 15 micro-op types 429*06c3fb27SDimitry Andric 430*06c3fb27SDimitry Andriclet Latency = 7, NumMicroOps = 15 in 431*06c3fb27SDimitry Andricdef V1Write_7c_5L01_5S_5V : SchedWriteRes<[V1UnitL01, V1UnitL01, 432*06c3fb27SDimitry Andric V1UnitL01, V1UnitL01, V1UnitL01, 433*06c3fb27SDimitry Andric V1UnitS, V1UnitS, 434*06c3fb27SDimitry Andric V1UnitS, V1UnitS, V1UnitS, 435*06c3fb27SDimitry Andric V1UnitV, V1UnitV, 436*06c3fb27SDimitry Andric V1UnitV, V1UnitV, V1UnitV]>; 437*06c3fb27SDimitry Andric 438*06c3fb27SDimitry Andric 439*06c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 440*06c3fb27SDimitry Andric// Define generic 18 micro-op types 441*06c3fb27SDimitry Andric 442*06c3fb27SDimitry Andriclet Latency = 19, NumMicroOps = 18 in 443*06c3fb27SDimitry Andricdef V1Write_11c_9L01_9V : SchedWriteRes<[V1UnitL01, V1UnitL01, V1UnitL01, 444*06c3fb27SDimitry Andric V1UnitL01, V1UnitL01, V1UnitL01, 445*06c3fb27SDimitry Andric V1UnitL01, V1UnitL01, V1UnitL01, 446*06c3fb27SDimitry Andric V1UnitV, V1UnitV, V1UnitV, 447*06c3fb27SDimitry Andric V1UnitV, V1UnitV, V1UnitV, 448*06c3fb27SDimitry Andric V1UnitV, V1UnitV, V1UnitV]>; 449*06c3fb27SDimitry Andriclet Latency = 19, NumMicroOps = 18 in 450*06c3fb27SDimitry Andricdef V1Write_19c_18V0 : SchedWriteRes<[V1UnitV0, V1UnitV0, V1UnitV0, 451*06c3fb27SDimitry Andric V1UnitV0, V1UnitV0, V1UnitV0, 452*06c3fb27SDimitry Andric V1UnitV0, V1UnitV0, V1UnitV0, 453*06c3fb27SDimitry Andric V1UnitV0, V1UnitV0, V1UnitV0, 454*06c3fb27SDimitry Andric V1UnitV0, V1UnitV0, V1UnitV0, 455*06c3fb27SDimitry Andric V1UnitV0, V1UnitV0, V1UnitV0]>; 456*06c3fb27SDimitry Andric 457*06c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 458*06c3fb27SDimitry Andric// Define generic 27 micro-op types 459*06c3fb27SDimitry Andric 460*06c3fb27SDimitry Andriclet Latency = 11, NumMicroOps = 27 in 461*06c3fb27SDimitry Andricdef V1Write_11c_9L01_9S_9V : SchedWriteRes<[V1UnitL01, V1UnitL01, V1UnitL01, 462*06c3fb27SDimitry Andric V1UnitL01, V1UnitL01, V1UnitL01, 463*06c3fb27SDimitry Andric V1UnitL01, V1UnitL01, V1UnitL01, 464*06c3fb27SDimitry Andric V1UnitS, V1UnitS, V1UnitS, 465*06c3fb27SDimitry Andric V1UnitS, V1UnitS, V1UnitS, 466*06c3fb27SDimitry Andric V1UnitS, V1UnitS, V1UnitS, 467*06c3fb27SDimitry Andric V1UnitV, V1UnitV, V1UnitV, 468*06c3fb27SDimitry Andric V1UnitV, V1UnitV, V1UnitV, 469*06c3fb27SDimitry Andric V1UnitV, V1UnitV, V1UnitV]>; 470*06c3fb27SDimitry Andric 471*06c3fb27SDimitry Andric 472*06c3fb27SDimitry Andric// Miscellaneous Instructions 473*06c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 474*06c3fb27SDimitry Andric 475*06c3fb27SDimitry Andric// COPY 476*06c3fb27SDimitry Andricdef : InstRW<[V1Write_1c_1I], (instrs COPY)>; 477*06c3fb27SDimitry Andric 478*06c3fb27SDimitry Andric// MSR 479*06c3fb27SDimitry Andricdef : WriteRes<WriteSys, []> { let Latency = 1; } 480*06c3fb27SDimitry Andric 481*06c3fb27SDimitry Andric 482*06c3fb27SDimitry Andric// Branch Instructions 483*06c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 484*06c3fb27SDimitry Andric 485*06c3fb27SDimitry Andric// Branch, immed 486*06c3fb27SDimitry Andric// Compare and branch 487*06c3fb27SDimitry Andricdef : SchedAlias<WriteBr, V1Write_1c_1B>; 488*06c3fb27SDimitry Andric 489*06c3fb27SDimitry Andric// Branch, register 490*06c3fb27SDimitry Andricdef : SchedAlias<WriteBrReg, V1Write_1c_1B>; 491*06c3fb27SDimitry Andric 492*06c3fb27SDimitry Andric// Branch and link, immed 493*06c3fb27SDimitry Andric// Branch and link, register 494*06c3fb27SDimitry Andricdef : InstRW<[V1Write_1c_1B_1S], (instrs BL, BLR)>; 495*06c3fb27SDimitry Andric 496*06c3fb27SDimitry Andric// Compare and branch 497*06c3fb27SDimitry Andricdef : InstRW<[V1Write_1c_1B], (instregex "^[CT]BN?Z[XW]$")>; 498*06c3fb27SDimitry Andric 499*06c3fb27SDimitry Andric 500*06c3fb27SDimitry Andric// Arithmetic and Logical Instructions 501*06c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 502*06c3fb27SDimitry Andric 503*06c3fb27SDimitry Andric// ALU, basic 504*06c3fb27SDimitry Andric// Conditional compare 505*06c3fb27SDimitry Andric// Conditional select 506*06c3fb27SDimitry Andric// Logical, basic 507*06c3fb27SDimitry Andric// Address generation 508*06c3fb27SDimitry Andric// Count leading 509*06c3fb27SDimitry Andric// Reverse bits/bytes 510*06c3fb27SDimitry Andric// Move immediate 511*06c3fb27SDimitry Andricdef : SchedAlias<WriteI, V1Write_1c_1I>; 512*06c3fb27SDimitry Andric 513*06c3fb27SDimitry Andric// ALU, basic, flagset 514*06c3fb27SDimitry Andricdef : InstRW<[V1Write_1c_1J], 515*06c3fb27SDimitry Andric (instregex "^(ADD|SUB)S[WX]r[ir]$", 516*06c3fb27SDimitry Andric "^(ADC|SBC)S[WX]r$", 517*06c3fb27SDimitry Andric "^ANDS[WX]ri$", 518*06c3fb27SDimitry Andric "^(AND|BIC)S[WX]rr$")>; 519*06c3fb27SDimitry Andric 520*06c3fb27SDimitry Andric// ALU, extend and shift 521*06c3fb27SDimitry Andricdef : SchedAlias<WriteIEReg, V1Write_2c_1M>; 522*06c3fb27SDimitry Andric 523*06c3fb27SDimitry Andric// Arithmetic, LSL shift, shift <= 4 524*06c3fb27SDimitry Andric// Arithmetic, LSR/ASR/ROR shift or LSL shift > 4 525*06c3fb27SDimitry Andricdef V1WriteISReg : SchedWriteVariant< 526*06c3fb27SDimitry Andric [SchedVar<IsCheapLSL, [V1Write_1c_1I]>, 527*06c3fb27SDimitry Andric SchedVar<NoSchedPred, [V1Write_2c_1M]>]>; 528*06c3fb27SDimitry Andricdef : SchedAlias<WriteISReg, V1WriteISReg>; 529*06c3fb27SDimitry Andric 530*06c3fb27SDimitry Andric// Arithmetic, flagset, LSL shift, shift <= 4 531*06c3fb27SDimitry Andric// Arithmetic, flagset, LSR/ASR/ROR shift or LSL shift > 4 532*06c3fb27SDimitry Andricdef V1WriteISRegS : SchedWriteVariant< 533*06c3fb27SDimitry Andric [SchedVar<IsCheapLSL, [V1Write_1c_1J]>, 534*06c3fb27SDimitry Andric SchedVar<NoSchedPred, [V1Write_2c_1M]>]>; 535*06c3fb27SDimitry Andricdef : InstRW<[V1WriteISRegS], 536*06c3fb27SDimitry Andric (instregex "^(ADD|SUB)S(([WX]r[sx])|Xrx64)$")>; 537*06c3fb27SDimitry Andric 538*06c3fb27SDimitry Andric// Logical, shift, no flagset 539*06c3fb27SDimitry Andricdef : InstRW<[V1Write_1c_1I], (instregex "^(AND|BIC|EON|EOR|ORN|ORR)[WX]rs$")>; 540*06c3fb27SDimitry Andric 541*06c3fb27SDimitry Andric// Logical, shift, flagset 542*06c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1M], (instregex "^(AND|BIC)S[WX]rs$")>; 543*06c3fb27SDimitry Andric 544*06c3fb27SDimitry Andric// Flag manipulation instructions 545*06c3fb27SDimitry Andricdef : InstRW<[V1Write_1c_1J], (instrs SETF8, SETF16, RMIF, CFINV)>; 546*06c3fb27SDimitry Andric 547*06c3fb27SDimitry Andric 548*06c3fb27SDimitry Andric// Divide and multiply instructions 549*06c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 550*06c3fb27SDimitry Andric 551*06c3fb27SDimitry Andric// Divide 552*06c3fb27SDimitry Andricdef : SchedAlias<WriteID32, V1Write_12c5_1M0>; 553*06c3fb27SDimitry Andricdef : SchedAlias<WriteID64, V1Write_20c5_1M0>; 554*06c3fb27SDimitry Andric 555*06c3fb27SDimitry Andric// Multiply 556*06c3fb27SDimitry Andric// Multiply accumulate 557*06c3fb27SDimitry Andric// Multiply accumulate, long 558*06c3fb27SDimitry Andric// Multiply long 559*06c3fb27SDimitry Andricdef V1WriteIM : SchedWriteVariant< 560*06c3fb27SDimitry Andric [SchedVar<NeoverseMULIdiomPred, [V1Write_2c_1M]>, 561*06c3fb27SDimitry Andric SchedVar<NoSchedPred, [V1Write_2c_1M0]>]>; 562*06c3fb27SDimitry Andricdef : SchedAlias<WriteIM32, V1WriteIM>; 563*06c3fb27SDimitry Andricdef : SchedAlias<WriteIM64, V1WriteIM>; 564*06c3fb27SDimitry Andric 565*06c3fb27SDimitry Andric// Multiply high 566*06c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1M, ReadIM, ReadIM], (instrs SMULHrr, UMULHrr)>; 567*06c3fb27SDimitry Andric 568*06c3fb27SDimitry Andric 569*06c3fb27SDimitry Andric// Pointer Authentication Instructions (v8.3 PAC) 570*06c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 571*06c3fb27SDimitry Andric 572*06c3fb27SDimitry Andric// Authenticate data address 573*06c3fb27SDimitry Andric// Authenticate instruction address 574*06c3fb27SDimitry Andric// Compute pointer authentication code for data address 575*06c3fb27SDimitry Andric// Compute pointer authentication code, using generic key 576*06c3fb27SDimitry Andric// Compute pointer authentication code for instruction address 577*06c3fb27SDimitry Andricdef : InstRW<[V1Write_5c_1M0], (instregex "^AUT", 578*06c3fb27SDimitry Andric "^PAC")>; 579*06c3fb27SDimitry Andric 580*06c3fb27SDimitry Andric// Branch and link, register, with pointer authentication 581*06c3fb27SDimitry Andric// Branch, register, with pointer authentication 582*06c3fb27SDimitry Andric// Branch, return, with pointer authentication 583*06c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_1B_1M0], (instregex "^BL?RA[AB]Z?$", 584*06c3fb27SDimitry Andric "^E?RETA[AB]$")>; 585*06c3fb27SDimitry Andric 586*06c3fb27SDimitry Andric// Load register, with pointer authentication 587*06c3fb27SDimitry Andricdef : InstRW<[V1Write_9c_1M0_1L], (instregex "^LDRA[AB](indexed|writeback)")>; 588*06c3fb27SDimitry Andric 589*06c3fb27SDimitry Andric// Strip pointer authentication code 590*06c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1M0], (instrs XPACD, XPACI, XPACLRI)>; 591*06c3fb27SDimitry Andric 592*06c3fb27SDimitry Andric 593*06c3fb27SDimitry Andric// Miscellaneous data-processing instructions 594*06c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 595*06c3fb27SDimitry Andric 596*06c3fb27SDimitry Andric// Bitfield extract, one reg 597*06c3fb27SDimitry Andric// Bitfield extract, two regs 598*06c3fb27SDimitry Andricdef V1WriteExtr : SchedWriteVariant< 599*06c3fb27SDimitry Andric [SchedVar<IsRORImmIdiomPred, [V1Write_1c_1I]>, 600*06c3fb27SDimitry Andric SchedVar<NoSchedPred, [V1Write_3c_1I_1M]>]>; 601*06c3fb27SDimitry Andricdef : SchedAlias<WriteExtr, V1WriteExtr>; 602*06c3fb27SDimitry Andric 603*06c3fb27SDimitry Andric// Bitfield move, basic 604*06c3fb27SDimitry Andric// Variable shift 605*06c3fb27SDimitry Andricdef : SchedAlias<WriteIS, V1Write_1c_1I>; 606*06c3fb27SDimitry Andric 607*06c3fb27SDimitry Andric// Bitfield move, insert 608*06c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1M], (instregex "^BFM[WX]ri$")>; 609*06c3fb27SDimitry Andric 610*06c3fb27SDimitry Andric// Move immediate 611*06c3fb27SDimitry Andricdef : SchedAlias<WriteImm, V1Write_1c_1I>; 612*06c3fb27SDimitry Andric 613*06c3fb27SDimitry Andric 614*06c3fb27SDimitry Andric// Load instructions 615*06c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 616*06c3fb27SDimitry Andric 617*06c3fb27SDimitry Andric// Load register, immed offset 618*06c3fb27SDimitry Andricdef : SchedAlias<WriteLD, V1Write_4c_1L>; 619*06c3fb27SDimitry Andric 620*06c3fb27SDimitry Andric// Load register, immed offset, index 621*06c3fb27SDimitry Andricdef : SchedAlias<WriteLDIdx, V1Write_4c_1L>; 622*06c3fb27SDimitry Andricdef : SchedAlias<WriteAdr, V1Write_1c_1I>; 623*06c3fb27SDimitry Andric 624*06c3fb27SDimitry Andric// Load pair, immed offset 625*06c3fb27SDimitry Andricdef : SchedAlias<WriteLDHi, V1Write_4c_1L>; 626*06c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_1L, V1Write_0c_0Z], (instrs LDPWi, LDNPWi)>; 627*06c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_1L, V1Write_0c_0Z, WriteAdr], 628*06c3fb27SDimitry Andric (instrs LDPWpost, LDPWpre)>; 629*06c3fb27SDimitry Andric 630*06c3fb27SDimitry Andric// Load pair, signed immed offset, signed words 631*06c3fb27SDimitry Andricdef : InstRW<[V1Write_5c_1I_1L, V1Write_0c_0Z], (instrs LDPSWi)>; 632*06c3fb27SDimitry Andric 633*06c3fb27SDimitry Andric// Load pair, immed post or pre-index, signed words 634*06c3fb27SDimitry Andricdef : InstRW<[V1Write_5c_1I_1L, V1Write_0c_0Z, WriteAdr], 635*06c3fb27SDimitry Andric (instrs LDPSWpost, LDPSWpre)>; 636*06c3fb27SDimitry Andric 637*06c3fb27SDimitry Andric 638*06c3fb27SDimitry Andric// Store instructions 639*06c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 640*06c3fb27SDimitry Andric 641*06c3fb27SDimitry Andric// Store register, immed offset 642*06c3fb27SDimitry Andricdef : SchedAlias<WriteST, V1Write_1c_1L01_1D>; 643*06c3fb27SDimitry Andric 644*06c3fb27SDimitry Andric// Store register, immed offset, index 645*06c3fb27SDimitry Andricdef : SchedAlias<WriteSTIdx, V1Write_1c_1L01_1D>; 646*06c3fb27SDimitry Andric 647*06c3fb27SDimitry Andric// Store pair, immed offset 648*06c3fb27SDimitry Andricdef : SchedAlias<WriteSTP, V1Write_1c_1L01_1D>; 649*06c3fb27SDimitry Andric 650*06c3fb27SDimitry Andric 651*06c3fb27SDimitry Andric// FP data processing instructions 652*06c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 653*06c3fb27SDimitry Andric 654*06c3fb27SDimitry Andric// FP absolute value 655*06c3fb27SDimitry Andric// FP arithmetic 656*06c3fb27SDimitry Andric// FP min/max 657*06c3fb27SDimitry Andric// FP negate 658*06c3fb27SDimitry Andricdef : SchedAlias<WriteF, V1Write_2c_1V>; 659*06c3fb27SDimitry Andric 660*06c3fb27SDimitry Andric// FP compare 661*06c3fb27SDimitry Andricdef : SchedAlias<WriteFCmp, V1Write_2c_1V0>; 662*06c3fb27SDimitry Andric 663*06c3fb27SDimitry Andric// FP divide 664*06c3fb27SDimitry Andric// FP square root 665*06c3fb27SDimitry Andricdef : SchedAlias<WriteFDiv, V1Write_10c7_1V02>; 666*06c3fb27SDimitry Andric 667*06c3fb27SDimitry Andric// FP divide, H-form 668*06c3fb27SDimitry Andric// FP square root, H-form 669*06c3fb27SDimitry Andricdef : InstRW<[V1Write_7c7_1V02], (instrs FDIVHrr, FSQRTHr)>; 670*06c3fb27SDimitry Andric 671*06c3fb27SDimitry Andric// FP divide, S-form 672*06c3fb27SDimitry Andric// FP square root, S-form 673*06c3fb27SDimitry Andricdef : InstRW<[V1Write_10c7_1V02], (instrs FDIVSrr, FSQRTSr)>; 674*06c3fb27SDimitry Andric 675*06c3fb27SDimitry Andric// FP divide, D-form 676*06c3fb27SDimitry Andricdef : InstRW<[V1Write_15c7_1V02], (instrs FDIVDrr)>; 677*06c3fb27SDimitry Andric 678*06c3fb27SDimitry Andric// FP square root, D-form 679*06c3fb27SDimitry Andricdef : InstRW<[V1Write_16c7_1V02], (instrs FSQRTDr)>; 680*06c3fb27SDimitry Andric 681*06c3fb27SDimitry Andric// FP multiply 682*06c3fb27SDimitry Andricdef : SchedAlias<WriteFMul, V1Write_3c_1V>; 683*06c3fb27SDimitry Andric 684*06c3fb27SDimitry Andric// FP multiply accumulate 685*06c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_1V], (instregex "^FN?M(ADD|SUB)[HSD]rrr$")>; 686*06c3fb27SDimitry Andric 687*06c3fb27SDimitry Andric// FP round to integral 688*06c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1V02], (instregex "^FRINT[AIMNPXZ][HSD]r$", 689*06c3fb27SDimitry Andric "^FRINT(32|64)[XZ][SD]r$")>; 690*06c3fb27SDimitry Andric 691*06c3fb27SDimitry Andric// FP select 692*06c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1V01], (instregex "^FCSEL[HSD]rrr$")>; 693*06c3fb27SDimitry Andric 694*06c3fb27SDimitry Andric 695*06c3fb27SDimitry Andric// FP miscellaneous instructions 696*06c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 697*06c3fb27SDimitry Andric 698*06c3fb27SDimitry Andric// FP convert, from gen to vec reg 699*06c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1M0], (instregex "^[SU]CVTF[SU][WX][HSD]ri$")>; 700*06c3fb27SDimitry Andric 701*06c3fb27SDimitry Andric// FP convert, from vec to gen reg 702*06c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1V0], (instregex "^FCVT[AMNPZ][SU][SU][WX][HSD]r$")>; 703*06c3fb27SDimitry Andric 704*06c3fb27SDimitry Andric// FP convert, Javascript from vec to gen reg 705*06c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1V0], (instrs FJCVTZS)>; 706*06c3fb27SDimitry Andric 707*06c3fb27SDimitry Andric// FP convert, from vec to vec reg 708*06c3fb27SDimitry Andricdef : SchedAlias<WriteFCvt, V1Write_3c_1V02>; 709*06c3fb27SDimitry Andric 710*06c3fb27SDimitry Andric// FP move, immed 711*06c3fb27SDimitry Andricdef : SchedAlias<WriteFImm, V1Write_2c_1V>; 712*06c3fb27SDimitry Andric 713*06c3fb27SDimitry Andric// FP move, register 714*06c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1V], (instrs FMOVHr, FMOVSr, FMOVDr)>; 715*06c3fb27SDimitry Andric 716*06c3fb27SDimitry Andric// FP transfer, from gen to low half of vec reg 717*06c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1M0], (instrs FMOVWHr, FMOVXHr, FMOVWSr, FMOVXDr)>; 718*06c3fb27SDimitry Andric 719*06c3fb27SDimitry Andric// FP transfer, from gen to high half of vec reg 720*06c3fb27SDimitry Andricdef : InstRW<[V1Write_5c_1M0_1V], (instrs FMOVXDHighr)>; 721*06c3fb27SDimitry Andric 722*06c3fb27SDimitry Andric// FP transfer, from vec to gen reg 723*06c3fb27SDimitry Andricdef : SchedAlias<WriteFCopy, V1Write_2c_1V1>; 724*06c3fb27SDimitry Andric 725*06c3fb27SDimitry Andric 726*06c3fb27SDimitry Andric// FP load instructions 727*06c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 728*06c3fb27SDimitry Andric 729*06c3fb27SDimitry Andric// Load vector reg, literal, S/D/Q forms 730*06c3fb27SDimitry Andric// Load vector reg, unscaled immed 731*06c3fb27SDimitry Andric// Load vector reg, unsigned immed 732*06c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_1L, ReadAdrBase], (instregex "^LDR[SDQ]l$", 733*06c3fb27SDimitry Andric "^LDUR[BHSDQ]i$", 734*06c3fb27SDimitry Andric "^LDR[BHSDQ]ui$")>; 735*06c3fb27SDimitry Andric 736*06c3fb27SDimitry Andric// Load vector reg, immed post-index 737*06c3fb27SDimitry Andric// Load vector reg, immed pre-index 738*06c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_1L, WriteAdr], 739*06c3fb27SDimitry Andric (instregex "^LDR[BHSDQ](post|pre)$")>; 740*06c3fb27SDimitry Andric 741*06c3fb27SDimitry Andric// Load vector reg, register offset, basic 742*06c3fb27SDimitry Andric// Load vector reg, register offset, scale, S/D-form 743*06c3fb27SDimitry Andric// Load vector reg, register offset, extend 744*06c3fb27SDimitry Andric// Load vector reg, register offset, extend, scale, S/D-form 745*06c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_1L, ReadAdrBase], (instregex "^LDR[BSD]ro[WX]$")>; 746*06c3fb27SDimitry Andric 747*06c3fb27SDimitry Andric// Load vector reg, register offset, scale, H/Q-form 748*06c3fb27SDimitry Andric// Load vector reg, register offset, extend, scale, H/Q-form 749*06c3fb27SDimitry Andricdef : InstRW<[V1Write_7c_1I_1L, ReadAdrBase], (instregex "^LDR[HQ]ro[WX]$")>; 750*06c3fb27SDimitry Andric 751*06c3fb27SDimitry Andric// Load vector pair, immed offset, S/D-form 752*06c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_1L, V1Write_0c_0Z], (instregex "^LDN?P[SD]i$")>; 753*06c3fb27SDimitry Andric 754*06c3fb27SDimitry Andric// Load vector pair, immed offset, Q-form 755*06c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_1L, WriteLDHi], (instrs LDPQi, LDNPQi)>; 756*06c3fb27SDimitry Andric 757*06c3fb27SDimitry Andric// Load vector pair, immed post-index, S/D-form 758*06c3fb27SDimitry Andric// Load vector pair, immed pre-index, S/D-form 759*06c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_1L, V1Write_0c_0Z, WriteAdr], 760*06c3fb27SDimitry Andric (instregex "^LDP[SD](pre|post)$")>; 761*06c3fb27SDimitry Andric 762*06c3fb27SDimitry Andric// Load vector pair, immed post-index, Q-form 763*06c3fb27SDimitry Andric// Load vector pair, immed pre-index, Q-form 764*06c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_1L, WriteLDHi, WriteAdr], 765*06c3fb27SDimitry Andric (instrs LDPQpost, LDPQpre)>; 766*06c3fb27SDimitry Andric 767*06c3fb27SDimitry Andric 768*06c3fb27SDimitry Andric// FP store instructions 769*06c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 770*06c3fb27SDimitry Andric 771*06c3fb27SDimitry Andric// Store vector reg, unscaled immed, B/H/S/D/Q-form 772*06c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1L01_1V01], (instregex "^STUR[BHSDQ]i$")>; 773*06c3fb27SDimitry Andric 774*06c3fb27SDimitry Andric// Store vector reg, immed post-index, B/H/S/D/Q-form 775*06c3fb27SDimitry Andric// Store vector reg, immed pre-index, B/H/S/D/Q-form 776*06c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1L01_1V01, WriteAdr], 777*06c3fb27SDimitry Andric (instregex "^STR[BHSDQ](pre|post)$")>; 778*06c3fb27SDimitry Andric 779*06c3fb27SDimitry Andric// Store vector reg, unsigned immed, B/H/S/D/Q-form 780*06c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1L01_1V01], (instregex "^STR[BHSDQ]ui$")>; 781*06c3fb27SDimitry Andric 782*06c3fb27SDimitry Andric// Store vector reg, register offset, basic, B/S/D-form 783*06c3fb27SDimitry Andric// Store vector reg, register offset, scale, B/S/D-form 784*06c3fb27SDimitry Andric// Store vector reg, register offset, extend, B/S/D-form 785*06c3fb27SDimitry Andric// Store vector reg, register offset, extend, scale, B/S/D-form 786*06c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1L01_1V01, ReadAdrBase], 787*06c3fb27SDimitry Andric (instregex "^STR[BSD]ro[WX]$")>; 788*06c3fb27SDimitry Andric 789*06c3fb27SDimitry Andric// Store vector reg, register offset, basic, H/Q-form 790*06c3fb27SDimitry Andric// Store vector reg, register offset, scale, H/Q-form 791*06c3fb27SDimitry Andric// Store vector reg, register offset, extend, H/Q-form 792*06c3fb27SDimitry Andric// Store vector reg, register offset, extend, scale, H/Q-form 793*06c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1I_1L01_1V01, ReadAdrBase], 794*06c3fb27SDimitry Andric (instregex "^STR[HQ]ro[WX]$")>; 795*06c3fb27SDimitry Andric 796*06c3fb27SDimitry Andric// Store vector pair, immed offset, S/D/Q-form 797*06c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1L01_1V01], (instregex "^STN?P[SDQ]i$")>; 798*06c3fb27SDimitry Andric 799*06c3fb27SDimitry Andric// Store vector pair, immed post-index, S/D-form 800*06c3fb27SDimitry Andric// Store vector pair, immed pre-index, S/D-form 801*06c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1L01_1V01, WriteAdr], 802*06c3fb27SDimitry Andric (instregex "^STP[SD](pre|post)$")>; 803*06c3fb27SDimitry Andric 804*06c3fb27SDimitry Andric// Store vector pair, immed post-index, Q-form 805*06c3fb27SDimitry Andric// Store vector pair, immed pre-index, Q-form 806*06c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_2L01_1V01, WriteAdr], (instrs STPQpre, STPQpost)>; 807*06c3fb27SDimitry Andric 808*06c3fb27SDimitry Andric 809*06c3fb27SDimitry Andric// ASIMD integer instructions 810*06c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 811*06c3fb27SDimitry Andric 812*06c3fb27SDimitry Andric// ASIMD absolute diff 813*06c3fb27SDimitry Andric// ASIMD absolute diff long 814*06c3fb27SDimitry Andric// ASIMD arith, basic 815*06c3fb27SDimitry Andric// ASIMD arith, complex 816*06c3fb27SDimitry Andric// ASIMD arith, pair-wise 817*06c3fb27SDimitry Andric// ASIMD compare 818*06c3fb27SDimitry Andric// ASIMD logical 819*06c3fb27SDimitry Andric// ASIMD max/min, basic and pair-wise 820*06c3fb27SDimitry Andricdef : SchedAlias<WriteVd, V1Write_2c_1V>; 821*06c3fb27SDimitry Andricdef : SchedAlias<WriteVq, V1Write_2c_1V>; 822*06c3fb27SDimitry Andric 823*06c3fb27SDimitry Andric// ASIMD absolute diff accum 824*06c3fb27SDimitry Andric// ASIMD absolute diff accum long 825*06c3fb27SDimitry Andric// ASIMD pairwise add and accumulate long 826*06c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_1V13], (instregex "^[SU]ABAL?v", "^[SU]ADALPv")>; 827*06c3fb27SDimitry Andric 828*06c3fb27SDimitry Andric// ASIMD arith, reduce, 4H/4S 829*06c3fb27SDimitry Andric// ASIMD max/min, reduce, 4H/4S 830*06c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1V13], (instregex "^(ADD|[SU]ADDL)Vv4(i16|i32)v$", 831*06c3fb27SDimitry Andric "^[SU](MAX|MIN)Vv4(i16|i32)v$")>; 832*06c3fb27SDimitry Andric 833*06c3fb27SDimitry Andric// ASIMD arith, reduce, 8B/8H 834*06c3fb27SDimitry Andric// ASIMD max/min, reduce, 8B/8H 835*06c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_1V13_1V], (instregex "^(ADD|[SU]ADDL)Vv8(i8|i16)v$", 836*06c3fb27SDimitry Andric "^[SU](MAX|MIN)Vv8(i8|i16)v$")>; 837*06c3fb27SDimitry Andric 838*06c3fb27SDimitry Andric// ASIMD arith, reduce, 16B 839*06c3fb27SDimitry Andric// ASIMD max/min, reduce, 16B 840*06c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_2V13], (instregex "^(ADD|[SU]ADDL)Vv16i8v$", 841*06c3fb27SDimitry Andric "[SU](MAX|MIN)Vv16i8v$")>; 842*06c3fb27SDimitry Andric 843*06c3fb27SDimitry Andric// ASIMD dot product 844*06c3fb27SDimitry Andric// ASIMD dot product using signed and unsigned integers 845*06c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1V], (instregex "^([SU]|SU|US)DOT(lane)?v(8|16)i8$")>; 846*06c3fb27SDimitry Andric 847*06c3fb27SDimitry Andric// ASIMD matrix multiply- accumulate 848*06c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1V], (instrs SMMLA, UMMLA, USMMLA)>; 849*06c3fb27SDimitry Andric 850*06c3fb27SDimitry Andric// ASIMD multiply 851*06c3fb27SDimitry Andric// ASIMD multiply accumulate 852*06c3fb27SDimitry Andric// ASIMD multiply accumulate long 853*06c3fb27SDimitry Andric// ASIMD multiply accumulate high 854*06c3fb27SDimitry Andric// ASIMD multiply accumulate saturating long 855*06c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_1V02], 856*06c3fb27SDimitry Andric (instregex "^MUL(v[148]i16|v[124]i32)$", 857*06c3fb27SDimitry Andric "^SQR?DMULH(v[48]i16|v[24]i32)$", 858*06c3fb27SDimitry Andric "^ML[AS](v[148]i16|v[124]i32)$", 859*06c3fb27SDimitry Andric "^[SU]ML[AS]Lv", 860*06c3fb27SDimitry Andric "^SQRDML[AS]H(v[148]i16|v[124]i32)$", 861*06c3fb27SDimitry Andric "^SQDML[AS]Lv")>; 862*06c3fb27SDimitry Andric 863*06c3fb27SDimitry Andric// ASIMD multiply/multiply long (8x8) polynomial 864*06c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1V01], (instregex "^PMULL?v(8|16)i8$")>; 865*06c3fb27SDimitry Andric 866*06c3fb27SDimitry Andric// ASIMD multiply long 867*06c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1V02], (instregex "^([SU]|SQD)MULLv")>; 868*06c3fb27SDimitry Andric 869*06c3fb27SDimitry Andric// ASIMD shift accumulate 870*06c3fb27SDimitry Andric// ASIMD shift by immed, complex 871*06c3fb27SDimitry Andric// ASIMD shift by register, complex 872*06c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_1V13], 873*06c3fb27SDimitry Andric (instregex "^[SU]R?SRAv", 874*06c3fb27SDimitry Andric "^RSHRNv", "^SQRSHRU?Nv", "^(SQSHLU?|UQSHL)[bhsd]$", 875*06c3fb27SDimitry Andric "^(SQSHLU?|UQSHL)(v8i8|v16i8|v4i16|v8i16|v2i32|v4i32|v2i64)_shift$", 876*06c3fb27SDimitry Andric "^SQSHU?RNv", "^[SU]RSHRv", "^UQR?SHRNv", 877*06c3fb27SDimitry Andric "^[SU]Q?RSHLv", "^[SU]QSHLv")>; 878*06c3fb27SDimitry Andric 879*06c3fb27SDimitry Andric// ASIMD shift by immed, basic 880*06c3fb27SDimitry Andric// ASIMD shift by immed and insert, basic 881*06c3fb27SDimitry Andric// ASIMD shift by register, basic 882*06c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1V13], (instregex "^SHLL?v", "^SHRNv", "^[SU]SHLLv", 883*06c3fb27SDimitry Andric "^[SU]SHRv", "^S[LR]Iv", "^[SU]SHLv")>; 884*06c3fb27SDimitry Andric 885*06c3fb27SDimitry Andric 886*06c3fb27SDimitry Andric// ASIMD FP instructions 887*06c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 888*06c3fb27SDimitry Andric 889*06c3fb27SDimitry Andric// ASIMD FP absolute value/difference 890*06c3fb27SDimitry Andric// ASIMD FP arith, normal 891*06c3fb27SDimitry Andric// ASIMD FP compare 892*06c3fb27SDimitry Andric// ASIMD FP complex add 893*06c3fb27SDimitry Andric// ASIMD FP max/min, normal 894*06c3fb27SDimitry Andric// ASIMD FP max/min, pairwise 895*06c3fb27SDimitry Andric// ASIMD FP negate 896*06c3fb27SDimitry Andric// Covered by "SchedAlias (WriteV[dq]...)" above 897*06c3fb27SDimitry Andric 898*06c3fb27SDimitry Andric// ASIMD FP complex multiply add 899*06c3fb27SDimitry Andric// ASIMD FP multiply accumulate 900*06c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_1V], (instregex "^FCADD(v[48]f16|v[24]f32|v2f64)$", 901*06c3fb27SDimitry Andric "^FML[AS]v")>; 902*06c3fb27SDimitry Andric 903*06c3fb27SDimitry Andric// ASIMD FP convert, long (F16 to F32) 904*06c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_2V02], (instregex "^FCVTLv[48]i16$")>; 905*06c3fb27SDimitry Andric 906*06c3fb27SDimitry Andric// ASIMD FP convert, long (F32 to F64) 907*06c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1V02], (instregex "^FCVTLv[24]i32$")>; 908*06c3fb27SDimitry Andric 909*06c3fb27SDimitry Andric// ASIMD FP convert, narrow (F32 to F16) 910*06c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_2V02], (instregex "^FCVTNv[48]i16$")>; 911*06c3fb27SDimitry Andric 912*06c3fb27SDimitry Andric// ASIMD FP convert, narrow (F64 to F32) 913*06c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1V02], (instregex "^FCVTNv[24]i32$", 914*06c3fb27SDimitry Andric "^FCVTXN(v[24]f32|v1i64)$")>; 915*06c3fb27SDimitry Andric 916*06c3fb27SDimitry Andric// ASIMD FP convert, other, D-form F32 and Q-form F64 917*06c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1V02], (instregex "^[FSU]CVT[AMNPZ][SU]v2f(32|64)$", 918*06c3fb27SDimitry Andric "^[SU]CVTFv2f(32|64)$")>; 919*06c3fb27SDimitry Andric 920*06c3fb27SDimitry Andric// ASIMD FP convert, other, D-form F16 and Q-form F32 921*06c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_2V02], (instregex "^[FSU]CVT[AMNPZ][SU]v4f(16|32)$", 922*06c3fb27SDimitry Andric "^[SU]CVTFv4f(16|32)$")>; 923*06c3fb27SDimitry Andric 924*06c3fb27SDimitry Andric// ASIMD FP convert, other, Q-form F16 925*06c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_4V02], (instregex "^[FSU]CVT[AMNPZ][SU]v8f16$", 926*06c3fb27SDimitry Andric "^[SU]CVTFv8f16$")>; 927*06c3fb27SDimitry Andric 928*06c3fb27SDimitry Andric// ASIMD FP divide, D-form, F16 929*06c3fb27SDimitry Andric// ASIMD FP square root, D-form, F16 930*06c3fb27SDimitry Andricdef : InstRW<[V1Write_7c7_1V02], (instrs FDIVv4f16, FSQRTv4f16)>; 931*06c3fb27SDimitry Andric 932*06c3fb27SDimitry Andric// ASIMD FP divide, F32 933*06c3fb27SDimitry Andric// ASIMD FP square root, F32 934*06c3fb27SDimitry Andricdef : InstRW<[V1Write_10c7_1V02], (instrs FDIVv2f32, FDIVv4f32, 935*06c3fb27SDimitry Andric FSQRTv2f32, FSQRTv4f32)>; 936*06c3fb27SDimitry Andric 937*06c3fb27SDimitry Andric// ASIMD FP divide, Q-form, F16 938*06c3fb27SDimitry Andricdef : InstRW<[V1Write_13c5_1V02], (instrs FDIVv8f16)>; 939*06c3fb27SDimitry Andric 940*06c3fb27SDimitry Andric// ASIMD FP divide, Q-form, F64 941*06c3fb27SDimitry Andricdef : InstRW<[V1Write_15c7_1V02], (instrs FDIVv2f64)>; 942*06c3fb27SDimitry Andric 943*06c3fb27SDimitry Andric// ASIMD FP square root, Q-form, F16 944*06c3fb27SDimitry Andricdef : InstRW<[V1Write_13c11_1V02], (instrs FSQRTv8f16)>; 945*06c3fb27SDimitry Andric 946*06c3fb27SDimitry Andric// ASIMD FP square root, Q-form, F64 947*06c3fb27SDimitry Andricdef : InstRW<[V1Write_16c7_1V02], (instrs FSQRTv2f64)>; 948*06c3fb27SDimitry Andric 949*06c3fb27SDimitry Andric// ASIMD FP max/min, reduce, F32 and D-form F16 950*06c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_2V], (instregex "^F(MAX|MIN)(NM)?Vv4(i16|i32)v$")>; 951*06c3fb27SDimitry Andric 952*06c3fb27SDimitry Andric// ASIMD FP max/min, reduce, Q-form F16 953*06c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_3V], (instregex "^F(MAX|MIN)(NM)?Vv8i16v$")>; 954*06c3fb27SDimitry Andric 955*06c3fb27SDimitry Andric// ASIMD FP multiply 956*06c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1V], (instregex "^FMULX?v")>; 957*06c3fb27SDimitry Andric 958*06c3fb27SDimitry Andric// ASIMD FP multiply accumulate long 959*06c3fb27SDimitry Andricdef : InstRW<[V1Write_5c_1V], (instregex "^FML[AS]L2?v")>; 960*06c3fb27SDimitry Andric 961*06c3fb27SDimitry Andric// ASIMD FP round, D-form F32 and Q-form F64 962*06c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1V02], (instregex "^FRINT[AIMNPXZ]v2f(32|64)$")>; 963*06c3fb27SDimitry Andric 964*06c3fb27SDimitry Andric// ASIMD FP round, D-form F16 and Q-form F32 965*06c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_2V02], (instregex "^FRINT[AIMNPXZ]v4f(16|32)$")>; 966*06c3fb27SDimitry Andric 967*06c3fb27SDimitry Andric// ASIMD FP round, Q-form F16 968*06c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_4V02], (instregex "^FRINT[AIMNPXZ]v8f16$")>; 969*06c3fb27SDimitry Andric 970*06c3fb27SDimitry Andric 971*06c3fb27SDimitry Andric// ASIMD BF instructions 972*06c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 973*06c3fb27SDimitry Andric 974*06c3fb27SDimitry Andric// ASIMD convert, F32 to BF16 975*06c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_1V02], (instrs BFCVTN, BFCVTN2)>; 976*06c3fb27SDimitry Andric 977*06c3fb27SDimitry Andric// ASIMD dot product 978*06c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_1V], (instregex "^BF(DOT|16DOTlane)v[48]bf16$")>; 979*06c3fb27SDimitry Andric 980*06c3fb27SDimitry Andric// ASIMD matrix multiply accumulate 981*06c3fb27SDimitry Andricdef : InstRW<[V1Write_5c_1V], (instrs BFMMLA)>; 982*06c3fb27SDimitry Andric 983*06c3fb27SDimitry Andric// ASIMD multiply accumulate long 984*06c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_1V], (instregex "^BFMLAL[BT](Idx)?$")>; 985*06c3fb27SDimitry Andric 986*06c3fb27SDimitry Andric// Scalar convert, F32 to BF16 987*06c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1V02], (instrs BFCVT)>; 988*06c3fb27SDimitry Andric 989*06c3fb27SDimitry Andric 990*06c3fb27SDimitry Andric// ASIMD miscellaneous instructions 991*06c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 992*06c3fb27SDimitry Andric 993*06c3fb27SDimitry Andric// ASIMD bit reverse 994*06c3fb27SDimitry Andric// ASIMD bitwise insert 995*06c3fb27SDimitry Andric// ASIMD count 996*06c3fb27SDimitry Andric// ASIMD duplicate, element 997*06c3fb27SDimitry Andric// ASIMD extract 998*06c3fb27SDimitry Andric// ASIMD extract narrow 999*06c3fb27SDimitry Andric// ASIMD insert, element to element 1000*06c3fb27SDimitry Andric// ASIMD move, FP immed 1001*06c3fb27SDimitry Andric// ASIMD move, integer immed 1002*06c3fb27SDimitry Andric// ASIMD reverse 1003*06c3fb27SDimitry Andric// ASIMD table lookup, 1 or 2 table regs 1004*06c3fb27SDimitry Andric// ASIMD table lookup extension, 1 table reg 1005*06c3fb27SDimitry Andric// ASIMD transfer, element to gen reg 1006*06c3fb27SDimitry Andric// ASIMD transpose 1007*06c3fb27SDimitry Andric// ASIMD unzip/zip 1008*06c3fb27SDimitry Andric// Covered by "SchedAlias (WriteV[dq]...)" above 1009*06c3fb27SDimitry Andric 1010*06c3fb27SDimitry Andric// ASIMD duplicate, gen reg 1011*06c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1M0], 1012*06c3fb27SDimitry Andric (instregex "^DUP((v16|v8)i8|(v8|v4)i16|(v4|v2)i32|v2i64)gpr$")>; 1013*06c3fb27SDimitry Andric 1014*06c3fb27SDimitry Andric// ASIMD extract narrow, saturating 1015*06c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_1V13], (instregex "^[SU]QXTNv", "^SQXTUNv")>; 1016*06c3fb27SDimitry Andric 1017*06c3fb27SDimitry Andric// ASIMD reciprocal and square root estimate, D-form U32 1018*06c3fb27SDimitry Andric// ASIMD reciprocal and square root estimate, D-form F32 and F64 1019*06c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1V02], (instrs URECPEv2i32, 1020*06c3fb27SDimitry Andric URSQRTEv2i32, 1021*06c3fb27SDimitry Andric FRECPEv1i32, FRECPEv2f32, FRECPEv1i64, 1022*06c3fb27SDimitry Andric FRSQRTEv1i32, FRSQRTEv2f32, FRSQRTEv1i64)>; 1023*06c3fb27SDimitry Andric 1024*06c3fb27SDimitry Andric// ASIMD reciprocal and square root estimate, Q-form U32 1025*06c3fb27SDimitry Andric// ASIMD reciprocal and square root estimate, D-form F16 and Q-form F32 and F64 1026*06c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_1V02], (instrs URECPEv4i32, 1027*06c3fb27SDimitry Andric URSQRTEv4i32, 1028*06c3fb27SDimitry Andric FRECPEv1f16, FRECPEv4f16, 1029*06c3fb27SDimitry Andric FRECPEv4f32, FRECPEv2f64, 1030*06c3fb27SDimitry Andric FRSQRTEv1f16, FRSQRTEv4f16, 1031*06c3fb27SDimitry Andric FRSQRTEv4f32, FRSQRTEv2f64)>; 1032*06c3fb27SDimitry Andric 1033*06c3fb27SDimitry Andric// ASIMD reciprocal and square root estimate, Q-form F16 1034*06c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_2V02], (instrs FRECPEv8f16, 1035*06c3fb27SDimitry Andric FRSQRTEv8f16)>; 1036*06c3fb27SDimitry Andric 1037*06c3fb27SDimitry Andric// ASIMD reciprocal exponent 1038*06c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1V02], (instrs FRECPXv1f16, FRECPXv1i32, FRECPXv1i64)>; 1039*06c3fb27SDimitry Andric 1040*06c3fb27SDimitry Andric// ASIMD reciprocal step 1041*06c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_1V], (instregex "^FRECPS(16|32|64)$", "^FRECPSv", 1042*06c3fb27SDimitry Andric "^FRSQRTS(16|32|64)$", "^FRSQRTSv")>; 1043*06c3fb27SDimitry Andric 1044*06c3fb27SDimitry Andric// ASIMD table lookup, 1 or 2 table regs 1045*06c3fb27SDimitry Andric// ASIMD table lookup extension, 1 table reg 1046*06c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_2V01], (instregex "^TBLv(8|16)i8(One|Two)$", 1047*06c3fb27SDimitry Andric "^TBXv(8|16)i8One$")>; 1048*06c3fb27SDimitry Andric 1049*06c3fb27SDimitry Andric// ASIMD table lookup, 3 table regs 1050*06c3fb27SDimitry Andric// ASIMD table lookup extension, 2 table reg 1051*06c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_2V01], (instrs TBLv8i8Three, TBLv16i8Three, 1052*06c3fb27SDimitry Andric TBXv8i8Two, TBXv16i8Two)>; 1053*06c3fb27SDimitry Andric 1054*06c3fb27SDimitry Andric// ASIMD table lookup, 4 table regs 1055*06c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_3V01], (instrs TBLv8i8Four, TBLv16i8Four)>; 1056*06c3fb27SDimitry Andric 1057*06c3fb27SDimitry Andric// ASIMD table lookup extension, 3 table reg 1058*06c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_3V01], (instrs TBXv8i8Three, TBXv16i8Three)>; 1059*06c3fb27SDimitry Andric 1060*06c3fb27SDimitry Andric// ASIMD table lookup extension, 4 table reg 1061*06c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_5V01], (instrs TBXv8i8Four, TBXv16i8Four)>; 1062*06c3fb27SDimitry Andric 1063*06c3fb27SDimitry Andric// ASIMD transfer, element to gen reg 1064*06c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1V], (instregex "^SMOVvi(((8|16)to(32|64))|32to64)$", 1065*06c3fb27SDimitry Andric "^UMOVvi(8|16|32|64)$")>; 1066*06c3fb27SDimitry Andric 1067*06c3fb27SDimitry Andric// ASIMD transfer, gen reg to element 1068*06c3fb27SDimitry Andricdef : InstRW<[V1Write_5c_1M0_1V], (instregex "^INSvi(8|16|32|64)gpr$")>; 1069*06c3fb27SDimitry Andric 1070*06c3fb27SDimitry Andric 1071*06c3fb27SDimitry Andric// ASIMD load instructions 1072*06c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 1073*06c3fb27SDimitry Andric 1074*06c3fb27SDimitry Andric// ASIMD load, 1 element, multiple, 1 reg 1075*06c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_1L], 1076*06c3fb27SDimitry Andric (instregex "^LD1Onev(8b|16b|4h|8h|2s|4s|1d|2d)$")>; 1077*06c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_1L, WriteAdr], 1078*06c3fb27SDimitry Andric (instregex "^LD1Onev(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>; 1079*06c3fb27SDimitry Andric 1080*06c3fb27SDimitry Andric// ASIMD load, 1 element, multiple, 2 reg 1081*06c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_2L], 1082*06c3fb27SDimitry Andric (instregex "^LD1Twov(8b|16b|4h|8h|2s|4s|1d|2d)$")>; 1083*06c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_2L, WriteAdr], 1084*06c3fb27SDimitry Andric (instregex "^LD1Twov(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>; 1085*06c3fb27SDimitry Andric 1086*06c3fb27SDimitry Andric// ASIMD load, 1 element, multiple, 3 reg 1087*06c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_3L], 1088*06c3fb27SDimitry Andric (instregex "^LD1Threev(8b|16b|4h|8h|2s|4s|1d|2d)$")>; 1089*06c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_3L, WriteAdr], 1090*06c3fb27SDimitry Andric (instregex "^LD1Threev(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>; 1091*06c3fb27SDimitry Andric 1092*06c3fb27SDimitry Andric// ASIMD load, 1 element, multiple, 4 reg, D-form 1093*06c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_2L], 1094*06c3fb27SDimitry Andric (instregex "^LD1Fourv(8b|4h|2s|1d)$")>; 1095*06c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_2L, WriteAdr], 1096*06c3fb27SDimitry Andric (instregex "^LD1Fourv(8b|4h|2s|1d)_POST$")>; 1097*06c3fb27SDimitry Andric 1098*06c3fb27SDimitry Andric// ASIMD load, 1 element, multiple, 4 reg, Q-form 1099*06c3fb27SDimitry Andricdef : InstRW<[V1Write_7c_4L], 1100*06c3fb27SDimitry Andric (instregex "^LD1Fourv(16b|8h|4s|2d)$")>; 1101*06c3fb27SDimitry Andricdef : InstRW<[V1Write_7c_4L, WriteAdr], 1102*06c3fb27SDimitry Andric (instregex "^LD1Fourv(16b|8h|4s|2d)_POST$")>; 1103*06c3fb27SDimitry Andric 1104*06c3fb27SDimitry Andric// ASIMD load, 1 element, one lane 1105*06c3fb27SDimitry Andric// ASIMD load, 1 element, all lanes 1106*06c3fb27SDimitry Andricdef : InstRW<[V1Write_8c_1L_1V], 1107*06c3fb27SDimitry Andric (instregex "^LD1(i|Rv)(8|16|32|64)$", 1108*06c3fb27SDimitry Andric "^LD1Rv(8b|16b|4h|8h|2s|4s|1d|2d)$")>; 1109*06c3fb27SDimitry Andricdef : InstRW<[V1Write_8c_1L_1V, WriteAdr], 1110*06c3fb27SDimitry Andric (instregex "^LD1i(8|16|32|64)_POST$", 1111*06c3fb27SDimitry Andric "^LD1Rv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>; 1112*06c3fb27SDimitry Andric 1113*06c3fb27SDimitry Andric// ASIMD load, 2 element, multiple, D-form 1114*06c3fb27SDimitry Andricdef : InstRW<[V1Write_8c_1L_2V], 1115*06c3fb27SDimitry Andric (instregex "^LD2Twov(8b|4h|2s)$")>; 1116*06c3fb27SDimitry Andricdef : InstRW<[V1Write_8c_1L_2V, WriteAdr], 1117*06c3fb27SDimitry Andric (instregex "^LD2Twov(8b|4h|2s)_POST$")>; 1118*06c3fb27SDimitry Andric 1119*06c3fb27SDimitry Andric// ASIMD load, 2 element, multiple, Q-form 1120*06c3fb27SDimitry Andricdef : InstRW<[V1Write_8c_2L_2V], 1121*06c3fb27SDimitry Andric (instregex "^LD2Twov(16b|8h|4s|2d)$")>; 1122*06c3fb27SDimitry Andricdef : InstRW<[V1Write_8c_2L_2V, WriteAdr], 1123*06c3fb27SDimitry Andric (instregex "^LD2Twov(16b|8h|4s|2d)_POST$")>; 1124*06c3fb27SDimitry Andric 1125*06c3fb27SDimitry Andric// ASIMD load, 2 element, one lane 1126*06c3fb27SDimitry Andric// ASIMD load, 2 element, all lanes 1127*06c3fb27SDimitry Andricdef : InstRW<[V1Write_8c_1L_2V], 1128*06c3fb27SDimitry Andric (instregex "^LD2i(8|16|32|64)$", 1129*06c3fb27SDimitry Andric "^LD2Rv(8b|16b|4h|8h|2s|4s|1d|2d)$")>; 1130*06c3fb27SDimitry Andricdef : InstRW<[V1Write_8c_1L_2V, WriteAdr], 1131*06c3fb27SDimitry Andric (instregex "^LD2i(8|16|32|64)_POST$", 1132*06c3fb27SDimitry Andric "^LD2Rv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>; 1133*06c3fb27SDimitry Andric 1134*06c3fb27SDimitry Andric// ASIMD load, 3 element, multiple, D-form 1135*06c3fb27SDimitry Andric// ASIMD load, 3 element, one lane 1136*06c3fb27SDimitry Andric// ASIMD load, 3 element, all lanes 1137*06c3fb27SDimitry Andricdef : InstRW<[V1Write_8c_2L_3V], 1138*06c3fb27SDimitry Andric (instregex "^LD3Threev(8b|4h|2s)$", 1139*06c3fb27SDimitry Andric "^LD3i(8|16|32|64)$", 1140*06c3fb27SDimitry Andric "^LD3Rv(8b|16b|4h|8h|2s|4s|1d|2d)$")>; 1141*06c3fb27SDimitry Andricdef : InstRW<[V1Write_8c_2L_3V, WriteAdr], 1142*06c3fb27SDimitry Andric (instregex "^LD3Threev(8b|4h|2s)_POST$", 1143*06c3fb27SDimitry Andric "^LD3i(8|16|32|64)_POST$", 1144*06c3fb27SDimitry Andric "^LD3Rv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>; 1145*06c3fb27SDimitry Andric 1146*06c3fb27SDimitry Andric// ASIMD load, 3 element, multiple, Q-form 1147*06c3fb27SDimitry Andricdef : InstRW<[V1Write_8c_3L_3V], 1148*06c3fb27SDimitry Andric (instregex "^LD3Threev(16b|8h|4s|2d)$")>; 1149*06c3fb27SDimitry Andricdef : InstRW<[V1Write_8c_3L_3V, WriteAdr], 1150*06c3fb27SDimitry Andric (instregex "^LD3Threev(16b|8h|4s|2d)_POST$")>; 1151*06c3fb27SDimitry Andric 1152*06c3fb27SDimitry Andric// ASIMD load, 4 element, multiple, D-form 1153*06c3fb27SDimitry Andric// ASIMD load, 4 element, one lane 1154*06c3fb27SDimitry Andric// ASIMD load, 4 element, all lanes 1155*06c3fb27SDimitry Andricdef : InstRW<[V1Write_8c_3L_4V], 1156*06c3fb27SDimitry Andric (instregex "^LD4Fourv(8b|4h|2s)$", 1157*06c3fb27SDimitry Andric "^LD4i(8|16|32|64)$", 1158*06c3fb27SDimitry Andric "^LD4Rv(8b|16b|4h|8h|2s|4s|1d|2d)$")>; 1159*06c3fb27SDimitry Andricdef : InstRW<[V1Write_8c_3L_4V, WriteAdr], 1160*06c3fb27SDimitry Andric (instregex "^LD4Fourv(8b|4h|2s)_POST$", 1161*06c3fb27SDimitry Andric "^LD4i(8|16|32|64)_POST$", 1162*06c3fb27SDimitry Andric "^LD4Rv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>; 1163*06c3fb27SDimitry Andric 1164*06c3fb27SDimitry Andric// ASIMD load, 4 element, multiple, Q-form 1165*06c3fb27SDimitry Andricdef : InstRW<[V1Write_9c_4L_4V], 1166*06c3fb27SDimitry Andric (instregex "^LD4Fourv(16b|8h|4s|2d)$")>; 1167*06c3fb27SDimitry Andricdef : InstRW<[V1Write_9c_4L_4V, WriteAdr], 1168*06c3fb27SDimitry Andric (instregex "^LD4Fourv(16b|8h|4s|2d)_POST$")>; 1169*06c3fb27SDimitry Andric 1170*06c3fb27SDimitry Andric 1171*06c3fb27SDimitry Andric// ASIMD store instructions 1172*06c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 1173*06c3fb27SDimitry Andric 1174*06c3fb27SDimitry Andric// ASIMD store, 1 element, multiple, 1 reg 1175*06c3fb27SDimitry Andric// ASIMD store, 1 element, multiple, 2 reg, D-form 1176*06c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1L01_1V01], 1177*06c3fb27SDimitry Andric (instregex "^ST1Onev(8b|16b|4h|8h|2s|4s|1d|2d)$", 1178*06c3fb27SDimitry Andric "^ST1Twov(8b|4h|2s|1d)$")>; 1179*06c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1L01_1V01, WriteAdr], 1180*06c3fb27SDimitry Andric (instregex "^ST1Onev(8b|16b|4h|8h|2s|4s|1d|2d)_POST$", 1181*06c3fb27SDimitry Andric "^ST1Twov(8b|4h|2s|1d)_POST$")>; 1182*06c3fb27SDimitry Andric 1183*06c3fb27SDimitry Andric// ASIMD store, 1 element, multiple, 2 reg, Q-form 1184*06c3fb27SDimitry Andric// ASIMD store, 1 element, multiple, 3 reg, D-form 1185*06c3fb27SDimitry Andric// ASIMD store, 1 element, multiple, 4 reg, D-form 1186*06c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_2L01_2V01], 1187*06c3fb27SDimitry Andric (instregex "^ST1Twov(16b|8h|4s|2d)$", 1188*06c3fb27SDimitry Andric "^ST1Threev(8b|4h|2s|1d)$", 1189*06c3fb27SDimitry Andric "^ST1Fourv(8b|4h|2s|1d)$")>; 1190*06c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_2L01_2V01, WriteAdr], 1191*06c3fb27SDimitry Andric (instregex "^ST1Twov(16b|8h|4s|2d)_POST$", 1192*06c3fb27SDimitry Andric "^ST1Threev(8b|4h|2s|1d)_POST$", 1193*06c3fb27SDimitry Andric "^ST1Fourv(8b|4h|2s|1d)_POST$")>; 1194*06c3fb27SDimitry Andric 1195*06c3fb27SDimitry Andric// ASIMD store, 1 element, multiple, 3 reg, Q-form 1196*06c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_3L01_3V01], 1197*06c3fb27SDimitry Andric (instregex "^ST1Threev(16b|8h|4s|2d)$")>; 1198*06c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_3L01_3V01, WriteAdr], 1199*06c3fb27SDimitry Andric (instregex "^ST1Threev(16b|8h|4s|2d)_POST$")>; 1200*06c3fb27SDimitry Andric 1201*06c3fb27SDimitry Andric// ASIMD store, 1 element, multiple, 4 reg, Q-form 1202*06c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_4L01_4V01], 1203*06c3fb27SDimitry Andric (instregex "^ST1Fourv(16b|8h|4s|2d)$")>; 1204*06c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_4L01_4V01, WriteAdr], 1205*06c3fb27SDimitry Andric (instregex "^ST1Fourv(16b|8h|4s|2d)_POST$")>; 1206*06c3fb27SDimitry Andric 1207*06c3fb27SDimitry Andric// ASIMD store, 1 element, one lane 1208*06c3fb27SDimitry Andric// ASIMD store, 2 element, multiple, D-form 1209*06c3fb27SDimitry Andric// ASIMD store, 2 element, one lane 1210*06c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_1L01_1V01], 1211*06c3fb27SDimitry Andric (instregex "^ST1i(8|16|32|64)$", 1212*06c3fb27SDimitry Andric "^ST2Twov(8b|4h|2s)$", 1213*06c3fb27SDimitry Andric "^ST2i(8|16|32|64)$")>; 1214*06c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_1L01_1V01, WriteAdr], 1215*06c3fb27SDimitry Andric (instregex "^ST1i(8|16|32|64)_POST$", 1216*06c3fb27SDimitry Andric "^ST2Twov(8b|4h|2s)_POST$", 1217*06c3fb27SDimitry Andric "^ST2i(8|16|32|64)_POST$")>; 1218*06c3fb27SDimitry Andric 1219*06c3fb27SDimitry Andric// ASIMD store, 2 element, multiple, Q-form 1220*06c3fb27SDimitry Andric// ASIMD store, 3 element, multiple, D-form 1221*06c3fb27SDimitry Andric// ASIMD store, 3 element, one lane 1222*06c3fb27SDimitry Andric// ASIMD store, 4 element, one lane, D 1223*06c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_2L01_2V01], 1224*06c3fb27SDimitry Andric (instregex "^ST2Twov(16b|8h|4s|2d)$", 1225*06c3fb27SDimitry Andric "^ST3Threev(8b|4h|2s)$", 1226*06c3fb27SDimitry Andric "^ST3i(8|16|32|64)$", 1227*06c3fb27SDimitry Andric "^ST4i64$")>; 1228*06c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_2L01_2V01, WriteAdr], 1229*06c3fb27SDimitry Andric (instregex "^ST2Twov(16b|8h|4s|2d)_POST$", 1230*06c3fb27SDimitry Andric "^ST3Threev(8b|4h|2s)_POST$", 1231*06c3fb27SDimitry Andric "^ST3i(8|16|32|64)_POST$", 1232*06c3fb27SDimitry Andric "^ST4i64_POST$")>; 1233*06c3fb27SDimitry Andric 1234*06c3fb27SDimitry Andric// ASIMD store, 3 element, multiple, Q-form 1235*06c3fb27SDimitry Andricdef : InstRW<[V1Write_5c_3L01_3V01], 1236*06c3fb27SDimitry Andric (instregex "^ST3Threev(16b|8h|4s|2d)$")>; 1237*06c3fb27SDimitry Andricdef : InstRW<[V1Write_5c_3L01_3V01, WriteAdr], 1238*06c3fb27SDimitry Andric (instregex "^ST3Threev(16b|8h|4s|2d)_POST$")>; 1239*06c3fb27SDimitry Andric 1240*06c3fb27SDimitry Andric// ASIMD store, 4 element, multiple, D-form 1241*06c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_3L01_3V01], 1242*06c3fb27SDimitry Andric (instregex "^ST4Fourv(8b|4h|2s)$")>; 1243*06c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_3L01_3V01, WriteAdr], 1244*06c3fb27SDimitry Andric (instregex "^ST4Fourv(8b|4h|2s)_POST$")>; 1245*06c3fb27SDimitry Andric 1246*06c3fb27SDimitry Andric// ASIMD store, 4 element, multiple, Q-form, B/H/S 1247*06c3fb27SDimitry Andricdef : InstRW<[V1Write_7c_6L01_6V01], 1248*06c3fb27SDimitry Andric (instregex "^ST4Fourv(16b|8h|4s)$")>; 1249*06c3fb27SDimitry Andricdef : InstRW<[V1Write_7c_6L01_6V01, WriteAdr], 1250*06c3fb27SDimitry Andric (instregex "^ST4Fourv(16b|8h|4s)_POST$")>; 1251*06c3fb27SDimitry Andric 1252*06c3fb27SDimitry Andric// ASIMD store, 4 element, multiple, Q-form, D 1253*06c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_4L01_4V01], 1254*06c3fb27SDimitry Andric (instrs ST4Fourv2d)>; 1255*06c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_4L01_4V01, WriteAdr], 1256*06c3fb27SDimitry Andric (instrs ST4Fourv2d_POST)>; 1257*06c3fb27SDimitry Andric 1258*06c3fb27SDimitry Andric// ASIMD store, 4 element, one lane, B/H/S 1259*06c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_3L_3V], 1260*06c3fb27SDimitry Andric (instregex "^ST4i(8|16|32)$")>; 1261*06c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_3L_3V, WriteAdr], 1262*06c3fb27SDimitry Andric (instregex "^ST4i(8|16|32)_POST$")>; 1263*06c3fb27SDimitry Andric 1264*06c3fb27SDimitry Andric 1265*06c3fb27SDimitry Andric// Cryptography extensions 1266*06c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 1267*06c3fb27SDimitry Andric 1268*06c3fb27SDimitry Andric// Crypto polynomial (64x64) multiply long 1269*06c3fb27SDimitry Andric// Covered by "SchedAlias (WriteV[dq]...)" above 1270*06c3fb27SDimitry Andric 1271*06c3fb27SDimitry Andric// Crypto AES ops 1272*06c3fb27SDimitry Andricdef V1WriteVC : WriteSequence<[V1Write_2c_1V]>; 1273*06c3fb27SDimitry Andricdef V1ReadVC : SchedReadAdvance<2, [V1WriteVC]>; 1274*06c3fb27SDimitry Andricdef : InstRW<[V1WriteVC], (instrs AESDrr, AESErr)>; 1275*06c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1V, V1ReadVC], (instrs AESMCrr, AESIMCrr)>; 1276*06c3fb27SDimitry Andric 1277*06c3fb27SDimitry Andric// Crypto SHA1 hash acceleration op 1278*06c3fb27SDimitry Andric// Crypto SHA1 schedule acceleration ops 1279*06c3fb27SDimitry Andric// Crypto SHA256 schedule acceleration ops 1280*06c3fb27SDimitry Andric// Crypto SHA512 hash acceleration ops 1281*06c3fb27SDimitry Andric// Crypto SM3 ops 1282*06c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1V0], (instregex "^SHA1(H|SU[01])rr$", 1283*06c3fb27SDimitry Andric "^SHA256SU[01]rr$", 1284*06c3fb27SDimitry Andric "^SHA512(H2?|SU[01])$", 1285*06c3fb27SDimitry Andric "^SM3(PARTW(1|2SM3SS1)|TT[12][AB])$")>; 1286*06c3fb27SDimitry Andric 1287*06c3fb27SDimitry Andric// Crypto SHA1 hash acceleration ops 1288*06c3fb27SDimitry Andric// Crypto SHA256 hash acceleration ops 1289*06c3fb27SDimitry Andric// Crypto SM4 ops 1290*06c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_1V0], (instregex "^SHA1[CMP]rrr$", 1291*06c3fb27SDimitry Andric "^SHA256H2?rrr$", 1292*06c3fb27SDimitry Andric "^SM4E(KEY)?$")>; 1293*06c3fb27SDimitry Andric 1294*06c3fb27SDimitry Andric// Crypto SHA3 ops 1295*06c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1V0], (instrs BCAX, EOR3, RAX1, XAR)>; 1296*06c3fb27SDimitry Andric 1297*06c3fb27SDimitry Andric 1298*06c3fb27SDimitry Andric// CRC instruction 1299*06c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 1300*06c3fb27SDimitry Andric 1301*06c3fb27SDimitry Andric// CRC checksum ops 1302*06c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1M0], (instregex "^CRC32C?[BHWX]rr$")>; 1303*06c3fb27SDimitry Andric 1304*06c3fb27SDimitry Andric 1305*06c3fb27SDimitry Andric// SVE Predicate instructions 1306*06c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 1307*06c3fb27SDimitry Andric 1308*06c3fb27SDimitry Andric// Loop control, based on predicate 1309*06c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1M0], (instregex "^BRK[AB]_PP[mz]P$")>; 1310*06c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1M0], (instrs BRKN_PPzP, BRKPA_PPzPP, BRKPB_PPzPP)>; 1311*06c3fb27SDimitry Andric 1312*06c3fb27SDimitry Andric// Loop control, based on predicate and flag setting 1313*06c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_2M0], (instrs BRKAS_PPzP, BRKBS_PPzP, BRKNS_PPzP, 1314*06c3fb27SDimitry Andric BRKPAS_PPzPP, BRKPBS_PPzPP)>; 1315*06c3fb27SDimitry Andric 1316*06c3fb27SDimitry Andric// Loop control, based on GPR 1317*06c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_2M0], (instregex "^WHILE(LE|LO|LS|LT)_P(WW|XX)_[BHSD]$")>; 1318*06c3fb27SDimitry Andric 1319*06c3fb27SDimitry Andric// Loop terminate 1320*06c3fb27SDimitry Andricdef : InstRW<[V1Write_1c_1M0], (instregex "^CTERM(EQ|NE)_(WW|XX)$")>; 1321*06c3fb27SDimitry Andric 1322*06c3fb27SDimitry Andric// Predicate counting scalar 1323*06c3fb27SDimitry Andric// Predicate counting scalar, active predicate 1324*06c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1M0], (instrs ADDPL_XXI, ADDVL_XXI, RDVLI_XI)>; 1325*06c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1M0], (instregex "^(CNT|([SU]Q)?(DEC|INC))[BHWD]_XPiI$", 1326*06c3fb27SDimitry Andric "^SQ(DEC|INC)[BHWD]_XPiWdI$", 1327*06c3fb27SDimitry Andric "^UQ(DEC|INC)[BHWD]_WPiI$", 1328*06c3fb27SDimitry Andric "^CNTP_XPP_[BHSD]$", 1329*06c3fb27SDimitry Andric "^([SU]Q)?(DEC|INC)P_XP_[BHSD]$", 1330*06c3fb27SDimitry Andric "^UQ(DEC|INC)P_WP_[BHSD]$", 1331*06c3fb27SDimitry Andric "^[SU]Q(DEC|INC)P_XPWd_[BHSD]$")>; 1332*06c3fb27SDimitry Andric 1333*06c3fb27SDimitry Andric// Predicate counting vector, active predicate 1334*06c3fb27SDimitry Andricdef : InstRW<[V1Write_7c_2M0_1V01], (instregex "^([SU]Q)?(DEC|INC)P_ZP_[HSD]$")>; 1335*06c3fb27SDimitry Andric 1336*06c3fb27SDimitry Andric// Predicate logical 1337*06c3fb27SDimitry Andricdef : InstRW<[V1Write_1c_1M0], 1338*06c3fb27SDimitry Andric (instregex "^(AND|BIC|EOR|NAND|NOR|ORN|ORR)_PPzPP$")>; 1339*06c3fb27SDimitry Andric 1340*06c3fb27SDimitry Andric// Predicate logical, flag setting 1341*06c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_2M0], 1342*06c3fb27SDimitry Andric (instregex "^(AND|BIC|EOR|NAND|NOR|ORN|ORR)S_PPzPP$")>; 1343*06c3fb27SDimitry Andric 1344*06c3fb27SDimitry Andric// Predicate reverse 1345*06c3fb27SDimitry Andric// Predicate set/initialize/find next 1346*06c3fb27SDimitry Andric// Predicate transpose 1347*06c3fb27SDimitry Andric// Predicate unpack and widen 1348*06c3fb27SDimitry Andric// Predicate zip/unzip 1349*06c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1M0], (instregex "^REV_PP_[BHSD]$", 1350*06c3fb27SDimitry Andric "^PFALSE$", "^PFIRST_B$", 1351*06c3fb27SDimitry Andric "^PNEXT_[BHSD]$", "^PTRUE_[BHSD]$", 1352*06c3fb27SDimitry Andric "^TRN[12]_PPP_[BHSDQ]$", 1353*06c3fb27SDimitry Andric "^(ZIP|UZP)[12]_PPP_[BHSDQ]$")>; 1354*06c3fb27SDimitry Andric 1355*06c3fb27SDimitry Andric// Predicate set/initialize/find next 1356*06c3fb27SDimitry Andric// Predicate unpack and widen 1357*06c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1M0], (instrs PTEST_PP, 1358*06c3fb27SDimitry Andric PUNPKHI_PP, PUNPKLO_PP)>; 1359*06c3fb27SDimitry Andric 1360*06c3fb27SDimitry Andric// Predicate select 1361*06c3fb27SDimitry Andricdef : InstRW<[V1Write_1c_1M0], (instrs SEL_PPPP)>; 1362*06c3fb27SDimitry Andric 1363*06c3fb27SDimitry Andric// Predicate set/initialize, set flags 1364*06c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_2M0], (instregex "^PTRUES_[BHSD]$")>; 1365*06c3fb27SDimitry Andric 1366*06c3fb27SDimitry Andric 1367*06c3fb27SDimitry Andric 1368*06c3fb27SDimitry Andric// SVE integer instructions 1369*06c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 1370*06c3fb27SDimitry Andric 1371*06c3fb27SDimitry Andric// Arithmetic, basic 1372*06c3fb27SDimitry Andric// Logical 1373*06c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1V01], 1374*06c3fb27SDimitry Andric (instregex "^(ABS|CNOT|NEG)_ZPmZ_[BHSD]$", 1375*06c3fb27SDimitry Andric "^(ADD|SUB)_Z(I|P[mZ]Z|ZZ)_[BHSD]$", 1376*06c3fb27SDimitry Andric "^ADR_[SU]XTW_ZZZ_D_[0123]$", 1377*06c3fb27SDimitry Andric "^ADR_LSL_ZZZ_[SD]_[0123]$", 1378*06c3fb27SDimitry Andric "^[SU]ABD_ZP[mZ]Z_[BHSD]$", 1379*06c3fb27SDimitry Andric "^[SU](MAX|MIN)_Z(I|P[mZ]Z)_[BHSD]$", 1380*06c3fb27SDimitry Andric "^[SU]Q(ADD|SUB)_Z(I|ZZ)_[BHSD]$", 1381*06c3fb27SDimitry Andric "^SUBR_Z(I|P[mZ]Z)_[BHSD]$", 1382*06c3fb27SDimitry Andric "^(AND|EOR|ORR)_ZI$", 1383*06c3fb27SDimitry Andric "^(AND|BIC|EOR|EOR(BT|TB)?|ORR)_ZZZ$", 1384*06c3fb27SDimitry Andric "^EOR(BT|TB)_ZZZ_[BHSD]$", 1385*06c3fb27SDimitry Andric "^(AND|BIC|EOR|NOT|ORR)_ZPmZ_[BHSD]$")>; 1386*06c3fb27SDimitry Andric 1387*06c3fb27SDimitry Andric// Arithmetic, shift 1388*06c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1V1], 1389*06c3fb27SDimitry Andric (instregex "^(ASR|LSL|LSR)_WIDE_Z(Pm|Z)Z_[BHS]", 1390*06c3fb27SDimitry Andric "^(ASR|LSL|LSR)_ZPm[IZ]_[BHSD]", 1391*06c3fb27SDimitry Andric "^(ASR|LSL|LSR)_ZZI_[BHSD]", 1392*06c3fb27SDimitry Andric "^(ASR|LSL|LSR)_ZPZ[IZ]_[BHSD]", 1393*06c3fb27SDimitry Andric "^(ASRR|LSLR|LSRR)_ZPmZ_[BHSD]")>; 1394*06c3fb27SDimitry Andric 1395*06c3fb27SDimitry Andric// Arithmetic, shift right for divide 1396*06c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_1V1], (instregex "^ASRD_ZP[mZ]I_[BHSD]$")>; 1397*06c3fb27SDimitry Andric 1398*06c3fb27SDimitry Andric// Count/reverse bits 1399*06c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1V01], (instregex "^(CLS|CLZ|CNT|RBIT)_ZPmZ_[BHSD]$")>; 1400*06c3fb27SDimitry Andric 1401*06c3fb27SDimitry Andric// Broadcast logical bitmask immediate to vector 1402*06c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1V01], (instrs DUPM_ZI)>; 1403*06c3fb27SDimitry Andric 1404*06c3fb27SDimitry Andric// Compare and set flags 1405*06c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_1M0_1V0], 1406*06c3fb27SDimitry Andric (instregex "^CMP(EQ|GE|GT|HI|HS|LE|LO|LS|LT|NE)_PPzZ[IZ]_[BHSD]$", 1407*06c3fb27SDimitry Andric "^CMP(EQ|GE|GT|HI|HS|LE|LO|LS|LT|NE)_WIDE_PPzZZ_[BHS]$")>; 1408*06c3fb27SDimitry Andric 1409*06c3fb27SDimitry Andric// Conditional extract operations, scalar form 1410*06c3fb27SDimitry Andricdef : InstRW<[V1Write_9c_1M0_1V1], (instregex "^CLAST[AB]_RPZ_[BHSD]$")>; 1411*06c3fb27SDimitry Andric 1412*06c3fb27SDimitry Andric// Conditional extract operations, SIMD&FP scalar and vector forms 1413*06c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1V1], (instregex "^CLAST[AB]_[VZ]PZ_[BHSD]$", 1414*06c3fb27SDimitry Andric "^COMPACT_ZPZ_[SD]$", 1415*06c3fb27SDimitry Andric "^SPLICE_ZPZZ?_[BHSD]$")>; 1416*06c3fb27SDimitry Andric 1417*06c3fb27SDimitry Andric// Convert to floating point, 64b to float or convert to double 1418*06c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1V0], (instregex "^[SU]CVTF_ZPmZ_Dto[HSD]", 1419*06c3fb27SDimitry Andric "^[SU]CVTF_ZPmZ_StoD")>; 1420*06c3fb27SDimitry Andric 1421*06c3fb27SDimitry Andric// Convert to floating point, 32b to single or half 1422*06c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_2V0], (instregex "^[SU]CVTF_ZPmZ_Sto[HS]$")>; 1423*06c3fb27SDimitry Andric 1424*06c3fb27SDimitry Andric// Convert to floating point, 16b to half 1425*06c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_4V0], (instregex "^[SU]CVTF_ZPmZ_HtoH$")>; 1426*06c3fb27SDimitry Andric 1427*06c3fb27SDimitry Andric// Copy, scalar 1428*06c3fb27SDimitry Andricdef : InstRW<[V1Write_5c_1M0_1V01], (instregex "^CPY_ZPmR_[BHSD]$")>; 1429*06c3fb27SDimitry Andric 1430*06c3fb27SDimitry Andric// Copy, scalar SIMD&FP or imm 1431*06c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1V01], (instregex "^CPY_ZP([mz]I|mV)_[BHSD]$")>; 1432*06c3fb27SDimitry Andric 1433*06c3fb27SDimitry Andric// Divides, 32 bit 1434*06c3fb27SDimitry Andricdef : InstRW<[V1Write_12c7_1V0], (instregex "^[SU]DIVR?_ZPmZ_S$")>; 1435*06c3fb27SDimitry Andric 1436*06c3fb27SDimitry Andric// Divides, 64 bit 1437*06c3fb27SDimitry Andricdef : InstRW<[V1Write_20c7_1V0], (instregex "^[SU]DIVR?_ZPmZ_D$")>; 1438*06c3fb27SDimitry Andric 1439*06c3fb27SDimitry Andric// Dot product, 8 bit 1440*06c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1V01], (instregex "^[SU]DOT_ZZZI?_S$")>; 1441*06c3fb27SDimitry Andric 1442*06c3fb27SDimitry Andric// Dot product, 8 bit, using signed and unsigned integers 1443*06c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1V], (instrs SUDOT_ZZZI, USDOT_ZZZ, USDOT_ZZZI)>; 1444*06c3fb27SDimitry Andric 1445*06c3fb27SDimitry Andric// Dot product, 16 bit 1446*06c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_1V01], (instregex "^[SU]DOT_ZZZI?_D$")>; 1447*06c3fb27SDimitry Andric 1448*06c3fb27SDimitry Andric// Duplicate, immediate and indexed form 1449*06c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1V01], (instregex "^DUP_ZI_[BHSD]$", 1450*06c3fb27SDimitry Andric "^DUP_ZZI_[BHSDQ]$")>; 1451*06c3fb27SDimitry Andric 1452*06c3fb27SDimitry Andric// Duplicate, scalar form 1453*06c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1M0], (instregex "^DUP_ZR_[BHSD]$")>; 1454*06c3fb27SDimitry Andric 1455*06c3fb27SDimitry Andric// Extend, sign or zero 1456*06c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1V1], (instregex "^[SU]XTB_ZPmZ_[HSD]$", 1457*06c3fb27SDimitry Andric "^[SU]XTH_ZPmZ_[SD]$", 1458*06c3fb27SDimitry Andric "^[SU]XTW_ZPmZ_[D]$")>; 1459*06c3fb27SDimitry Andric 1460*06c3fb27SDimitry Andric// Extract 1461*06c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1V01], (instrs EXT_ZZI)>; 1462*06c3fb27SDimitry Andric 1463*06c3fb27SDimitry Andric// Extract/insert operation, SIMD and FP scalar form 1464*06c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1V1], (instregex "^LAST[AB]_VPZ_[BHSD]$", 1465*06c3fb27SDimitry Andric "^INSR_ZV_[BHSD]$")>; 1466*06c3fb27SDimitry Andric 1467*06c3fb27SDimitry Andric// Extract/insert operation, scalar 1468*06c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_1M0_1V1], (instregex "^LAST[AB]_RPZ_[BHSD]$", 1469*06c3fb27SDimitry Andric "^INSR_ZR_[BHSD]$")>; 1470*06c3fb27SDimitry Andric 1471*06c3fb27SDimitry Andric// Horizontal operations, B, H, S form, imm, imm 1472*06c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_1V0], (instregex "^INDEX_II_[BHS]$")>; 1473*06c3fb27SDimitry Andric 1474*06c3fb27SDimitry Andric// Horizontal operations, B, H, S form, scalar, imm / scalar / imm, scalar 1475*06c3fb27SDimitry Andricdef : InstRW<[V1Write_7c_1M0_1V0], (instregex "^INDEX_(IR|RI|RR)_[BHS]$")>; 1476*06c3fb27SDimitry Andric 1477*06c3fb27SDimitry Andric// Horizontal operations, D form, imm, imm 1478*06c3fb27SDimitry Andricdef : InstRW<[V1Write_5c_2V0], (instrs INDEX_II_D)>; 1479*06c3fb27SDimitry Andric 1480*06c3fb27SDimitry Andric// Horizontal operations, D form, scalar, imm / scalar / imm, scalar 1481*06c3fb27SDimitry Andricdef : InstRW<[V1Write_8c_2M0_2V0], (instregex "^INDEX_(IR|RI|RR)_D$")>; 1482*06c3fb27SDimitry Andric 1483*06c3fb27SDimitry Andric// Move prefix 1484*06c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1V01], (instregex "^MOVPRFX_ZP[mz]Z_[BHSD]$", 1485*06c3fb27SDimitry Andric "^MOVPRFX_ZZ$")>; 1486*06c3fb27SDimitry Andric 1487*06c3fb27SDimitry Andric// Matrix multiply-accumulate 1488*06c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1V01], (instrs SMMLA_ZZZ, UMMLA_ZZZ, USMMLA_ZZZ)>; 1489*06c3fb27SDimitry Andric 1490*06c3fb27SDimitry Andric// Multiply, B, H, S element size 1491*06c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_1V0], (instregex "^MUL_(ZI|ZPmZ)_[BHS]$", 1492*06c3fb27SDimitry Andric "^[SU]MULH_(ZPmZ|ZZZ)_[BHS]$")>; 1493*06c3fb27SDimitry Andric 1494*06c3fb27SDimitry Andric// Multiply, D element size 1495*06c3fb27SDimitry Andric// Multiply accumulate, D element size 1496*06c3fb27SDimitry Andricdef : InstRW<[V1Write_5c_2V0], (instregex "^MUL_(ZI|ZPmZ)_D$", 1497*06c3fb27SDimitry Andric "^[SU]MULH_ZPmZ_D$", 1498*06c3fb27SDimitry Andric "^(MLA|MLS|MAD|MSB)_ZPmZZ_D$")>; 1499*06c3fb27SDimitry Andric 1500*06c3fb27SDimitry Andric// Multiply accumulate, B, H, S element size 1501*06c3fb27SDimitry Andric// NOTE: This is not specified in the SOG. 1502*06c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_1V0], (instregex "^(ML[AS]|MAD|MSB)_ZPmZZ_[BHS]")>; 1503*06c3fb27SDimitry Andric 1504*06c3fb27SDimitry Andric// Predicate counting vector 1505*06c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1V0], (instregex "^([SU]Q)?(DEC|INC)[HWD]_ZPiI$")>; 1506*06c3fb27SDimitry Andric 1507*06c3fb27SDimitry Andric// Reduction, arithmetic, B form 1508*06c3fb27SDimitry Andricdef : InstRW<[V1Write_14c_1V_1V0_2V1_1V13], 1509*06c3fb27SDimitry Andric (instregex "^[SU](ADD|MAX|MIN)V_VPZ_B")>; 1510*06c3fb27SDimitry Andric 1511*06c3fb27SDimitry Andric// Reduction, arithmetic, H form 1512*06c3fb27SDimitry Andricdef : InstRW<[V1Write_12c_1V_1V01_2V1], 1513*06c3fb27SDimitry Andric (instregex "^[SU](ADD|MAX|MIN)V_VPZ_H")>; 1514*06c3fb27SDimitry Andric 1515*06c3fb27SDimitry Andric// Reduction, arithmetic, S form 1516*06c3fb27SDimitry Andricdef : InstRW<[V1Write_10c_1V_1V01_2V1], 1517*06c3fb27SDimitry Andric (instregex "^[SU](ADD|MAX|MIN)V_VPZ_S")>; 1518*06c3fb27SDimitry Andric 1519*06c3fb27SDimitry Andric// Reduction, arithmetic, D form 1520*06c3fb27SDimitry Andricdef : InstRW<[V1Write_8c_1V_1V01], 1521*06c3fb27SDimitry Andric (instregex "^[SU](ADD|MAX|MIN)V_VPZ_D")>; 1522*06c3fb27SDimitry Andric 1523*06c3fb27SDimitry Andric// Reduction, logical 1524*06c3fb27SDimitry Andricdef : InstRW<[V1Write_12c_4V01], (instregex "^(AND|EOR|OR)V_VPZ_[BHSD]$")>; 1525*06c3fb27SDimitry Andric 1526*06c3fb27SDimitry Andric// Reverse, vector 1527*06c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1V01], (instregex "^REV_ZZ_[BHSD]$", 1528*06c3fb27SDimitry Andric "^REVB_ZPmZ_[HSD]$", 1529*06c3fb27SDimitry Andric "^REVH_ZPmZ_[SD]$", 1530*06c3fb27SDimitry Andric "^REVW_ZPmZ_D$")>; 1531*06c3fb27SDimitry Andric 1532*06c3fb27SDimitry Andric// Select, vector form 1533*06c3fb27SDimitry Andric// Table lookup 1534*06c3fb27SDimitry Andric// Table lookup extension 1535*06c3fb27SDimitry Andric// Transpose, vector form 1536*06c3fb27SDimitry Andric// Unpack and extend 1537*06c3fb27SDimitry Andric// Zip/unzip 1538*06c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1V01], (instregex "^SEL_ZPZZ_[BHSD]$", 1539*06c3fb27SDimitry Andric "^TB[LX]_ZZZ_[BHSD]$", 1540*06c3fb27SDimitry Andric "^TRN[12]_ZZZ_[BHSDQ]$", 1541*06c3fb27SDimitry Andric "^[SU]UNPK(HI|LO)_ZZ_[HSD]$", 1542*06c3fb27SDimitry Andric "^(UZP|ZIP)[12]_ZZZ_[BHSDQ]$")>; 1543*06c3fb27SDimitry Andric 1544*06c3fb27SDimitry Andric 1545*06c3fb27SDimitry Andric// SVE floating-point instructions 1546*06c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 1547*06c3fb27SDimitry Andric 1548*06c3fb27SDimitry Andric// Floating point absolute value/difference 1549*06c3fb27SDimitry Andric// Floating point arithmetic 1550*06c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1V01], (instregex "^FAB[SD]_ZPmZ_[HSD]$", 1551*06c3fb27SDimitry Andric "^F(ADD|SUB)_(ZPm[IZ]|ZZZ)_[HSD]$", 1552*06c3fb27SDimitry Andric "^FADDP_ZPmZZ_[HSD]$", 1553*06c3fb27SDimitry Andric "^FNEG_ZPmZ_[HSD]$", 1554*06c3fb27SDimitry Andric "^FSUBR_ZPm[IZ]_[HSD]$")>; 1555*06c3fb27SDimitry Andric 1556*06c3fb27SDimitry Andric// Floating point associative add, F16 1557*06c3fb27SDimitry Andricdef : InstRW<[V1Write_19c_18V0], (instrs FADDA_VPZ_H)>; 1558*06c3fb27SDimitry Andric 1559*06c3fb27SDimitry Andric// Floating point associative add, F32 1560*06c3fb27SDimitry Andricdef : InstRW<[V1Write_11c_10V0], (instrs FADDA_VPZ_S)>; 1561*06c3fb27SDimitry Andric 1562*06c3fb27SDimitry Andric// Floating point associative add, F64 1563*06c3fb27SDimitry Andricdef : InstRW<[V1Write_8c_3V01], (instrs FADDA_VPZ_D)>; 1564*06c3fb27SDimitry Andric 1565*06c3fb27SDimitry Andric// Floating point compare 1566*06c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1V0], (instregex "^FAC(GE|GT)_PPzZZ_[HSD]$", 1567*06c3fb27SDimitry Andric "^FCM(EQ|GE|GT|NE|UO)_PPzZZ_[HSD]$", 1568*06c3fb27SDimitry Andric "^FCM(EQ|GE|GT|LE|LT|NE)_PPzZ0_[HSD]$")>; 1569*06c3fb27SDimitry Andric 1570*06c3fb27SDimitry Andric// Floating point complex add 1571*06c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1V01], (instregex "^FCADD_ZPmZ_[HSD]$")>; 1572*06c3fb27SDimitry Andric 1573*06c3fb27SDimitry Andric// Floating point complex multiply add 1574*06c3fb27SDimitry Andricdef : InstRW<[V1Write_5c_1V01], (instregex "^FCMLA_ZPmZZ_[HSD]$", 1575*06c3fb27SDimitry Andric "^FCMLA_ZZZI_[HS]$")>; 1576*06c3fb27SDimitry Andric 1577*06c3fb27SDimitry Andric// Floating point convert, long or narrow (F16 to F32 or F32 to F16) 1578*06c3fb27SDimitry Andric// Floating point convert to integer, F32 1579*06c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_2V0], (instregex "^FCVT_ZPmZ_(HtoS|StoH)$", 1580*06c3fb27SDimitry Andric "^FCVTZ[SU]_ZPmZ_(HtoS|StoS)$")>; 1581*06c3fb27SDimitry Andric 1582*06c3fb27SDimitry Andric// Floating point convert, long or narrow (F16 to F64, F32 to F64, F64 to F32 or F64 to F16) 1583*06c3fb27SDimitry Andric// Floating point convert to integer, F64 1584*06c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1V0], (instregex "^FCVT_ZPmZ_(HtoD|StoD|DtoS|DtoH)$", 1585*06c3fb27SDimitry Andric "^FCVTZ[SU]_ZPmZ_(HtoD|StoD|DtoS|DtoD)$")>; 1586*06c3fb27SDimitry Andric 1587*06c3fb27SDimitry Andric// Floating point convert to integer, F16 1588*06c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_4V0], (instregex "^FCVTZ[SU]_ZPmZ_HtoH$")>; 1589*06c3fb27SDimitry Andric 1590*06c3fb27SDimitry Andric// Floating point copy 1591*06c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1V01], (instregex "^FCPY_ZPmI_[HSD]$", 1592*06c3fb27SDimitry Andric "^FDUP_ZI_[HSD]$")>; 1593*06c3fb27SDimitry Andric 1594*06c3fb27SDimitry Andric// Floating point divide, F16 1595*06c3fb27SDimitry Andricdef : InstRW<[V1Write_13c10_1V0], (instregex "^FDIVR?_ZPmZ_H$")>; 1596*06c3fb27SDimitry Andric 1597*06c3fb27SDimitry Andric// Floating point divide, F32 1598*06c3fb27SDimitry Andricdef : InstRW<[V1Write_10c7_1V0], (instregex "^FDIVR?_ZPmZ_S$")>; 1599*06c3fb27SDimitry Andric 1600*06c3fb27SDimitry Andric// Floating point divide, F64 1601*06c3fb27SDimitry Andricdef : InstRW<[V1Write_15c7_1V0], (instregex "^FDIVR?_ZPmZ_D$")>; 1602*06c3fb27SDimitry Andric 1603*06c3fb27SDimitry Andric// Floating point min/max 1604*06c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1V01], (instregex "^F(MAX|MIN)(NM)?_ZPm[IZ]_[HSD]$")>; 1605*06c3fb27SDimitry Andric 1606*06c3fb27SDimitry Andric// Floating point multiply 1607*06c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1V01], (instregex "^F(SCALE|MULX)_ZPmZ_[HSD]$", 1608*06c3fb27SDimitry Andric "^FMUL_(ZPm[IZ]|ZZZI?)_[HSD]$")>; 1609*06c3fb27SDimitry Andric 1610*06c3fb27SDimitry Andric// Floating point multiply accumulate 1611*06c3fb27SDimitry Andric// Floating point reciprocal step 1612*06c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_1V01], (instregex "^F(N?M(AD|SB)|N?ML[AS])_ZPmZZ_[HSD]$", 1613*06c3fb27SDimitry Andric "^FML[AS]_ZZZI_[HSD]$", 1614*06c3fb27SDimitry Andric "^F(RECPS|RSQRTS)_ZZZ_[HSD]$")>; 1615*06c3fb27SDimitry Andric 1616*06c3fb27SDimitry Andric// Floating point reciprocal estimate, F16 1617*06c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_4V0], (instrs FRECPE_ZZ_H, FRSQRTE_ZZ_H)>; 1618*06c3fb27SDimitry Andric 1619*06c3fb27SDimitry Andric// Floating point reciprocal estimate, F32 1620*06c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_2V0], (instrs FRECPE_ZZ_S, FRSQRTE_ZZ_S)>; 1621*06c3fb27SDimitry Andric 1622*06c3fb27SDimitry Andric// Floating point reciprocal estimate, F64 1623*06c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1V0], (instrs FRECPE_ZZ_D, FRSQRTE_ZZ_D)>; 1624*06c3fb27SDimitry Andric 1625*06c3fb27SDimitry Andric// Floating point reciprocal exponent 1626*06c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1V0], (instregex "^FRECPX_ZPmZ_[HSD]$")>; 1627*06c3fb27SDimitry Andric 1628*06c3fb27SDimitry Andric// Floating point reduction, F16 1629*06c3fb27SDimitry Andricdef : InstRW<[V1Write_13c_6V01], (instregex "^F(ADD|((MAX|MIN)(NM)?))V_VPZ_H$")>; 1630*06c3fb27SDimitry Andric 1631*06c3fb27SDimitry Andric// Floating point reduction, F32 1632*06c3fb27SDimitry Andricdef : InstRW<[V1Write_11c_1V_5V01], (instregex "^F(ADD|((MAX|MIN)(NM)?))V_VPZ_S$")>; 1633*06c3fb27SDimitry Andric 1634*06c3fb27SDimitry Andric// Floating point reduction, F64 1635*06c3fb27SDimitry Andricdef : InstRW<[V1Write_9c_1V_4V01], (instregex "^F(ADD|((MAX|MIN)(NM)?))V_VPZ_D$")>; 1636*06c3fb27SDimitry Andric 1637*06c3fb27SDimitry Andric// Floating point round to integral, F16 1638*06c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_1V0], (instregex "^FRINT[AIMNPXZ]_ZPmZ_H$")>; 1639*06c3fb27SDimitry Andric 1640*06c3fb27SDimitry Andric// Floating point round to integral, F32 1641*06c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_1V0], (instregex "^FRINT[AIMNPXZ]_ZPmZ_S$")>; 1642*06c3fb27SDimitry Andric 1643*06c3fb27SDimitry Andric// Floating point round to integral, F64 1644*06c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1V0], (instregex "^FRINT[AIMNPXZ]_ZPmZ_D$")>; 1645*06c3fb27SDimitry Andric 1646*06c3fb27SDimitry Andric// Floating point square root, F16 1647*06c3fb27SDimitry Andricdef : InstRW<[V1Write_13c10_1V0], (instrs FSQRT_ZPmZ_H)>; 1648*06c3fb27SDimitry Andric 1649*06c3fb27SDimitry Andric// Floating point square root, F32 1650*06c3fb27SDimitry Andricdef : InstRW<[V1Write_10c7_1V0], (instrs FSQRT_ZPmZ_S)>; 1651*06c3fb27SDimitry Andric 1652*06c3fb27SDimitry Andric// Floating point square root, F64 1653*06c3fb27SDimitry Andricdef : InstRW<[V1Write_16c7_1V0], (instrs FSQRT_ZPmZ_D)>; 1654*06c3fb27SDimitry Andric 1655*06c3fb27SDimitry Andric// Floating point trigonometric 1656*06c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_1V01], (instregex "^FEXPA_ZZ_[HSD]$", 1657*06c3fb27SDimitry Andric "^FTMAD_ZZI_[HSD]$", 1658*06c3fb27SDimitry Andric "^FTS(MUL|SEL)_ZZZ_[HSD]$")>; 1659*06c3fb27SDimitry Andric 1660*06c3fb27SDimitry Andric 1661*06c3fb27SDimitry Andric// SVE BFloat16 (BF16) instructions 1662*06c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 1663*06c3fb27SDimitry Andric 1664*06c3fb27SDimitry Andric// Convert, F32 to BF16 1665*06c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_1V0], (instrs BFCVT_ZPmZ, BFCVTNT_ZPmZ)>; 1666*06c3fb27SDimitry Andric 1667*06c3fb27SDimitry Andric// Dot product 1668*06c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_1V01], (instrs BFDOT_ZZI, BFDOT_ZZZ)>; 1669*06c3fb27SDimitry Andric 1670*06c3fb27SDimitry Andric// Matrix multiply accumulate 1671*06c3fb27SDimitry Andricdef : InstRW<[V1Write_5c_1V01], (instrs BFMMLA_ZZZ)>; 1672*06c3fb27SDimitry Andric 1673*06c3fb27SDimitry Andric// Multiply accumulate long 1674*06c3fb27SDimitry Andricdef : InstRW<[V1Write_5c_1V01], (instregex "^BFMLAL[BT]_ZZZ(I)?$")>; 1675*06c3fb27SDimitry Andric 1676*06c3fb27SDimitry Andric 1677*06c3fb27SDimitry Andric// SVE Load instructions 1678*06c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 1679*06c3fb27SDimitry Andric 1680*06c3fb27SDimitry Andric// Load vector 1681*06c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_1L01], (instrs LDR_ZXI)>; 1682*06c3fb27SDimitry Andric 1683*06c3fb27SDimitry Andric// Load predicate 1684*06c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_1L_1M], (instrs LDR_PXI)>; 1685*06c3fb27SDimitry Andric 1686*06c3fb27SDimitry Andric// Contiguous load, scalar + imm 1687*06c3fb27SDimitry Andric// Contiguous load, scalar + scalar 1688*06c3fb27SDimitry Andric// Contiguous load broadcast, scalar + imm 1689*06c3fb27SDimitry Andric// Contiguous load broadcast, scalar + scalar 1690*06c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_1L01], (instregex "^LD1[BHWD]_IMM_REAL$", 1691*06c3fb27SDimitry Andric "^LD1S?B_[HSD]_IMM_REAL$", 1692*06c3fb27SDimitry Andric "^LD1S?H_[SD]_IMM_REAL$", 1693*06c3fb27SDimitry Andric "^LD1S?W_D_IMM_REAL$", 1694*06c3fb27SDimitry Andric "^LD1[BWD]$", 1695*06c3fb27SDimitry Andric "^LD1S?B_[HSD]$", 1696*06c3fb27SDimitry Andric "^LD1S?W_D$", 1697*06c3fb27SDimitry Andric "^LD1R[BHWD]_IMM$", 1698*06c3fb27SDimitry Andric "^LD1RSW_IMM$", 1699*06c3fb27SDimitry Andric "^LD1RS?B_[HSD]_IMM$", 1700*06c3fb27SDimitry Andric "^LD1RS?H_[SD]_IMM$", 1701*06c3fb27SDimitry Andric "^LD1RS?W_D_IMM$", 1702*06c3fb27SDimitry Andric "^LD1RQ_[BHWD]_IMM$", 1703*06c3fb27SDimitry Andric "^LD1RQ_[BWD]$")>; 1704*06c3fb27SDimitry Andricdef : InstRW<[V1Write_7c_1L01_1S], (instregex "^LD1H$", 1705*06c3fb27SDimitry Andric "^LD1S?H_[SD]$", 1706*06c3fb27SDimitry Andric "^LD1RQ_H$")>; 1707*06c3fb27SDimitry Andric 1708*06c3fb27SDimitry Andric// Non temporal load, scalar + imm 1709*06c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_1L01], (instregex "^LDNT1[BHWD]_ZRI$")>; 1710*06c3fb27SDimitry Andric 1711*06c3fb27SDimitry Andric// Non temporal load, scalar + scalar 1712*06c3fb27SDimitry Andricdef : InstRW<[V1Write_7c_1L01_1S], (instrs LDNT1H_ZRR)>; 1713*06c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_1L01_1S], (instregex "^LDNT1[BWD]_ZRR$")>; 1714*06c3fb27SDimitry Andric 1715*06c3fb27SDimitry Andric// Contiguous first faulting load, scalar + scalar 1716*06c3fb27SDimitry Andricdef : InstRW<[V1Write_7c_1L01_1S], (instregex "^LDFF1H_REAL$", 1717*06c3fb27SDimitry Andric "^LDFF1S?H_[SD]_REAL$")>; 1718*06c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_1L01_1S], (instregex "^LDFF1[BWD]_REAL$", 1719*06c3fb27SDimitry Andric "^LDFF1S?B_[HSD]_REAL$", 1720*06c3fb27SDimitry Andric "^LDFF1S?W_D_REAL$")>; 1721*06c3fb27SDimitry Andric 1722*06c3fb27SDimitry Andric// Contiguous non faulting load, scalar + imm 1723*06c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_1L01], (instregex "^LDNF1[BHWD]_IMM_REAL$", 1724*06c3fb27SDimitry Andric "^LDNF1S?B_[HSD]_IMM_REAL$", 1725*06c3fb27SDimitry Andric "^LDNF1S?H_[SD]_IMM_REAL$", 1726*06c3fb27SDimitry Andric "^LDNF1S?W_D_IMM_REAL$")>; 1727*06c3fb27SDimitry Andric 1728*06c3fb27SDimitry Andric// Contiguous Load two structures to two vectors, scalar + imm 1729*06c3fb27SDimitry Andricdef : InstRW<[V1Write_8c_2L01_2V01], (instregex "^LD2[BHWD]_IMM$")>; 1730*06c3fb27SDimitry Andric 1731*06c3fb27SDimitry Andric// Contiguous Load two structures to two vectors, scalar + scalar 1732*06c3fb27SDimitry Andricdef : InstRW<[V1Write_10c_2L01_2V01], (instrs LD2H)>; 1733*06c3fb27SDimitry Andricdef : InstRW<[V1Write_9c_2L01_2V01], (instregex "^LD2[BWD]$")>; 1734*06c3fb27SDimitry Andric 1735*06c3fb27SDimitry Andric// Contiguous Load three structures to three vectors, scalar + imm 1736*06c3fb27SDimitry Andricdef : InstRW<[V1Write_11c_3L01_3V01], (instregex "^LD3[BHWD]_IMM$")>; 1737*06c3fb27SDimitry Andric 1738*06c3fb27SDimitry Andric// Contiguous Load three structures to three vectors, scalar + scalar 1739*06c3fb27SDimitry Andricdef : InstRW<[V1Write_13c_3L01_1S_3V01], (instregex "^LD3[BHWD]$")>; 1740*06c3fb27SDimitry Andric 1741*06c3fb27SDimitry Andric// Contiguous Load four structures to four vectors, scalar + imm 1742*06c3fb27SDimitry Andricdef : InstRW<[V1Write_12c_4L01_4V01], (instregex "^LD4[BHWD]_IMM$")>; 1743*06c3fb27SDimitry Andric 1744*06c3fb27SDimitry Andric// Contiguous Load four structures to four vectors, scalar + scalar 1745*06c3fb27SDimitry Andricdef : InstRW<[V1Write_13c_4L01_2S_4V01], (instregex "^LD4[BHWD]$")>; 1746*06c3fb27SDimitry Andric 1747*06c3fb27SDimitry Andric// Gather load, vector + imm, 32-bit element size 1748*06c3fb27SDimitry Andricdef : InstRW<[V1Write_11c_1L_1V], (instregex "^GLD(FF)?1S?[BH]_S_IMM_REAL$", 1749*06c3fb27SDimitry Andric "^GLD(FF)?1W_IMM_REAL$")>; 1750*06c3fb27SDimitry Andric 1751*06c3fb27SDimitry Andric// Gather load, vector + imm, 64-bit element size 1752*06c3fb27SDimitry Andricdef : InstRW<[V1Write_9c_2L_2V], 1753*06c3fb27SDimitry Andric (instregex "^GLD(FF)?1S?[BHW]_D_IMM_REAL$", 1754*06c3fb27SDimitry Andric "^GLD(FF)?1S?[BHW]_D_([SU]XTW_)?(SCALED_)?REAL$", 1755*06c3fb27SDimitry Andric "^GLD(FF)?1D_IMM_REAL$", 1756*06c3fb27SDimitry Andric "^GLD(FF)?1D_([SU]XTW_)?(SCALED_)?REAL$")>; 1757*06c3fb27SDimitry Andric 1758*06c3fb27SDimitry Andric// Gather load, 32-bit scaled offset 1759*06c3fb27SDimitry Andricdef : InstRW<[V1Write_11c_2L_2V], 1760*06c3fb27SDimitry Andric (instregex "^GLD(FF)?1S?[HW]_S_[SU]XTW_SCALED_REAL$", 1761*06c3fb27SDimitry Andric "^GLD(FF)?1W_[SU]XTW_SCALED_REAL")>; 1762*06c3fb27SDimitry Andric 1763*06c3fb27SDimitry Andric// Gather load, 32-bit unpacked unscaled offset 1764*06c3fb27SDimitry Andricdef : InstRW<[V1Write_9c_1L_1V], 1765*06c3fb27SDimitry Andric (instregex "^GLD(FF)?1S?[BH]_S_[SU]XTW_REAL$", 1766*06c3fb27SDimitry Andric "^GLD(FF)?1W_[SU]XTW_REAL$")>; 1767*06c3fb27SDimitry Andric 1768*06c3fb27SDimitry Andric// Prefetch 1769*06c3fb27SDimitry Andric// NOTE: This is not specified in the SOG. 1770*06c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_1L01], (instregex "^PRF[BHWD]")>; 1771*06c3fb27SDimitry Andric 1772*06c3fb27SDimitry Andric 1773*06c3fb27SDimitry Andric// SVE Store instructions 1774*06c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 1775*06c3fb27SDimitry Andric 1776*06c3fb27SDimitry Andric// Store from predicate reg 1777*06c3fb27SDimitry Andricdef : InstRW<[V1Write_1c_1L01], (instrs STR_PXI)>; 1778*06c3fb27SDimitry Andric 1779*06c3fb27SDimitry Andric// Store from vector reg 1780*06c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1L01_1V], (instrs STR_ZXI)>; 1781*06c3fb27SDimitry Andric 1782*06c3fb27SDimitry Andric// Contiguous store, scalar + imm 1783*06c3fb27SDimitry Andric// Contiguous store, scalar + scalar 1784*06c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1L01_1V], (instregex "^ST1[BHWD]_IMM$", 1785*06c3fb27SDimitry Andric "^ST1B_[HSD]_IMM$", 1786*06c3fb27SDimitry Andric "^ST1H_[SD]_IMM$", 1787*06c3fb27SDimitry Andric "^ST1W_D_IMM$", 1788*06c3fb27SDimitry Andric "^ST1[BWD]$", 1789*06c3fb27SDimitry Andric "^ST1B_[HSD]$", 1790*06c3fb27SDimitry Andric "^ST1W_D$")>; 1791*06c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1L01_1S_1V], (instregex "^ST1H(_[SD])?$")>; 1792*06c3fb27SDimitry Andric 1793*06c3fb27SDimitry Andric// Contiguous store two structures from two vectors, scalar + imm 1794*06c3fb27SDimitry Andric// Contiguous store two structures from two vectors, scalar + scalar 1795*06c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_1L01_1V], (instregex "^ST2[BHWD]_IMM$", 1796*06c3fb27SDimitry Andric "^ST2[BWD]$")>; 1797*06c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_1L01_1S_1V], (instrs ST2H)>; 1798*06c3fb27SDimitry Andric 1799*06c3fb27SDimitry Andric// Contiguous store three structures from three vectors, scalar + imm 1800*06c3fb27SDimitry Andricdef : InstRW<[V1Write_7c_5L01_5V], (instregex "^ST3[BHWD]_IMM$")>; 1801*06c3fb27SDimitry Andric 1802*06c3fb27SDimitry Andric// Contiguous store three structures from three vectors, scalar + scalar 1803*06c3fb27SDimitry Andricdef : InstRW<[V1Write_7c_5L01_5S_5V], (instregex "^ST3[BHWD]$")>; 1804*06c3fb27SDimitry Andric 1805*06c3fb27SDimitry Andric// Contiguous store four structures from four vectors, scalar + imm 1806*06c3fb27SDimitry Andricdef : InstRW<[V1Write_11c_9L01_9V], (instregex "^ST4[BHWD]_IMM$")>; 1807*06c3fb27SDimitry Andric 1808*06c3fb27SDimitry Andric// Contiguous store four structures from four vectors, scalar + scalar 1809*06c3fb27SDimitry Andricdef : InstRW<[V1Write_11c_9L01_9S_9V], (instregex "^ST4[BHWD]$")>; 1810*06c3fb27SDimitry Andric 1811*06c3fb27SDimitry Andric// Non temporal store, scalar + imm 1812*06c3fb27SDimitry Andric// Non temporal store, scalar + scalar 1813*06c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1L01_1V], (instregex "^STNT1[BHWD]_ZRI$", 1814*06c3fb27SDimitry Andric "^STNT1[BWD]_ZRR$")>; 1815*06c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1L01_1S_1V], (instrs STNT1H_ZRR)>; 1816*06c3fb27SDimitry Andric 1817*06c3fb27SDimitry Andric// Scatter store vector + imm 32-bit element size 1818*06c3fb27SDimitry Andric// Scatter store, 32-bit scaled offset 1819*06c3fb27SDimitry Andric// Scatter store, 32-bit unscaled offset 1820*06c3fb27SDimitry Andricdef : InstRW<[V1Write_10c_2L01_2V], (instregex "^SST1[BH]_S_IMM$", 1821*06c3fb27SDimitry Andric "^SST1W_IMM$", 1822*06c3fb27SDimitry Andric "^SST1(H_S|W)_[SU]XTW_SCALED$", 1823*06c3fb27SDimitry Andric "^SST1[BH]_S_[SU]XTW$", 1824*06c3fb27SDimitry Andric "^SST1W_[SU]XTW$")>; 1825*06c3fb27SDimitry Andric 1826*06c3fb27SDimitry Andric// Scatter store, 32-bit unpacked unscaled offset 1827*06c3fb27SDimitry Andric// Scatter store, 32-bit unpacked scaled offset 1828*06c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_1L01_1V], (instregex "^SST1[BHW]_D_[SU]XTW$", 1829*06c3fb27SDimitry Andric "^SST1D_[SU]XTW$", 1830*06c3fb27SDimitry Andric "^SST1[HW]_D_[SU]XTW_SCALED$", 1831*06c3fb27SDimitry Andric "^SST1D_[SU]XTW_SCALED$")>; 1832*06c3fb27SDimitry Andric 1833*06c3fb27SDimitry Andric// Scatter store vector + imm 64-bit element size 1834*06c3fb27SDimitry Andric// Scatter store, 64-bit scaled offset 1835*06c3fb27SDimitry Andric// Scatter store, 64-bit unscaled offset 1836*06c3fb27SDimitry Andricdef : InstRW<[V1Write_6c_1L01_1V], (instregex "^SST1[BHW]_D_IMM$", 1837*06c3fb27SDimitry Andric "^SST1D_IMM$", 1838*06c3fb27SDimitry Andric "^SST1[HW]_D_SCALED$", 1839*06c3fb27SDimitry Andric "^SST1D_SCALED$", 1840*06c3fb27SDimitry Andric "^SST1[BHW]_D$", 1841*06c3fb27SDimitry Andric "^SST1D$")>; 1842*06c3fb27SDimitry Andric 1843*06c3fb27SDimitry Andric 1844*06c3fb27SDimitry Andric// SVE Miscellaneous instructions 1845*06c3fb27SDimitry Andric// ----------------------------------------------------------------------------- 1846*06c3fb27SDimitry Andric 1847*06c3fb27SDimitry Andric// Read first fault register, unpredicated 1848*06c3fb27SDimitry Andric// Set first fault register 1849*06c3fb27SDimitry Andric// Write to first fault register 1850*06c3fb27SDimitry Andricdef : InstRW<[V1Write_2c_1M0], (instrs RDFFR_P_REAL, 1851*06c3fb27SDimitry Andric SETFFR, 1852*06c3fb27SDimitry Andric WRFFR)>; 1853*06c3fb27SDimitry Andric 1854*06c3fb27SDimitry Andric// Read first fault register, predicated 1855*06c3fb27SDimitry Andricdef : InstRW<[V1Write_3c_2M0], (instrs RDFFR_PPz_REAL)>; 1856*06c3fb27SDimitry Andric 1857*06c3fb27SDimitry Andric// Read first fault register and set flags 1858*06c3fb27SDimitry Andricdef : InstRW<[V1Write_4c_1M], (instrs RDFFRS_PPz)>; 1859*06c3fb27SDimitry Andric 1860*06c3fb27SDimitry Andric 1861*06c3fb27SDimitry Andric} 1862