1//===- AArch64SchedPredNeoverse.td - AArch64 Sched Preds -----*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines scheduling predicate definitions that are used by the
10// AArch64 Neoverse processors.
11//
12//===----------------------------------------------------------------------===//
13
14// Auxiliary predicates.
15
16// Check for LSL shift == 0
17def NeoverseNoLSL : MCSchedPredicate<
18                      CheckAll<[CheckShiftLSL,
19                                CheckShiftBy0]>>;
20
21// Identify LDR/STR H/Q-form scaled (and potentially extended) FP instructions
22def NeoverseHQForm : MCSchedPredicate<
23                       CheckAll<[
24                         CheckAny<[CheckHForm, CheckQForm]>,
25                         CheckImmOperand<4, 1>]>>;
26
27// Check if <Pd> == <Pg>
28def NeoversePdIsPgFn : TIIPredicate<
29                         "isNeoversePdSameAsPg",
30                         MCOpcodeSwitchStatement<
31                           [MCOpcodeSwitchCase<[BRKA_PPmP, BRKB_PPmP],
32                             MCReturnStatement<CheckSameRegOperand<1, 2>>>],
33                           MCReturnStatement<CheckSameRegOperand<0, 1>>>>;
34def NeoversePdIsPg : MCSchedPredicate<NeoversePdIsPgFn>;
35
36// Check if SVE INC/DEC (scalar), ALL, {1, 2, 4}
37def NeoverseCheapIncDec : MCSchedPredicate<
38                            CheckAll<[CheckOpcode<[
39                                        INCB_XPiI, INCH_XPiI,
40                                        INCW_XPiI, INCD_XPiI,
41                                        DECB_XPiI, DECH_XPiI,
42                                        DECW_XPiI, DECD_XPiI]>,
43                                      CheckImmOperand<2, 31>,
44                                      CheckAny<[
45                                        CheckImmOperand<3, 1>,
46                                        CheckImmOperand<3, 2>,
47                                        CheckImmOperand<3, 4>]>]>>;
48
49// Identify "[SU]?(MADD|MSUB)L?" as the alias for "[SU]?(MUL|MNEG)L?".
50def NeoverseMULIdiomPred : MCSchedPredicate< // <op> Rd, Rs, Rv, ZR
51                             CheckAll<[CheckOpcode<
52                                         [MADDWrrr, MADDXrrr,
53                                          MSUBWrrr, MSUBXrrr,
54                                          SMADDLrrr, UMADDLrrr,
55                                          SMSUBLrrr, UMSUBLrrr]>,
56                                       CheckIsReg3Zero]>>;
57
58def NeoverseZeroMove : MCSchedPredicate<
59                         CheckAny<[
60                           // MOV Wd, #0
61                           // MOV Xd, #0
62                           CheckAll<[CheckOpcode<[MOVZWi, MOVZXi]>,
63                                     CheckAll<[CheckImmOperand<1, 0>,
64                                               CheckImmOperand<2, 0>]>]>,
65                           // MOV Wd, WZR
66                           // MOV Xd, XZR
67                           // MOV Wd, Wn
68                           // MOV Xd, Xn
69                           CheckAll<[CheckOpcode<[ORRWrs, ORRXrs]>,
70                                     CheckAll<[CheckIsReg1Zero,
71                                               CheckImmOperand<3, 0>]>]>,
72                           // FMOV Hd, WZR
73                           // FMOV Hd, XZR
74                           // FMOV Sd, WZR
75                           // FMOV Dd, XZR
76                           CheckAll<[CheckOpcode<[FMOVWHr, FMOVXHr,
77                                                  FMOVWSr, FMOVXDr]>,
78                                     CheckIsReg1Zero]>,
79                           // MOVI Dd, #0
80                           // MOVI Vd.2D, #0
81                           CheckAll<[CheckOpcode<[MOVID, MOVIv2d_ns]>,
82                                     CheckImmOperand<1, 0>]>
83                         ]>>;
84