1e8d8bef9SDimitry Andric//==- AArch64SchedTSV110.td - Huawei TSV110 Scheduling Definitions -*- tablegen -*-=// 2e8d8bef9SDimitry Andric// 3e8d8bef9SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4e8d8bef9SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 5e8d8bef9SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6e8d8bef9SDimitry Andric// 7e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 8e8d8bef9SDimitry Andric// 9e8d8bef9SDimitry Andric// This file defines the machine model for Huawei TSV110 to support 10e8d8bef9SDimitry Andric// instruction scheduling and other instruction cost heuristics. 11e8d8bef9SDimitry Andric// 12e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 13e8d8bef9SDimitry Andric 14e8d8bef9SDimitry Andric// ===---------------------------------------------------------------------===// 15e8d8bef9SDimitry Andric// The following definitions describe the simpler per-operand machine model. 16e8d8bef9SDimitry Andric// This works with MachineScheduler. See llvm/MC/MCSchedule.h for details. 17e8d8bef9SDimitry Andric 18e8d8bef9SDimitry Andric// Huawei TSV110 scheduling machine model. 19e8d8bef9SDimitry Andricdef TSV110Model : SchedMachineModel { 20e8d8bef9SDimitry Andric let IssueWidth = 4; // 4 micro-ops dispatched per cycle. 21e8d8bef9SDimitry Andric let MicroOpBufferSize = 128; // 128 micro-op re-order buffer 22e8d8bef9SDimitry Andric let LoopMicroOpBufferSize = 16; 23e8d8bef9SDimitry Andric let LoadLatency = 4; // Optimistic load latency. 24e8d8bef9SDimitry Andric let MispredictPenalty = 14; // Fetch + Decode/Rename/Dispatch + Branch 25e8d8bef9SDimitry Andric let CompleteModel = 1; 26e8d8bef9SDimitry Andric 27e8d8bef9SDimitry Andric list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F, 2881ad6265SDimitry Andric PAUnsupported.F, 29753f127fSDimitry Andric SMEUnsupported.F, 30*4c2d3b02SDimitry Andric [HasMTE, HasCSSC]); 31e8d8bef9SDimitry Andric} 32e8d8bef9SDimitry Andric 33e8d8bef9SDimitry Andric// Define each kind of processor resource and number available on the TSV110, 34e8d8bef9SDimitry Andric// which has 8 pipelines, each with its own queue where micro-ops wait for 35e8d8bef9SDimitry Andric// their operands and issue out-of-order to one of eight execution pipelines. 36e8d8bef9SDimitry Andriclet SchedModel = TSV110Model in { 37e8d8bef9SDimitry Andric def TSV110UnitALU : ProcResource<1>; // Int ALU 38e8d8bef9SDimitry Andric def TSV110UnitAB : ProcResource<2>; // Int ALU/BRU 39e8d8bef9SDimitry Andric def TSV110UnitMDU : ProcResource<1>; // Multi-Cycle 40e8d8bef9SDimitry Andric def TSV110UnitFSU1 : ProcResource<1>; // FP/ASIMD 41e8d8bef9SDimitry Andric def TSV110UnitFSU2 : ProcResource<1>; // FP/ASIMD 42bdd1243dSDimitry Andric def TSV110UnitLd0St : ProcResource<1>; // Load/Store 43bdd1243dSDimitry Andric def TSV110UnitLd1 : ProcResource<1>; // Load 44e8d8bef9SDimitry Andric 45bdd1243dSDimitry Andric def TSV110UnitLd : ProcResGroup<[TSV110UnitLd0St, TSV110UnitLd1]>; // Any load 46e8d8bef9SDimitry Andric def TSV110UnitF : ProcResGroup<[TSV110UnitFSU1, TSV110UnitFSU2]>; 47e8d8bef9SDimitry Andric def TSV110UnitALUAB : ProcResGroup<[TSV110UnitALU, TSV110UnitAB]>; 48e8d8bef9SDimitry Andric} 49e8d8bef9SDimitry Andric 50e8d8bef9SDimitry Andriclet SchedModel = TSV110Model in { 51e8d8bef9SDimitry Andric 52e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 53bdd1243dSDimitry Andric// Map the target-defined scheduler read/write resources and latency for TSV110 54e8d8bef9SDimitry Andric 55e8d8bef9SDimitry Andric// Integer ALU 56bdd1243dSDimitry Andric// TODO: Use SchedVariant to select BRU for ALU ops that sets NZCV flags 57bdd1243dSDimitry Andric// (including ops that shift and/or extend): 58bdd1243dSDimitry Andric// 1cyc_1BRU: ADDS, ADCS, ANDS, BICS, SUBS, SBCS, CCMN, CCMP 59bdd1243dSDimitry Andric// 2cyc_1BRU: ADDSshfr, SUBSshfr, ANDSshfr, ADDSextr, SUBSextr 60e8d8bef9SDimitry Andricdef : WriteRes<WriteImm, [TSV110UnitALUAB]> { let Latency = 1; } 61e8d8bef9SDimitry Andricdef : WriteRes<WriteI, [TSV110UnitALUAB]> { let Latency = 1; } 62e8d8bef9SDimitry Andricdef : WriteRes<WriteISReg, [TSV110UnitMDU]> { let Latency = 2; } 63e8d8bef9SDimitry Andricdef : WriteRes<WriteIEReg, [TSV110UnitMDU]> { let Latency = 2; } 64e8d8bef9SDimitry Andricdef : WriteRes<WriteExtr, [TSV110UnitALUAB]> { let Latency = 1; } 65e8d8bef9SDimitry Andricdef : WriteRes<WriteIS, [TSV110UnitALUAB]> { let Latency = 1; } 66e8d8bef9SDimitry Andric 67e8d8bef9SDimitry Andric// Integer Mul/MAC/Div 68e8d8bef9SDimitry Andricdef : WriteRes<WriteID32, [TSV110UnitMDU]> { let Latency = 12; 695f757f3fSDimitry Andric let ReleaseAtCycles = [12]; } 70e8d8bef9SDimitry Andricdef : WriteRes<WriteID64, [TSV110UnitMDU]> { let Latency = 20; 715f757f3fSDimitry Andric let ReleaseAtCycles = [20]; } 72e8d8bef9SDimitry Andricdef : WriteRes<WriteIM32, [TSV110UnitMDU]> { let Latency = 3; } 73e8d8bef9SDimitry Andricdef : WriteRes<WriteIM64, [TSV110UnitMDU]> { let Latency = 4; } 74e8d8bef9SDimitry Andric 75e8d8bef9SDimitry Andric// Load 76bdd1243dSDimitry Andricdef : WriteRes<WriteLD, [TSV110UnitLd]> { let Latency = 4; } 77bdd1243dSDimitry Andricdef : WriteRes<WriteLDIdx, [TSV110UnitLd]> { let Latency = 4; } 78e8d8bef9SDimitry Andricdef : WriteRes<WriteLDHi, []> { let Latency = 4; } 79e8d8bef9SDimitry Andric 80e8d8bef9SDimitry Andric// Pre/Post Indexing 81e8d8bef9SDimitry Andricdef : WriteRes<WriteAdr, [TSV110UnitALUAB]> { let Latency = 1; } 82e8d8bef9SDimitry Andric 83e8d8bef9SDimitry Andric// Store 84bdd1243dSDimitry Andricdef : WriteRes<WriteST, [TSV110UnitLd0St]> { let Latency = 1; } 85bdd1243dSDimitry Andricdef : WriteRes<WriteSTP, [TSV110UnitLd0St]> { let Latency = 1; } 86bdd1243dSDimitry Andricdef : WriteRes<WriteSTIdx, [TSV110UnitLd0St]> { let Latency = 1; } 87e8d8bef9SDimitry Andric 88e8d8bef9SDimitry Andric// FP 89e8d8bef9SDimitry Andricdef : WriteRes<WriteF, [TSV110UnitF]> { let Latency = 2; } 90e8d8bef9SDimitry Andricdef : WriteRes<WriteFCmp, [TSV110UnitF]> { let Latency = 3; } 91e8d8bef9SDimitry Andricdef : WriteRes<WriteFCvt, [TSV110UnitF]> { let Latency = 3; } 92e8d8bef9SDimitry Andricdef : WriteRes<WriteFCopy, [TSV110UnitF]> { let Latency = 2; } 93e8d8bef9SDimitry Andricdef : WriteRes<WriteFImm, [TSV110UnitF]> { let Latency = 2; } 94e8d8bef9SDimitry Andricdef : WriteRes<WriteFMul, [TSV110UnitF]> { let Latency = 5; } 95e8d8bef9SDimitry Andric 96e8d8bef9SDimitry Andric// FP Div, Sqrt 975f757f3fSDimitry Andricdef : WriteRes<WriteFDiv, [TSV110UnitFSU1]> { let Latency = 18; let ReleaseAtCycles = [18]; } 98e8d8bef9SDimitry Andric 99349cc55cSDimitry Andricdef : WriteRes<WriteVd, [TSV110UnitF]> { let Latency = 4; } 100349cc55cSDimitry Andricdef : WriteRes<WriteVq, [TSV110UnitF]> { let Latency = 4; } 101e8d8bef9SDimitry Andricdef : WriteRes<WriteVST, [TSV110UnitF]> { let Latency = 1; } 102e8d8bef9SDimitry Andric 103e8d8bef9SDimitry Andric// Branch 104e8d8bef9SDimitry Andricdef : WriteRes<WriteBr, [TSV110UnitAB]> { let Latency = 1; } 105e8d8bef9SDimitry Andricdef : WriteRes<WriteBrReg, [TSV110UnitAB]> { let Latency = 1; } 106e8d8bef9SDimitry Andricdef : WriteRes<WriteSys, []> { let Latency = 1; } 107e8d8bef9SDimitry Andricdef : WriteRes<WriteBarrier, []> { let Latency = 1; } 108e8d8bef9SDimitry Andricdef : WriteRes<WriteHint, []> { let Latency = 1; } 109e8d8bef9SDimitry Andric 110e8d8bef9SDimitry Andricdef : WriteRes<WriteAtomic, []> { let Unsupported = 1; } 111e8d8bef9SDimitry Andric 112e8d8bef9SDimitry Andric// Forwarding logic is modeled only for multiply and accumulate. 113e8d8bef9SDimitry Andricdef : ReadAdvance<ReadI, 0>; 114e8d8bef9SDimitry Andricdef : ReadAdvance<ReadISReg, 0>; 115e8d8bef9SDimitry Andricdef : ReadAdvance<ReadIEReg, 0>; 116e8d8bef9SDimitry Andricdef : ReadAdvance<ReadIM, 0>; 117e8d8bef9SDimitry Andricdef : ReadAdvance<ReadIMA, 2, [WriteIM32, WriteIM64]>; 118e8d8bef9SDimitry Andricdef : ReadAdvance<ReadID, 0>; 119e8d8bef9SDimitry Andricdef : ReadAdvance<ReadExtrHi, 0>; 120e8d8bef9SDimitry Andricdef : ReadAdvance<ReadAdrBase, 0>; 121e8d8bef9SDimitry Andricdef : ReadAdvance<ReadVLD, 0>; 122349cc55cSDimitry Andricdef : ReadAdvance<ReadST, 0>; 123e8d8bef9SDimitry Andric 124e8d8bef9SDimitry Andricdef : InstRW<[WriteI], (instrs COPY)>; 125e8d8bef9SDimitry Andric 126e8d8bef9SDimitry Andric// Detailed Refinements 127e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 128e8d8bef9SDimitry Andric 129e8d8bef9SDimitry Andric// Contains all of the TSV110 specific SchedWriteRes types. The approach 130e8d8bef9SDimitry Andric// below is to define a generic SchedWriteRes for every combination of 131e8d8bef9SDimitry Andric// latency and microOps. The naming conventions is to use a prefix, one field 132e8d8bef9SDimitry Andric// for latency, and one or more microOp count/type designators. 133e8d8bef9SDimitry Andric// Prefix: TSV110Wr 134e8d8bef9SDimitry Andric// Latency: #cyc 135e8d8bef9SDimitry Andric// MicroOp Count/Types: #(ALU|AB|MDU|FSU1|FSU2|LdSt|ALUAB|F|FLdSt) 136e8d8bef9SDimitry Andric// 137e8d8bef9SDimitry Andric// e.g. TSV110Wr_6cyc_1ALU_6MDU_4LdSt means the total latency is 6 and there are 138e8d8bef9SDimitry Andric// 1 micro-ops to be issued down one ALU pipe, six MDU pipes and four LdSt pipes. 139e8d8bef9SDimitry Andric// 140e8d8bef9SDimitry Andric 141e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 142e8d8bef9SDimitry Andric// Define Generic 1 micro-op types 143e8d8bef9SDimitry Andric 144e8d8bef9SDimitry Andricdef TSV110Wr_1cyc_1AB : SchedWriteRes<[TSV110UnitAB]> { let Latency = 1; } 145e8d8bef9SDimitry Andricdef TSV110Wr_1cyc_1ALU : SchedWriteRes<[TSV110UnitALU]> { let Latency = 1; } 146e8d8bef9SDimitry Andricdef TSV110Wr_1cyc_1ALUAB : SchedWriteRes<[TSV110UnitALUAB]> { let Latency = 1; } 147bdd1243dSDimitry Andricdef TSV110Wr_1cyc_1LdSt : SchedWriteRes<[TSV110UnitLd0St]> { let Latency = 1; } 148e8d8bef9SDimitry Andric 1495f757f3fSDimitry Andricdef TSV110Wr_2cyc_1AB : SchedWriteRes<[TSV110UnitAB]> { let Latency = 2; let ReleaseAtCycles = [2]; } 150e8d8bef9SDimitry Andricdef TSV110Wr_2cyc_1ALU : SchedWriteRes<[TSV110UnitALU]> { let Latency = 2; } 151e8d8bef9SDimitry Andricdef TSV110Wr_2cyc_1MDU : SchedWriteRes<[TSV110UnitMDU]> { let Latency = 2; } 152e8d8bef9SDimitry Andricdef TSV110Wr_2cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]> { let Latency = 2; } 153e8d8bef9SDimitry Andricdef TSV110Wr_2cyc_1F : SchedWriteRes<[TSV110UnitF]> { let Latency = 2; } 154e8d8bef9SDimitry Andric 155e8d8bef9SDimitry Andricdef TSV110Wr_3cyc_1F : SchedWriteRes<[TSV110UnitF]> { let Latency = 3; } 156e8d8bef9SDimitry Andricdef TSV110Wr_3cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]> { let Latency = 3; } 157e8d8bef9SDimitry Andricdef TSV110Wr_3cyc_1MDU : SchedWriteRes<[TSV110UnitMDU]> { let Latency = 3; } 158e8d8bef9SDimitry Andric 159e8d8bef9SDimitry Andricdef TSV110Wr_4cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]> { let Latency = 4; } 160e8d8bef9SDimitry Andricdef TSV110Wr_4cyc_1F : SchedWriteRes<[TSV110UnitF]> { let Latency = 4; } 161bdd1243dSDimitry Andricdef TSV110Wr_4cyc_1LdSt : SchedWriteRes<[TSV110UnitLd]> { let Latency = 4; } 162e8d8bef9SDimitry Andricdef TSV110Wr_4cyc_1MDU : SchedWriteRes<[TSV110UnitMDU]> { let Latency = 4; } 163e8d8bef9SDimitry Andric 164e8d8bef9SDimitry Andricdef TSV110Wr_5cyc_1F : SchedWriteRes<[TSV110UnitF]> { let Latency = 5; } 165e8d8bef9SDimitry Andricdef TSV110Wr_5cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]> { let Latency = 5; } 166e8d8bef9SDimitry Andricdef TSV110Wr_5cyc_1FSU2 : SchedWriteRes<[TSV110UnitFSU2]> { let Latency = 5; } 167bdd1243dSDimitry Andricdef TSV110Wr_5cyc_1LdSt : SchedWriteRes<[TSV110UnitLd]> { let Latency = 5; } 168e8d8bef9SDimitry Andric 169e8d8bef9SDimitry Andricdef TSV110Wr_6cyc_1F : SchedWriteRes<[TSV110UnitF]> { let Latency = 6; } 170e8d8bef9SDimitry Andric 171e8d8bef9SDimitry Andricdef TSV110Wr_7cyc_1F : SchedWriteRes<[TSV110UnitF]> { let Latency = 7; } 172e8d8bef9SDimitry Andric 173e8d8bef9SDimitry Andricdef TSV110Wr_8cyc_1F : SchedWriteRes<[TSV110UnitF]> { let Latency = 8; } 174e8d8bef9SDimitry Andric 1755f757f3fSDimitry Andricdef TSV110Wr_11cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]> { let Latency = 11; let ReleaseAtCycles = [11]; } 176e8d8bef9SDimitry Andric 1775f757f3fSDimitry Andricdef TSV110Wr_12cyc_1MDU : SchedWriteRes<[TSV110UnitMDU]> { let Latency = 12; let ReleaseAtCycles = [12]; } 178e8d8bef9SDimitry Andric 1795f757f3fSDimitry Andricdef TSV110Wr_17cyc_1FSU2 : SchedWriteRes<[TSV110UnitFSU2]> { let Latency = 17; let ReleaseAtCycles = [17]; } 180e8d8bef9SDimitry Andric 1815f757f3fSDimitry Andricdef TSV110Wr_18cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]> { let Latency = 18; let ReleaseAtCycles = [18]; } 182e8d8bef9SDimitry Andric 1835f757f3fSDimitry Andricdef TSV110Wr_20cyc_1MDU : SchedWriteRes<[TSV110UnitMDU]> { let Latency = 20; let ReleaseAtCycles = [20]; } 184e8d8bef9SDimitry Andric 1855f757f3fSDimitry Andricdef TSV110Wr_24cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]> { let Latency = 24; let ReleaseAtCycles = [24]; } 186e8d8bef9SDimitry Andric 1875f757f3fSDimitry Andricdef TSV110Wr_31cyc_1FSU2 : SchedWriteRes<[TSV110UnitFSU2]> { let Latency = 31; let ReleaseAtCycles = [31]; } 188e8d8bef9SDimitry Andric 1895f757f3fSDimitry Andricdef TSV110Wr_36cyc_1FSU2 : SchedWriteRes<[TSV110UnitFSU2]> { let Latency = 36; let ReleaseAtCycles = [36]; } 190e8d8bef9SDimitry Andric 1915f757f3fSDimitry Andricdef TSV110Wr_38cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]> { let Latency = 38; let ReleaseAtCycles = [38]; } 192e8d8bef9SDimitry Andric 1935f757f3fSDimitry Andricdef TSV110Wr_64cyc_1FSU2 : SchedWriteRes<[TSV110UnitFSU2]> { let Latency = 64; let ReleaseAtCycles = [64]; } 194e8d8bef9SDimitry Andric 195e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 196e8d8bef9SDimitry Andric// Define Generic 2 micro-op types 197e8d8bef9SDimitry Andric 198bdd1243dSDimitry Andricdef TSV110Wr_1cyc_1LdSt_1ALUAB : SchedWriteRes<[TSV110UnitLd0St, 199e8d8bef9SDimitry Andric TSV110UnitALUAB]> { 200e8d8bef9SDimitry Andric let Latency = 1; 201e8d8bef9SDimitry Andric let NumMicroOps = 2; 202e8d8bef9SDimitry Andric} 203e8d8bef9SDimitry Andric 204bdd1243dSDimitry Andricdef TSV110Wr_2cyc_1LdSt_1ALUAB : SchedWriteRes<[TSV110UnitLd0St, 205e8d8bef9SDimitry Andric TSV110UnitALUAB]> { 206e8d8bef9SDimitry Andric let Latency = 2; 207e8d8bef9SDimitry Andric let NumMicroOps = 2; 208e8d8bef9SDimitry Andric} 209e8d8bef9SDimitry Andric 210bdd1243dSDimitry Andricdef TSV110Wr_2cyc_2LdSt : SchedWriteRes<[TSV110UnitLd0St, 211bdd1243dSDimitry Andric TSV110UnitLd0St]> { 212e8d8bef9SDimitry Andric let Latency = 2; 213e8d8bef9SDimitry Andric let NumMicroOps = 2; 214e8d8bef9SDimitry Andric} 215e8d8bef9SDimitry Andric 216e8d8bef9SDimitry Andricdef TSV110Wr_2cyc_2F : SchedWriteRes<[TSV110UnitF, 217e8d8bef9SDimitry Andric TSV110UnitF]> { 218e8d8bef9SDimitry Andric let Latency = 2; 219e8d8bef9SDimitry Andric let NumMicroOps = 2; 220e8d8bef9SDimitry Andric} 221e8d8bef9SDimitry Andric 222e8d8bef9SDimitry Andricdef TSV110Wr_2cyc_1FSU1_1FSU2 : SchedWriteRes<[TSV110UnitFSU1, 223e8d8bef9SDimitry Andric TSV110UnitFSU2]> { 224e8d8bef9SDimitry Andric let Latency = 2; 225e8d8bef9SDimitry Andric let NumMicroOps = 2; 226e8d8bef9SDimitry Andric} 227e8d8bef9SDimitry Andric 228e8d8bef9SDimitry Andricdef TSV110Wr_4cyc_2F : SchedWriteRes<[TSV110UnitF, 229e8d8bef9SDimitry Andric TSV110UnitF]> { 230e8d8bef9SDimitry Andric let Latency = 4; 231e8d8bef9SDimitry Andric let NumMicroOps = 2; 232e8d8bef9SDimitry Andric} 233e8d8bef9SDimitry Andric 234e8d8bef9SDimitry Andricdef TSV110Wr_4cyc_1FSU1_1FSU2 : SchedWriteRes<[TSV110UnitFSU1, 235e8d8bef9SDimitry Andric TSV110UnitFSU2]> { 236e8d8bef9SDimitry Andric let Latency = 4; 237e8d8bef9SDimitry Andric let NumMicroOps = 2; 238e8d8bef9SDimitry Andric} 239e8d8bef9SDimitry Andric 240bdd1243dSDimitry Andricdef TSV110Wr_4cyc_1LdSt_1ALUAB : SchedWriteRes<[TSV110UnitLd, 241e8d8bef9SDimitry Andric TSV110UnitALUAB]> { 242e8d8bef9SDimitry Andric let Latency = 4; 243e8d8bef9SDimitry Andric let NumMicroOps = 2; 244e8d8bef9SDimitry Andric} 245e8d8bef9SDimitry Andric 246e8d8bef9SDimitry Andricdef TSV110Wr_5cyc_1ALU_1F : SchedWriteRes<[TSV110UnitALU, 247e8d8bef9SDimitry Andric TSV110UnitF]> { 248e8d8bef9SDimitry Andric let Latency = 5; 249e8d8bef9SDimitry Andric let NumMicroOps = 2; 250e8d8bef9SDimitry Andric} 251e8d8bef9SDimitry Andric 252bdd1243dSDimitry Andricdef TSV110Wr_6cyc_2LdSt : SchedWriteRes<[TSV110UnitLd, 253bdd1243dSDimitry Andric TSV110UnitLd]> { 254e8d8bef9SDimitry Andric let Latency = 6; 255e8d8bef9SDimitry Andric let NumMicroOps = 2; 256e8d8bef9SDimitry Andric} 257e8d8bef9SDimitry Andric 258bdd1243dSDimitry Andricdef TSV110Wr_6cyc_1LdSt_1ALUAB : SchedWriteRes<[TSV110UnitLd, 259e8d8bef9SDimitry Andric TSV110UnitALUAB]> { 260e8d8bef9SDimitry Andric let Latency = 6; 261e8d8bef9SDimitry Andric let NumMicroOps = 2; 262e8d8bef9SDimitry Andric} 263e8d8bef9SDimitry Andric 264e8d8bef9SDimitry Andricdef TSV110Wr_7cyc_1F_1LdSt : SchedWriteRes<[TSV110UnitF, 265bdd1243dSDimitry Andric TSV110UnitLd]> { 266e8d8bef9SDimitry Andric let Latency = 7; 267e8d8bef9SDimitry Andric let NumMicroOps = 2; 268e8d8bef9SDimitry Andric} 269e8d8bef9SDimitry Andric 270e8d8bef9SDimitry Andricdef TSV110Wr_8cyc_2FSU1 : SchedWriteRes<[TSV110UnitFSU1, 271e8d8bef9SDimitry Andric TSV110UnitFSU1]> { 272e8d8bef9SDimitry Andric let Latency = 8; 273e8d8bef9SDimitry Andric let NumMicroOps = 2; 274e8d8bef9SDimitry Andric} 275e8d8bef9SDimitry Andric 276e8d8bef9SDimitry Andric 277e8d8bef9SDimitry Andricdef TSV110Wr_8cyc_1FSU1_1FSU2 : SchedWriteRes<[TSV110UnitFSU1, 278e8d8bef9SDimitry Andric TSV110UnitFSU2]> { 279e8d8bef9SDimitry Andric let Latency = 8; 280e8d8bef9SDimitry Andric let NumMicroOps = 2; 281e8d8bef9SDimitry Andric} 282e8d8bef9SDimitry Andric 283e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 284e8d8bef9SDimitry Andric// Define Generic 3 micro-op types 285e8d8bef9SDimitry Andric 286e8d8bef9SDimitry Andricdef TSV110Wr_6cyc_3F : SchedWriteRes<[TSV110UnitF, TSV110UnitF, 287e8d8bef9SDimitry Andric TSV110UnitF]> { 288e8d8bef9SDimitry Andric let Latency = 6; 289e8d8bef9SDimitry Andric let NumMicroOps = 3; 290e8d8bef9SDimitry Andric} 291e8d8bef9SDimitry Andric 292bdd1243dSDimitry Andricdef TSV110Wr_6cyc_3LdSt : SchedWriteRes<[TSV110UnitLd, TSV110UnitLd, 293bdd1243dSDimitry Andric TSV110UnitLd]> { 294e8d8bef9SDimitry Andric let Latency = 6; 295e8d8bef9SDimitry Andric let NumMicroOps = 3; 296e8d8bef9SDimitry Andric} 297e8d8bef9SDimitry Andric 298e8d8bef9SDimitry Andricdef TSV110Wr_7cyc_2F_1LdSt : SchedWriteRes<[TSV110UnitF, TSV110UnitF, 299bdd1243dSDimitry Andric TSV110UnitLd]> { 300e8d8bef9SDimitry Andric let Latency = 7; 301e8d8bef9SDimitry Andric let NumMicroOps = 3; 302e8d8bef9SDimitry Andric} 303e8d8bef9SDimitry Andric 304e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 305e8d8bef9SDimitry Andric// Define Generic 4 micro-op types 306e8d8bef9SDimitry Andric 307e8d8bef9SDimitry Andricdef TSV110Wr_8cyc_4F : SchedWriteRes<[TSV110UnitF, TSV110UnitF, 308e8d8bef9SDimitry Andric TSV110UnitF, TSV110UnitF]> { 309e8d8bef9SDimitry Andric let Latency = 8; 310e8d8bef9SDimitry Andric let NumMicroOps = 4; 311e8d8bef9SDimitry Andric} 312e8d8bef9SDimitry Andric 313e8d8bef9SDimitry Andricdef TSV110Wr_8cyc_3F_1LdSt : SchedWriteRes<[TSV110UnitF, TSV110UnitF, 314bdd1243dSDimitry Andric TSV110UnitF, TSV110UnitLd]> { 315e8d8bef9SDimitry Andric let Latency = 8; 316e8d8bef9SDimitry Andric let NumMicroOps = 4; 317e8d8bef9SDimitry Andric} 318e8d8bef9SDimitry Andric 319e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 320e8d8bef9SDimitry Andric// Define Generic 5 micro-op types 321e8d8bef9SDimitry Andric 322e8d8bef9SDimitry Andricdef TSV110Wr_8cyc_3F_2LdSt : SchedWriteRes<[TSV110UnitF, TSV110UnitF, TSV110UnitF, 323bdd1243dSDimitry Andric TSV110UnitLd, TSV110UnitLd]> { 324e8d8bef9SDimitry Andric let Latency = 8; 325e8d8bef9SDimitry Andric let NumMicroOps = 5; 326e8d8bef9SDimitry Andric} 327e8d8bef9SDimitry Andric 328e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 329e8d8bef9SDimitry Andric// Define Generic 8 micro-op types 330e8d8bef9SDimitry Andric 331e8d8bef9SDimitry Andricdef TSV110Wr_10cyc_4F_4LdSt : SchedWriteRes<[TSV110UnitF, TSV110UnitF, 332e8d8bef9SDimitry Andric TSV110UnitF, TSV110UnitF, 333bdd1243dSDimitry Andric TSV110UnitLd, TSV110UnitLd, 334bdd1243dSDimitry Andric TSV110UnitLd, TSV110UnitLd]> { 335e8d8bef9SDimitry Andric let Latency = 10; 336e8d8bef9SDimitry Andric let NumMicroOps = 8; 337e8d8bef9SDimitry Andric} 338e8d8bef9SDimitry Andric 339e8d8bef9SDimitry Andric 340e8d8bef9SDimitry Andric// Branch Instructions 341e8d8bef9SDimitry Andric// ----------------------------------------------------------------------------- 342e8d8bef9SDimitry Andric 343e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_1cyc_1AB], (instrs B)>; 344e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_1cyc_1AB], (instrs BL)>; 345e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_1cyc_1AB], (instrs BLR)>; 346e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_1cyc_1AB], (instregex "^(BR|RET|(CBZ|CBNZ|TBZ|TBNZ))$")>; 347e8d8bef9SDimitry Andric 348e8d8bef9SDimitry Andric 349e8d8bef9SDimitry Andric// Cryptography Extensions 350e8d8bef9SDimitry Andric// ----------------------------------------------------------------------------- 351e8d8bef9SDimitry Andric 352e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_3cyc_1FSU1], (instregex "^AES[DE]")>; 353e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_3cyc_1FSU1], (instregex "^AESI?MC")>; 354e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_2cyc_1FSU1], (instregex "^SHA1SU1")>; 355e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_2cyc_2F], (instregex "^SHA1(H|SU0)")>; 356e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_5cyc_1FSU1], (instregex "^SHA1[CMP]")>; 357e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_2cyc_1FSU1], (instregex "^SHA256SU0")>; 358e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_3cyc_1FSU1], (instregex "^SHA256SU1")>; 359e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_5cyc_1FSU1], (instregex "^SHA256(H|H2)")>; 360e8d8bef9SDimitry Andricdef TSV110ReadCRC: SchedReadAdvance<1, [TSV110Wr_2cyc_1MDU]>; 361e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_2cyc_1MDU, TSV110ReadCRC], (instregex "^CRC32.*$")>; 362e8d8bef9SDimitry Andric 363e8d8bef9SDimitry Andric 364e8d8bef9SDimitry Andric// Arithmetic and Logical Instructions 365e8d8bef9SDimitry Andric// ----------------------------------------------------------------------------- 366e8d8bef9SDimitry Andric 367e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_1cyc_1ALUAB], (instregex "(BIC|EON|ORN)[WX]rr")>; 368e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_1cyc_1AB], (instregex "(BIC)S[WX]rr")>; 369e8d8bef9SDimitry Andric 370e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_1cyc_1ALUAB], (instregex "(ADD|AND|EOR|ORR|SUB)[WX]r(r|i)")>; 371e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_1cyc_1AB], (instregex "(ADD|AND|EOR|ORR|SUB)S[WX]r(r|i)")>; 372e8d8bef9SDimitry Andric 373e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_1cyc_1ALUAB], (instregex "^(ADC|SBC|BIC)[WX]r$")>; 374e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_1cyc_1AB], (instregex "^(ADC|SBC)S[WX]r$")>; 375e8d8bef9SDimitry Andric 376bdd1243dSDimitry Andric 377bdd1243dSDimitry Andric// Shifted Register with Shift == 0 378bdd1243dSDimitry Andric// ---------------------------------------------------------------------------- 379bdd1243dSDimitry Andric 380bdd1243dSDimitry Andricdef TSV110WrISReg : SchedWriteVariant<[ 381bdd1243dSDimitry Andric SchedVar<RegShiftedPred, [WriteISReg]>, 382bdd1243dSDimitry Andric SchedVar<NoSchedPred, [WriteI]>]>; 383bdd1243dSDimitry Andricdef : InstRW<[TSV110WrISReg], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|ORR|SUB)[WX]rs$")>; 384bdd1243dSDimitry Andric 385bdd1243dSDimitry Andricdef TSV110WrISRegBr : SchedWriteVariant<[ 386bdd1243dSDimitry Andric SchedVar<RegShiftedPred, [TSV110Wr_2cyc_1AB]>, 387bdd1243dSDimitry Andric SchedVar<NoSchedPred, [WriteBr]>]>; 388bdd1243dSDimitry Andricdef : InstRW<[TSV110WrISRegBr], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|ORR|SUB)S[WX]rs$")>; 389bdd1243dSDimitry Andric 390bdd1243dSDimitry Andric// Extended Register with Extend == 0 391bdd1243dSDimitry Andric// ---------------------------------------------------------------------------- 392bdd1243dSDimitry Andric 393bdd1243dSDimitry Andricdef TSV110WrIEReg : SchedWriteVariant<[ 394bdd1243dSDimitry Andric SchedVar<RegExtendedPred, [WriteISReg]>, 395bdd1243dSDimitry Andric SchedVar<NoSchedPred, [WriteI]>]>; 396bdd1243dSDimitry Andricdef : InstRW<[TSV110WrIEReg], (instregex "^(ADD|SUB)[WX]r(x|x64)$")>; 397bdd1243dSDimitry Andric 398bdd1243dSDimitry Andricdef TSV110WrIERegBr : SchedWriteVariant<[ 399bdd1243dSDimitry Andric SchedVar<RegExtendedPred, [TSV110Wr_2cyc_1AB]>, 400bdd1243dSDimitry Andric SchedVar<NoSchedPred, [WriteBr]>]>; 401bdd1243dSDimitry Andricdef : InstRW<[TSV110WrIERegBr], (instregex "^(ADD|SUB)S[WX]r(x|x64)$")>; 402e8d8bef9SDimitry Andric 403e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_1cyc_1AB], (instregex "^(CCMN|CCMP)(W|X)(r|i)$")>; 404e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_1cyc_1ALUAB], (instregex "^(CSEL|CSINC|CSINV|CSNEG)(W|X)r$")>; 405e8d8bef9SDimitry Andric 406e8d8bef9SDimitry Andric 407e8d8bef9SDimitry Andric// Move and Shift Instructions 408e8d8bef9SDimitry Andric// ----------------------------------------------------------------------------- 409e8d8bef9SDimitry Andric 410e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_1cyc_1ALUAB], (instrs ADR, ADRP)>; 411e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_1cyc_1ALUAB], (instregex "^MOV[NZK][WX]i")>; 412e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_1cyc_1ALUAB], (instregex "(LSLV|LSRV|ASRV|RORV)(W|X)r")>; 413e8d8bef9SDimitry Andric 414e8d8bef9SDimitry Andric 415e8d8bef9SDimitry Andric// Divide and Multiply Instructions 416e8d8bef9SDimitry Andric// ----------------------------------------------------------------------------- 417e8d8bef9SDimitry Andric 418e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_12cyc_1MDU], (instregex "^(S|U)DIVWr$")>; 419e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_20cyc_1MDU], (instregex "^(S|U)DIVXr$")>; 420e8d8bef9SDimitry Andric 421e8d8bef9SDimitry Andricdef TSV110ReadMAW : SchedReadAdvance<2, [TSV110Wr_3cyc_1MDU]>; 422e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_3cyc_1MDU, TSV110ReadMAW], (instrs MADDWrrr, MSUBWrrr)>; 423e8d8bef9SDimitry Andricdef TSV110ReadMAQ : SchedReadAdvance<3, [TSV110Wr_4cyc_1MDU]>; 424e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_4cyc_1MDU, TSV110ReadMAQ], (instrs MADDXrrr, MSUBXrrr)>; 425e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_3cyc_1MDU, TSV110ReadMAW], (instregex "(S|U)(MADDL|MSUBL)rrr")>; 426e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_4cyc_1MDU], (instregex "^(S|U)MULHrr$")>; 427e8d8bef9SDimitry Andric 428e8d8bef9SDimitry Andric 429e8d8bef9SDimitry Andric// Miscellaneous Data-Processing Instructions 430e8d8bef9SDimitry Andric// ----------------------------------------------------------------------------- 431e8d8bef9SDimitry Andric 432e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_1cyc_1ALUAB], (instregex "^EXTR(W|X)rri$")>; 433e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_1cyc_1ALUAB], (instregex "^(S|U)?BFM(W|X)ri$")>; 434e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_1cyc_1ALUAB], (instregex "^(CLS|CLZ|RBIT|REV(16|32)?)(W|X)r$")>; 435e8d8bef9SDimitry Andric 436e8d8bef9SDimitry Andric 437e8d8bef9SDimitry Andric// Load Instructions 438e8d8bef9SDimitry Andric// ----------------------------------------------------------------------------- 439e8d8bef9SDimitry Andric 440e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_4cyc_1LdSt], (instregex "^LDR(W|X)l$")>; 441e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_4cyc_1LdSt], (instrs LDRSWl)>; 442e8d8bef9SDimitry Andric 443e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_4cyc_1LdSt], (instregex "^LDR(BB|HH|W|X)ui$")>; 444e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_4cyc_1LdSt], (instregex "^LDRS(BW|BX|HW|HX|W)ui$")>; 445e8d8bef9SDimitry Andric 4465f757f3fSDimitry Andricdef : InstRW<[WriteAdr, TSV110Wr_4cyc_1LdSt], (instregex "^LDR(BB|HH|W|X)(post|pre)$")>; 4475f757f3fSDimitry Andricdef : InstRW<[WriteAdr, TSV110Wr_4cyc_1LdSt], (instregex "^LDRS(BW|BX|HW|HX|W)(post|pre)$")>; 448e8d8bef9SDimitry Andric 449e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_4cyc_1LdSt], (instregex "^LDTR(B|H|W|X)i$")>; 450e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_4cyc_1LdSt], (instregex "^LDUR(BB|HH|W|X)i$")>; 451e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_4cyc_1LdSt], (instregex "^LDTRS(BW|BX|HW|HX|W)i$")>; 452e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_4cyc_1LdSt], (instregex "^LDURS(BW|BX|HW|HX|W)i$")>; 453e8d8bef9SDimitry Andric 454e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_4cyc_1LdSt, WriteLDHi], (instregex "^LDNP(W|X)i$")>; 455e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_4cyc_1LdSt, WriteLDHi], (instregex "^LDP(W|X)i$")>; 4565f757f3fSDimitry Andricdef : InstRW<[WriteAdr, TSV110Wr_4cyc_1LdSt_1ALUAB, WriteLDHi],(instregex "^LDP(W|X)(post|pre)$")>; 457e8d8bef9SDimitry Andric 458e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_4cyc_1LdSt, WriteLDHi], (instrs LDPSWi)>; 4595f757f3fSDimitry Andricdef : InstRW<[WriteAdr, TSV110Wr_4cyc_1LdSt, WriteLDHi], (instrs LDPSWpost)>; 4605f757f3fSDimitry Andricdef : InstRW<[WriteAdr, TSV110Wr_4cyc_1LdSt, WriteLDHi], (instrs LDPSWpre)>; 461e8d8bef9SDimitry Andric 462e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_4cyc_1LdSt], (instrs PRFMl)>; 463e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_4cyc_1LdSt], (instrs PRFUMi)>; 464e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_4cyc_1LdSt], (instregex "^PRFMui$")>; 465e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_4cyc_1LdSt], (instregex "^PRFMro(W|X)$")>; 466e8d8bef9SDimitry Andric 467e8d8bef9SDimitry Andric 468e8d8bef9SDimitry Andric// Store Instructions 469e8d8bef9SDimitry Andric// ----------------------------------------------------------------------------- 470e8d8bef9SDimitry Andric 471e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_1cyc_1LdSt], (instregex "^STN?P(W|X)i$")>; 4725f757f3fSDimitry Andricdef : InstRW<[WriteAdr, TSV110Wr_1cyc_1LdSt], (instregex "^STP(W|X)(post|pre)$")>; 473e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_1cyc_1LdSt], (instregex "^STUR(BB|HH|W|X)i$")>; 474e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_1cyc_1LdSt], (instregex "^STTR(B|H|W|X)i$")>; 475e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_1cyc_1LdSt], (instregex "^STR(BB|HH|W|X)ui$")>; 476e8d8bef9SDimitry Andric 4775f757f3fSDimitry Andricdef : InstRW<[WriteAdr, TSV110Wr_1cyc_1LdSt], (instregex "^STR(BB|HH|W|X)(post|pre)$")>; 4785f757f3fSDimitry Andricdef : InstRW<[WriteAdr, TSV110Wr_1cyc_1LdSt], (instregex "^STR(BB|HH|W|X)ro(W|X)$")>; 479e8d8bef9SDimitry Andric 480e8d8bef9SDimitry Andric 481e8d8bef9SDimitry Andric// FP Data Processing Instructions 482e8d8bef9SDimitry Andric// ----------------------------------------------------------------------------- 483e8d8bef9SDimitry Andric 484e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_2cyc_1F], (instregex "F(ABS|NEG)(D|S)r")>; 485e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_3cyc_1F], (instregex "^FCCMP(E)?(S|D)rr$")>; 486e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_3cyc_1F], (instregex "^FCMP(E)?(S|D)r(r|i)$")>; 487e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_3cyc_1F], (instregex "^FCSEL(S|D)rrr$")>; 488e8d8bef9SDimitry Andric 489e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_11cyc_1FSU1], (instrs FDIVSrr)>; 490e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_18cyc_1FSU1], (instrs FDIVDrr)>; 491e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_17cyc_1FSU2], (instrs FSQRTSr)>; 492e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_31cyc_1FSU2], (instrs FSQRTDr)>; 493e8d8bef9SDimitry Andric 494e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_2cyc_1F], (instregex "^F(MAX|MIN).+rr")>; 495e8d8bef9SDimitry Andric 496e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_4cyc_1F], (instregex "^FN?M(ADD|SUB)Hrrr")>; 497e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_5cyc_1F], (instregex "^FN?M(ADD|SUB)Srrr")>; 498e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_7cyc_1F], (instregex "^FN?M(ADD|SUB)Drrr")>; 499e8d8bef9SDimitry Andric 500e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_4cyc_1F], (instregex "^F(ADD|SUB)Hrr")>; 501e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_5cyc_1F], (instregex "^F(ADD|SUB)Srr")>; 502e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_4cyc_1F], (instregex "^F(ADD|SUB)Drr")>; 503e8d8bef9SDimitry Andric 504e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_4cyc_1F], (instregex "^F(N)?MULHrr$")>; 505e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_5cyc_1F], (instregex "^F(N)?MULSrr$")>; 506e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_5cyc_1F], (instregex "^F(N)?MULDrr$")>; 507e8d8bef9SDimitry Andric 508e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_3cyc_1F], (instregex "^FRINT.+r")>; 509e8d8bef9SDimitry Andric 510e8d8bef9SDimitry Andric 511e8d8bef9SDimitry Andric// FP Miscellaneous Instructions 512e8d8bef9SDimitry Andric// ----------------------------------------------------------------------------- 513e8d8bef9SDimitry Andric 514e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_5cyc_1ALU_1F], (instregex "^[SU]CVTF[SU][WX][SD]ri")>; 515e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_4cyc_1FSU1], (instregex "^FCVT(A|M|N|P|Z)(S|U)U(W|X)(S|D)r$")>; 516e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_3cyc_1F], (instregex "^FCVT[HSD][HSD]r")>; 517e8d8bef9SDimitry Andric 518e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_2cyc_1FSU1], (instregex "^FMOV(DX|WS|XD|SW|DXHigh|XDHigh)r$")>; 519e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_2cyc_1F], (instregex "^FMOV[SD][ir]$")>; 520e8d8bef9SDimitry Andric 521e8d8bef9SDimitry Andric 522e8d8bef9SDimitry Andric// FP Load Instructions 523e8d8bef9SDimitry Andric// ----------------------------------------------------------------------------- 524e8d8bef9SDimitry Andric 525e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_5cyc_1LdSt], (instregex "^LDR[DSQ]l")>; 526e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_5cyc_1LdSt], (instregex "^LDUR[BDHSQ]i")>; 5275f757f3fSDimitry Andricdef : InstRW<[WriteAdr, TSV110Wr_5cyc_1LdSt], (instregex "^LDR[BDHSQ](post|pre)")>; 528e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_5cyc_1LdSt], (instregex "^LDR[BDHSQ]ui")>; 529e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_6cyc_1LdSt_1ALUAB, ReadAdrBase], (instregex "^LDR(Q|D|H|S|B)ro(W|X)$")>; 530e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_5cyc_1LdSt, WriteLDHi], (instregex "^LDN?P[DQS]i")>; 5315f757f3fSDimitry Andricdef : InstRW<[WriteAdr, TSV110Wr_5cyc_1LdSt, WriteLDHi], (instregex "^LDP[DQS](post|pre)")>; 532e8d8bef9SDimitry Andric 533e8d8bef9SDimitry Andric 534e8d8bef9SDimitry Andric// FP Store Instructions 535e8d8bef9SDimitry Andric// ----------------------------------------------------------------------------- 536e8d8bef9SDimitry Andric 537e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_1cyc_1LdSt], (instregex "^STUR[BHSDQ]i")>; 538e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_1cyc_1LdSt_1ALUAB, ReadAdrBase], (instregex "^STR[BHSDQ](post|pre)")>; 539e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_1cyc_1LdSt], (instregex "^STR[BHSDQ]ui")>; 540e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_2cyc_1LdSt_1ALUAB, ReadAdrBase], (instregex "^STR[BHSDQ]ro[WX]")>; 541e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_2cyc_2LdSt], (instregex "^STN?P[SDQ]i")>; 5425f757f3fSDimitry Andricdef : InstRW<[WriteAdr, TSV110Wr_2cyc_2LdSt], (instregex "^STP[SDQ](post|pre)")>; 543e8d8bef9SDimitry Andric 544e8d8bef9SDimitry Andric 545e8d8bef9SDimitry Andric// ASIMD Integer Instructions 546e8d8bef9SDimitry Andric// ----------------------------------------------------------------------------- 547e8d8bef9SDimitry Andric 548e8d8bef9SDimitry Andric// Reference for forms in this group 549e8d8bef9SDimitry Andric// D form - v8i8, v4i16, v2i32 550e8d8bef9SDimitry Andric// Q form - v16i8, v8i16, v4i32 551e8d8bef9SDimitry Andric// D form - v1i8, v1i16, v1i32, v1i64 552e8d8bef9SDimitry Andric// Q form - v16i8, v8i16, v4i32, v2i64 553e8d8bef9SDimitry Andric// D form - v8i8_v8i16, v4i16_v4i32, v2i32_v2i64 554e8d8bef9SDimitry Andric// Q form - v16i8_v8i16, v8i16_v4i32, v4i32_v2i64 555e8d8bef9SDimitry Andric 556e8d8bef9SDimitry Andric// ASIMD simple arithmetic 557e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^(ABS|ADD(P)?|NEG|SUB)v")>; 558e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^[SU](ADD(L|LP|W)|SUB(L|W))v")>; 559e8d8bef9SDimitry Andric 560e8d8bef9SDimitry Andric// ASIMD complex arithmetic 561e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_4cyc_1FSU1_1FSU2], (instregex "^[SU]H(ADD|SUB)v")>; 562e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_4cyc_1FSU1_1FSU2], (instregex "^R?(ADD|SUB)HN2?v")>; 563e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_4cyc_1FSU1_1FSU2], (instregex "^[SU]Q(ADD|SUB)v")>; 564e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_4cyc_1FSU1_1FSU2], (instregex "^(SU|US)QADDv")>; 565e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_4cyc_1FSU1_1FSU2], (instregex "^[SU]RHADDv")>; 566e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_4cyc_1FSU1_1FSU2], (instregex "^[SU]ABAL?v")>; 567e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_4cyc_1FSU1_1FSU2], (instregex "^[SU]ABDL?v")>; 568e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_4cyc_1FSU1_1FSU2], (instregex "^[SU]ADALPv")>; 569e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_4cyc_1FSU1_1FSU2], (instregex "^((SQ)(ABS|NEG))v")>; 570e8d8bef9SDimitry Andric 571e8d8bef9SDimitry Andric// ASIMD compare 572e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^CM(EQ|GE|GT|HI|HS|LE|LT|TST)v")>; 573e8d8bef9SDimitry Andric 574e8d8bef9SDimitry Andric// ASIMD max/min 575e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^[SU](MIN|MAX)P?v")>; 576e8d8bef9SDimitry Andric 577e8d8bef9SDimitry Andric// ASIMD logical 578e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^(AND|BIC|BIF|BIT|BSL|EOR|MVN|NOT|ORN|ORR)v")>; 579e8d8bef9SDimitry Andric 580e8d8bef9SDimitry Andric// ASIMD multiply accumulate, D-form 581e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_4cyc_1FSU1], (instregex "^(MUL|ML[AS]|SQR?D(MULH))(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v1i64)")>; 582e8d8bef9SDimitry Andric// ASIMD multiply accumulate, Q-form 583e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_8cyc_2FSU1], (instregex "^(MUL|ML[AS]|SQR?D(MULH))(v16i8|v8i16|v4i32)")>; 584e8d8bef9SDimitry Andric 585e8d8bef9SDimitry Andric// ASIMD multiply accumulate long 586e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_4cyc_1FSU1], (instregex "(S|U|SQD)(MLAL|MLSL|MULL)v.*")>; 587e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_2cyc_1FSU1], (instregex "^PMULL(v8i8|v16i8)")>; 588e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_2cyc_1FSU1], (instregex "^PMULL(v1i64|v2i64)")>; 589e8d8bef9SDimitry Andric 590e8d8bef9SDimitry Andric// ASIMD shift 591e8d8bef9SDimitry Andric// ASIMD shift accumulate 592e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_4cyc_1FSU1], (instregex "^(S|SR|U|UR)SRA")>; 593e8d8bef9SDimitry Andric// ASIMD shift by immed, basic 594e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_4cyc_1FSU1], 595e8d8bef9SDimitry Andric (instregex "SHLv","SLIv","SRIv","SHRNv","SQXTNv","SQXTUNv","UQXTNv")>; 596e8d8bef9SDimitry Andric// ASIMD shift by immed, complex 597e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_4cyc_1FSU1], (instregex "^[SU]?(Q|R){1,2}SHR")>; 598e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_4cyc_1FSU1], (instregex "^SQSHLU")>; 599e8d8bef9SDimitry Andric// ASIMD shift by register, basic, Q-form 600e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_4cyc_1FSU1], (instregex "^[SU]SHL(v16i8|v8i16|v4i32|v2i64)")>; 601e8d8bef9SDimitry Andric// ASIMD shift by register, complex, D-form 602e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_4cyc_1FSU1], (instregex "^[SU][QR]{1,2}SHL(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2i32|b|d|h|s)")>; 603e8d8bef9SDimitry Andric// ASIMD shift by register, complex, Q-form 604e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_4cyc_1FSU1], (instregex "^[SU][QR]{1,2}SHL(v16i8|v8i16|v4i32|v2i64)")>; 605e8d8bef9SDimitry Andric 606e8d8bef9SDimitry Andric// ASIMD reduction 607e8d8bef9SDimitry Andric// ASIMD arith, reduce, 4H/4S 608e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_4cyc_1FSU1_1FSU2], (instregex "^[SU]?ADDL?V(v8i8|v4i16|v2i32)v$")>; 609e8d8bef9SDimitry Andric// ASIMD arith, reduce, 8B/8H 610e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_8cyc_1FSU1_1FSU2], (instregex "^[SU]?ADDL?V(v8i16|v4i32)v$")>; 611e8d8bef9SDimitry Andric// ASIMD arith, reduce, 16B 612e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_8cyc_1FSU1_1FSU2], (instregex "^[SU]?ADDL?Vv16i8v$")>; 613e8d8bef9SDimitry Andric 614e8d8bef9SDimitry Andric// ASIMD max/min, reduce, 4H/4S 615e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_4cyc_1FSU1_1FSU2], (instregex "^[SU](MIN|MAX)V(v4i16|v4i32)v$")>; 616e8d8bef9SDimitry Andric// ASIMD max/min, reduce, 8B/8H 617e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_8cyc_1FSU1_1FSU2], (instregex "^[SU](MIN|MAX)V(v8i8|v8i16)v$")>; 618e8d8bef9SDimitry Andric// ASIMD max/min, reduce, 16B 619e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_8cyc_1FSU1_1FSU2], (instregex "^[SU](MIN|MAX)Vv16i8v$")>; 620e8d8bef9SDimitry Andric 621e8d8bef9SDimitry Andric 622e8d8bef9SDimitry Andric// Vector - Floating Point 623e8d8bef9SDimitry Andric// ----------------------------------------------------------------------------- 624e8d8bef9SDimitry Andric 625e8d8bef9SDimitry Andric// Reference for forms in this group 626e8d8bef9SDimitry Andric// D form - v2f32 627e8d8bef9SDimitry Andric// Q form - v4f32, v2f64 628e8d8bef9SDimitry Andric// D form - 32, 64 629e8d8bef9SDimitry Andric// D form - v1i32, v1i64 630e8d8bef9SDimitry Andric// D form - v2i32 631e8d8bef9SDimitry Andric// Q form - v4i32, v2i64 632e8d8bef9SDimitry Andric 633e8d8bef9SDimitry Andric// ASIMD FP sign manipulation 634e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_2cyc_1F], (instregex "^FABSv")>; 635e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_2cyc_1F], (instregex "^FNEGv")>; 636e8d8bef9SDimitry Andric 637e8d8bef9SDimitry Andric// ASIMD FP compare 638e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_2cyc_1F], (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)v")>; 639e8d8bef9SDimitry Andric 640e8d8bef9SDimitry Andric// ASIMD FP convert 641e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_2cyc_1F], (instregex "^FCVT[AMNPZ][SU]v")>; 642e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_3cyc_1F], (instregex "^FCVT(L)v")>; 643e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_5cyc_1F], (instregex "^FCVT(N|XN)v")>; 644e8d8bef9SDimitry Andric 645e8d8bef9SDimitry Andric// ASIMD FP divide, D-form, F32 646e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_11cyc_1FSU1], (instregex "FDIVv2f32")>; 647e8d8bef9SDimitry Andric// ASIMD FP divide, Q-form, F32 648e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_24cyc_1FSU1], (instregex "FDIVv4f32")>; 649e8d8bef9SDimitry Andric// ASIMD FP divide, Q-form, F64 650e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_38cyc_1FSU1], (instregex "FDIVv2f64")>; 651e8d8bef9SDimitry Andric 652e8d8bef9SDimitry Andric// ASIMD FP SQRT 653e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_17cyc_1FSU2], (instrs FSQRTv2f32)>; 654e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_36cyc_1FSU2], (instrs FSQRTv4f32)>; 655e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_64cyc_1FSU2], (instrs FSQRTv2f64)>; 656e8d8bef9SDimitry Andric 657e8d8bef9SDimitry Andric// ASIMD FP max,min 658e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_2cyc_1F], (instregex "^F(MAX|MIN)(NM)?v")>; 659e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_2cyc_1F], (instregex "^F(MAX|MIN)(NM)?Pv")>; 660e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_4cyc_1F], (instregex "^F(MAX|MIN)(NM)?Vv")>; 661e8d8bef9SDimitry Andric 662e8d8bef9SDimitry Andric// ASIMD FP add 663e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_5cyc_1F], (instregex "^F(ADD|ADDP|SUB)v")>; 664e8d8bef9SDimitry Andric 665e8d8bef9SDimitry Andric// ASIMD FP multiply 666e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_5cyc_1F], (instregex "^FMULX?v")>; 667e8d8bef9SDimitry Andric 668e8d8bef9SDimitry Andric 669e8d8bef9SDimitry Andric// ASIMD Miscellaneous Instructions 670e8d8bef9SDimitry Andric// ----------------------------------------------------------------------------- 671e8d8bef9SDimitry Andric 672e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^(CLS|CLZ|CNT)v")>; 673e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^(DUP|INS)v.+lane")>; 674e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^REV(16|32|64)v")>; 675e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^(UZP|ZIP)[12]v")>; 676e8d8bef9SDimitry Andric 677e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^EXTv")>; 678e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^XTNv")>; 679e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^RBITv")>; 680e8d8bef9SDimitry Andric 681e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_4cyc_1F], (instregex "^(INS|DUP)v.+gpr")>; 682e8d8bef9SDimitry Andric 683e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_3cyc_1FSU1], (instregex "^[SU]MOVv")>; 684e8d8bef9SDimitry Andric 685e8d8bef9SDimitry Andric// ASIMD table lookup, D-form 686e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_2cyc_1F], (instregex "^TB[LX]v8i8One")>; 687e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_4cyc_2F], (instregex "^TB[LX]v8i8Two")>; 688e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_6cyc_3F], (instregex "^TB[LX]v8i8Three")>; 689e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_8cyc_4F], (instregex "^TB[LX]v8i8Four")>; 690e8d8bef9SDimitry Andric// ASIMD table lookup, Q-form 691e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_2cyc_1F], (instregex "^TB[LX]v16i8One")>; 692e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_4cyc_2F], (instregex "^TB[LX]v16i8Two")>; 693e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_6cyc_3F], (instregex "^TB[LX]v16i8Three")>; 694e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_8cyc_4F], (instregex "^TB[LX]v16i8Four")>; 695e8d8bef9SDimitry Andric 696e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_2cyc_1F], (instregex "^FMOVv")>; 697e8d8bef9SDimitry Andric 698e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_3cyc_1F], (instregex "^FRINT[AIMNPXZ]v")>; 699e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_3cyc_1F], (instregex "^[SU]CVTFv")>; 700e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_3cyc_1F], (instregex "^[FU](RECP|RSQRT)(E|X)v")>; 701e8d8bef9SDimitry Andric 702e8d8bef9SDimitry Andric 703e8d8bef9SDimitry Andric// ASIMD Load Instructions 704e8d8bef9SDimitry Andric// ----------------------------------------------------------------------------- 705e8d8bef9SDimitry Andric 706e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_7cyc_1F_1LdSt], (instregex "^LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 7075f757f3fSDimitry Andricdef : InstRW<[WriteAdr, TSV110Wr_7cyc_1F_1LdSt], (instregex "^LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 708e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_7cyc_2F_1LdSt], (instregex "^LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 7095f757f3fSDimitry Andricdef : InstRW<[WriteAdr, TSV110Wr_7cyc_2F_1LdSt], (instregex "^LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 710e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_8cyc_3F_1LdSt], (instregex "^LD3Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 7115f757f3fSDimitry Andricdef : InstRW<[WriteAdr, TSV110Wr_8cyc_3F_1LdSt], (instregex "^LD3Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 712e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_8cyc_3F_2LdSt], (instregex "^LD4Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 7135f757f3fSDimitry Andricdef : InstRW<[WriteAdr, TSV110Wr_8cyc_3F_2LdSt], (instregex "^LD4Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 714e8d8bef9SDimitry Andric 715e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_7cyc_1F_1LdSt], (instregex "LD1i(8|16|32|64)$")>; 7165f757f3fSDimitry Andricdef : InstRW<[WriteAdr, TSV110Wr_7cyc_1F_1LdSt], (instregex "LD1i(8|16|32|64)_POST$")>; 717e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_7cyc_2F_1LdSt], (instregex "LD2i(8|16|32|64)$")>; 7185f757f3fSDimitry Andricdef : InstRW<[WriteAdr, TSV110Wr_7cyc_2F_1LdSt], (instregex "LD2i(8|16|32|64)_POST$")>; 719e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_8cyc_3F_1LdSt], (instregex "LD3i(8|16|32|64)$")>; 7205f757f3fSDimitry Andricdef : InstRW<[WriteAdr, TSV110Wr_8cyc_3F_1LdSt], (instregex "LD3i(8|16|32|64)_POST$")>; 721e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_8cyc_3F_2LdSt], (instregex "LD4i(8|16|32|64)$")>; 7225f757f3fSDimitry Andricdef : InstRW<[WriteAdr, TSV110Wr_8cyc_3F_2LdSt], (instregex "LD4i(8|16|32|64)_POST$")>; 723e8d8bef9SDimitry Andric 724e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_5cyc_1LdSt], (instregex "^LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 7255f757f3fSDimitry Andricdef : InstRW<[WriteAdr, TSV110Wr_5cyc_1LdSt], (instregex "^LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 726e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_5cyc_1LdSt], (instregex "^LD1Twov(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 7275f757f3fSDimitry Andricdef : InstRW<[WriteAdr, TSV110Wr_5cyc_1LdSt], (instregex "^LD1Twov(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 728e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_6cyc_3LdSt], (instregex "^LD1Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 7295f757f3fSDimitry Andricdef : InstRW<[WriteAdr, TSV110Wr_6cyc_3LdSt], (instregex "^LD1Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 730e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_6cyc_2LdSt], (instregex "^LD1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 7315f757f3fSDimitry Andricdef : InstRW<[WriteAdr, TSV110Wr_6cyc_2LdSt], (instregex "^LD1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 732e8d8bef9SDimitry Andric 733e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_7cyc_2F_1LdSt], (instregex "^LD2Twov(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 7345f757f3fSDimitry Andricdef : InstRW<[WriteAdr, TSV110Wr_7cyc_2F_1LdSt], (instregex "^LD2Twov(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 735e8d8bef9SDimitry Andric 736e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_8cyc_3F_1LdSt], (instregex "^LD3Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 7375f757f3fSDimitry Andricdef : InstRW<[WriteAdr, TSV110Wr_8cyc_3F_1LdSt], (instregex "^LD3Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 738e8d8bef9SDimitry Andric 739e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_10cyc_4F_4LdSt], (instregex "^LD4Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 7405f757f3fSDimitry Andricdef : InstRW<[WriteAdr, TSV110Wr_10cyc_4F_4LdSt], (instregex "^LD4Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 741e8d8bef9SDimitry Andric 742e8d8bef9SDimitry Andric 743e8d8bef9SDimitry Andric// ASIMD Store Instructions 744e8d8bef9SDimitry Andric// ----------------------------------------------------------------------------- 745e8d8bef9SDimitry Andric 746e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_3cyc_1F], (instregex "ST1i(8|16|32|64)$")>; 7475f757f3fSDimitry Andricdef : InstRW<[WriteAdr, TSV110Wr_3cyc_1F], (instregex "ST1i(8|16|32|64)_POST$")>; 748e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_4cyc_1F], (instregex "ST2i(8|16|32|64)$")>; 7495f757f3fSDimitry Andricdef : InstRW<[WriteAdr, TSV110Wr_4cyc_1F], (instregex "ST2i(8|16|32|64)_POST$")>; 750e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_5cyc_1F], (instregex "ST3i(8|16|32|64)$")>; 7515f757f3fSDimitry Andricdef : InstRW<[WriteAdr, TSV110Wr_5cyc_1F], (instregex "ST3i(8|16|32|64)_POST$")>; 752e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_6cyc_1F], (instregex "ST4i(8|16|32|64)$")>; 7535f757f3fSDimitry Andricdef : InstRW<[WriteAdr, TSV110Wr_6cyc_1F], (instregex "ST4i(8|16|32|64)_POST$")>; 754e8d8bef9SDimitry Andric 755e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_3cyc_1F], (instregex "^ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 7565f757f3fSDimitry Andricdef : InstRW<[WriteAdr, TSV110Wr_3cyc_1F], (instregex "^ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 757e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_4cyc_1F], (instregex "^ST1Twov(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 7585f757f3fSDimitry Andricdef : InstRW<[WriteAdr, TSV110Wr_4cyc_1F], (instregex "^ST1Twov(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 759e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_5cyc_1F], (instregex "^ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 7605f757f3fSDimitry Andricdef : InstRW<[WriteAdr, TSV110Wr_5cyc_1F], (instregex "^ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 761e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_6cyc_1F], (instregex "^ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 7625f757f3fSDimitry Andricdef : InstRW<[WriteAdr, TSV110Wr_6cyc_1F], (instregex "^ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 763e8d8bef9SDimitry Andric 764e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_4cyc_1F], (instregex "^ST2Twov(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 7655f757f3fSDimitry Andricdef : InstRW<[WriteAdr, TSV110Wr_4cyc_1F], (instregex "^ST2Twov(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 766e8d8bef9SDimitry Andric 767e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_5cyc_1F], (instregex "^ST3Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 7685f757f3fSDimitry Andricdef : InstRW<[WriteAdr, TSV110Wr_5cyc_1F], (instregex "^ST3Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 769e8d8bef9SDimitry Andric 770e8d8bef9SDimitry Andricdef : InstRW<[TSV110Wr_8cyc_1F], (instregex "^ST4Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 7715f757f3fSDimitry Andricdef : InstRW<[WriteAdr, TSV110Wr_8cyc_1F], (instregex "^ST4Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 772e8d8bef9SDimitry Andric 773e8d8bef9SDimitry Andric} // SchedModel = TSV110Model 774