1 //===- AArch64Disassembler.cpp - Disassembler for AArch64 -----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // 10 //===----------------------------------------------------------------------===// 11 12 #include "AArch64Disassembler.h" 13 #include "AArch64ExternalSymbolizer.h" 14 #include "MCTargetDesc/AArch64AddressingModes.h" 15 #include "MCTargetDesc/AArch64MCTargetDesc.h" 16 #include "TargetInfo/AArch64TargetInfo.h" 17 #include "Utils/AArch64BaseInfo.h" 18 #include "llvm-c/Disassembler.h" 19 #include "llvm/MC/MCDisassembler/MCRelocationInfo.h" 20 #include "llvm/MC/MCFixedLenDisassembler.h" 21 #include "llvm/MC/MCInst.h" 22 #include "llvm/MC/MCRegisterInfo.h" 23 #include "llvm/MC/MCSubtargetInfo.h" 24 #include "llvm/Support/Compiler.h" 25 #include "llvm/Support/Debug.h" 26 #include "llvm/Support/ErrorHandling.h" 27 #include "llvm/Support/TargetRegistry.h" 28 #include <algorithm> 29 #include <memory> 30 31 using namespace llvm; 32 33 #define DEBUG_TYPE "aarch64-disassembler" 34 35 // Pull DecodeStatus and its enum values into the global namespace. 36 using DecodeStatus = MCDisassembler::DecodeStatus; 37 38 // Forward declare these because the autogenerated code will reference them. 39 // Definitions are further down. 40 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, 41 unsigned RegNo, uint64_t Address, 42 const void *Decoder); 43 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, 44 unsigned RegNo, 45 uint64_t Address, 46 const void *Decoder); 47 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, 48 uint64_t Address, 49 const void *Decoder); 50 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, 51 uint64_t Address, 52 const void *Decoder); 53 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, 54 uint64_t Address, 55 const void *Decoder); 56 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, 57 uint64_t Address, 58 const void *Decoder); 59 static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, 60 uint64_t Address, 61 const void *Decoder); 62 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, 63 uint64_t Address, 64 const void *Decoder); 65 static DecodeStatus DecodeGPR64x8ClassRegisterClass(MCInst &Inst, 66 unsigned RegNo, 67 uint64_t Address, 68 const void *Decoder); 69 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, 70 unsigned RegNo, uint64_t Address, 71 const void *Decoder); 72 static DecodeStatus DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst, 73 unsigned RegNo, 74 uint64_t Address, 75 const void *Decoder); 76 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, 77 uint64_t Address, 78 const void *Decoder); 79 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, 80 unsigned RegNo, uint64_t Address, 81 const void *Decoder); 82 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, 83 uint64_t Address, 84 const void *Decoder); 85 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, 86 uint64_t Address, 87 const void *Decoder); 88 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, 89 uint64_t Address, 90 const void *Decoder); 91 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, 92 uint64_t Address, 93 const void *Decoder); 94 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, 95 uint64_t Address, 96 const void *Decoder); 97 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, 98 uint64_t Address, 99 const void *Decoder); 100 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, 101 uint64_t Address, 102 const void *Decoder); 103 static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo, 104 uint64_t Address, 105 const void *Decoder); 106 static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 107 uint64_t Address, 108 const void *Decoder); 109 static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, 110 uint64_t Address, 111 const void *Decoder); 112 static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, 113 uint64_t Address, 114 const void *Decoder); 115 static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, 116 uint64_t Address, 117 const void *Decoder); 118 template <unsigned NumBitsForTile> 119 static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo, 120 uint64_t Address, const void *Decoder); 121 static DecodeStatus DecodeMatrixTileListRegisterClass(MCInst &Inst, 122 unsigned RegMask, 123 uint64_t Address, 124 const void *Decoder); 125 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, 126 uint64_t Address, 127 const void *Decoder); 128 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 129 uint64_t Address, 130 const void *Decoder); 131 132 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, 133 uint64_t Address, 134 const void *Decoder); 135 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, 136 uint64_t Address, 137 const void *Decoder); 138 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, 139 uint64_t Address, const void *Decoder); 140 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, 141 uint64_t Address, const void *Decoder); 142 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, 143 uint64_t Address, const void *Decoder); 144 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, 145 uint64_t Address, const void *Decoder); 146 static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, 147 uint64_t Address, 148 const void *Decoder); 149 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, 150 uint64_t Address, 151 const void *Decoder); 152 static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, 153 uint64_t Address, 154 const void *Decoder); 155 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, 156 uint64_t Address, 157 const void *Decoder); 158 static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, 159 uint64_t Address, 160 const void *Decoder); 161 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, 162 uint64_t Address, 163 const void *Decoder); 164 static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn, 165 uint64_t Address, 166 const void *Decoder); 167 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, 168 uint64_t Address, 169 const void *Decoder); 170 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, 171 uint64_t Address, 172 const void *Decoder); 173 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, 174 uint64_t Address, 175 const void *Decoder); 176 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, 177 uint64_t Address, 178 const void *Decoder); 179 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, 180 uint64_t Address, const void *Decoder); 181 static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn, 182 uint64_t Address, const void *Decoder); 183 static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, 184 uint64_t Address, 185 const void *Decoder); 186 static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn, 187 uint64_t Address, 188 const void *Decoder); 189 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, 190 uint64_t Address, const void *Decoder); 191 192 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, 193 uint64_t Address, 194 const void *Decoder); 195 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, 196 uint64_t Addr, const void *Decoder); 197 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, 198 uint64_t Addr, 199 const void *Decoder); 200 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, 201 uint64_t Addr, const void *Decoder); 202 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, 203 uint64_t Addr, 204 const void *Decoder); 205 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, 206 uint64_t Addr, const void *Decoder); 207 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, 208 uint64_t Addr, 209 const void *Decoder); 210 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, 211 uint64_t Addr, const void *Decoder); 212 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, 213 uint64_t Addr, const void *Decoder); 214 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, 215 uint64_t Addr, const void *Decoder); 216 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, 217 uint64_t Addr, const void *Decoder); 218 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, 219 uint64_t Addr, const void *Decoder); 220 static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, 221 unsigned RegNo, 222 uint64_t Addr, 223 const void *Decoder); 224 static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, 225 unsigned RegNo, 226 uint64_t Addr, 227 const void *Decoder); 228 static DecodeStatus DecodeSVELogicalImmInstruction(llvm::MCInst &Inst, 229 uint32_t insn, 230 uint64_t Address, 231 const void *Decoder); 232 template<int Bits> 233 static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm, 234 uint64_t Address, const void *Decoder); 235 template <int ElementWidth> 236 static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, 237 uint64_t Addr, const void *Decoder); 238 static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, 239 uint64_t Addr, const void *Decoder); 240 static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address, 241 const void *Decoder); 242 243 static bool Check(DecodeStatus &Out, DecodeStatus In) { 244 switch (In) { 245 case MCDisassembler::Success: 246 // Out stays the same. 247 return true; 248 case MCDisassembler::SoftFail: 249 Out = In; 250 return true; 251 case MCDisassembler::Fail: 252 Out = In; 253 return false; 254 } 255 llvm_unreachable("Invalid DecodeStatus!"); 256 } 257 258 #include "AArch64GenDisassemblerTables.inc" 259 #include "AArch64GenInstrInfo.inc" 260 261 #define Success MCDisassembler::Success 262 #define Fail MCDisassembler::Fail 263 #define SoftFail MCDisassembler::SoftFail 264 265 static MCDisassembler *createAArch64Disassembler(const Target &T, 266 const MCSubtargetInfo &STI, 267 MCContext &Ctx) { 268 return new AArch64Disassembler(STI, Ctx); 269 } 270 271 DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size, 272 ArrayRef<uint8_t> Bytes, 273 uint64_t Address, 274 raw_ostream &CS) const { 275 CommentStream = &CS; 276 277 Size = 0; 278 // We want to read exactly 4 bytes of data. 279 if (Bytes.size() < 4) 280 return Fail; 281 Size = 4; 282 283 // Encoded as a small-endian 32-bit word in the stream. 284 uint32_t Insn = 285 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 286 287 const uint8_t *Tables[] = {DecoderTable32, DecoderTableFallback32}; 288 289 for (auto Table : Tables) { 290 DecodeStatus Result = 291 decodeInstruction(Table, MI, Insn, Address, this, STI); 292 293 switch (MI.getOpcode()) { 294 default: 295 break; 296 // For Scalable Matrix Extension (SME) instructions that have an implicit 297 // operand for the accumulator (ZA) which isn't encoded, manually insert 298 // operand. 299 case AArch64::LDR_ZA: 300 case AArch64::STR_ZA: { 301 MI.insert(MI.begin(), MCOperand::createReg(AArch64::ZA)); 302 // Spill and fill instructions have a single immediate used for both the 303 // vector select offset and optional memory offset. Replicate the decoded 304 // immediate. 305 const MCOperand &Imm4Op = MI.getOperand(2); 306 assert(Imm4Op.isImm() && "Unexpected operand type!"); 307 MI.addOperand(Imm4Op); 308 break; 309 } 310 case AArch64::LD1_MXIPXX_H_B: 311 case AArch64::LD1_MXIPXX_V_B: 312 case AArch64::ST1_MXIPXX_H_B: 313 case AArch64::ST1_MXIPXX_V_B: 314 case AArch64::INSERT_MXIPZ_H_B: 315 case AArch64::INSERT_MXIPZ_V_B: 316 // e.g. 317 // MOVA ZA0<HV>.B[<Ws>, <imm>], <Pg>/M, <Zn>.B 318 // ^ insert implicit 8-bit element tile 319 MI.insert(MI.begin(), MCOperand::createReg(AArch64::ZAB0)); 320 break; 321 case AArch64::EXTRACT_ZPMXI_H_B: 322 case AArch64::EXTRACT_ZPMXI_V_B: 323 // MOVA <Zd>.B, <Pg>/M, ZA0<HV>.B[<Ws>, <imm>] 324 // ^ insert implicit 8-bit element tile 325 MI.insert(MI.begin()+2, MCOperand::createReg(AArch64::ZAB0)); 326 break; 327 } 328 329 if (Result != MCDisassembler::Fail) 330 return Result; 331 } 332 333 return MCDisassembler::Fail; 334 } 335 336 static MCSymbolizer * 337 createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo, 338 LLVMSymbolLookupCallback SymbolLookUp, 339 void *DisInfo, MCContext *Ctx, 340 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 341 return new AArch64ExternalSymbolizer(*Ctx, std::move(RelInfo), GetOpInfo, 342 SymbolLookUp, DisInfo); 343 } 344 345 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Disassembler() { 346 TargetRegistry::RegisterMCDisassembler(getTheAArch64leTarget(), 347 createAArch64Disassembler); 348 TargetRegistry::RegisterMCDisassembler(getTheAArch64beTarget(), 349 createAArch64Disassembler); 350 TargetRegistry::RegisterMCSymbolizer(getTheAArch64leTarget(), 351 createAArch64ExternalSymbolizer); 352 TargetRegistry::RegisterMCSymbolizer(getTheAArch64beTarget(), 353 createAArch64ExternalSymbolizer); 354 TargetRegistry::RegisterMCDisassembler(getTheAArch64_32Target(), 355 createAArch64Disassembler); 356 TargetRegistry::RegisterMCSymbolizer(getTheAArch64_32Target(), 357 createAArch64ExternalSymbolizer); 358 359 TargetRegistry::RegisterMCDisassembler(getTheARM64Target(), 360 createAArch64Disassembler); 361 TargetRegistry::RegisterMCSymbolizer(getTheARM64Target(), 362 createAArch64ExternalSymbolizer); 363 TargetRegistry::RegisterMCDisassembler(getTheARM64_32Target(), 364 createAArch64Disassembler); 365 TargetRegistry::RegisterMCSymbolizer(getTheARM64_32Target(), 366 createAArch64ExternalSymbolizer); 367 } 368 369 static const unsigned FPR128DecoderTable[] = { 370 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, 371 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, 372 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, 373 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, 374 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, 375 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, 376 AArch64::Q30, AArch64::Q31 377 }; 378 379 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo, 380 uint64_t Addr, 381 const void *Decoder) { 382 if (RegNo > 31) 383 return Fail; 384 385 unsigned Register = FPR128DecoderTable[RegNo]; 386 Inst.addOperand(MCOperand::createReg(Register)); 387 return Success; 388 } 389 390 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo, 391 uint64_t Addr, 392 const void *Decoder) { 393 if (RegNo > 15) 394 return Fail; 395 return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder); 396 } 397 398 static const unsigned FPR64DecoderTable[] = { 399 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, 400 AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9, 401 AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, 402 AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19, 403 AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24, 404 AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29, 405 AArch64::D30, AArch64::D31 406 }; 407 408 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, 409 uint64_t Addr, 410 const void *Decoder) { 411 if (RegNo > 31) 412 return Fail; 413 414 unsigned Register = FPR64DecoderTable[RegNo]; 415 Inst.addOperand(MCOperand::createReg(Register)); 416 return Success; 417 } 418 419 static const unsigned FPR32DecoderTable[] = { 420 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, 421 AArch64::S5, AArch64::S6, AArch64::S7, AArch64::S8, AArch64::S9, 422 AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14, 423 AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19, 424 AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24, 425 AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29, 426 AArch64::S30, AArch64::S31 427 }; 428 429 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, 430 uint64_t Addr, 431 const void *Decoder) { 432 if (RegNo > 31) 433 return Fail; 434 435 unsigned Register = FPR32DecoderTable[RegNo]; 436 Inst.addOperand(MCOperand::createReg(Register)); 437 return Success; 438 } 439 440 static const unsigned FPR16DecoderTable[] = { 441 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, 442 AArch64::H5, AArch64::H6, AArch64::H7, AArch64::H8, AArch64::H9, 443 AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14, 444 AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19, 445 AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24, 446 AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29, 447 AArch64::H30, AArch64::H31 448 }; 449 450 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, 451 uint64_t Addr, 452 const void *Decoder) { 453 if (RegNo > 31) 454 return Fail; 455 456 unsigned Register = FPR16DecoderTable[RegNo]; 457 Inst.addOperand(MCOperand::createReg(Register)); 458 return Success; 459 } 460 461 static const unsigned FPR8DecoderTable[] = { 462 AArch64::B0, AArch64::B1, AArch64::B2, AArch64::B3, AArch64::B4, 463 AArch64::B5, AArch64::B6, AArch64::B7, AArch64::B8, AArch64::B9, 464 AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14, 465 AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19, 466 AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24, 467 AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29, 468 AArch64::B30, AArch64::B31 469 }; 470 471 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, 472 uint64_t Addr, 473 const void *Decoder) { 474 if (RegNo > 31) 475 return Fail; 476 477 unsigned Register = FPR8DecoderTable[RegNo]; 478 Inst.addOperand(MCOperand::createReg(Register)); 479 return Success; 480 } 481 482 static const unsigned GPR64DecoderTable[] = { 483 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, 484 AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, 485 AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, 486 AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, 487 AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, 488 AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, 489 AArch64::LR, AArch64::XZR 490 }; 491 492 static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, 493 uint64_t Addr, 494 const void *Decoder) { 495 if (RegNo > 30) 496 return Fail; 497 498 unsigned Register = GPR64DecoderTable[RegNo]; 499 Inst.addOperand(MCOperand::createReg(Register)); 500 return Success; 501 } 502 503 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, 504 uint64_t Addr, 505 const void *Decoder) { 506 if (RegNo > 31) 507 return Fail; 508 509 unsigned Register = GPR64DecoderTable[RegNo]; 510 Inst.addOperand(MCOperand::createReg(Register)); 511 return Success; 512 } 513 514 static const unsigned GPR64x8DecoderTable[] = { 515 AArch64::X0_X1_X2_X3_X4_X5_X6_X7, 516 AArch64::X2_X3_X4_X5_X6_X7_X8_X9, 517 AArch64::X4_X5_X6_X7_X8_X9_X10_X11, 518 AArch64::X6_X7_X8_X9_X10_X11_X12_X13, 519 AArch64::X8_X9_X10_X11_X12_X13_X14_X15, 520 AArch64::X10_X11_X12_X13_X14_X15_X16_X17, 521 AArch64::X12_X13_X14_X15_X16_X17_X18_X19, 522 AArch64::X14_X15_X16_X17_X18_X19_X20_X21, 523 AArch64::X16_X17_X18_X19_X20_X21_X22_X23, 524 AArch64::X18_X19_X20_X21_X22_X23_X24_X25, 525 AArch64::X20_X21_X22_X23_X24_X25_X26_X27, 526 AArch64::X22_X23_X24_X25_X26_X27_X28_FP, 527 }; 528 529 static DecodeStatus DecodeGPR64x8ClassRegisterClass(MCInst &Inst, 530 unsigned RegNo, 531 uint64_t Address, 532 const void *Decoder) { 533 if (RegNo > 22) 534 return Fail; 535 if (RegNo & 1) 536 return Fail; 537 538 unsigned Register = GPR64x8DecoderTable[RegNo >> 1]; 539 Inst.addOperand(MCOperand::createReg(Register)); 540 return Success; 541 } 542 543 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo, 544 uint64_t Addr, 545 const void *Decoder) { 546 if (RegNo > 31) 547 return Fail; 548 unsigned Register = GPR64DecoderTable[RegNo]; 549 if (Register == AArch64::XZR) 550 Register = AArch64::SP; 551 Inst.addOperand(MCOperand::createReg(Register)); 552 return Success; 553 } 554 555 static const unsigned MatrixIndexGPR32_12_15DecoderTable[] = { 556 AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15 557 }; 558 559 static DecodeStatus DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst, 560 unsigned RegNo, 561 uint64_t Addr, 562 const void *Decoder) { 563 if (RegNo > 3) 564 return Fail; 565 566 unsigned Register = MatrixIndexGPR32_12_15DecoderTable[RegNo]; 567 Inst.addOperand(MCOperand::createReg(Register)); 568 return Success; 569 } 570 571 static const unsigned GPR32DecoderTable[] = { 572 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, 573 AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, 574 AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, 575 AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, 576 AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, 577 AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, 578 AArch64::W30, AArch64::WZR 579 }; 580 581 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, 582 uint64_t Addr, 583 const void *Decoder) { 584 if (RegNo > 31) 585 return Fail; 586 587 unsigned Register = GPR32DecoderTable[RegNo]; 588 Inst.addOperand(MCOperand::createReg(Register)); 589 return Success; 590 } 591 592 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo, 593 uint64_t Addr, 594 const void *Decoder) { 595 if (RegNo > 31) 596 return Fail; 597 598 unsigned Register = GPR32DecoderTable[RegNo]; 599 if (Register == AArch64::WZR) 600 Register = AArch64::WSP; 601 Inst.addOperand(MCOperand::createReg(Register)); 602 return Success; 603 } 604 static const unsigned ZPRDecoderTable[] = { 605 AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, 606 AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7, 607 AArch64::Z8, AArch64::Z9, AArch64::Z10, AArch64::Z11, 608 AArch64::Z12, AArch64::Z13, AArch64::Z14, AArch64::Z15, 609 AArch64::Z16, AArch64::Z17, AArch64::Z18, AArch64::Z19, 610 AArch64::Z20, AArch64::Z21, AArch64::Z22, AArch64::Z23, 611 AArch64::Z24, AArch64::Z25, AArch64::Z26, AArch64::Z27, 612 AArch64::Z28, AArch64::Z29, AArch64::Z30, AArch64::Z31 613 }; 614 615 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, 616 uint64_t Address, 617 const void* Decoder) { 618 if (RegNo > 31) 619 return Fail; 620 621 unsigned Register = ZPRDecoderTable[RegNo]; 622 Inst.addOperand(MCOperand::createReg(Register)); 623 return Success; 624 } 625 626 static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo, 627 uint64_t Address, 628 const void *Decoder) { 629 if (RegNo > 15) 630 return Fail; 631 return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder); 632 } 633 634 static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 635 uint64_t Address, 636 const void *Decoder) { 637 if (RegNo > 7) 638 return Fail; 639 return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder); 640 } 641 642 static const unsigned ZZDecoderTable[] = { 643 AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, 644 AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8, 645 AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12, 646 AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15, AArch64::Z15_Z16, 647 AArch64::Z16_Z17, AArch64::Z17_Z18, AArch64::Z18_Z19, AArch64::Z19_Z20, 648 AArch64::Z20_Z21, AArch64::Z21_Z22, AArch64::Z22_Z23, AArch64::Z23_Z24, 649 AArch64::Z24_Z25, AArch64::Z25_Z26, AArch64::Z26_Z27, AArch64::Z27_Z28, 650 AArch64::Z28_Z29, AArch64::Z29_Z30, AArch64::Z30_Z31, AArch64::Z31_Z0 651 }; 652 653 static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, 654 uint64_t Address, 655 const void* Decoder) { 656 if (RegNo > 31) 657 return Fail; 658 unsigned Register = ZZDecoderTable[RegNo]; 659 Inst.addOperand(MCOperand::createReg(Register)); 660 return Success; 661 } 662 663 static const unsigned ZZZDecoderTable[] = { 664 AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, 665 AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, 666 AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, 667 AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, 668 AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16, 669 AArch64::Z15_Z16_Z17, AArch64::Z16_Z17_Z18, AArch64::Z17_Z18_Z19, 670 AArch64::Z18_Z19_Z20, AArch64::Z19_Z20_Z21, AArch64::Z20_Z21_Z22, 671 AArch64::Z21_Z22_Z23, AArch64::Z22_Z23_Z24, AArch64::Z23_Z24_Z25, 672 AArch64::Z24_Z25_Z26, AArch64::Z25_Z26_Z27, AArch64::Z26_Z27_Z28, 673 AArch64::Z27_Z28_Z29, AArch64::Z28_Z29_Z30, AArch64::Z29_Z30_Z31, 674 AArch64::Z30_Z31_Z0, AArch64::Z31_Z0_Z1 675 }; 676 677 static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, 678 uint64_t Address, 679 const void* Decoder) { 680 if (RegNo > 31) 681 return Fail; 682 unsigned Register = ZZZDecoderTable[RegNo]; 683 Inst.addOperand(MCOperand::createReg(Register)); 684 return Success; 685 } 686 687 static const unsigned ZZZZDecoderTable[] = { 688 AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, 689 AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, 690 AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, 691 AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, 692 AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z14_Z15_Z16_Z17, 693 AArch64::Z15_Z16_Z17_Z18, AArch64::Z16_Z17_Z18_Z19, AArch64::Z17_Z18_Z19_Z20, 694 AArch64::Z18_Z19_Z20_Z21, AArch64::Z19_Z20_Z21_Z22, AArch64::Z20_Z21_Z22_Z23, 695 AArch64::Z21_Z22_Z23_Z24, AArch64::Z22_Z23_Z24_Z25, AArch64::Z23_Z24_Z25_Z26, 696 AArch64::Z24_Z25_Z26_Z27, AArch64::Z25_Z26_Z27_Z28, AArch64::Z26_Z27_Z28_Z29, 697 AArch64::Z27_Z28_Z29_Z30, AArch64::Z28_Z29_Z30_Z31, AArch64::Z29_Z30_Z31_Z0, 698 AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2 699 }; 700 701 static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, 702 uint64_t Address, 703 const void* Decoder) { 704 if (RegNo > 31) 705 return Fail; 706 unsigned Register = ZZZZDecoderTable[RegNo]; 707 Inst.addOperand(MCOperand::createReg(Register)); 708 return Success; 709 } 710 711 static DecodeStatus DecodeMatrixTileListRegisterClass(MCInst &Inst, 712 unsigned RegMask, 713 uint64_t Address, 714 const void *Decoder) { 715 if (RegMask > 0xFF) 716 return Fail; 717 Inst.addOperand(MCOperand::createImm(RegMask)); 718 return Success; 719 } 720 721 static const SmallVector<SmallVector<unsigned, 16>, 5> 722 MatrixZATileDecoderTable = { 723 {AArch64::ZAB0}, 724 {AArch64::ZAH0, AArch64::ZAH1}, 725 {AArch64::ZAS0, AArch64::ZAS1, AArch64::ZAS2, AArch64::ZAS3}, 726 {AArch64::ZAD0, AArch64::ZAD1, AArch64::ZAD2, AArch64::ZAD3, 727 AArch64::ZAD4, AArch64::ZAD5, AArch64::ZAD6, AArch64::ZAD7}, 728 {AArch64::ZAQ0, AArch64::ZAQ1, AArch64::ZAQ2, AArch64::ZAQ3, 729 AArch64::ZAQ4, AArch64::ZAQ5, AArch64::ZAQ6, AArch64::ZAQ7, 730 AArch64::ZAQ8, AArch64::ZAQ9, AArch64::ZAQ10, AArch64::ZAQ11, 731 AArch64::ZAQ12, AArch64::ZAQ13, AArch64::ZAQ14, AArch64::ZAQ15}}; 732 733 template <unsigned NumBitsForTile> 734 static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo, 735 uint64_t Address, const void *Decoder) { 736 unsigned LastReg = (1 << NumBitsForTile) - 1; 737 if (RegNo > LastReg) 738 return Fail; 739 Inst.addOperand( 740 MCOperand::createReg(MatrixZATileDecoderTable[NumBitsForTile][RegNo])); 741 return Success; 742 } 743 744 static const unsigned PPRDecoderTable[] = { 745 AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, 746 AArch64::P4, AArch64::P5, AArch64::P6, AArch64::P7, 747 AArch64::P8, AArch64::P9, AArch64::P10, AArch64::P11, 748 AArch64::P12, AArch64::P13, AArch64::P14, AArch64::P15 749 }; 750 751 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, 752 uint64_t Addr, const void *Decoder) { 753 if (RegNo > 15) 754 return Fail; 755 756 unsigned Register = PPRDecoderTable[RegNo]; 757 Inst.addOperand(MCOperand::createReg(Register)); 758 return Success; 759 } 760 761 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 762 uint64_t Addr, 763 const void* Decoder) { 764 if (RegNo > 7) 765 return Fail; 766 767 // Just reuse the PPR decode table 768 return DecodePPRRegisterClass(Inst, RegNo, Addr, Decoder); 769 } 770 771 static const unsigned VectorDecoderTable[] = { 772 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, 773 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, 774 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, 775 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, 776 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, 777 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, 778 AArch64::Q30, AArch64::Q31 779 }; 780 781 static DecodeStatus DecodeVectorRegisterClass(MCInst &Inst, unsigned RegNo, 782 uint64_t Addr, 783 const void *Decoder) { 784 if (RegNo > 31) 785 return Fail; 786 787 unsigned Register = VectorDecoderTable[RegNo]; 788 Inst.addOperand(MCOperand::createReg(Register)); 789 return Success; 790 } 791 792 static const unsigned QQDecoderTable[] = { 793 AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, 794 AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, 795 AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, 796 AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16, 797 AArch64::Q16_Q17, AArch64::Q17_Q18, AArch64::Q18_Q19, AArch64::Q19_Q20, 798 AArch64::Q20_Q21, AArch64::Q21_Q22, AArch64::Q22_Q23, AArch64::Q23_Q24, 799 AArch64::Q24_Q25, AArch64::Q25_Q26, AArch64::Q26_Q27, AArch64::Q27_Q28, 800 AArch64::Q28_Q29, AArch64::Q29_Q30, AArch64::Q30_Q31, AArch64::Q31_Q0 801 }; 802 803 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, 804 uint64_t Addr, const void *Decoder) { 805 if (RegNo > 31) 806 return Fail; 807 unsigned Register = QQDecoderTable[RegNo]; 808 Inst.addOperand(MCOperand::createReg(Register)); 809 return Success; 810 } 811 812 static const unsigned QQQDecoderTable[] = { 813 AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, 814 AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, 815 AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, 816 AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, 817 AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, 818 AArch64::Q15_Q16_Q17, AArch64::Q16_Q17_Q18, AArch64::Q17_Q18_Q19, 819 AArch64::Q18_Q19_Q20, AArch64::Q19_Q20_Q21, AArch64::Q20_Q21_Q22, 820 AArch64::Q21_Q22_Q23, AArch64::Q22_Q23_Q24, AArch64::Q23_Q24_Q25, 821 AArch64::Q24_Q25_Q26, AArch64::Q25_Q26_Q27, AArch64::Q26_Q27_Q28, 822 AArch64::Q27_Q28_Q29, AArch64::Q28_Q29_Q30, AArch64::Q29_Q30_Q31, 823 AArch64::Q30_Q31_Q0, AArch64::Q31_Q0_Q1 824 }; 825 826 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, 827 uint64_t Addr, const void *Decoder) { 828 if (RegNo > 31) 829 return Fail; 830 unsigned Register = QQQDecoderTable[RegNo]; 831 Inst.addOperand(MCOperand::createReg(Register)); 832 return Success; 833 } 834 835 static const unsigned QQQQDecoderTable[] = { 836 AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, 837 AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, 838 AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, 839 AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, 840 AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, 841 AArch64::Q15_Q16_Q17_Q18, AArch64::Q16_Q17_Q18_Q19, AArch64::Q17_Q18_Q19_Q20, 842 AArch64::Q18_Q19_Q20_Q21, AArch64::Q19_Q20_Q21_Q22, AArch64::Q20_Q21_Q22_Q23, 843 AArch64::Q21_Q22_Q23_Q24, AArch64::Q22_Q23_Q24_Q25, AArch64::Q23_Q24_Q25_Q26, 844 AArch64::Q24_Q25_Q26_Q27, AArch64::Q25_Q26_Q27_Q28, AArch64::Q26_Q27_Q28_Q29, 845 AArch64::Q27_Q28_Q29_Q30, AArch64::Q28_Q29_Q30_Q31, AArch64::Q29_Q30_Q31_Q0, 846 AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2 847 }; 848 849 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, 850 uint64_t Addr, 851 const void *Decoder) { 852 if (RegNo > 31) 853 return Fail; 854 unsigned Register = QQQQDecoderTable[RegNo]; 855 Inst.addOperand(MCOperand::createReg(Register)); 856 return Success; 857 } 858 859 static const unsigned DDDecoderTable[] = { 860 AArch64::D0_D1, AArch64::D1_D2, AArch64::D2_D3, AArch64::D3_D4, 861 AArch64::D4_D5, AArch64::D5_D6, AArch64::D6_D7, AArch64::D7_D8, 862 AArch64::D8_D9, AArch64::D9_D10, AArch64::D10_D11, AArch64::D11_D12, 863 AArch64::D12_D13, AArch64::D13_D14, AArch64::D14_D15, AArch64::D15_D16, 864 AArch64::D16_D17, AArch64::D17_D18, AArch64::D18_D19, AArch64::D19_D20, 865 AArch64::D20_D21, AArch64::D21_D22, AArch64::D22_D23, AArch64::D23_D24, 866 AArch64::D24_D25, AArch64::D25_D26, AArch64::D26_D27, AArch64::D27_D28, 867 AArch64::D28_D29, AArch64::D29_D30, AArch64::D30_D31, AArch64::D31_D0 868 }; 869 870 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, 871 uint64_t Addr, const void *Decoder) { 872 if (RegNo > 31) 873 return Fail; 874 unsigned Register = DDDecoderTable[RegNo]; 875 Inst.addOperand(MCOperand::createReg(Register)); 876 return Success; 877 } 878 879 static const unsigned DDDDecoderTable[] = { 880 AArch64::D0_D1_D2, AArch64::D1_D2_D3, AArch64::D2_D3_D4, 881 AArch64::D3_D4_D5, AArch64::D4_D5_D6, AArch64::D5_D6_D7, 882 AArch64::D6_D7_D8, AArch64::D7_D8_D9, AArch64::D8_D9_D10, 883 AArch64::D9_D10_D11, AArch64::D10_D11_D12, AArch64::D11_D12_D13, 884 AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D14_D15_D16, 885 AArch64::D15_D16_D17, AArch64::D16_D17_D18, AArch64::D17_D18_D19, 886 AArch64::D18_D19_D20, AArch64::D19_D20_D21, AArch64::D20_D21_D22, 887 AArch64::D21_D22_D23, AArch64::D22_D23_D24, AArch64::D23_D24_D25, 888 AArch64::D24_D25_D26, AArch64::D25_D26_D27, AArch64::D26_D27_D28, 889 AArch64::D27_D28_D29, AArch64::D28_D29_D30, AArch64::D29_D30_D31, 890 AArch64::D30_D31_D0, AArch64::D31_D0_D1 891 }; 892 893 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, 894 uint64_t Addr, const void *Decoder) { 895 if (RegNo > 31) 896 return Fail; 897 unsigned Register = DDDDecoderTable[RegNo]; 898 Inst.addOperand(MCOperand::createReg(Register)); 899 return Success; 900 } 901 902 static const unsigned DDDDDecoderTable[] = { 903 AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5, 904 AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8, 905 AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11, 906 AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14, 907 AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D14_D15_D16_D17, 908 AArch64::D15_D16_D17_D18, AArch64::D16_D17_D18_D19, AArch64::D17_D18_D19_D20, 909 AArch64::D18_D19_D20_D21, AArch64::D19_D20_D21_D22, AArch64::D20_D21_D22_D23, 910 AArch64::D21_D22_D23_D24, AArch64::D22_D23_D24_D25, AArch64::D23_D24_D25_D26, 911 AArch64::D24_D25_D26_D27, AArch64::D25_D26_D27_D28, AArch64::D26_D27_D28_D29, 912 AArch64::D27_D28_D29_D30, AArch64::D28_D29_D30_D31, AArch64::D29_D30_D31_D0, 913 AArch64::D30_D31_D0_D1, AArch64::D31_D0_D1_D2 914 }; 915 916 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, 917 uint64_t Addr, 918 const void *Decoder) { 919 if (RegNo > 31) 920 return Fail; 921 unsigned Register = DDDDDecoderTable[RegNo]; 922 Inst.addOperand(MCOperand::createReg(Register)); 923 return Success; 924 } 925 926 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, 927 uint64_t Addr, 928 const void *Decoder) { 929 // scale{5} is asserted as 1 in tblgen. 930 Imm |= 0x20; 931 Inst.addOperand(MCOperand::createImm(64 - Imm)); 932 return Success; 933 } 934 935 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, 936 uint64_t Addr, 937 const void *Decoder) { 938 Inst.addOperand(MCOperand::createImm(64 - Imm)); 939 return Success; 940 } 941 942 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, 943 uint64_t Addr, const void *Decoder) { 944 int64_t ImmVal = Imm; 945 const AArch64Disassembler *Dis = 946 static_cast<const AArch64Disassembler *>(Decoder); 947 948 // Sign-extend 19-bit immediate. 949 if (ImmVal & (1 << (19 - 1))) 950 ImmVal |= ~((1LL << 19) - 1); 951 952 if (!Dis->tryAddingSymbolicOperand(Inst, ImmVal * 4, Addr, 953 Inst.getOpcode() != AArch64::LDRXl, 0, 4)) 954 Inst.addOperand(MCOperand::createImm(ImmVal)); 955 return Success; 956 } 957 958 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, 959 uint64_t Address, const void *Decoder) { 960 Inst.addOperand(MCOperand::createImm((Imm >> 1) & 1)); 961 Inst.addOperand(MCOperand::createImm(Imm & 1)); 962 return Success; 963 } 964 965 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, 966 uint64_t Address, 967 const void *Decoder) { 968 Inst.addOperand(MCOperand::createImm(Imm)); 969 970 // Every system register in the encoding space is valid with the syntax 971 // S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds. 972 return Success; 973 } 974 975 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, 976 uint64_t Address, 977 const void *Decoder) { 978 Inst.addOperand(MCOperand::createImm(Imm)); 979 980 return Success; 981 } 982 983 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, 984 uint64_t Address, 985 const void *Decoder) { 986 // This decoder exists to add the dummy Lane operand to the MCInst, which must 987 // be 1 in assembly but has no other real manifestation. 988 unsigned Rd = fieldFromInstruction(Insn, 0, 5); 989 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 990 unsigned IsToVec = fieldFromInstruction(Insn, 16, 1); 991 992 if (IsToVec) { 993 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder); 994 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder); 995 } else { 996 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder); 997 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder); 998 } 999 1000 // Add the lane 1001 Inst.addOperand(MCOperand::createImm(1)); 1002 1003 return Success; 1004 } 1005 1006 static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm, 1007 unsigned Add) { 1008 Inst.addOperand(MCOperand::createImm(Add - Imm)); 1009 return Success; 1010 } 1011 1012 static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm, 1013 unsigned Add) { 1014 Inst.addOperand(MCOperand::createImm((Imm + Add) & (Add - 1))); 1015 return Success; 1016 } 1017 1018 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, 1019 uint64_t Addr, const void *Decoder) { 1020 return DecodeVecShiftRImm(Inst, Imm, 64); 1021 } 1022 1023 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, 1024 uint64_t Addr, 1025 const void *Decoder) { 1026 return DecodeVecShiftRImm(Inst, Imm | 0x20, 64); 1027 } 1028 1029 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, 1030 uint64_t Addr, const void *Decoder) { 1031 return DecodeVecShiftRImm(Inst, Imm, 32); 1032 } 1033 1034 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, 1035 uint64_t Addr, 1036 const void *Decoder) { 1037 return DecodeVecShiftRImm(Inst, Imm | 0x10, 32); 1038 } 1039 1040 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, 1041 uint64_t Addr, const void *Decoder) { 1042 return DecodeVecShiftRImm(Inst, Imm, 16); 1043 } 1044 1045 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, 1046 uint64_t Addr, 1047 const void *Decoder) { 1048 return DecodeVecShiftRImm(Inst, Imm | 0x8, 16); 1049 } 1050 1051 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, 1052 uint64_t Addr, const void *Decoder) { 1053 return DecodeVecShiftRImm(Inst, Imm, 8); 1054 } 1055 1056 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, 1057 uint64_t Addr, const void *Decoder) { 1058 return DecodeVecShiftLImm(Inst, Imm, 64); 1059 } 1060 1061 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, 1062 uint64_t Addr, const void *Decoder) { 1063 return DecodeVecShiftLImm(Inst, Imm, 32); 1064 } 1065 1066 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, 1067 uint64_t Addr, const void *Decoder) { 1068 return DecodeVecShiftLImm(Inst, Imm, 16); 1069 } 1070 1071 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, 1072 uint64_t Addr, const void *Decoder) { 1073 return DecodeVecShiftLImm(Inst, Imm, 8); 1074 } 1075 1076 static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, 1077 uint64_t Addr, 1078 const void *Decoder) { 1079 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1080 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1081 unsigned Rm = fieldFromInstruction(insn, 16, 5); 1082 unsigned shiftHi = fieldFromInstruction(insn, 22, 2); 1083 unsigned shiftLo = fieldFromInstruction(insn, 10, 6); 1084 unsigned shift = (shiftHi << 6) | shiftLo; 1085 switch (Inst.getOpcode()) { 1086 default: 1087 return Fail; 1088 case AArch64::ADDWrs: 1089 case AArch64::ADDSWrs: 1090 case AArch64::SUBWrs: 1091 case AArch64::SUBSWrs: 1092 // if shift == '11' then ReservedValue() 1093 if (shiftHi == 0x3) 1094 return Fail; 1095 LLVM_FALLTHROUGH; 1096 case AArch64::ANDWrs: 1097 case AArch64::ANDSWrs: 1098 case AArch64::BICWrs: 1099 case AArch64::BICSWrs: 1100 case AArch64::ORRWrs: 1101 case AArch64::ORNWrs: 1102 case AArch64::EORWrs: 1103 case AArch64::EONWrs: { 1104 // if sf == '0' and imm6<5> == '1' then ReservedValue() 1105 if (shiftLo >> 5 == 1) 1106 return Fail; 1107 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1108 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); 1109 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1110 break; 1111 } 1112 case AArch64::ADDXrs: 1113 case AArch64::ADDSXrs: 1114 case AArch64::SUBXrs: 1115 case AArch64::SUBSXrs: 1116 // if shift == '11' then ReservedValue() 1117 if (shiftHi == 0x3) 1118 return Fail; 1119 LLVM_FALLTHROUGH; 1120 case AArch64::ANDXrs: 1121 case AArch64::ANDSXrs: 1122 case AArch64::BICXrs: 1123 case AArch64::BICSXrs: 1124 case AArch64::ORRXrs: 1125 case AArch64::ORNXrs: 1126 case AArch64::EORXrs: 1127 case AArch64::EONXrs: 1128 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1129 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); 1130 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1131 break; 1132 } 1133 1134 Inst.addOperand(MCOperand::createImm(shift)); 1135 return Success; 1136 } 1137 1138 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, 1139 uint64_t Addr, 1140 const void *Decoder) { 1141 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1142 unsigned imm = fieldFromInstruction(insn, 5, 16); 1143 unsigned shift = fieldFromInstruction(insn, 21, 2); 1144 shift <<= 4; 1145 switch (Inst.getOpcode()) { 1146 default: 1147 return Fail; 1148 case AArch64::MOVZWi: 1149 case AArch64::MOVNWi: 1150 case AArch64::MOVKWi: 1151 if (shift & (1U << 5)) 1152 return Fail; 1153 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1154 break; 1155 case AArch64::MOVZXi: 1156 case AArch64::MOVNXi: 1157 case AArch64::MOVKXi: 1158 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1159 break; 1160 } 1161 1162 if (Inst.getOpcode() == AArch64::MOVKWi || 1163 Inst.getOpcode() == AArch64::MOVKXi) 1164 Inst.addOperand(Inst.getOperand(0)); 1165 1166 Inst.addOperand(MCOperand::createImm(imm)); 1167 Inst.addOperand(MCOperand::createImm(shift)); 1168 return Success; 1169 } 1170 1171 static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, 1172 uint64_t Addr, 1173 const void *Decoder) { 1174 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1175 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1176 unsigned offset = fieldFromInstruction(insn, 10, 12); 1177 const AArch64Disassembler *Dis = 1178 static_cast<const AArch64Disassembler *>(Decoder); 1179 1180 switch (Inst.getOpcode()) { 1181 default: 1182 return Fail; 1183 case AArch64::PRFMui: 1184 // Rt is an immediate in prefetch. 1185 Inst.addOperand(MCOperand::createImm(Rt)); 1186 break; 1187 case AArch64::STRBBui: 1188 case AArch64::LDRBBui: 1189 case AArch64::LDRSBWui: 1190 case AArch64::STRHHui: 1191 case AArch64::LDRHHui: 1192 case AArch64::LDRSHWui: 1193 case AArch64::STRWui: 1194 case AArch64::LDRWui: 1195 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1196 break; 1197 case AArch64::LDRSBXui: 1198 case AArch64::LDRSHXui: 1199 case AArch64::LDRSWui: 1200 case AArch64::STRXui: 1201 case AArch64::LDRXui: 1202 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1203 break; 1204 case AArch64::LDRQui: 1205 case AArch64::STRQui: 1206 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1207 break; 1208 case AArch64::LDRDui: 1209 case AArch64::STRDui: 1210 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1211 break; 1212 case AArch64::LDRSui: 1213 case AArch64::STRSui: 1214 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1215 break; 1216 case AArch64::LDRHui: 1217 case AArch64::STRHui: 1218 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); 1219 break; 1220 case AArch64::LDRBui: 1221 case AArch64::STRBui: 1222 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); 1223 break; 1224 } 1225 1226 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1227 if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4)) 1228 Inst.addOperand(MCOperand::createImm(offset)); 1229 return Success; 1230 } 1231 1232 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, 1233 uint64_t Addr, 1234 const void *Decoder) { 1235 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1236 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1237 int64_t offset = fieldFromInstruction(insn, 12, 9); 1238 1239 // offset is a 9-bit signed immediate, so sign extend it to 1240 // fill the unsigned. 1241 if (offset & (1 << (9 - 1))) 1242 offset |= ~((1LL << 9) - 1); 1243 1244 // First operand is always the writeback to the address register, if needed. 1245 switch (Inst.getOpcode()) { 1246 default: 1247 break; 1248 case AArch64::LDRSBWpre: 1249 case AArch64::LDRSHWpre: 1250 case AArch64::STRBBpre: 1251 case AArch64::LDRBBpre: 1252 case AArch64::STRHHpre: 1253 case AArch64::LDRHHpre: 1254 case AArch64::STRWpre: 1255 case AArch64::LDRWpre: 1256 case AArch64::LDRSBWpost: 1257 case AArch64::LDRSHWpost: 1258 case AArch64::STRBBpost: 1259 case AArch64::LDRBBpost: 1260 case AArch64::STRHHpost: 1261 case AArch64::LDRHHpost: 1262 case AArch64::STRWpost: 1263 case AArch64::LDRWpost: 1264 case AArch64::LDRSBXpre: 1265 case AArch64::LDRSHXpre: 1266 case AArch64::STRXpre: 1267 case AArch64::LDRSWpre: 1268 case AArch64::LDRXpre: 1269 case AArch64::LDRSBXpost: 1270 case AArch64::LDRSHXpost: 1271 case AArch64::STRXpost: 1272 case AArch64::LDRSWpost: 1273 case AArch64::LDRXpost: 1274 case AArch64::LDRQpre: 1275 case AArch64::STRQpre: 1276 case AArch64::LDRQpost: 1277 case AArch64::STRQpost: 1278 case AArch64::LDRDpre: 1279 case AArch64::STRDpre: 1280 case AArch64::LDRDpost: 1281 case AArch64::STRDpost: 1282 case AArch64::LDRSpre: 1283 case AArch64::STRSpre: 1284 case AArch64::LDRSpost: 1285 case AArch64::STRSpost: 1286 case AArch64::LDRHpre: 1287 case AArch64::STRHpre: 1288 case AArch64::LDRHpost: 1289 case AArch64::STRHpost: 1290 case AArch64::LDRBpre: 1291 case AArch64::STRBpre: 1292 case AArch64::LDRBpost: 1293 case AArch64::STRBpost: 1294 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1295 break; 1296 } 1297 1298 switch (Inst.getOpcode()) { 1299 default: 1300 return Fail; 1301 case AArch64::PRFUMi: 1302 // Rt is an immediate in prefetch. 1303 Inst.addOperand(MCOperand::createImm(Rt)); 1304 break; 1305 case AArch64::STURBBi: 1306 case AArch64::LDURBBi: 1307 case AArch64::LDURSBWi: 1308 case AArch64::STURHHi: 1309 case AArch64::LDURHHi: 1310 case AArch64::LDURSHWi: 1311 case AArch64::STURWi: 1312 case AArch64::LDURWi: 1313 case AArch64::LDTRSBWi: 1314 case AArch64::LDTRSHWi: 1315 case AArch64::STTRWi: 1316 case AArch64::LDTRWi: 1317 case AArch64::STTRHi: 1318 case AArch64::LDTRHi: 1319 case AArch64::LDTRBi: 1320 case AArch64::STTRBi: 1321 case AArch64::LDRSBWpre: 1322 case AArch64::LDRSHWpre: 1323 case AArch64::STRBBpre: 1324 case AArch64::LDRBBpre: 1325 case AArch64::STRHHpre: 1326 case AArch64::LDRHHpre: 1327 case AArch64::STRWpre: 1328 case AArch64::LDRWpre: 1329 case AArch64::LDRSBWpost: 1330 case AArch64::LDRSHWpost: 1331 case AArch64::STRBBpost: 1332 case AArch64::LDRBBpost: 1333 case AArch64::STRHHpost: 1334 case AArch64::LDRHHpost: 1335 case AArch64::STRWpost: 1336 case AArch64::LDRWpost: 1337 case AArch64::STLURBi: 1338 case AArch64::STLURHi: 1339 case AArch64::STLURWi: 1340 case AArch64::LDAPURBi: 1341 case AArch64::LDAPURSBWi: 1342 case AArch64::LDAPURHi: 1343 case AArch64::LDAPURSHWi: 1344 case AArch64::LDAPURi: 1345 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1346 break; 1347 case AArch64::LDURSBXi: 1348 case AArch64::LDURSHXi: 1349 case AArch64::LDURSWi: 1350 case AArch64::STURXi: 1351 case AArch64::LDURXi: 1352 case AArch64::LDTRSBXi: 1353 case AArch64::LDTRSHXi: 1354 case AArch64::LDTRSWi: 1355 case AArch64::STTRXi: 1356 case AArch64::LDTRXi: 1357 case AArch64::LDRSBXpre: 1358 case AArch64::LDRSHXpre: 1359 case AArch64::STRXpre: 1360 case AArch64::LDRSWpre: 1361 case AArch64::LDRXpre: 1362 case AArch64::LDRSBXpost: 1363 case AArch64::LDRSHXpost: 1364 case AArch64::STRXpost: 1365 case AArch64::LDRSWpost: 1366 case AArch64::LDRXpost: 1367 case AArch64::LDAPURSWi: 1368 case AArch64::LDAPURSHXi: 1369 case AArch64::LDAPURSBXi: 1370 case AArch64::STLURXi: 1371 case AArch64::LDAPURXi: 1372 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1373 break; 1374 case AArch64::LDURQi: 1375 case AArch64::STURQi: 1376 case AArch64::LDRQpre: 1377 case AArch64::STRQpre: 1378 case AArch64::LDRQpost: 1379 case AArch64::STRQpost: 1380 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1381 break; 1382 case AArch64::LDURDi: 1383 case AArch64::STURDi: 1384 case AArch64::LDRDpre: 1385 case AArch64::STRDpre: 1386 case AArch64::LDRDpost: 1387 case AArch64::STRDpost: 1388 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1389 break; 1390 case AArch64::LDURSi: 1391 case AArch64::STURSi: 1392 case AArch64::LDRSpre: 1393 case AArch64::STRSpre: 1394 case AArch64::LDRSpost: 1395 case AArch64::STRSpost: 1396 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1397 break; 1398 case AArch64::LDURHi: 1399 case AArch64::STURHi: 1400 case AArch64::LDRHpre: 1401 case AArch64::STRHpre: 1402 case AArch64::LDRHpost: 1403 case AArch64::STRHpost: 1404 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); 1405 break; 1406 case AArch64::LDURBi: 1407 case AArch64::STURBi: 1408 case AArch64::LDRBpre: 1409 case AArch64::STRBpre: 1410 case AArch64::LDRBpost: 1411 case AArch64::STRBpost: 1412 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); 1413 break; 1414 } 1415 1416 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1417 Inst.addOperand(MCOperand::createImm(offset)); 1418 1419 bool IsLoad = fieldFromInstruction(insn, 22, 1); 1420 bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0; 1421 bool IsFP = fieldFromInstruction(insn, 26, 1); 1422 1423 // Cannot write back to a transfer register (but xzr != sp). 1424 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn) 1425 return SoftFail; 1426 1427 return Success; 1428 } 1429 1430 static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, 1431 uint64_t Addr, 1432 const void *Decoder) { 1433 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1434 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1435 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); 1436 unsigned Rs = fieldFromInstruction(insn, 16, 5); 1437 1438 unsigned Opcode = Inst.getOpcode(); 1439 switch (Opcode) { 1440 default: 1441 return Fail; 1442 case AArch64::STLXRW: 1443 case AArch64::STLXRB: 1444 case AArch64::STLXRH: 1445 case AArch64::STXRW: 1446 case AArch64::STXRB: 1447 case AArch64::STXRH: 1448 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1449 LLVM_FALLTHROUGH; 1450 case AArch64::LDARW: 1451 case AArch64::LDARB: 1452 case AArch64::LDARH: 1453 case AArch64::LDAXRW: 1454 case AArch64::LDAXRB: 1455 case AArch64::LDAXRH: 1456 case AArch64::LDXRW: 1457 case AArch64::LDXRB: 1458 case AArch64::LDXRH: 1459 case AArch64::STLRW: 1460 case AArch64::STLRB: 1461 case AArch64::STLRH: 1462 case AArch64::STLLRW: 1463 case AArch64::STLLRB: 1464 case AArch64::STLLRH: 1465 case AArch64::LDLARW: 1466 case AArch64::LDLARB: 1467 case AArch64::LDLARH: 1468 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1469 break; 1470 case AArch64::STLXRX: 1471 case AArch64::STXRX: 1472 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1473 LLVM_FALLTHROUGH; 1474 case AArch64::LDARX: 1475 case AArch64::LDAXRX: 1476 case AArch64::LDXRX: 1477 case AArch64::STLRX: 1478 case AArch64::LDLARX: 1479 case AArch64::STLLRX: 1480 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1481 break; 1482 case AArch64::STLXPW: 1483 case AArch64::STXPW: 1484 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1485 LLVM_FALLTHROUGH; 1486 case AArch64::LDAXPW: 1487 case AArch64::LDXPW: 1488 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1489 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1490 break; 1491 case AArch64::STLXPX: 1492 case AArch64::STXPX: 1493 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1494 LLVM_FALLTHROUGH; 1495 case AArch64::LDAXPX: 1496 case AArch64::LDXPX: 1497 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1498 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1499 break; 1500 } 1501 1502 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1503 1504 // You shouldn't load to the same register twice in an instruction... 1505 if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW || 1506 Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) && 1507 Rt == Rt2) 1508 return SoftFail; 1509 1510 return Success; 1511 } 1512 1513 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, 1514 uint64_t Addr, 1515 const void *Decoder) { 1516 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1517 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1518 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); 1519 int64_t offset = fieldFromInstruction(insn, 15, 7); 1520 bool IsLoad = fieldFromInstruction(insn, 22, 1); 1521 1522 // offset is a 7-bit signed immediate, so sign extend it to 1523 // fill the unsigned. 1524 if (offset & (1 << (7 - 1))) 1525 offset |= ~((1LL << 7) - 1); 1526 1527 unsigned Opcode = Inst.getOpcode(); 1528 bool NeedsDisjointWritebackTransfer = false; 1529 1530 // First operand is always writeback of base register. 1531 switch (Opcode) { 1532 default: 1533 break; 1534 case AArch64::LDPXpost: 1535 case AArch64::STPXpost: 1536 case AArch64::LDPSWpost: 1537 case AArch64::LDPXpre: 1538 case AArch64::STPXpre: 1539 case AArch64::LDPSWpre: 1540 case AArch64::LDPWpost: 1541 case AArch64::STPWpost: 1542 case AArch64::LDPWpre: 1543 case AArch64::STPWpre: 1544 case AArch64::LDPQpost: 1545 case AArch64::STPQpost: 1546 case AArch64::LDPQpre: 1547 case AArch64::STPQpre: 1548 case AArch64::LDPDpost: 1549 case AArch64::STPDpost: 1550 case AArch64::LDPDpre: 1551 case AArch64::STPDpre: 1552 case AArch64::LDPSpost: 1553 case AArch64::STPSpost: 1554 case AArch64::LDPSpre: 1555 case AArch64::STPSpre: 1556 case AArch64::STGPpre: 1557 case AArch64::STGPpost: 1558 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1559 break; 1560 } 1561 1562 switch (Opcode) { 1563 default: 1564 return Fail; 1565 case AArch64::LDPXpost: 1566 case AArch64::STPXpost: 1567 case AArch64::LDPSWpost: 1568 case AArch64::LDPXpre: 1569 case AArch64::STPXpre: 1570 case AArch64::LDPSWpre: 1571 case AArch64::STGPpre: 1572 case AArch64::STGPpost: 1573 NeedsDisjointWritebackTransfer = true; 1574 LLVM_FALLTHROUGH; 1575 case AArch64::LDNPXi: 1576 case AArch64::STNPXi: 1577 case AArch64::LDPXi: 1578 case AArch64::STPXi: 1579 case AArch64::LDPSWi: 1580 case AArch64::STGPi: 1581 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1582 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1583 break; 1584 case AArch64::LDPWpost: 1585 case AArch64::STPWpost: 1586 case AArch64::LDPWpre: 1587 case AArch64::STPWpre: 1588 NeedsDisjointWritebackTransfer = true; 1589 LLVM_FALLTHROUGH; 1590 case AArch64::LDNPWi: 1591 case AArch64::STNPWi: 1592 case AArch64::LDPWi: 1593 case AArch64::STPWi: 1594 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1595 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1596 break; 1597 case AArch64::LDNPQi: 1598 case AArch64::STNPQi: 1599 case AArch64::LDPQpost: 1600 case AArch64::STPQpost: 1601 case AArch64::LDPQi: 1602 case AArch64::STPQi: 1603 case AArch64::LDPQpre: 1604 case AArch64::STPQpre: 1605 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1606 DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder); 1607 break; 1608 case AArch64::LDNPDi: 1609 case AArch64::STNPDi: 1610 case AArch64::LDPDpost: 1611 case AArch64::STPDpost: 1612 case AArch64::LDPDi: 1613 case AArch64::STPDi: 1614 case AArch64::LDPDpre: 1615 case AArch64::STPDpre: 1616 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1617 DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1618 break; 1619 case AArch64::LDNPSi: 1620 case AArch64::STNPSi: 1621 case AArch64::LDPSpost: 1622 case AArch64::STPSpost: 1623 case AArch64::LDPSi: 1624 case AArch64::STPSi: 1625 case AArch64::LDPSpre: 1626 case AArch64::STPSpre: 1627 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1628 DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1629 break; 1630 } 1631 1632 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1633 Inst.addOperand(MCOperand::createImm(offset)); 1634 1635 // You shouldn't load to the same register twice in an instruction... 1636 if (IsLoad && Rt == Rt2) 1637 return SoftFail; 1638 1639 // ... or do any operation that writes-back to a transfer register. But note 1640 // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different. 1641 if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn)) 1642 return SoftFail; 1643 1644 return Success; 1645 } 1646 1647 static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn, 1648 uint64_t Addr, 1649 const void *Decoder) { 1650 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1651 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1652 uint64_t offset = fieldFromInstruction(insn, 22, 1) << 9 | 1653 fieldFromInstruction(insn, 12, 9); 1654 unsigned writeback = fieldFromInstruction(insn, 11, 1); 1655 1656 switch (Inst.getOpcode()) { 1657 default: 1658 return Fail; 1659 case AArch64::LDRAAwriteback: 1660 case AArch64::LDRABwriteback: 1661 DecodeGPR64spRegisterClass(Inst, Rn /* writeback register */, Addr, 1662 Decoder); 1663 break; 1664 case AArch64::LDRAAindexed: 1665 case AArch64::LDRABindexed: 1666 break; 1667 } 1668 1669 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1670 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1671 DecodeSImm<10>(Inst, offset, Addr, Decoder); 1672 1673 if (writeback && Rt == Rn && Rn != 31) { 1674 return SoftFail; 1675 } 1676 1677 return Success; 1678 } 1679 1680 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, 1681 uint64_t Addr, 1682 const void *Decoder) { 1683 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1684 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1685 unsigned Rm = fieldFromInstruction(insn, 16, 5); 1686 unsigned extend = fieldFromInstruction(insn, 10, 6); 1687 1688 unsigned shift = extend & 0x7; 1689 if (shift > 4) 1690 return Fail; 1691 1692 switch (Inst.getOpcode()) { 1693 default: 1694 return Fail; 1695 case AArch64::ADDWrx: 1696 case AArch64::SUBWrx: 1697 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1698 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1699 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1700 break; 1701 case AArch64::ADDSWrx: 1702 case AArch64::SUBSWrx: 1703 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1704 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1705 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1706 break; 1707 case AArch64::ADDXrx: 1708 case AArch64::SUBXrx: 1709 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1710 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1711 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1712 break; 1713 case AArch64::ADDSXrx: 1714 case AArch64::SUBSXrx: 1715 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1716 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1717 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1718 break; 1719 case AArch64::ADDXrx64: 1720 case AArch64::SUBXrx64: 1721 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1722 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1723 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1724 break; 1725 case AArch64::SUBSXrx64: 1726 case AArch64::ADDSXrx64: 1727 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1728 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1729 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1730 break; 1731 } 1732 1733 Inst.addOperand(MCOperand::createImm(extend)); 1734 return Success; 1735 } 1736 1737 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, 1738 uint64_t Addr, 1739 const void *Decoder) { 1740 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1741 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1742 unsigned Datasize = fieldFromInstruction(insn, 31, 1); 1743 unsigned imm; 1744 1745 if (Datasize) { 1746 if (Inst.getOpcode() == AArch64::ANDSXri) 1747 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1748 else 1749 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1750 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); 1751 imm = fieldFromInstruction(insn, 10, 13); 1752 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64)) 1753 return Fail; 1754 } else { 1755 if (Inst.getOpcode() == AArch64::ANDSWri) 1756 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1757 else 1758 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1759 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); 1760 imm = fieldFromInstruction(insn, 10, 12); 1761 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32)) 1762 return Fail; 1763 } 1764 Inst.addOperand(MCOperand::createImm(imm)); 1765 return Success; 1766 } 1767 1768 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, 1769 uint64_t Addr, 1770 const void *Decoder) { 1771 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1772 unsigned cmode = fieldFromInstruction(insn, 12, 4); 1773 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; 1774 imm |= fieldFromInstruction(insn, 5, 5); 1775 1776 if (Inst.getOpcode() == AArch64::MOVID) 1777 DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder); 1778 else 1779 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); 1780 1781 Inst.addOperand(MCOperand::createImm(imm)); 1782 1783 switch (Inst.getOpcode()) { 1784 default: 1785 break; 1786 case AArch64::MOVIv4i16: 1787 case AArch64::MOVIv8i16: 1788 case AArch64::MVNIv4i16: 1789 case AArch64::MVNIv8i16: 1790 case AArch64::MOVIv2i32: 1791 case AArch64::MOVIv4i32: 1792 case AArch64::MVNIv2i32: 1793 case AArch64::MVNIv4i32: 1794 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2)); 1795 break; 1796 case AArch64::MOVIv2s_msl: 1797 case AArch64::MOVIv4s_msl: 1798 case AArch64::MVNIv2s_msl: 1799 case AArch64::MVNIv4s_msl: 1800 Inst.addOperand(MCOperand::createImm((cmode & 1) ? 0x110 : 0x108)); 1801 break; 1802 } 1803 1804 return Success; 1805 } 1806 1807 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, 1808 uint64_t Addr, 1809 const void *Decoder) { 1810 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1811 unsigned cmode = fieldFromInstruction(insn, 12, 4); 1812 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; 1813 imm |= fieldFromInstruction(insn, 5, 5); 1814 1815 // Tied operands added twice. 1816 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); 1817 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); 1818 1819 Inst.addOperand(MCOperand::createImm(imm)); 1820 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2)); 1821 1822 return Success; 1823 } 1824 1825 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, 1826 uint64_t Addr, const void *Decoder) { 1827 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1828 int64_t imm = fieldFromInstruction(insn, 5, 19) << 2; 1829 imm |= fieldFromInstruction(insn, 29, 2); 1830 const AArch64Disassembler *Dis = 1831 static_cast<const AArch64Disassembler *>(Decoder); 1832 1833 // Sign-extend the 21-bit immediate. 1834 if (imm & (1 << (21 - 1))) 1835 imm |= ~((1LL << 21) - 1); 1836 1837 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1838 if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4)) 1839 Inst.addOperand(MCOperand::createImm(imm)); 1840 1841 return Success; 1842 } 1843 1844 static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn, 1845 uint64_t Addr, const void *Decoder) { 1846 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1847 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1848 unsigned Imm = fieldFromInstruction(insn, 10, 14); 1849 unsigned S = fieldFromInstruction(insn, 29, 1); 1850 unsigned Datasize = fieldFromInstruction(insn, 31, 1); 1851 1852 unsigned ShifterVal = (Imm >> 12) & 3; 1853 unsigned ImmVal = Imm & 0xFFF; 1854 const AArch64Disassembler *Dis = 1855 static_cast<const AArch64Disassembler *>(Decoder); 1856 1857 if (ShifterVal != 0 && ShifterVal != 1) 1858 return Fail; 1859 1860 if (Datasize) { 1861 if (Rd == 31 && !S) 1862 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1863 else 1864 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1865 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1866 } else { 1867 if (Rd == 31 && !S) 1868 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1869 else 1870 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1871 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1872 } 1873 1874 if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4)) 1875 Inst.addOperand(MCOperand::createImm(ImmVal)); 1876 Inst.addOperand(MCOperand::createImm(12 * ShifterVal)); 1877 return Success; 1878 } 1879 1880 static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, 1881 uint64_t Addr, 1882 const void *Decoder) { 1883 int64_t imm = fieldFromInstruction(insn, 0, 26); 1884 const AArch64Disassembler *Dis = 1885 static_cast<const AArch64Disassembler *>(Decoder); 1886 1887 // Sign-extend the 26-bit immediate. 1888 if (imm & (1 << (26 - 1))) 1889 imm |= ~((1LL << 26) - 1); 1890 1891 if (!Dis->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 4)) 1892 Inst.addOperand(MCOperand::createImm(imm)); 1893 1894 return Success; 1895 } 1896 1897 static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn, 1898 uint64_t Addr, 1899 const void *Decoder) { 1900 uint64_t op1 = fieldFromInstruction(insn, 16, 3); 1901 uint64_t op2 = fieldFromInstruction(insn, 5, 3); 1902 uint64_t crm = fieldFromInstruction(insn, 8, 4); 1903 uint64_t pstate_field = (op1 << 3) | op2; 1904 1905 switch (pstate_field) { 1906 case 0x01: // XAFlag 1907 case 0x02: // AXFlag 1908 return Fail; 1909 } 1910 1911 if ((pstate_field == AArch64PState::PAN || 1912 pstate_field == AArch64PState::UAO || 1913 pstate_field == AArch64PState::SSBS) && crm > 1) 1914 return Fail; 1915 1916 Inst.addOperand(MCOperand::createImm(pstate_field)); 1917 Inst.addOperand(MCOperand::createImm(crm)); 1918 1919 const AArch64Disassembler *Dis = 1920 static_cast<const AArch64Disassembler *>(Decoder); 1921 auto PState = AArch64PState::lookupPStateByEncoding(pstate_field); 1922 if (PState && PState->haveFeatures(Dis->getSubtargetInfo().getFeatureBits())) 1923 return Success; 1924 return Fail; 1925 } 1926 1927 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, 1928 uint64_t Addr, const void *Decoder) { 1929 uint64_t Rt = fieldFromInstruction(insn, 0, 5); 1930 uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5; 1931 bit |= fieldFromInstruction(insn, 19, 5); 1932 int64_t dst = fieldFromInstruction(insn, 5, 14); 1933 const AArch64Disassembler *Dis = 1934 static_cast<const AArch64Disassembler *>(Decoder); 1935 1936 // Sign-extend 14-bit immediate. 1937 if (dst & (1 << (14 - 1))) 1938 dst |= ~((1LL << 14) - 1); 1939 1940 if (fieldFromInstruction(insn, 31, 1) == 0) 1941 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1942 else 1943 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1944 Inst.addOperand(MCOperand::createImm(bit)); 1945 if (!Dis->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 4)) 1946 Inst.addOperand(MCOperand::createImm(dst)); 1947 1948 return Success; 1949 } 1950 1951 static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, 1952 unsigned RegClassID, 1953 unsigned RegNo, 1954 uint64_t Addr, 1955 const void *Decoder) { 1956 // Register number must be even (see CASP instruction) 1957 if (RegNo & 0x1) 1958 return Fail; 1959 1960 unsigned Reg = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo / 2); 1961 Inst.addOperand(MCOperand::createReg(Reg)); 1962 return Success; 1963 } 1964 1965 static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, 1966 unsigned RegNo, 1967 uint64_t Addr, 1968 const void *Decoder) { 1969 return DecodeGPRSeqPairsClassRegisterClass(Inst, 1970 AArch64::WSeqPairsClassRegClassID, 1971 RegNo, Addr, Decoder); 1972 } 1973 1974 static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, 1975 unsigned RegNo, 1976 uint64_t Addr, 1977 const void *Decoder) { 1978 return DecodeGPRSeqPairsClassRegisterClass(Inst, 1979 AArch64::XSeqPairsClassRegClassID, 1980 RegNo, Addr, Decoder); 1981 } 1982 1983 static DecodeStatus DecodeSVELogicalImmInstruction(llvm::MCInst &Inst, 1984 uint32_t insn, 1985 uint64_t Addr, 1986 const void *Decoder) { 1987 unsigned Zdn = fieldFromInstruction(insn, 0, 5); 1988 unsigned imm = fieldFromInstruction(insn, 5, 13); 1989 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64)) 1990 return Fail; 1991 1992 // The same (tied) operand is added twice to the instruction. 1993 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); 1994 if (Inst.getOpcode() != AArch64::DUPM_ZI) 1995 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); 1996 Inst.addOperand(MCOperand::createImm(imm)); 1997 return Success; 1998 } 1999 2000 template<int Bits> 2001 static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm, 2002 uint64_t Address, const void *Decoder) { 2003 if (Imm & ~((1LL << Bits) - 1)) 2004 return Fail; 2005 2006 // Imm is a signed immediate, so sign extend it. 2007 if (Imm & (1 << (Bits - 1))) 2008 Imm |= ~((1LL << Bits) - 1); 2009 2010 Inst.addOperand(MCOperand::createImm(Imm)); 2011 return Success; 2012 } 2013 2014 // Decode 8-bit signed/unsigned immediate for a given element width. 2015 template <int ElementWidth> 2016 static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, 2017 uint64_t Addr, const void *Decoder) { 2018 unsigned Val = (uint8_t)Imm; 2019 unsigned Shift = (Imm & 0x100) ? 8 : 0; 2020 if (ElementWidth == 8 && Shift) 2021 return Fail; 2022 Inst.addOperand(MCOperand::createImm(Val)); 2023 Inst.addOperand(MCOperand::createImm(Shift)); 2024 return Success; 2025 } 2026 2027 // Decode uimm4 ranged from 1-16. 2028 static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, 2029 uint64_t Addr, const void *Decoder) { 2030 Inst.addOperand(MCOperand::createImm(Imm + 1)); 2031 return Success; 2032 } 2033 2034 static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address, 2035 const void *Decoder) { 2036 if (AArch64SVCR::lookupSVCRByEncoding(Imm)) { 2037 Inst.addOperand(MCOperand::createImm(Imm)); 2038 return Success; 2039 } 2040 return Fail; 2041 } 2042