1 //===- AArch64Disassembler.cpp - Disassembler for AArch64 -----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // 10 //===----------------------------------------------------------------------===// 11 12 #include "AArch64Disassembler.h" 13 #include "AArch64ExternalSymbolizer.h" 14 #include "MCTargetDesc/AArch64AddressingModes.h" 15 #include "MCTargetDesc/AArch64MCTargetDesc.h" 16 #include "TargetInfo/AArch64TargetInfo.h" 17 #include "Utils/AArch64BaseInfo.h" 18 #include "llvm-c/Disassembler.h" 19 #include "llvm/MC/MCDecoderOps.h" 20 #include "llvm/MC/MCDisassembler/MCRelocationInfo.h" 21 #include "llvm/MC/MCInst.h" 22 #include "llvm/MC/MCInstrDesc.h" 23 #include "llvm/MC/MCRegisterInfo.h" 24 #include "llvm/MC/MCSubtargetInfo.h" 25 #include "llvm/MC/TargetRegistry.h" 26 #include "llvm/Support/Compiler.h" 27 #include "llvm/Support/Debug.h" 28 #include "llvm/Support/ErrorHandling.h" 29 #include <algorithm> 30 #include <memory> 31 32 using namespace llvm; 33 34 #define DEBUG_TYPE "aarch64-disassembler" 35 36 // Pull DecodeStatus and its enum values into the global namespace. 37 using DecodeStatus = MCDisassembler::DecodeStatus; 38 39 // Forward declare these because the autogenerated code will reference them. 40 // Definitions are further down. 41 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo, 42 uint64_t Address, 43 const MCDisassembler *Decoder); 44 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo, 45 uint64_t Address, 46 const MCDisassembler *Decoder); 47 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, 48 uint64_t Address, 49 const MCDisassembler *Decoder); 50 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, 51 uint64_t Address, 52 const MCDisassembler *Decoder); 53 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, 54 uint64_t Address, 55 const MCDisassembler *Decoder); 56 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, 57 uint64_t Address, 58 const MCDisassembler *Decoder); 59 static DecodeStatus 60 DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 61 const MCDisassembler *Decoder); 62 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, 63 uint64_t Address, 64 const MCDisassembler *Decoder); 65 static DecodeStatus 66 DecodeGPR64x8ClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 67 const MCDisassembler *Decoder); 68 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo, 69 uint64_t Address, 70 const MCDisassembler *Decoder); 71 static DecodeStatus 72 DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst, unsigned RegNo, 73 uint64_t Address, 74 const MCDisassembler *Decoder); 75 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, 76 uint64_t Address, 77 const MCDisassembler *Decoder); 78 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo, 79 uint64_t Address, 80 const MCDisassembler *Decoder); 81 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, 82 uint64_t Address, 83 const MCDisassembler *Decoder); 84 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, 85 uint64_t Address, 86 const MCDisassembler *Decoder); 87 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, 88 uint64_t Address, 89 const MCDisassembler *Decoder); 90 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, 91 uint64_t Address, 92 const MCDisassembler *Decoder); 93 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, 94 uint64_t Address, 95 const MCDisassembler *Decoder); 96 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, 97 uint64_t Address, 98 const MCDisassembler *Decoder); 99 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, 100 uint64_t Address, 101 const MCDisassembler *Decoder); 102 static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo, 103 uint64_t Address, 104 const MCDisassembler *Decoder); 105 static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 106 uint64_t Address, 107 const MCDisassembler *Decoder); 108 static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, 109 uint64_t Address, 110 const MCDisassembler *Decoder); 111 static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, 112 uint64_t Address, 113 const MCDisassembler *Decoder); 114 static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, 115 uint64_t Address, 116 const MCDisassembler *Decoder); 117 template <unsigned NumBitsForTile> 118 static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo, 119 uint64_t Address, 120 const MCDisassembler *Decoder); 121 static DecodeStatus 122 DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask, 123 uint64_t Address, 124 const MCDisassembler *Decoder); 125 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, 126 uint64_t Address, 127 const MCDisassembler *Decoder); 128 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 129 uint64_t Address, 130 const MCDisassembler *Decoder); 131 132 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, 133 uint64_t Address, 134 const MCDisassembler *Decoder); 135 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, 136 uint64_t Address, 137 const MCDisassembler *Decoder); 138 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, 139 uint64_t Address, 140 const MCDisassembler *Decoder); 141 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, 142 uint64_t Address, 143 const MCDisassembler *Decoder); 144 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, 145 uint64_t Address, 146 const MCDisassembler *Decoder); 147 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, 148 uint64_t Address, 149 const MCDisassembler *Decoder); 150 static DecodeStatus 151 DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, 152 const MCDisassembler *Decoder); 153 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, 154 uint64_t Address, 155 const MCDisassembler *Decoder); 156 static DecodeStatus 157 DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, 158 const MCDisassembler *Decoder); 159 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, 160 uint64_t Address, 161 const MCDisassembler *Decoder); 162 static DecodeStatus 163 DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, 164 const MCDisassembler *Decoder); 165 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, 166 uint64_t Address, 167 const MCDisassembler *Decoder); 168 static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn, 169 uint64_t Address, 170 const MCDisassembler *Decoder); 171 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, 172 uint64_t Address, 173 const MCDisassembler *Decoder); 174 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, 175 uint64_t Address, 176 const MCDisassembler *Decoder); 177 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, 178 uint64_t Address, 179 const MCDisassembler *Decoder); 180 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, 181 uint64_t Address, 182 const MCDisassembler *Decoder); 183 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, 184 uint64_t Address, 185 const MCDisassembler *Decoder); 186 static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn, 187 uint64_t Address, 188 const MCDisassembler *Decoder); 189 static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, 190 uint64_t Address, 191 const MCDisassembler *Decoder); 192 static DecodeStatus 193 DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, 194 const MCDisassembler *Decoder); 195 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, 196 uint64_t Address, 197 const MCDisassembler *Decoder); 198 199 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, 200 uint64_t Address, 201 const MCDisassembler *Decoder); 202 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, 203 uint64_t Addr, 204 const MCDisassembler *Decoder); 205 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, 206 uint64_t Addr, 207 const MCDisassembler *Decoder); 208 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, 209 uint64_t Addr, 210 const MCDisassembler *Decoder); 211 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, 212 uint64_t Addr, 213 const MCDisassembler *Decoder); 214 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, 215 uint64_t Addr, 216 const MCDisassembler *Decoder); 217 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, 218 uint64_t Addr, 219 const MCDisassembler *Decoder); 220 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, 221 uint64_t Addr, 222 const MCDisassembler *Decoder); 223 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, 224 uint64_t Addr, 225 const MCDisassembler *Decoder); 226 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, 227 uint64_t Addr, 228 const MCDisassembler *Decoder); 229 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, 230 uint64_t Addr, 231 const MCDisassembler *Decoder); 232 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, 233 uint64_t Addr, 234 const MCDisassembler *Decoder); 235 static DecodeStatus 236 DecodeWSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, 237 const MCDisassembler *Decoder); 238 static DecodeStatus 239 DecodeXSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, 240 const MCDisassembler *Decoder); 241 static DecodeStatus 242 DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, 243 const MCDisassembler *Decoder); 244 template <int Bits> 245 static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address, 246 const MCDisassembler *Decoder); 247 template <int ElementWidth> 248 static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, uint64_t Addr, 249 const MCDisassembler *Decoder); 250 static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, 251 uint64_t Addr, 252 const MCDisassembler *Decoder); 253 static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address, 254 const MCDisassembler *Decoder); 255 static DecodeStatus DecodeCPYMemOpInstruction(MCInst &Inst, uint32_t insn, 256 uint64_t Addr, 257 const MCDisassembler *Decoder); 258 static DecodeStatus DecodeSETMemOpInstruction(MCInst &Inst, uint32_t insn, 259 uint64_t Addr, 260 const MCDisassembler *Decoder); 261 262 static bool Check(DecodeStatus &Out, DecodeStatus In) { 263 switch (In) { 264 case MCDisassembler::Success: 265 // Out stays the same. 266 return true; 267 case MCDisassembler::SoftFail: 268 Out = In; 269 return true; 270 case MCDisassembler::Fail: 271 Out = In; 272 return false; 273 } 274 llvm_unreachable("Invalid DecodeStatus!"); 275 } 276 277 #include "AArch64GenDisassemblerTables.inc" 278 #include "AArch64GenInstrInfo.inc" 279 280 #define Success MCDisassembler::Success 281 #define Fail MCDisassembler::Fail 282 #define SoftFail MCDisassembler::SoftFail 283 284 static MCDisassembler *createAArch64Disassembler(const Target &T, 285 const MCSubtargetInfo &STI, 286 MCContext &Ctx) { 287 288 return new AArch64Disassembler(STI, Ctx, T.createMCInstrInfo()); 289 } 290 291 DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size, 292 ArrayRef<uint8_t> Bytes, 293 uint64_t Address, 294 raw_ostream &CS) const { 295 CommentStream = &CS; 296 297 Size = 0; 298 // We want to read exactly 4 bytes of data. 299 if (Bytes.size() < 4) 300 return Fail; 301 Size = 4; 302 303 // Encoded as a small-endian 32-bit word in the stream. 304 uint32_t Insn = 305 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 306 307 const uint8_t *Tables[] = {DecoderTable32, DecoderTableFallback32}; 308 309 for (auto Table : Tables) { 310 DecodeStatus Result = 311 decodeInstruction(Table, MI, Insn, Address, this, STI); 312 313 const MCInstrDesc &Desc = MCII->get(MI.getOpcode()); 314 315 // For Scalable Matrix Extension (SME) instructions that have an implicit 316 // operand for the accumulator (ZA) or implicit immediate zero which isn't 317 // encoded, manually insert operand. 318 for (unsigned i = 0; i < Desc.getNumOperands(); i++) { 319 if (Desc.OpInfo[i].OperandType == MCOI::OPERAND_REGISTER) { 320 switch (Desc.OpInfo[i].RegClass) { 321 default: 322 break; 323 case AArch64::MPRRegClassID: 324 MI.insert(MI.begin() + i, MCOperand::createReg(AArch64::ZA)); 325 break; 326 case AArch64::MPR8RegClassID: 327 MI.insert(MI.begin() + i, MCOperand::createReg(AArch64::ZAB0)); 328 break; 329 } 330 } else if (Desc.OpInfo[i].OperandType == 331 AArch64::OPERAND_IMPLICIT_IMM_0) { 332 MI.insert(MI.begin() + i, MCOperand::createImm(0)); 333 } 334 } 335 336 if (MI.getOpcode() == AArch64::LDR_ZA || 337 MI.getOpcode() == AArch64::STR_ZA) { 338 // Spill and fill instructions have a single immediate used for both 339 // the vector select offset and optional memory offset. Replicate 340 // the decoded immediate. 341 const MCOperand &Imm4Op = MI.getOperand(2); 342 assert(Imm4Op.isImm() && "Unexpected operand type!"); 343 MI.addOperand(Imm4Op); 344 } 345 346 if (Result != MCDisassembler::Fail) 347 return Result; 348 } 349 350 return MCDisassembler::Fail; 351 } 352 353 uint64_t AArch64Disassembler::suggestBytesToSkip(ArrayRef<uint8_t> Bytes, 354 uint64_t Address) const { 355 // AArch64 instructions are always 4 bytes wide, so there's no point 356 // in skipping any smaller number of bytes if an instruction can't 357 // be decoded. 358 return 4; 359 } 360 361 static MCSymbolizer * 362 createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo, 363 LLVMSymbolLookupCallback SymbolLookUp, 364 void *DisInfo, MCContext *Ctx, 365 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 366 return new AArch64ExternalSymbolizer(*Ctx, std::move(RelInfo), GetOpInfo, 367 SymbolLookUp, DisInfo); 368 } 369 370 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Disassembler() { 371 TargetRegistry::RegisterMCDisassembler(getTheAArch64leTarget(), 372 createAArch64Disassembler); 373 TargetRegistry::RegisterMCDisassembler(getTheAArch64beTarget(), 374 createAArch64Disassembler); 375 TargetRegistry::RegisterMCSymbolizer(getTheAArch64leTarget(), 376 createAArch64ExternalSymbolizer); 377 TargetRegistry::RegisterMCSymbolizer(getTheAArch64beTarget(), 378 createAArch64ExternalSymbolizer); 379 TargetRegistry::RegisterMCDisassembler(getTheAArch64_32Target(), 380 createAArch64Disassembler); 381 TargetRegistry::RegisterMCSymbolizer(getTheAArch64_32Target(), 382 createAArch64ExternalSymbolizer); 383 384 TargetRegistry::RegisterMCDisassembler(getTheARM64Target(), 385 createAArch64Disassembler); 386 TargetRegistry::RegisterMCSymbolizer(getTheARM64Target(), 387 createAArch64ExternalSymbolizer); 388 TargetRegistry::RegisterMCDisassembler(getTheARM64_32Target(), 389 createAArch64Disassembler); 390 TargetRegistry::RegisterMCSymbolizer(getTheARM64_32Target(), 391 createAArch64ExternalSymbolizer); 392 } 393 394 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo, 395 uint64_t Addr, 396 const MCDisassembler *Decoder) { 397 if (RegNo > 31) 398 return Fail; 399 400 unsigned Register = 401 AArch64MCRegisterClasses[AArch64::FPR128RegClassID].getRegister(RegNo); 402 Inst.addOperand(MCOperand::createReg(Register)); 403 return Success; 404 } 405 406 static DecodeStatus 407 DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, 408 const MCDisassembler *Decoder) { 409 if (RegNo > 15) 410 return Fail; 411 return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder); 412 } 413 414 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, 415 uint64_t Addr, 416 const MCDisassembler *Decoder) { 417 if (RegNo > 31) 418 return Fail; 419 420 unsigned Register = 421 AArch64MCRegisterClasses[AArch64::FPR64RegClassID].getRegister(RegNo); 422 Inst.addOperand(MCOperand::createReg(Register)); 423 return Success; 424 } 425 426 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, 427 uint64_t Addr, 428 const MCDisassembler *Decoder) { 429 if (RegNo > 31) 430 return Fail; 431 432 unsigned Register = 433 AArch64MCRegisterClasses[AArch64::FPR32RegClassID].getRegister(RegNo); 434 Inst.addOperand(MCOperand::createReg(Register)); 435 return Success; 436 } 437 438 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, 439 uint64_t Addr, 440 const MCDisassembler *Decoder) { 441 if (RegNo > 31) 442 return Fail; 443 444 unsigned Register = 445 AArch64MCRegisterClasses[AArch64::FPR16RegClassID].getRegister(RegNo); 446 Inst.addOperand(MCOperand::createReg(Register)); 447 return Success; 448 } 449 450 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, 451 uint64_t Addr, 452 const MCDisassembler *Decoder) { 453 if (RegNo > 31) 454 return Fail; 455 456 unsigned Register = 457 AArch64MCRegisterClasses[AArch64::FPR8RegClassID].getRegister(RegNo); 458 Inst.addOperand(MCOperand::createReg(Register)); 459 return Success; 460 } 461 462 static DecodeStatus 463 DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, 464 const MCDisassembler *Decoder) { 465 if (RegNo > 30) 466 return Fail; 467 468 unsigned Register = 469 AArch64MCRegisterClasses[AArch64::GPR64commonRegClassID].getRegister( 470 RegNo); 471 Inst.addOperand(MCOperand::createReg(Register)); 472 return Success; 473 } 474 475 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, 476 uint64_t Addr, 477 const MCDisassembler *Decoder) { 478 if (RegNo > 31) 479 return Fail; 480 481 unsigned Register = 482 AArch64MCRegisterClasses[AArch64::GPR64RegClassID].getRegister(RegNo); 483 Inst.addOperand(MCOperand::createReg(Register)); 484 return Success; 485 } 486 487 static DecodeStatus 488 DecodeGPR64x8ClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 489 const MCDisassembler *Decoder) { 490 if (RegNo > 22) 491 return Fail; 492 if (RegNo & 1) 493 return Fail; 494 495 unsigned Register = 496 AArch64MCRegisterClasses[AArch64::GPR64x8ClassRegClassID].getRegister( 497 RegNo >> 1); 498 Inst.addOperand(MCOperand::createReg(Register)); 499 return Success; 500 } 501 502 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo, 503 uint64_t Addr, 504 const MCDisassembler *Decoder) { 505 if (RegNo > 31) 506 return Fail; 507 unsigned Register = 508 AArch64MCRegisterClasses[AArch64::GPR64spRegClassID].getRegister(RegNo); 509 Inst.addOperand(MCOperand::createReg(Register)); 510 return Success; 511 } 512 513 static DecodeStatus 514 DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst, unsigned RegNo, 515 uint64_t Addr, 516 const MCDisassembler *Decoder) { 517 if (RegNo > 3) 518 return Fail; 519 520 unsigned Register = 521 AArch64MCRegisterClasses[AArch64::MatrixIndexGPR32_12_15RegClassID] 522 .getRegister(RegNo); 523 Inst.addOperand(MCOperand::createReg(Register)); 524 return Success; 525 } 526 527 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, 528 uint64_t Addr, 529 const MCDisassembler *Decoder) { 530 if (RegNo > 31) 531 return Fail; 532 533 unsigned Register = 534 AArch64MCRegisterClasses[AArch64::GPR32RegClassID].getRegister(RegNo); 535 Inst.addOperand(MCOperand::createReg(Register)); 536 return Success; 537 } 538 539 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo, 540 uint64_t Addr, 541 const MCDisassembler *Decoder) { 542 if (RegNo > 31) 543 return Fail; 544 545 unsigned Register = 546 AArch64MCRegisterClasses[AArch64::GPR32spRegClassID].getRegister(RegNo); 547 Inst.addOperand(MCOperand::createReg(Register)); 548 return Success; 549 } 550 551 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, 552 uint64_t Address, 553 const MCDisassembler *Decoder) { 554 if (RegNo > 31) 555 return Fail; 556 557 unsigned Register = 558 AArch64MCRegisterClasses[AArch64::ZPRRegClassID].getRegister(RegNo); 559 Inst.addOperand(MCOperand::createReg(Register)); 560 return Success; 561 } 562 563 static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo, 564 uint64_t Address, 565 const MCDisassembler *Decoder) { 566 if (RegNo > 15) 567 return Fail; 568 return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder); 569 } 570 571 static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 572 uint64_t Address, 573 const MCDisassembler *Decoder) { 574 if (RegNo > 7) 575 return Fail; 576 return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder); 577 } 578 579 static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, 580 uint64_t Address, 581 const MCDisassembler *Decoder) { 582 if (RegNo > 31) 583 return Fail; 584 unsigned Register = 585 AArch64MCRegisterClasses[AArch64::ZPR2RegClassID].getRegister(RegNo); 586 Inst.addOperand(MCOperand::createReg(Register)); 587 return Success; 588 } 589 590 static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, 591 uint64_t Address, 592 const MCDisassembler *Decoder) { 593 if (RegNo > 31) 594 return Fail; 595 unsigned Register = 596 AArch64MCRegisterClasses[AArch64::ZPR3RegClassID].getRegister(RegNo); 597 Inst.addOperand(MCOperand::createReg(Register)); 598 return Success; 599 } 600 601 static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, 602 uint64_t Address, 603 const MCDisassembler *Decoder) { 604 if (RegNo > 31) 605 return Fail; 606 unsigned Register = 607 AArch64MCRegisterClasses[AArch64::ZPR4RegClassID].getRegister(RegNo); 608 Inst.addOperand(MCOperand::createReg(Register)); 609 return Success; 610 } 611 612 static DecodeStatus 613 DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask, 614 uint64_t Address, 615 const MCDisassembler *Decoder) { 616 if (RegMask > 0xFF) 617 return Fail; 618 Inst.addOperand(MCOperand::createImm(RegMask)); 619 return Success; 620 } 621 622 static const SmallVector<SmallVector<unsigned, 16>, 5> 623 MatrixZATileDecoderTable = { 624 {AArch64::ZAB0}, 625 {AArch64::ZAH0, AArch64::ZAH1}, 626 {AArch64::ZAS0, AArch64::ZAS1, AArch64::ZAS2, AArch64::ZAS3}, 627 {AArch64::ZAD0, AArch64::ZAD1, AArch64::ZAD2, AArch64::ZAD3, 628 AArch64::ZAD4, AArch64::ZAD5, AArch64::ZAD6, AArch64::ZAD7}, 629 {AArch64::ZAQ0, AArch64::ZAQ1, AArch64::ZAQ2, AArch64::ZAQ3, 630 AArch64::ZAQ4, AArch64::ZAQ5, AArch64::ZAQ6, AArch64::ZAQ7, 631 AArch64::ZAQ8, AArch64::ZAQ9, AArch64::ZAQ10, AArch64::ZAQ11, 632 AArch64::ZAQ12, AArch64::ZAQ13, AArch64::ZAQ14, AArch64::ZAQ15}}; 633 634 template <unsigned NumBitsForTile> 635 static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo, 636 uint64_t Address, 637 const MCDisassembler *Decoder) { 638 unsigned LastReg = (1 << NumBitsForTile) - 1; 639 if (RegNo > LastReg) 640 return Fail; 641 Inst.addOperand( 642 MCOperand::createReg(MatrixZATileDecoderTable[NumBitsForTile][RegNo])); 643 return Success; 644 } 645 646 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, 647 uint64_t Addr, 648 const MCDisassembler *Decoder) { 649 if (RegNo > 15) 650 return Fail; 651 652 unsigned Register = 653 AArch64MCRegisterClasses[AArch64::PPRRegClassID].getRegister(RegNo); 654 Inst.addOperand(MCOperand::createReg(Register)); 655 return Success; 656 } 657 658 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 659 uint64_t Addr, 660 const MCDisassembler *Decoder) { 661 if (RegNo > 7) 662 return Fail; 663 664 // Just reuse the PPR decode table 665 return DecodePPRRegisterClass(Inst, RegNo, Addr, Decoder); 666 } 667 668 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, 669 uint64_t Addr, 670 const MCDisassembler *Decoder) { 671 if (RegNo > 31) 672 return Fail; 673 unsigned Register = 674 AArch64MCRegisterClasses[AArch64::QQRegClassID].getRegister(RegNo); 675 Inst.addOperand(MCOperand::createReg(Register)); 676 return Success; 677 } 678 679 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, 680 uint64_t Addr, 681 const MCDisassembler *Decoder) { 682 if (RegNo > 31) 683 return Fail; 684 unsigned Register = 685 AArch64MCRegisterClasses[AArch64::QQQRegClassID].getRegister(RegNo); 686 Inst.addOperand(MCOperand::createReg(Register)); 687 return Success; 688 } 689 690 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, 691 uint64_t Addr, 692 const MCDisassembler *Decoder) { 693 if (RegNo > 31) 694 return Fail; 695 unsigned Register = 696 AArch64MCRegisterClasses[AArch64::QQQQRegClassID].getRegister(RegNo); 697 Inst.addOperand(MCOperand::createReg(Register)); 698 return Success; 699 } 700 701 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, 702 uint64_t Addr, 703 const MCDisassembler *Decoder) { 704 if (RegNo > 31) 705 return Fail; 706 unsigned Register = 707 AArch64MCRegisterClasses[AArch64::DDRegClassID].getRegister(RegNo); 708 Inst.addOperand(MCOperand::createReg(Register)); 709 return Success; 710 } 711 712 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, 713 uint64_t Addr, 714 const MCDisassembler *Decoder) { 715 if (RegNo > 31) 716 return Fail; 717 unsigned Register = 718 AArch64MCRegisterClasses[AArch64::DDDRegClassID].getRegister(RegNo); 719 Inst.addOperand(MCOperand::createReg(Register)); 720 return Success; 721 } 722 723 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, 724 uint64_t Addr, 725 const MCDisassembler *Decoder) { 726 if (RegNo > 31) 727 return Fail; 728 unsigned Register = 729 AArch64MCRegisterClasses[AArch64::DDDDRegClassID].getRegister(RegNo); 730 Inst.addOperand(MCOperand::createReg(Register)); 731 return Success; 732 } 733 734 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, 735 uint64_t Addr, 736 const MCDisassembler *Decoder) { 737 // scale{5} is asserted as 1 in tblgen. 738 Imm |= 0x20; 739 Inst.addOperand(MCOperand::createImm(64 - Imm)); 740 return Success; 741 } 742 743 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, 744 uint64_t Addr, 745 const MCDisassembler *Decoder) { 746 Inst.addOperand(MCOperand::createImm(64 - Imm)); 747 return Success; 748 } 749 750 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, 751 uint64_t Addr, 752 const MCDisassembler *Decoder) { 753 int64_t ImmVal = Imm; 754 755 // Sign-extend 19-bit immediate. 756 if (ImmVal & (1 << (19 - 1))) 757 ImmVal |= ~((1LL << 19) - 1); 758 759 if (!Decoder->tryAddingSymbolicOperand( 760 Inst, ImmVal * 4, Addr, Inst.getOpcode() != AArch64::LDRXl, 0, 0, 4)) 761 Inst.addOperand(MCOperand::createImm(ImmVal)); 762 return Success; 763 } 764 765 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, 766 uint64_t Address, 767 const MCDisassembler *Decoder) { 768 Inst.addOperand(MCOperand::createImm((Imm >> 1) & 1)); 769 Inst.addOperand(MCOperand::createImm(Imm & 1)); 770 return Success; 771 } 772 773 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, 774 uint64_t Address, 775 const MCDisassembler *Decoder) { 776 Inst.addOperand(MCOperand::createImm(Imm)); 777 778 // Every system register in the encoding space is valid with the syntax 779 // S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds. 780 return Success; 781 } 782 783 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, 784 uint64_t Address, 785 const MCDisassembler *Decoder) { 786 Inst.addOperand(MCOperand::createImm(Imm)); 787 788 return Success; 789 } 790 791 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, 792 uint64_t Address, 793 const MCDisassembler *Decoder) { 794 // This decoder exists to add the dummy Lane operand to the MCInst, which must 795 // be 1 in assembly but has no other real manifestation. 796 unsigned Rd = fieldFromInstruction(Insn, 0, 5); 797 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 798 unsigned IsToVec = fieldFromInstruction(Insn, 16, 1); 799 800 if (IsToVec) { 801 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder); 802 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder); 803 } else { 804 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder); 805 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder); 806 } 807 808 // Add the lane 809 Inst.addOperand(MCOperand::createImm(1)); 810 811 return Success; 812 } 813 814 static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm, 815 unsigned Add) { 816 Inst.addOperand(MCOperand::createImm(Add - Imm)); 817 return Success; 818 } 819 820 static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm, 821 unsigned Add) { 822 Inst.addOperand(MCOperand::createImm((Imm + Add) & (Add - 1))); 823 return Success; 824 } 825 826 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, 827 uint64_t Addr, 828 const MCDisassembler *Decoder) { 829 return DecodeVecShiftRImm(Inst, Imm, 64); 830 } 831 832 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, 833 uint64_t Addr, 834 const MCDisassembler *Decoder) { 835 return DecodeVecShiftRImm(Inst, Imm | 0x20, 64); 836 } 837 838 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, 839 uint64_t Addr, 840 const MCDisassembler *Decoder) { 841 return DecodeVecShiftRImm(Inst, Imm, 32); 842 } 843 844 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, 845 uint64_t Addr, 846 const MCDisassembler *Decoder) { 847 return DecodeVecShiftRImm(Inst, Imm | 0x10, 32); 848 } 849 850 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, 851 uint64_t Addr, 852 const MCDisassembler *Decoder) { 853 return DecodeVecShiftRImm(Inst, Imm, 16); 854 } 855 856 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, 857 uint64_t Addr, 858 const MCDisassembler *Decoder) { 859 return DecodeVecShiftRImm(Inst, Imm | 0x8, 16); 860 } 861 862 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, 863 uint64_t Addr, 864 const MCDisassembler *Decoder) { 865 return DecodeVecShiftRImm(Inst, Imm, 8); 866 } 867 868 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, 869 uint64_t Addr, 870 const MCDisassembler *Decoder) { 871 return DecodeVecShiftLImm(Inst, Imm, 64); 872 } 873 874 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, 875 uint64_t Addr, 876 const MCDisassembler *Decoder) { 877 return DecodeVecShiftLImm(Inst, Imm, 32); 878 } 879 880 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, 881 uint64_t Addr, 882 const MCDisassembler *Decoder) { 883 return DecodeVecShiftLImm(Inst, Imm, 16); 884 } 885 886 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, 887 uint64_t Addr, 888 const MCDisassembler *Decoder) { 889 return DecodeVecShiftLImm(Inst, Imm, 8); 890 } 891 892 static DecodeStatus 893 DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, 894 const MCDisassembler *Decoder) { 895 unsigned Rd = fieldFromInstruction(insn, 0, 5); 896 unsigned Rn = fieldFromInstruction(insn, 5, 5); 897 unsigned Rm = fieldFromInstruction(insn, 16, 5); 898 unsigned shiftHi = fieldFromInstruction(insn, 22, 2); 899 unsigned shiftLo = fieldFromInstruction(insn, 10, 6); 900 unsigned shift = (shiftHi << 6) | shiftLo; 901 switch (Inst.getOpcode()) { 902 default: 903 return Fail; 904 case AArch64::ADDWrs: 905 case AArch64::ADDSWrs: 906 case AArch64::SUBWrs: 907 case AArch64::SUBSWrs: 908 // if shift == '11' then ReservedValue() 909 if (shiftHi == 0x3) 910 return Fail; 911 LLVM_FALLTHROUGH; 912 case AArch64::ANDWrs: 913 case AArch64::ANDSWrs: 914 case AArch64::BICWrs: 915 case AArch64::BICSWrs: 916 case AArch64::ORRWrs: 917 case AArch64::ORNWrs: 918 case AArch64::EORWrs: 919 case AArch64::EONWrs: { 920 // if sf == '0' and imm6<5> == '1' then ReservedValue() 921 if (shiftLo >> 5 == 1) 922 return Fail; 923 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 924 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); 925 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 926 break; 927 } 928 case AArch64::ADDXrs: 929 case AArch64::ADDSXrs: 930 case AArch64::SUBXrs: 931 case AArch64::SUBSXrs: 932 // if shift == '11' then ReservedValue() 933 if (shiftHi == 0x3) 934 return Fail; 935 LLVM_FALLTHROUGH; 936 case AArch64::ANDXrs: 937 case AArch64::ANDSXrs: 938 case AArch64::BICXrs: 939 case AArch64::BICSXrs: 940 case AArch64::ORRXrs: 941 case AArch64::ORNXrs: 942 case AArch64::EORXrs: 943 case AArch64::EONXrs: 944 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 945 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); 946 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 947 break; 948 } 949 950 Inst.addOperand(MCOperand::createImm(shift)); 951 return Success; 952 } 953 954 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, 955 uint64_t Addr, 956 const MCDisassembler *Decoder) { 957 unsigned Rd = fieldFromInstruction(insn, 0, 5); 958 unsigned imm = fieldFromInstruction(insn, 5, 16); 959 unsigned shift = fieldFromInstruction(insn, 21, 2); 960 shift <<= 4; 961 switch (Inst.getOpcode()) { 962 default: 963 return Fail; 964 case AArch64::MOVZWi: 965 case AArch64::MOVNWi: 966 case AArch64::MOVKWi: 967 if (shift & (1U << 5)) 968 return Fail; 969 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 970 break; 971 case AArch64::MOVZXi: 972 case AArch64::MOVNXi: 973 case AArch64::MOVKXi: 974 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 975 break; 976 } 977 978 if (Inst.getOpcode() == AArch64::MOVKWi || 979 Inst.getOpcode() == AArch64::MOVKXi) 980 Inst.addOperand(Inst.getOperand(0)); 981 982 Inst.addOperand(MCOperand::createImm(imm)); 983 Inst.addOperand(MCOperand::createImm(shift)); 984 return Success; 985 } 986 987 static DecodeStatus 988 DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, 989 const MCDisassembler *Decoder) { 990 unsigned Rt = fieldFromInstruction(insn, 0, 5); 991 unsigned Rn = fieldFromInstruction(insn, 5, 5); 992 unsigned offset = fieldFromInstruction(insn, 10, 12); 993 994 switch (Inst.getOpcode()) { 995 default: 996 return Fail; 997 case AArch64::PRFMui: 998 // Rt is an immediate in prefetch. 999 Inst.addOperand(MCOperand::createImm(Rt)); 1000 break; 1001 case AArch64::STRBBui: 1002 case AArch64::LDRBBui: 1003 case AArch64::LDRSBWui: 1004 case AArch64::STRHHui: 1005 case AArch64::LDRHHui: 1006 case AArch64::LDRSHWui: 1007 case AArch64::STRWui: 1008 case AArch64::LDRWui: 1009 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1010 break; 1011 case AArch64::LDRSBXui: 1012 case AArch64::LDRSHXui: 1013 case AArch64::LDRSWui: 1014 case AArch64::STRXui: 1015 case AArch64::LDRXui: 1016 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1017 break; 1018 case AArch64::LDRQui: 1019 case AArch64::STRQui: 1020 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1021 break; 1022 case AArch64::LDRDui: 1023 case AArch64::STRDui: 1024 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1025 break; 1026 case AArch64::LDRSui: 1027 case AArch64::STRSui: 1028 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1029 break; 1030 case AArch64::LDRHui: 1031 case AArch64::STRHui: 1032 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); 1033 break; 1034 case AArch64::LDRBui: 1035 case AArch64::STRBui: 1036 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); 1037 break; 1038 } 1039 1040 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1041 if (!Decoder->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 0, 4)) 1042 Inst.addOperand(MCOperand::createImm(offset)); 1043 return Success; 1044 } 1045 1046 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, 1047 uint64_t Addr, 1048 const MCDisassembler *Decoder) { 1049 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1050 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1051 int64_t offset = fieldFromInstruction(insn, 12, 9); 1052 1053 // offset is a 9-bit signed immediate, so sign extend it to 1054 // fill the unsigned. 1055 if (offset & (1 << (9 - 1))) 1056 offset |= ~((1LL << 9) - 1); 1057 1058 // First operand is always the writeback to the address register, if needed. 1059 switch (Inst.getOpcode()) { 1060 default: 1061 break; 1062 case AArch64::LDRSBWpre: 1063 case AArch64::LDRSHWpre: 1064 case AArch64::STRBBpre: 1065 case AArch64::LDRBBpre: 1066 case AArch64::STRHHpre: 1067 case AArch64::LDRHHpre: 1068 case AArch64::STRWpre: 1069 case AArch64::LDRWpre: 1070 case AArch64::LDRSBWpost: 1071 case AArch64::LDRSHWpost: 1072 case AArch64::STRBBpost: 1073 case AArch64::LDRBBpost: 1074 case AArch64::STRHHpost: 1075 case AArch64::LDRHHpost: 1076 case AArch64::STRWpost: 1077 case AArch64::LDRWpost: 1078 case AArch64::LDRSBXpre: 1079 case AArch64::LDRSHXpre: 1080 case AArch64::STRXpre: 1081 case AArch64::LDRSWpre: 1082 case AArch64::LDRXpre: 1083 case AArch64::LDRSBXpost: 1084 case AArch64::LDRSHXpost: 1085 case AArch64::STRXpost: 1086 case AArch64::LDRSWpost: 1087 case AArch64::LDRXpost: 1088 case AArch64::LDRQpre: 1089 case AArch64::STRQpre: 1090 case AArch64::LDRQpost: 1091 case AArch64::STRQpost: 1092 case AArch64::LDRDpre: 1093 case AArch64::STRDpre: 1094 case AArch64::LDRDpost: 1095 case AArch64::STRDpost: 1096 case AArch64::LDRSpre: 1097 case AArch64::STRSpre: 1098 case AArch64::LDRSpost: 1099 case AArch64::STRSpost: 1100 case AArch64::LDRHpre: 1101 case AArch64::STRHpre: 1102 case AArch64::LDRHpost: 1103 case AArch64::STRHpost: 1104 case AArch64::LDRBpre: 1105 case AArch64::STRBpre: 1106 case AArch64::LDRBpost: 1107 case AArch64::STRBpost: 1108 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1109 break; 1110 } 1111 1112 switch (Inst.getOpcode()) { 1113 default: 1114 return Fail; 1115 case AArch64::PRFUMi: 1116 // Rt is an immediate in prefetch. 1117 Inst.addOperand(MCOperand::createImm(Rt)); 1118 break; 1119 case AArch64::STURBBi: 1120 case AArch64::LDURBBi: 1121 case AArch64::LDURSBWi: 1122 case AArch64::STURHHi: 1123 case AArch64::LDURHHi: 1124 case AArch64::LDURSHWi: 1125 case AArch64::STURWi: 1126 case AArch64::LDURWi: 1127 case AArch64::LDTRSBWi: 1128 case AArch64::LDTRSHWi: 1129 case AArch64::STTRWi: 1130 case AArch64::LDTRWi: 1131 case AArch64::STTRHi: 1132 case AArch64::LDTRHi: 1133 case AArch64::LDTRBi: 1134 case AArch64::STTRBi: 1135 case AArch64::LDRSBWpre: 1136 case AArch64::LDRSHWpre: 1137 case AArch64::STRBBpre: 1138 case AArch64::LDRBBpre: 1139 case AArch64::STRHHpre: 1140 case AArch64::LDRHHpre: 1141 case AArch64::STRWpre: 1142 case AArch64::LDRWpre: 1143 case AArch64::LDRSBWpost: 1144 case AArch64::LDRSHWpost: 1145 case AArch64::STRBBpost: 1146 case AArch64::LDRBBpost: 1147 case AArch64::STRHHpost: 1148 case AArch64::LDRHHpost: 1149 case AArch64::STRWpost: 1150 case AArch64::LDRWpost: 1151 case AArch64::STLURBi: 1152 case AArch64::STLURHi: 1153 case AArch64::STLURWi: 1154 case AArch64::LDAPURBi: 1155 case AArch64::LDAPURSBWi: 1156 case AArch64::LDAPURHi: 1157 case AArch64::LDAPURSHWi: 1158 case AArch64::LDAPURi: 1159 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1160 break; 1161 case AArch64::LDURSBXi: 1162 case AArch64::LDURSHXi: 1163 case AArch64::LDURSWi: 1164 case AArch64::STURXi: 1165 case AArch64::LDURXi: 1166 case AArch64::LDTRSBXi: 1167 case AArch64::LDTRSHXi: 1168 case AArch64::LDTRSWi: 1169 case AArch64::STTRXi: 1170 case AArch64::LDTRXi: 1171 case AArch64::LDRSBXpre: 1172 case AArch64::LDRSHXpre: 1173 case AArch64::STRXpre: 1174 case AArch64::LDRSWpre: 1175 case AArch64::LDRXpre: 1176 case AArch64::LDRSBXpost: 1177 case AArch64::LDRSHXpost: 1178 case AArch64::STRXpost: 1179 case AArch64::LDRSWpost: 1180 case AArch64::LDRXpost: 1181 case AArch64::LDAPURSWi: 1182 case AArch64::LDAPURSHXi: 1183 case AArch64::LDAPURSBXi: 1184 case AArch64::STLURXi: 1185 case AArch64::LDAPURXi: 1186 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1187 break; 1188 case AArch64::LDURQi: 1189 case AArch64::STURQi: 1190 case AArch64::LDRQpre: 1191 case AArch64::STRQpre: 1192 case AArch64::LDRQpost: 1193 case AArch64::STRQpost: 1194 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1195 break; 1196 case AArch64::LDURDi: 1197 case AArch64::STURDi: 1198 case AArch64::LDRDpre: 1199 case AArch64::STRDpre: 1200 case AArch64::LDRDpost: 1201 case AArch64::STRDpost: 1202 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1203 break; 1204 case AArch64::LDURSi: 1205 case AArch64::STURSi: 1206 case AArch64::LDRSpre: 1207 case AArch64::STRSpre: 1208 case AArch64::LDRSpost: 1209 case AArch64::STRSpost: 1210 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1211 break; 1212 case AArch64::LDURHi: 1213 case AArch64::STURHi: 1214 case AArch64::LDRHpre: 1215 case AArch64::STRHpre: 1216 case AArch64::LDRHpost: 1217 case AArch64::STRHpost: 1218 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); 1219 break; 1220 case AArch64::LDURBi: 1221 case AArch64::STURBi: 1222 case AArch64::LDRBpre: 1223 case AArch64::STRBpre: 1224 case AArch64::LDRBpost: 1225 case AArch64::STRBpost: 1226 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); 1227 break; 1228 } 1229 1230 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1231 Inst.addOperand(MCOperand::createImm(offset)); 1232 1233 bool IsLoad = fieldFromInstruction(insn, 22, 1); 1234 bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0; 1235 bool IsFP = fieldFromInstruction(insn, 26, 1); 1236 1237 // Cannot write back to a transfer register (but xzr != sp). 1238 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn) 1239 return SoftFail; 1240 1241 return Success; 1242 } 1243 1244 static DecodeStatus 1245 DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, 1246 const MCDisassembler *Decoder) { 1247 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1248 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1249 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); 1250 unsigned Rs = fieldFromInstruction(insn, 16, 5); 1251 1252 unsigned Opcode = Inst.getOpcode(); 1253 switch (Opcode) { 1254 default: 1255 return Fail; 1256 case AArch64::STLXRW: 1257 case AArch64::STLXRB: 1258 case AArch64::STLXRH: 1259 case AArch64::STXRW: 1260 case AArch64::STXRB: 1261 case AArch64::STXRH: 1262 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1263 LLVM_FALLTHROUGH; 1264 case AArch64::LDARW: 1265 case AArch64::LDARB: 1266 case AArch64::LDARH: 1267 case AArch64::LDAXRW: 1268 case AArch64::LDAXRB: 1269 case AArch64::LDAXRH: 1270 case AArch64::LDXRW: 1271 case AArch64::LDXRB: 1272 case AArch64::LDXRH: 1273 case AArch64::STLRW: 1274 case AArch64::STLRB: 1275 case AArch64::STLRH: 1276 case AArch64::STLLRW: 1277 case AArch64::STLLRB: 1278 case AArch64::STLLRH: 1279 case AArch64::LDLARW: 1280 case AArch64::LDLARB: 1281 case AArch64::LDLARH: 1282 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1283 break; 1284 case AArch64::STLXRX: 1285 case AArch64::STXRX: 1286 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1287 LLVM_FALLTHROUGH; 1288 case AArch64::LDARX: 1289 case AArch64::LDAXRX: 1290 case AArch64::LDXRX: 1291 case AArch64::STLRX: 1292 case AArch64::LDLARX: 1293 case AArch64::STLLRX: 1294 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1295 break; 1296 case AArch64::STLXPW: 1297 case AArch64::STXPW: 1298 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1299 LLVM_FALLTHROUGH; 1300 case AArch64::LDAXPW: 1301 case AArch64::LDXPW: 1302 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1303 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1304 break; 1305 case AArch64::STLXPX: 1306 case AArch64::STXPX: 1307 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1308 LLVM_FALLTHROUGH; 1309 case AArch64::LDAXPX: 1310 case AArch64::LDXPX: 1311 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1312 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1313 break; 1314 } 1315 1316 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1317 1318 // You shouldn't load to the same register twice in an instruction... 1319 if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW || 1320 Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) && 1321 Rt == Rt2) 1322 return SoftFail; 1323 1324 return Success; 1325 } 1326 1327 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, 1328 uint64_t Addr, 1329 const MCDisassembler *Decoder) { 1330 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1331 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1332 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); 1333 int64_t offset = fieldFromInstruction(insn, 15, 7); 1334 bool IsLoad = fieldFromInstruction(insn, 22, 1); 1335 1336 // offset is a 7-bit signed immediate, so sign extend it to 1337 // fill the unsigned. 1338 if (offset & (1 << (7 - 1))) 1339 offset |= ~((1LL << 7) - 1); 1340 1341 unsigned Opcode = Inst.getOpcode(); 1342 bool NeedsDisjointWritebackTransfer = false; 1343 1344 // First operand is always writeback of base register. 1345 switch (Opcode) { 1346 default: 1347 break; 1348 case AArch64::LDPXpost: 1349 case AArch64::STPXpost: 1350 case AArch64::LDPSWpost: 1351 case AArch64::LDPXpre: 1352 case AArch64::STPXpre: 1353 case AArch64::LDPSWpre: 1354 case AArch64::LDPWpost: 1355 case AArch64::STPWpost: 1356 case AArch64::LDPWpre: 1357 case AArch64::STPWpre: 1358 case AArch64::LDPQpost: 1359 case AArch64::STPQpost: 1360 case AArch64::LDPQpre: 1361 case AArch64::STPQpre: 1362 case AArch64::LDPDpost: 1363 case AArch64::STPDpost: 1364 case AArch64::LDPDpre: 1365 case AArch64::STPDpre: 1366 case AArch64::LDPSpost: 1367 case AArch64::STPSpost: 1368 case AArch64::LDPSpre: 1369 case AArch64::STPSpre: 1370 case AArch64::STGPpre: 1371 case AArch64::STGPpost: 1372 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1373 break; 1374 } 1375 1376 switch (Opcode) { 1377 default: 1378 return Fail; 1379 case AArch64::LDPXpost: 1380 case AArch64::STPXpost: 1381 case AArch64::LDPSWpost: 1382 case AArch64::LDPXpre: 1383 case AArch64::STPXpre: 1384 case AArch64::LDPSWpre: 1385 case AArch64::STGPpre: 1386 case AArch64::STGPpost: 1387 NeedsDisjointWritebackTransfer = true; 1388 LLVM_FALLTHROUGH; 1389 case AArch64::LDNPXi: 1390 case AArch64::STNPXi: 1391 case AArch64::LDPXi: 1392 case AArch64::STPXi: 1393 case AArch64::LDPSWi: 1394 case AArch64::STGPi: 1395 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1396 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1397 break; 1398 case AArch64::LDPWpost: 1399 case AArch64::STPWpost: 1400 case AArch64::LDPWpre: 1401 case AArch64::STPWpre: 1402 NeedsDisjointWritebackTransfer = true; 1403 LLVM_FALLTHROUGH; 1404 case AArch64::LDNPWi: 1405 case AArch64::STNPWi: 1406 case AArch64::LDPWi: 1407 case AArch64::STPWi: 1408 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1409 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1410 break; 1411 case AArch64::LDNPQi: 1412 case AArch64::STNPQi: 1413 case AArch64::LDPQpost: 1414 case AArch64::STPQpost: 1415 case AArch64::LDPQi: 1416 case AArch64::STPQi: 1417 case AArch64::LDPQpre: 1418 case AArch64::STPQpre: 1419 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1420 DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder); 1421 break; 1422 case AArch64::LDNPDi: 1423 case AArch64::STNPDi: 1424 case AArch64::LDPDpost: 1425 case AArch64::STPDpost: 1426 case AArch64::LDPDi: 1427 case AArch64::STPDi: 1428 case AArch64::LDPDpre: 1429 case AArch64::STPDpre: 1430 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1431 DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1432 break; 1433 case AArch64::LDNPSi: 1434 case AArch64::STNPSi: 1435 case AArch64::LDPSpost: 1436 case AArch64::STPSpost: 1437 case AArch64::LDPSi: 1438 case AArch64::STPSi: 1439 case AArch64::LDPSpre: 1440 case AArch64::STPSpre: 1441 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1442 DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1443 break; 1444 } 1445 1446 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1447 Inst.addOperand(MCOperand::createImm(offset)); 1448 1449 // You shouldn't load to the same register twice in an instruction... 1450 if (IsLoad && Rt == Rt2) 1451 return SoftFail; 1452 1453 // ... or do any operation that writes-back to a transfer register. But note 1454 // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different. 1455 if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn)) 1456 return SoftFail; 1457 1458 return Success; 1459 } 1460 1461 static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn, 1462 uint64_t Addr, 1463 const MCDisassembler *Decoder) { 1464 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1465 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1466 uint64_t offset = fieldFromInstruction(insn, 22, 1) << 9 | 1467 fieldFromInstruction(insn, 12, 9); 1468 unsigned writeback = fieldFromInstruction(insn, 11, 1); 1469 1470 switch (Inst.getOpcode()) { 1471 default: 1472 return Fail; 1473 case AArch64::LDRAAwriteback: 1474 case AArch64::LDRABwriteback: 1475 DecodeGPR64spRegisterClass(Inst, Rn /* writeback register */, Addr, 1476 Decoder); 1477 break; 1478 case AArch64::LDRAAindexed: 1479 case AArch64::LDRABindexed: 1480 break; 1481 } 1482 1483 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1484 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1485 DecodeSImm<10>(Inst, offset, Addr, Decoder); 1486 1487 if (writeback && Rt == Rn && Rn != 31) { 1488 return SoftFail; 1489 } 1490 1491 return Success; 1492 } 1493 1494 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, 1495 uint64_t Addr, 1496 const MCDisassembler *Decoder) { 1497 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1498 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1499 unsigned Rm = fieldFromInstruction(insn, 16, 5); 1500 unsigned extend = fieldFromInstruction(insn, 10, 6); 1501 1502 unsigned shift = extend & 0x7; 1503 if (shift > 4) 1504 return Fail; 1505 1506 switch (Inst.getOpcode()) { 1507 default: 1508 return Fail; 1509 case AArch64::ADDWrx: 1510 case AArch64::SUBWrx: 1511 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1512 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1513 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1514 break; 1515 case AArch64::ADDSWrx: 1516 case AArch64::SUBSWrx: 1517 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1518 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1519 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1520 break; 1521 case AArch64::ADDXrx: 1522 case AArch64::SUBXrx: 1523 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1524 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1525 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1526 break; 1527 case AArch64::ADDSXrx: 1528 case AArch64::SUBSXrx: 1529 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1530 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1531 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1532 break; 1533 case AArch64::ADDXrx64: 1534 case AArch64::SUBXrx64: 1535 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1536 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1537 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1538 break; 1539 case AArch64::SUBSXrx64: 1540 case AArch64::ADDSXrx64: 1541 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1542 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1543 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1544 break; 1545 } 1546 1547 Inst.addOperand(MCOperand::createImm(extend)); 1548 return Success; 1549 } 1550 1551 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, 1552 uint64_t Addr, 1553 const MCDisassembler *Decoder) { 1554 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1555 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1556 unsigned Datasize = fieldFromInstruction(insn, 31, 1); 1557 unsigned imm; 1558 1559 if (Datasize) { 1560 if (Inst.getOpcode() == AArch64::ANDSXri) 1561 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1562 else 1563 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1564 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); 1565 imm = fieldFromInstruction(insn, 10, 13); 1566 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64)) 1567 return Fail; 1568 } else { 1569 if (Inst.getOpcode() == AArch64::ANDSWri) 1570 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1571 else 1572 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1573 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); 1574 imm = fieldFromInstruction(insn, 10, 12); 1575 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32)) 1576 return Fail; 1577 } 1578 Inst.addOperand(MCOperand::createImm(imm)); 1579 return Success; 1580 } 1581 1582 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, 1583 uint64_t Addr, 1584 const MCDisassembler *Decoder) { 1585 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1586 unsigned cmode = fieldFromInstruction(insn, 12, 4); 1587 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; 1588 imm |= fieldFromInstruction(insn, 5, 5); 1589 1590 if (Inst.getOpcode() == AArch64::MOVID) 1591 DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder); 1592 else 1593 DecodeFPR128RegisterClass(Inst, Rd, Addr, Decoder); 1594 1595 Inst.addOperand(MCOperand::createImm(imm)); 1596 1597 switch (Inst.getOpcode()) { 1598 default: 1599 break; 1600 case AArch64::MOVIv4i16: 1601 case AArch64::MOVIv8i16: 1602 case AArch64::MVNIv4i16: 1603 case AArch64::MVNIv8i16: 1604 case AArch64::MOVIv2i32: 1605 case AArch64::MOVIv4i32: 1606 case AArch64::MVNIv2i32: 1607 case AArch64::MVNIv4i32: 1608 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2)); 1609 break; 1610 case AArch64::MOVIv2s_msl: 1611 case AArch64::MOVIv4s_msl: 1612 case AArch64::MVNIv2s_msl: 1613 case AArch64::MVNIv4s_msl: 1614 Inst.addOperand(MCOperand::createImm((cmode & 1) ? 0x110 : 0x108)); 1615 break; 1616 } 1617 1618 return Success; 1619 } 1620 1621 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, 1622 uint64_t Addr, 1623 const MCDisassembler *Decoder) { 1624 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1625 unsigned cmode = fieldFromInstruction(insn, 12, 4); 1626 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; 1627 imm |= fieldFromInstruction(insn, 5, 5); 1628 1629 // Tied operands added twice. 1630 DecodeFPR128RegisterClass(Inst, Rd, Addr, Decoder); 1631 DecodeFPR128RegisterClass(Inst, Rd, Addr, Decoder); 1632 1633 Inst.addOperand(MCOperand::createImm(imm)); 1634 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2)); 1635 1636 return Success; 1637 } 1638 1639 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, 1640 uint64_t Addr, 1641 const MCDisassembler *Decoder) { 1642 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1643 int64_t imm = fieldFromInstruction(insn, 5, 19) << 2; 1644 imm |= fieldFromInstruction(insn, 29, 2); 1645 1646 // Sign-extend the 21-bit immediate. 1647 if (imm & (1 << (21 - 1))) 1648 imm |= ~((1LL << 21) - 1); 1649 1650 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1651 if (!Decoder->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 0, 4)) 1652 Inst.addOperand(MCOperand::createImm(imm)); 1653 1654 return Success; 1655 } 1656 1657 static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn, 1658 uint64_t Addr, 1659 const MCDisassembler *Decoder) { 1660 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1661 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1662 unsigned Imm = fieldFromInstruction(insn, 10, 14); 1663 unsigned S = fieldFromInstruction(insn, 29, 1); 1664 unsigned Datasize = fieldFromInstruction(insn, 31, 1); 1665 1666 unsigned ShifterVal = (Imm >> 12) & 3; 1667 unsigned ImmVal = Imm & 0xFFF; 1668 1669 if (ShifterVal != 0 && ShifterVal != 1) 1670 return Fail; 1671 1672 if (Datasize) { 1673 if (Rd == 31 && !S) 1674 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1675 else 1676 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1677 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1678 } else { 1679 if (Rd == 31 && !S) 1680 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1681 else 1682 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1683 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1684 } 1685 1686 if (!Decoder->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 0, 4)) 1687 Inst.addOperand(MCOperand::createImm(ImmVal)); 1688 Inst.addOperand(MCOperand::createImm(12 * ShifterVal)); 1689 return Success; 1690 } 1691 1692 static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, 1693 uint64_t Addr, 1694 const MCDisassembler *Decoder) { 1695 int64_t imm = fieldFromInstruction(insn, 0, 26); 1696 1697 // Sign-extend the 26-bit immediate. 1698 if (imm & (1 << (26 - 1))) 1699 imm |= ~((1LL << 26) - 1); 1700 1701 if (!Decoder->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 0, 4)) 1702 Inst.addOperand(MCOperand::createImm(imm)); 1703 1704 return Success; 1705 } 1706 1707 static DecodeStatus 1708 DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, 1709 const MCDisassembler *Decoder) { 1710 uint64_t op1 = fieldFromInstruction(insn, 16, 3); 1711 uint64_t op2 = fieldFromInstruction(insn, 5, 3); 1712 uint64_t crm = fieldFromInstruction(insn, 8, 4); 1713 uint64_t pstate_field = (op1 << 3) | op2; 1714 1715 switch (pstate_field) { 1716 case 0x01: // XAFlag 1717 case 0x02: // AXFlag 1718 return Fail; 1719 } 1720 1721 if ((pstate_field == AArch64PState::PAN || 1722 pstate_field == AArch64PState::UAO || 1723 pstate_field == AArch64PState::SSBS) && crm > 1) 1724 return Fail; 1725 1726 Inst.addOperand(MCOperand::createImm(pstate_field)); 1727 Inst.addOperand(MCOperand::createImm(crm)); 1728 1729 auto PState = AArch64PState::lookupPStateByEncoding(pstate_field); 1730 if (PState && 1731 PState->haveFeatures(Decoder->getSubtargetInfo().getFeatureBits())) 1732 return Success; 1733 return Fail; 1734 } 1735 1736 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, 1737 uint64_t Addr, 1738 const MCDisassembler *Decoder) { 1739 uint64_t Rt = fieldFromInstruction(insn, 0, 5); 1740 uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5; 1741 bit |= fieldFromInstruction(insn, 19, 5); 1742 int64_t dst = fieldFromInstruction(insn, 5, 14); 1743 1744 // Sign-extend 14-bit immediate. 1745 if (dst & (1 << (14 - 1))) 1746 dst |= ~((1LL << 14) - 1); 1747 1748 if (fieldFromInstruction(insn, 31, 1) == 0) 1749 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1750 else 1751 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1752 Inst.addOperand(MCOperand::createImm(bit)); 1753 if (!Decoder->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 0, 4)) 1754 Inst.addOperand(MCOperand::createImm(dst)); 1755 1756 return Success; 1757 } 1758 1759 static DecodeStatus 1760 DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegClassID, 1761 unsigned RegNo, uint64_t Addr, 1762 const MCDisassembler *Decoder) { 1763 // Register number must be even (see CASP instruction) 1764 if (RegNo & 0x1) 1765 return Fail; 1766 1767 unsigned Reg = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo / 2); 1768 Inst.addOperand(MCOperand::createReg(Reg)); 1769 return Success; 1770 } 1771 1772 static DecodeStatus 1773 DecodeWSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, 1774 const MCDisassembler *Decoder) { 1775 return DecodeGPRSeqPairsClassRegisterClass(Inst, 1776 AArch64::WSeqPairsClassRegClassID, 1777 RegNo, Addr, Decoder); 1778 } 1779 1780 static DecodeStatus 1781 DecodeXSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, 1782 const MCDisassembler *Decoder) { 1783 return DecodeGPRSeqPairsClassRegisterClass(Inst, 1784 AArch64::XSeqPairsClassRegClassID, 1785 RegNo, Addr, Decoder); 1786 } 1787 1788 static DecodeStatus 1789 DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, 1790 const MCDisassembler *Decoder) { 1791 unsigned Zdn = fieldFromInstruction(insn, 0, 5); 1792 unsigned imm = fieldFromInstruction(insn, 5, 13); 1793 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64)) 1794 return Fail; 1795 1796 // The same (tied) operand is added twice to the instruction. 1797 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); 1798 if (Inst.getOpcode() != AArch64::DUPM_ZI) 1799 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); 1800 Inst.addOperand(MCOperand::createImm(imm)); 1801 return Success; 1802 } 1803 1804 template <int Bits> 1805 static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address, 1806 const MCDisassembler *Decoder) { 1807 if (Imm & ~((1LL << Bits) - 1)) 1808 return Fail; 1809 1810 // Imm is a signed immediate, so sign extend it. 1811 if (Imm & (1 << (Bits - 1))) 1812 Imm |= ~((1LL << Bits) - 1); 1813 1814 Inst.addOperand(MCOperand::createImm(Imm)); 1815 return Success; 1816 } 1817 1818 // Decode 8-bit signed/unsigned immediate for a given element width. 1819 template <int ElementWidth> 1820 static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, uint64_t Addr, 1821 const MCDisassembler *Decoder) { 1822 unsigned Val = (uint8_t)Imm; 1823 unsigned Shift = (Imm & 0x100) ? 8 : 0; 1824 if (ElementWidth == 8 && Shift) 1825 return Fail; 1826 Inst.addOperand(MCOperand::createImm(Val)); 1827 Inst.addOperand(MCOperand::createImm(Shift)); 1828 return Success; 1829 } 1830 1831 // Decode uimm4 ranged from 1-16. 1832 static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, 1833 uint64_t Addr, 1834 const MCDisassembler *Decoder) { 1835 Inst.addOperand(MCOperand::createImm(Imm + 1)); 1836 return Success; 1837 } 1838 1839 static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address, 1840 const MCDisassembler *Decoder) { 1841 if (AArch64SVCR::lookupSVCRByEncoding(Imm)) { 1842 Inst.addOperand(MCOperand::createImm(Imm)); 1843 return Success; 1844 } 1845 return Fail; 1846 } 1847 1848 static DecodeStatus DecodeCPYMemOpInstruction(MCInst &Inst, uint32_t insn, 1849 uint64_t Addr, 1850 const MCDisassembler *Decoder) { 1851 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1852 unsigned Rs = fieldFromInstruction(insn, 16, 5); 1853 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1854 1855 // None of the registers may alias: if they do, then the instruction is not 1856 // merely unpredictable but actually entirely unallocated. 1857 if (Rd == Rs || Rs == Rn || Rd == Rn) 1858 return MCDisassembler::Fail; 1859 1860 // All three register operands are written back, so they all appear 1861 // twice in the operand list, once as outputs and once as inputs. 1862 if (!DecodeGPR64commonRegisterClass(Inst, Rd, Addr, Decoder) || 1863 !DecodeGPR64commonRegisterClass(Inst, Rs, Addr, Decoder) || 1864 !DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder) || 1865 !DecodeGPR64commonRegisterClass(Inst, Rd, Addr, Decoder) || 1866 !DecodeGPR64commonRegisterClass(Inst, Rs, Addr, Decoder) || 1867 !DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder)) 1868 return MCDisassembler::Fail; 1869 1870 return MCDisassembler::Success; 1871 } 1872 1873 static DecodeStatus DecodeSETMemOpInstruction(MCInst &Inst, uint32_t insn, 1874 uint64_t Addr, 1875 const MCDisassembler *Decoder) { 1876 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1877 unsigned Rm = fieldFromInstruction(insn, 16, 5); 1878 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1879 1880 // None of the registers may alias: if they do, then the instruction is not 1881 // merely unpredictable but actually entirely unallocated. 1882 if (Rd == Rm || Rm == Rn || Rd == Rn) 1883 return MCDisassembler::Fail; 1884 1885 // Rd and Rn (not Rm) register operands are written back, so they appear 1886 // twice in the operand list, once as outputs and once as inputs. 1887 if (!DecodeGPR64commonRegisterClass(Inst, Rd, Addr, Decoder) || 1888 !DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder) || 1889 !DecodeGPR64commonRegisterClass(Inst, Rd, Addr, Decoder) || 1890 !DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder) || 1891 !DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder)) 1892 return MCDisassembler::Fail; 1893 1894 return MCDisassembler::Success; 1895 } 1896