1 //===- AArch64Disassembler.cpp - Disassembler for AArch64 -----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // 10 //===----------------------------------------------------------------------===// 11 12 #include "AArch64Disassembler.h" 13 #include "AArch64ExternalSymbolizer.h" 14 #include "MCTargetDesc/AArch64AddressingModes.h" 15 #include "MCTargetDesc/AArch64MCTargetDesc.h" 16 #include "TargetInfo/AArch64TargetInfo.h" 17 #include "Utils/AArch64BaseInfo.h" 18 #include "llvm-c/Disassembler.h" 19 #include "llvm/MC/MCDecoderOps.h" 20 #include "llvm/MC/MCDisassembler/MCRelocationInfo.h" 21 #include "llvm/MC/MCInst.h" 22 #include "llvm/MC/MCInstrDesc.h" 23 #include "llvm/MC/MCRegisterInfo.h" 24 #include "llvm/MC/MCSubtargetInfo.h" 25 #include "llvm/MC/TargetRegistry.h" 26 #include "llvm/Support/Compiler.h" 27 #include "llvm/Support/Debug.h" 28 #include "llvm/Support/ErrorHandling.h" 29 #include <algorithm> 30 #include <memory> 31 32 using namespace llvm; 33 34 #define DEBUG_TYPE "aarch64-disassembler" 35 36 // Pull DecodeStatus and its enum values into the global namespace. 37 using DecodeStatus = MCDisassembler::DecodeStatus; 38 39 // Forward declare these because the autogenerated code will reference them. 40 // Definitions are further down. 41 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo, 42 uint64_t Address, 43 const MCDisassembler *Decoder); 44 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo, 45 uint64_t Address, 46 const MCDisassembler *Decoder); 47 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, 48 uint64_t Address, 49 const MCDisassembler *Decoder); 50 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, 51 uint64_t Address, 52 const MCDisassembler *Decoder); 53 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, 54 uint64_t Address, 55 const MCDisassembler *Decoder); 56 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, 57 uint64_t Address, 58 const MCDisassembler *Decoder); 59 static DecodeStatus 60 DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 61 const MCDisassembler *Decoder); 62 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, 63 uint64_t Address, 64 const MCDisassembler *Decoder); 65 static DecodeStatus 66 DecodeGPR64x8ClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 67 const MCDisassembler *Decoder); 68 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo, 69 uint64_t Address, 70 const MCDisassembler *Decoder); 71 static DecodeStatus 72 DecodeMatrixIndexGPR32_8_11RegisterClass(MCInst &Inst, unsigned RegNo, 73 uint64_t Address, const void *Decoder); 74 static DecodeStatus 75 DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst, unsigned RegNo, 76 uint64_t Address, 77 const MCDisassembler *Decoder); 78 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, 79 uint64_t Address, 80 const MCDisassembler *Decoder); 81 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo, 82 uint64_t Address, 83 const MCDisassembler *Decoder); 84 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, 85 uint64_t Address, 86 const MCDisassembler *Decoder); 87 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, 88 uint64_t Address, 89 const MCDisassembler *Decoder); 90 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, 91 uint64_t Address, 92 const MCDisassembler *Decoder); 93 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, 94 uint64_t Address, 95 const MCDisassembler *Decoder); 96 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, 97 uint64_t Address, 98 const MCDisassembler *Decoder); 99 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, 100 uint64_t Address, 101 const MCDisassembler *Decoder); 102 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, 103 uint64_t Address, 104 const MCDisassembler *Decoder); 105 static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo, 106 uint64_t Address, 107 const MCDisassembler *Decoder); 108 static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 109 uint64_t Address, 110 const MCDisassembler *Decoder); 111 static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, 112 uint64_t Address, 113 const MCDisassembler *Decoder); 114 static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, 115 uint64_t Address, 116 const MCDisassembler *Decoder); 117 static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, 118 uint64_t Address, 119 const MCDisassembler *Decoder); 120 static DecodeStatus DecodeZPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo, 121 uint64_t Address, 122 const void *Decoder); 123 static DecodeStatus DecodeZPR4Mul4RegisterClass(MCInst &Inst, unsigned RegNo, 124 uint64_t Address, 125 const void *Decoder); 126 static DecodeStatus DecodeZPR2StridedRegisterClass(MCInst &Inst, unsigned RegNo, 127 uint64_t Address, 128 const void *Decoder); 129 static DecodeStatus DecodeZPR4StridedRegisterClass(MCInst &Inst, unsigned RegNo, 130 uint64_t Address, 131 const void *Decoder); 132 template <unsigned NumBitsForTile> 133 static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo, 134 uint64_t Address, 135 const MCDisassembler *Decoder); 136 static DecodeStatus 137 DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask, 138 uint64_t Address, 139 const MCDisassembler *Decoder); 140 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, 141 uint64_t Address, 142 const MCDisassembler *Decoder); 143 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 144 uint64_t Address, 145 const MCDisassembler *Decoder); 146 static DecodeStatus 147 DecodePPR_p8to15RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 148 const MCDisassembler *Decoder); 149 static DecodeStatus DecodePPR2RegisterClass(MCInst &Inst, unsigned RegNo, 150 uint64_t Address, 151 const void *Decoder); 152 static DecodeStatus DecodePPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo, 153 uint64_t Address, 154 const void *Decoder); 155 156 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, 157 uint64_t Address, 158 const MCDisassembler *Decoder); 159 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, 160 uint64_t Address, 161 const MCDisassembler *Decoder); 162 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, 163 uint64_t Address, 164 const MCDisassembler *Decoder); 165 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, 166 uint64_t Address, 167 const MCDisassembler *Decoder); 168 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, 169 uint64_t Address, 170 const MCDisassembler *Decoder); 171 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, 172 uint64_t Address, 173 const MCDisassembler *Decoder); 174 static DecodeStatus 175 DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, 176 const MCDisassembler *Decoder); 177 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, 178 uint64_t Address, 179 const MCDisassembler *Decoder); 180 static DecodeStatus 181 DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, 182 const MCDisassembler *Decoder); 183 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, 184 uint64_t Address, 185 const MCDisassembler *Decoder); 186 static DecodeStatus 187 DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, 188 const MCDisassembler *Decoder); 189 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, 190 uint64_t Address, 191 const MCDisassembler *Decoder); 192 static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn, 193 uint64_t Address, 194 const MCDisassembler *Decoder); 195 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, 196 uint64_t Address, 197 const MCDisassembler *Decoder); 198 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, 199 uint64_t Address, 200 const MCDisassembler *Decoder); 201 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, 202 uint64_t Address, 203 const MCDisassembler *Decoder); 204 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, 205 uint64_t Address, 206 const MCDisassembler *Decoder); 207 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, 208 uint64_t Address, 209 const MCDisassembler *Decoder); 210 static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn, 211 uint64_t Address, 212 const MCDisassembler *Decoder); 213 static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, 214 uint64_t Address, 215 const MCDisassembler *Decoder); 216 static DecodeStatus 217 DecodeSystemPStateImm0_15Instruction(MCInst &Inst, uint32_t insn, 218 uint64_t Address, 219 const MCDisassembler *Decoder); 220 static DecodeStatus 221 DecodeSystemPStateImm0_1Instruction(MCInst &Inst, uint32_t insn, 222 uint64_t Address, 223 const MCDisassembler *Decoder); 224 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, 225 uint64_t Address, 226 const MCDisassembler *Decoder); 227 228 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, 229 uint64_t Address, 230 const MCDisassembler *Decoder); 231 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, 232 uint64_t Addr, 233 const MCDisassembler *Decoder); 234 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, 235 uint64_t Addr, 236 const MCDisassembler *Decoder); 237 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, 238 uint64_t Addr, 239 const MCDisassembler *Decoder); 240 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, 241 uint64_t Addr, 242 const MCDisassembler *Decoder); 243 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, 244 uint64_t Addr, 245 const MCDisassembler *Decoder); 246 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, 247 uint64_t Addr, 248 const MCDisassembler *Decoder); 249 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, 250 uint64_t Addr, 251 const MCDisassembler *Decoder); 252 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, 253 uint64_t Addr, 254 const MCDisassembler *Decoder); 255 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, 256 uint64_t Addr, 257 const MCDisassembler *Decoder); 258 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, 259 uint64_t Addr, 260 const MCDisassembler *Decoder); 261 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, 262 uint64_t Addr, 263 const MCDisassembler *Decoder); 264 static DecodeStatus 265 DecodeWSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, 266 const MCDisassembler *Decoder); 267 static DecodeStatus 268 DecodeXSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, 269 const MCDisassembler *Decoder); 270 static DecodeStatus DecodeSyspXzrInstruction(MCInst &Inst, uint32_t insn, 271 uint64_t Addr, 272 const MCDisassembler *Decoder); 273 static DecodeStatus 274 DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, 275 const MCDisassembler *Decoder); 276 template <int Bits> 277 static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address, 278 const MCDisassembler *Decoder); 279 template <int ElementWidth> 280 static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, uint64_t Addr, 281 const MCDisassembler *Decoder); 282 static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, 283 uint64_t Addr, 284 const MCDisassembler *Decoder); 285 static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address, 286 const MCDisassembler *Decoder); 287 static DecodeStatus DecodeCPYMemOpInstruction(MCInst &Inst, uint32_t insn, 288 uint64_t Addr, 289 const MCDisassembler *Decoder); 290 static DecodeStatus DecodeSETMemOpInstruction(MCInst &Inst, uint32_t insn, 291 uint64_t Addr, 292 const MCDisassembler *Decoder); 293 static DecodeStatus DecodePRFMRegInstruction(MCInst &Inst, uint32_t insn, 294 uint64_t Address, 295 const MCDisassembler *Decoder); 296 297 #include "AArch64GenDisassemblerTables.inc" 298 #include "AArch64GenInstrInfo.inc" 299 300 #define Success MCDisassembler::Success 301 #define Fail MCDisassembler::Fail 302 #define SoftFail MCDisassembler::SoftFail 303 304 static MCDisassembler *createAArch64Disassembler(const Target &T, 305 const MCSubtargetInfo &STI, 306 MCContext &Ctx) { 307 308 return new AArch64Disassembler(STI, Ctx, T.createMCInstrInfo()); 309 } 310 311 DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size, 312 ArrayRef<uint8_t> Bytes, 313 uint64_t Address, 314 raw_ostream &CS) const { 315 CommentStream = &CS; 316 317 Size = 0; 318 // We want to read exactly 4 bytes of data. 319 if (Bytes.size() < 4) 320 return Fail; 321 Size = 4; 322 323 // Encoded as a small-endian 32-bit word in the stream. 324 uint32_t Insn = 325 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 326 327 const uint8_t *Tables[] = {DecoderTable32, DecoderTableFallback32}; 328 329 for (const auto *Table : Tables) { 330 DecodeStatus Result = 331 decodeInstruction(Table, MI, Insn, Address, this, STI); 332 333 const MCInstrDesc &Desc = MCII->get(MI.getOpcode()); 334 335 // For Scalable Matrix Extension (SME) instructions that have an implicit 336 // operand for the accumulator (ZA) or implicit immediate zero which isn't 337 // encoded, manually insert operand. 338 for (unsigned i = 0; i < Desc.getNumOperands(); i++) { 339 if (Desc.operands()[i].OperandType == MCOI::OPERAND_REGISTER) { 340 switch (Desc.operands()[i].RegClass) { 341 default: 342 break; 343 case AArch64::MPRRegClassID: 344 MI.insert(MI.begin() + i, MCOperand::createReg(AArch64::ZA)); 345 break; 346 case AArch64::MPR8RegClassID: 347 MI.insert(MI.begin() + i, MCOperand::createReg(AArch64::ZAB0)); 348 break; 349 case AArch64::ZTRRegClassID: 350 MI.insert(MI.begin() + i, MCOperand::createReg(AArch64::ZT0)); 351 break; 352 } 353 } else if (Desc.operands()[i].OperandType == 354 AArch64::OPERAND_IMPLICIT_IMM_0) { 355 MI.insert(MI.begin() + i, MCOperand::createImm(0)); 356 } 357 } 358 359 if (MI.getOpcode() == AArch64::LDR_ZA || 360 MI.getOpcode() == AArch64::STR_ZA) { 361 // Spill and fill instructions have a single immediate used for both 362 // the vector select offset and optional memory offset. Replicate 363 // the decoded immediate. 364 const MCOperand &Imm4Op = MI.getOperand(2); 365 assert(Imm4Op.isImm() && "Unexpected operand type!"); 366 MI.addOperand(Imm4Op); 367 } 368 369 if (Result != MCDisassembler::Fail) 370 return Result; 371 } 372 373 return MCDisassembler::Fail; 374 } 375 376 uint64_t AArch64Disassembler::suggestBytesToSkip(ArrayRef<uint8_t> Bytes, 377 uint64_t Address) const { 378 // AArch64 instructions are always 4 bytes wide, so there's no point 379 // in skipping any smaller number of bytes if an instruction can't 380 // be decoded. 381 return 4; 382 } 383 384 static MCSymbolizer * 385 createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo, 386 LLVMSymbolLookupCallback SymbolLookUp, 387 void *DisInfo, MCContext *Ctx, 388 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 389 return new AArch64ExternalSymbolizer(*Ctx, std::move(RelInfo), GetOpInfo, 390 SymbolLookUp, DisInfo); 391 } 392 393 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Disassembler() { 394 TargetRegistry::RegisterMCDisassembler(getTheAArch64leTarget(), 395 createAArch64Disassembler); 396 TargetRegistry::RegisterMCDisassembler(getTheAArch64beTarget(), 397 createAArch64Disassembler); 398 TargetRegistry::RegisterMCSymbolizer(getTheAArch64leTarget(), 399 createAArch64ExternalSymbolizer); 400 TargetRegistry::RegisterMCSymbolizer(getTheAArch64beTarget(), 401 createAArch64ExternalSymbolizer); 402 TargetRegistry::RegisterMCDisassembler(getTheAArch64_32Target(), 403 createAArch64Disassembler); 404 TargetRegistry::RegisterMCSymbolizer(getTheAArch64_32Target(), 405 createAArch64ExternalSymbolizer); 406 407 TargetRegistry::RegisterMCDisassembler(getTheARM64Target(), 408 createAArch64Disassembler); 409 TargetRegistry::RegisterMCSymbolizer(getTheARM64Target(), 410 createAArch64ExternalSymbolizer); 411 TargetRegistry::RegisterMCDisassembler(getTheARM64_32Target(), 412 createAArch64Disassembler); 413 TargetRegistry::RegisterMCSymbolizer(getTheARM64_32Target(), 414 createAArch64ExternalSymbolizer); 415 } 416 417 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo, 418 uint64_t Addr, 419 const MCDisassembler *Decoder) { 420 if (RegNo > 31) 421 return Fail; 422 423 unsigned Register = 424 AArch64MCRegisterClasses[AArch64::FPR128RegClassID].getRegister(RegNo); 425 Inst.addOperand(MCOperand::createReg(Register)); 426 return Success; 427 } 428 429 static DecodeStatus 430 DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, 431 const MCDisassembler *Decoder) { 432 if (RegNo > 15) 433 return Fail; 434 return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder); 435 } 436 437 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, 438 uint64_t Addr, 439 const MCDisassembler *Decoder) { 440 if (RegNo > 31) 441 return Fail; 442 443 unsigned Register = 444 AArch64MCRegisterClasses[AArch64::FPR64RegClassID].getRegister(RegNo); 445 Inst.addOperand(MCOperand::createReg(Register)); 446 return Success; 447 } 448 449 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, 450 uint64_t Addr, 451 const MCDisassembler *Decoder) { 452 if (RegNo > 31) 453 return Fail; 454 455 unsigned Register = 456 AArch64MCRegisterClasses[AArch64::FPR32RegClassID].getRegister(RegNo); 457 Inst.addOperand(MCOperand::createReg(Register)); 458 return Success; 459 } 460 461 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, 462 uint64_t Addr, 463 const MCDisassembler *Decoder) { 464 if (RegNo > 31) 465 return Fail; 466 467 unsigned Register = 468 AArch64MCRegisterClasses[AArch64::FPR16RegClassID].getRegister(RegNo); 469 Inst.addOperand(MCOperand::createReg(Register)); 470 return Success; 471 } 472 473 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, 474 uint64_t Addr, 475 const MCDisassembler *Decoder) { 476 if (RegNo > 31) 477 return Fail; 478 479 unsigned Register = 480 AArch64MCRegisterClasses[AArch64::FPR8RegClassID].getRegister(RegNo); 481 Inst.addOperand(MCOperand::createReg(Register)); 482 return Success; 483 } 484 485 static DecodeStatus 486 DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, 487 const MCDisassembler *Decoder) { 488 if (RegNo > 30) 489 return Fail; 490 491 unsigned Register = 492 AArch64MCRegisterClasses[AArch64::GPR64commonRegClassID].getRegister( 493 RegNo); 494 Inst.addOperand(MCOperand::createReg(Register)); 495 return Success; 496 } 497 498 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, 499 uint64_t Addr, 500 const MCDisassembler *Decoder) { 501 if (RegNo > 31) 502 return Fail; 503 504 unsigned Register = 505 AArch64MCRegisterClasses[AArch64::GPR64RegClassID].getRegister(RegNo); 506 Inst.addOperand(MCOperand::createReg(Register)); 507 return Success; 508 } 509 510 static DecodeStatus 511 DecodeGPR64x8ClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 512 const MCDisassembler *Decoder) { 513 if (RegNo > 22) 514 return Fail; 515 if (RegNo & 1) 516 return Fail; 517 518 unsigned Register = 519 AArch64MCRegisterClasses[AArch64::GPR64x8ClassRegClassID].getRegister( 520 RegNo >> 1); 521 Inst.addOperand(MCOperand::createReg(Register)); 522 return Success; 523 } 524 525 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo, 526 uint64_t Addr, 527 const MCDisassembler *Decoder) { 528 if (RegNo > 31) 529 return Fail; 530 unsigned Register = 531 AArch64MCRegisterClasses[AArch64::GPR64spRegClassID].getRegister(RegNo); 532 Inst.addOperand(MCOperand::createReg(Register)); 533 return Success; 534 } 535 536 static DecodeStatus 537 DecodeMatrixIndexGPR32_8_11RegisterClass(MCInst &Inst, unsigned RegNo, 538 uint64_t Addr, const void *Decoder) { 539 if (RegNo > 3) 540 return Fail; 541 542 unsigned Register = 543 AArch64MCRegisterClasses[AArch64::MatrixIndexGPR32_8_11RegClassID] 544 .getRegister(RegNo); 545 Inst.addOperand(MCOperand::createReg(Register)); 546 return Success; 547 } 548 549 static DecodeStatus 550 DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst, unsigned RegNo, 551 uint64_t Addr, 552 const MCDisassembler *Decoder) { 553 if (RegNo > 3) 554 return Fail; 555 556 unsigned Register = 557 AArch64MCRegisterClasses[AArch64::MatrixIndexGPR32_12_15RegClassID] 558 .getRegister(RegNo); 559 Inst.addOperand(MCOperand::createReg(Register)); 560 return Success; 561 } 562 563 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, 564 uint64_t Addr, 565 const MCDisassembler *Decoder) { 566 if (RegNo > 31) 567 return Fail; 568 569 unsigned Register = 570 AArch64MCRegisterClasses[AArch64::GPR32RegClassID].getRegister(RegNo); 571 Inst.addOperand(MCOperand::createReg(Register)); 572 return Success; 573 } 574 575 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo, 576 uint64_t Addr, 577 const MCDisassembler *Decoder) { 578 if (RegNo > 31) 579 return Fail; 580 581 unsigned Register = 582 AArch64MCRegisterClasses[AArch64::GPR32spRegClassID].getRegister(RegNo); 583 Inst.addOperand(MCOperand::createReg(Register)); 584 return Success; 585 } 586 587 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, 588 uint64_t Address, 589 const MCDisassembler *Decoder) { 590 if (RegNo > 31) 591 return Fail; 592 593 unsigned Register = 594 AArch64MCRegisterClasses[AArch64::ZPRRegClassID].getRegister(RegNo); 595 Inst.addOperand(MCOperand::createReg(Register)); 596 return Success; 597 } 598 599 static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo, 600 uint64_t Address, 601 const MCDisassembler *Decoder) { 602 if (RegNo > 15) 603 return Fail; 604 return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder); 605 } 606 607 static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 608 uint64_t Address, 609 const MCDisassembler *Decoder) { 610 if (RegNo > 7) 611 return Fail; 612 return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder); 613 } 614 615 static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, 616 uint64_t Address, 617 const MCDisassembler *Decoder) { 618 if (RegNo > 31) 619 return Fail; 620 unsigned Register = 621 AArch64MCRegisterClasses[AArch64::ZPR2RegClassID].getRegister(RegNo); 622 Inst.addOperand(MCOperand::createReg(Register)); 623 return Success; 624 } 625 626 static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, 627 uint64_t Address, 628 const MCDisassembler *Decoder) { 629 if (RegNo > 31) 630 return Fail; 631 unsigned Register = 632 AArch64MCRegisterClasses[AArch64::ZPR3RegClassID].getRegister(RegNo); 633 Inst.addOperand(MCOperand::createReg(Register)); 634 return Success; 635 } 636 637 static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, 638 uint64_t Address, 639 const MCDisassembler *Decoder) { 640 if (RegNo > 31) 641 return Fail; 642 unsigned Register = 643 AArch64MCRegisterClasses[AArch64::ZPR4RegClassID].getRegister(RegNo); 644 Inst.addOperand(MCOperand::createReg(Register)); 645 return Success; 646 } 647 648 static DecodeStatus DecodeZPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo, 649 uint64_t Address, 650 const void *Decoder) { 651 if (RegNo * 2 > 30) 652 return Fail; 653 unsigned Register = 654 AArch64MCRegisterClasses[AArch64::ZPR2RegClassID].getRegister(RegNo * 2); 655 Inst.addOperand(MCOperand::createReg(Register)); 656 return Success; 657 } 658 659 static DecodeStatus DecodeZPR4Mul4RegisterClass(MCInst &Inst, unsigned RegNo, 660 uint64_t Address, 661 const void *Decoder) { 662 if (RegNo * 4 > 28) 663 return Fail; 664 unsigned Register = 665 AArch64MCRegisterClasses[AArch64::ZPR4RegClassID].getRegister(RegNo * 4); 666 Inst.addOperand(MCOperand::createReg(Register)); 667 return Success; 668 } 669 670 static DecodeStatus DecodeZPR2StridedRegisterClass(MCInst &Inst, unsigned RegNo, 671 uint64_t Address, 672 const void *Decoder) { 673 if (RegNo > 15) 674 return Fail; 675 unsigned Register = 676 AArch64MCRegisterClasses[AArch64::ZPR2StridedRegClassID].getRegister( 677 RegNo); 678 Inst.addOperand(MCOperand::createReg(Register)); 679 return Success; 680 } 681 682 static DecodeStatus DecodeZPR4StridedRegisterClass(MCInst &Inst, unsigned RegNo, 683 uint64_t Address, 684 const void *Decoder) { 685 if (RegNo > 7) 686 return Fail; 687 unsigned Register = 688 AArch64MCRegisterClasses[AArch64::ZPR4StridedRegClassID].getRegister( 689 RegNo); 690 Inst.addOperand(MCOperand::createReg(Register)); 691 return Success; 692 } 693 694 static DecodeStatus 695 DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask, 696 uint64_t Address, 697 const MCDisassembler *Decoder) { 698 if (RegMask > 0xFF) 699 return Fail; 700 Inst.addOperand(MCOperand::createImm(RegMask)); 701 return Success; 702 } 703 704 static const SmallVector<SmallVector<unsigned, 16>, 5> 705 MatrixZATileDecoderTable = { 706 {AArch64::ZAB0}, 707 {AArch64::ZAH0, AArch64::ZAH1}, 708 {AArch64::ZAS0, AArch64::ZAS1, AArch64::ZAS2, AArch64::ZAS3}, 709 {AArch64::ZAD0, AArch64::ZAD1, AArch64::ZAD2, AArch64::ZAD3, 710 AArch64::ZAD4, AArch64::ZAD5, AArch64::ZAD6, AArch64::ZAD7}, 711 {AArch64::ZAQ0, AArch64::ZAQ1, AArch64::ZAQ2, AArch64::ZAQ3, 712 AArch64::ZAQ4, AArch64::ZAQ5, AArch64::ZAQ6, AArch64::ZAQ7, 713 AArch64::ZAQ8, AArch64::ZAQ9, AArch64::ZAQ10, AArch64::ZAQ11, 714 AArch64::ZAQ12, AArch64::ZAQ13, AArch64::ZAQ14, AArch64::ZAQ15}}; 715 716 template <unsigned NumBitsForTile> 717 static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo, 718 uint64_t Address, 719 const MCDisassembler *Decoder) { 720 unsigned LastReg = (1 << NumBitsForTile) - 1; 721 if (RegNo > LastReg) 722 return Fail; 723 Inst.addOperand( 724 MCOperand::createReg(MatrixZATileDecoderTable[NumBitsForTile][RegNo])); 725 return Success; 726 } 727 728 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, 729 uint64_t Addr, 730 const MCDisassembler *Decoder) { 731 if (RegNo > 15) 732 return Fail; 733 734 unsigned Register = 735 AArch64MCRegisterClasses[AArch64::PPRRegClassID].getRegister(RegNo); 736 Inst.addOperand(MCOperand::createReg(Register)); 737 return Success; 738 } 739 740 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 741 uint64_t Addr, 742 const MCDisassembler *Decoder) { 743 if (RegNo > 7) 744 return Fail; 745 746 // Just reuse the PPR decode table 747 return DecodePPRRegisterClass(Inst, RegNo, Addr, Decoder); 748 } 749 750 static DecodeStatus 751 DecodePPR_p8to15RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, 752 const MCDisassembler *Decoder) { 753 if (RegNo > 7) 754 return Fail; 755 756 // Just reuse the PPR decode table 757 return DecodePPRRegisterClass(Inst, RegNo + 8, Addr, Decoder); 758 } 759 760 static DecodeStatus DecodePPR2RegisterClass(MCInst &Inst, unsigned RegNo, 761 uint64_t Address, 762 const void *Decoder) { 763 if (RegNo > 15) 764 return Fail; 765 766 unsigned Register = 767 AArch64MCRegisterClasses[AArch64::PPR2RegClassID].getRegister(RegNo); 768 Inst.addOperand(MCOperand::createReg(Register)); 769 return Success; 770 } 771 772 static DecodeStatus DecodePPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo, 773 uint64_t Address, 774 const void *Decoder) { 775 if ((RegNo * 2) > 14) 776 return Fail; 777 unsigned Register = 778 AArch64MCRegisterClasses[AArch64::PPR2RegClassID].getRegister(RegNo * 2); 779 Inst.addOperand(MCOperand::createReg(Register)); 780 return Success; 781 } 782 783 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, 784 uint64_t Addr, 785 const MCDisassembler *Decoder) { 786 if (RegNo > 31) 787 return Fail; 788 unsigned Register = 789 AArch64MCRegisterClasses[AArch64::QQRegClassID].getRegister(RegNo); 790 Inst.addOperand(MCOperand::createReg(Register)); 791 return Success; 792 } 793 794 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, 795 uint64_t Addr, 796 const MCDisassembler *Decoder) { 797 if (RegNo > 31) 798 return Fail; 799 unsigned Register = 800 AArch64MCRegisterClasses[AArch64::QQQRegClassID].getRegister(RegNo); 801 Inst.addOperand(MCOperand::createReg(Register)); 802 return Success; 803 } 804 805 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, 806 uint64_t Addr, 807 const MCDisassembler *Decoder) { 808 if (RegNo > 31) 809 return Fail; 810 unsigned Register = 811 AArch64MCRegisterClasses[AArch64::QQQQRegClassID].getRegister(RegNo); 812 Inst.addOperand(MCOperand::createReg(Register)); 813 return Success; 814 } 815 816 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, 817 uint64_t Addr, 818 const MCDisassembler *Decoder) { 819 if (RegNo > 31) 820 return Fail; 821 unsigned Register = 822 AArch64MCRegisterClasses[AArch64::DDRegClassID].getRegister(RegNo); 823 Inst.addOperand(MCOperand::createReg(Register)); 824 return Success; 825 } 826 827 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, 828 uint64_t Addr, 829 const MCDisassembler *Decoder) { 830 if (RegNo > 31) 831 return Fail; 832 unsigned Register = 833 AArch64MCRegisterClasses[AArch64::DDDRegClassID].getRegister(RegNo); 834 Inst.addOperand(MCOperand::createReg(Register)); 835 return Success; 836 } 837 838 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, 839 uint64_t Addr, 840 const MCDisassembler *Decoder) { 841 if (RegNo > 31) 842 return Fail; 843 unsigned Register = 844 AArch64MCRegisterClasses[AArch64::DDDDRegClassID].getRegister(RegNo); 845 Inst.addOperand(MCOperand::createReg(Register)); 846 return Success; 847 } 848 849 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, 850 uint64_t Addr, 851 const MCDisassembler *Decoder) { 852 // scale{5} is asserted as 1 in tblgen. 853 Imm |= 0x20; 854 Inst.addOperand(MCOperand::createImm(64 - Imm)); 855 return Success; 856 } 857 858 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, 859 uint64_t Addr, 860 const MCDisassembler *Decoder) { 861 Inst.addOperand(MCOperand::createImm(64 - Imm)); 862 return Success; 863 } 864 865 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, 866 uint64_t Addr, 867 const MCDisassembler *Decoder) { 868 int64_t ImmVal = Imm; 869 870 // Sign-extend 19-bit immediate. 871 if (ImmVal & (1 << (19 - 1))) 872 ImmVal |= ~((1LL << 19) - 1); 873 874 if (!Decoder->tryAddingSymbolicOperand( 875 Inst, ImmVal * 4, Addr, Inst.getOpcode() != AArch64::LDRXl, 0, 0, 4)) 876 Inst.addOperand(MCOperand::createImm(ImmVal)); 877 return Success; 878 } 879 880 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, 881 uint64_t Address, 882 const MCDisassembler *Decoder) { 883 Inst.addOperand(MCOperand::createImm((Imm >> 1) & 1)); 884 Inst.addOperand(MCOperand::createImm(Imm & 1)); 885 return Success; 886 } 887 888 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, 889 uint64_t Address, 890 const MCDisassembler *Decoder) { 891 Inst.addOperand(MCOperand::createImm(Imm)); 892 893 // Every system register in the encoding space is valid with the syntax 894 // S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds. 895 return Success; 896 } 897 898 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, 899 uint64_t Address, 900 const MCDisassembler *Decoder) { 901 Inst.addOperand(MCOperand::createImm(Imm)); 902 903 return Success; 904 } 905 906 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, 907 uint64_t Address, 908 const MCDisassembler *Decoder) { 909 // This decoder exists to add the dummy Lane operand to the MCInst, which must 910 // be 1 in assembly but has no other real manifestation. 911 unsigned Rd = fieldFromInstruction(Insn, 0, 5); 912 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 913 unsigned IsToVec = fieldFromInstruction(Insn, 16, 1); 914 915 if (IsToVec) { 916 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder); 917 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder); 918 } else { 919 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder); 920 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder); 921 } 922 923 // Add the lane 924 Inst.addOperand(MCOperand::createImm(1)); 925 926 return Success; 927 } 928 929 static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm, 930 unsigned Add) { 931 Inst.addOperand(MCOperand::createImm(Add - Imm)); 932 return Success; 933 } 934 935 static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm, 936 unsigned Add) { 937 Inst.addOperand(MCOperand::createImm((Imm + Add) & (Add - 1))); 938 return Success; 939 } 940 941 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, 942 uint64_t Addr, 943 const MCDisassembler *Decoder) { 944 return DecodeVecShiftRImm(Inst, Imm, 64); 945 } 946 947 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, 948 uint64_t Addr, 949 const MCDisassembler *Decoder) { 950 return DecodeVecShiftRImm(Inst, Imm | 0x20, 64); 951 } 952 953 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, 954 uint64_t Addr, 955 const MCDisassembler *Decoder) { 956 return DecodeVecShiftRImm(Inst, Imm, 32); 957 } 958 959 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, 960 uint64_t Addr, 961 const MCDisassembler *Decoder) { 962 return DecodeVecShiftRImm(Inst, Imm | 0x10, 32); 963 } 964 965 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, 966 uint64_t Addr, 967 const MCDisassembler *Decoder) { 968 return DecodeVecShiftRImm(Inst, Imm, 16); 969 } 970 971 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, 972 uint64_t Addr, 973 const MCDisassembler *Decoder) { 974 return DecodeVecShiftRImm(Inst, Imm | 0x8, 16); 975 } 976 977 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, 978 uint64_t Addr, 979 const MCDisassembler *Decoder) { 980 return DecodeVecShiftRImm(Inst, Imm, 8); 981 } 982 983 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, 984 uint64_t Addr, 985 const MCDisassembler *Decoder) { 986 return DecodeVecShiftLImm(Inst, Imm, 64); 987 } 988 989 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, 990 uint64_t Addr, 991 const MCDisassembler *Decoder) { 992 return DecodeVecShiftLImm(Inst, Imm, 32); 993 } 994 995 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, 996 uint64_t Addr, 997 const MCDisassembler *Decoder) { 998 return DecodeVecShiftLImm(Inst, Imm, 16); 999 } 1000 1001 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, 1002 uint64_t Addr, 1003 const MCDisassembler *Decoder) { 1004 return DecodeVecShiftLImm(Inst, Imm, 8); 1005 } 1006 1007 static DecodeStatus 1008 DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, 1009 const MCDisassembler *Decoder) { 1010 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1011 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1012 unsigned Rm = fieldFromInstruction(insn, 16, 5); 1013 unsigned shiftHi = fieldFromInstruction(insn, 22, 2); 1014 unsigned shiftLo = fieldFromInstruction(insn, 10, 6); 1015 unsigned shift = (shiftHi << 6) | shiftLo; 1016 switch (Inst.getOpcode()) { 1017 default: 1018 return Fail; 1019 case AArch64::ADDWrs: 1020 case AArch64::ADDSWrs: 1021 case AArch64::SUBWrs: 1022 case AArch64::SUBSWrs: 1023 // if shift == '11' then ReservedValue() 1024 if (shiftHi == 0x3) 1025 return Fail; 1026 [[fallthrough]]; 1027 case AArch64::ANDWrs: 1028 case AArch64::ANDSWrs: 1029 case AArch64::BICWrs: 1030 case AArch64::BICSWrs: 1031 case AArch64::ORRWrs: 1032 case AArch64::ORNWrs: 1033 case AArch64::EORWrs: 1034 case AArch64::EONWrs: { 1035 // if sf == '0' and imm6<5> == '1' then ReservedValue() 1036 if (shiftLo >> 5 == 1) 1037 return Fail; 1038 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1039 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); 1040 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1041 break; 1042 } 1043 case AArch64::ADDXrs: 1044 case AArch64::ADDSXrs: 1045 case AArch64::SUBXrs: 1046 case AArch64::SUBSXrs: 1047 // if shift == '11' then ReservedValue() 1048 if (shiftHi == 0x3) 1049 return Fail; 1050 [[fallthrough]]; 1051 case AArch64::ANDXrs: 1052 case AArch64::ANDSXrs: 1053 case AArch64::BICXrs: 1054 case AArch64::BICSXrs: 1055 case AArch64::ORRXrs: 1056 case AArch64::ORNXrs: 1057 case AArch64::EORXrs: 1058 case AArch64::EONXrs: 1059 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1060 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); 1061 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1062 break; 1063 } 1064 1065 Inst.addOperand(MCOperand::createImm(shift)); 1066 return Success; 1067 } 1068 1069 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, 1070 uint64_t Addr, 1071 const MCDisassembler *Decoder) { 1072 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1073 unsigned imm = fieldFromInstruction(insn, 5, 16); 1074 unsigned shift = fieldFromInstruction(insn, 21, 2); 1075 shift <<= 4; 1076 switch (Inst.getOpcode()) { 1077 default: 1078 return Fail; 1079 case AArch64::MOVZWi: 1080 case AArch64::MOVNWi: 1081 case AArch64::MOVKWi: 1082 if (shift & (1U << 5)) 1083 return Fail; 1084 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1085 break; 1086 case AArch64::MOVZXi: 1087 case AArch64::MOVNXi: 1088 case AArch64::MOVKXi: 1089 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1090 break; 1091 } 1092 1093 if (Inst.getOpcode() == AArch64::MOVKWi || 1094 Inst.getOpcode() == AArch64::MOVKXi) 1095 Inst.addOperand(Inst.getOperand(0)); 1096 1097 Inst.addOperand(MCOperand::createImm(imm)); 1098 Inst.addOperand(MCOperand::createImm(shift)); 1099 return Success; 1100 } 1101 1102 static DecodeStatus 1103 DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, 1104 const MCDisassembler *Decoder) { 1105 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1106 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1107 unsigned offset = fieldFromInstruction(insn, 10, 12); 1108 1109 switch (Inst.getOpcode()) { 1110 default: 1111 return Fail; 1112 case AArch64::PRFMui: 1113 // Rt is an immediate in prefetch. 1114 Inst.addOperand(MCOperand::createImm(Rt)); 1115 break; 1116 case AArch64::STRBBui: 1117 case AArch64::LDRBBui: 1118 case AArch64::LDRSBWui: 1119 case AArch64::STRHHui: 1120 case AArch64::LDRHHui: 1121 case AArch64::LDRSHWui: 1122 case AArch64::STRWui: 1123 case AArch64::LDRWui: 1124 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1125 break; 1126 case AArch64::LDRSBXui: 1127 case AArch64::LDRSHXui: 1128 case AArch64::LDRSWui: 1129 case AArch64::STRXui: 1130 case AArch64::LDRXui: 1131 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1132 break; 1133 case AArch64::LDRQui: 1134 case AArch64::STRQui: 1135 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1136 break; 1137 case AArch64::LDRDui: 1138 case AArch64::STRDui: 1139 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1140 break; 1141 case AArch64::LDRSui: 1142 case AArch64::STRSui: 1143 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1144 break; 1145 case AArch64::LDRHui: 1146 case AArch64::STRHui: 1147 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); 1148 break; 1149 case AArch64::LDRBui: 1150 case AArch64::STRBui: 1151 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); 1152 break; 1153 } 1154 1155 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1156 if (!Decoder->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 0, 4)) 1157 Inst.addOperand(MCOperand::createImm(offset)); 1158 return Success; 1159 } 1160 1161 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, 1162 uint64_t Addr, 1163 const MCDisassembler *Decoder) { 1164 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1165 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1166 int64_t offset = fieldFromInstruction(insn, 12, 9); 1167 1168 // offset is a 9-bit signed immediate, so sign extend it to 1169 // fill the unsigned. 1170 if (offset & (1 << (9 - 1))) 1171 offset |= ~((1LL << 9) - 1); 1172 1173 // First operand is always the writeback to the address register, if needed. 1174 switch (Inst.getOpcode()) { 1175 default: 1176 break; 1177 case AArch64::LDRSBWpre: 1178 case AArch64::LDRSHWpre: 1179 case AArch64::STRBBpre: 1180 case AArch64::LDRBBpre: 1181 case AArch64::STRHHpre: 1182 case AArch64::LDRHHpre: 1183 case AArch64::STRWpre: 1184 case AArch64::LDRWpre: 1185 case AArch64::LDRSBWpost: 1186 case AArch64::LDRSHWpost: 1187 case AArch64::STRBBpost: 1188 case AArch64::LDRBBpost: 1189 case AArch64::STRHHpost: 1190 case AArch64::LDRHHpost: 1191 case AArch64::STRWpost: 1192 case AArch64::LDRWpost: 1193 case AArch64::LDRSBXpre: 1194 case AArch64::LDRSHXpre: 1195 case AArch64::STRXpre: 1196 case AArch64::LDRSWpre: 1197 case AArch64::LDRXpre: 1198 case AArch64::LDRSBXpost: 1199 case AArch64::LDRSHXpost: 1200 case AArch64::STRXpost: 1201 case AArch64::LDRSWpost: 1202 case AArch64::LDRXpost: 1203 case AArch64::LDRQpre: 1204 case AArch64::STRQpre: 1205 case AArch64::LDRQpost: 1206 case AArch64::STRQpost: 1207 case AArch64::LDRDpre: 1208 case AArch64::STRDpre: 1209 case AArch64::LDRDpost: 1210 case AArch64::STRDpost: 1211 case AArch64::LDRSpre: 1212 case AArch64::STRSpre: 1213 case AArch64::LDRSpost: 1214 case AArch64::STRSpost: 1215 case AArch64::LDRHpre: 1216 case AArch64::STRHpre: 1217 case AArch64::LDRHpost: 1218 case AArch64::STRHpost: 1219 case AArch64::LDRBpre: 1220 case AArch64::STRBpre: 1221 case AArch64::LDRBpost: 1222 case AArch64::STRBpost: 1223 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1224 break; 1225 } 1226 1227 switch (Inst.getOpcode()) { 1228 default: 1229 return Fail; 1230 case AArch64::PRFUMi: 1231 // Rt is an immediate in prefetch. 1232 Inst.addOperand(MCOperand::createImm(Rt)); 1233 break; 1234 case AArch64::STURBBi: 1235 case AArch64::LDURBBi: 1236 case AArch64::LDURSBWi: 1237 case AArch64::STURHHi: 1238 case AArch64::LDURHHi: 1239 case AArch64::LDURSHWi: 1240 case AArch64::STURWi: 1241 case AArch64::LDURWi: 1242 case AArch64::LDTRSBWi: 1243 case AArch64::LDTRSHWi: 1244 case AArch64::STTRWi: 1245 case AArch64::LDTRWi: 1246 case AArch64::STTRHi: 1247 case AArch64::LDTRHi: 1248 case AArch64::LDTRBi: 1249 case AArch64::STTRBi: 1250 case AArch64::LDRSBWpre: 1251 case AArch64::LDRSHWpre: 1252 case AArch64::STRBBpre: 1253 case AArch64::LDRBBpre: 1254 case AArch64::STRHHpre: 1255 case AArch64::LDRHHpre: 1256 case AArch64::STRWpre: 1257 case AArch64::LDRWpre: 1258 case AArch64::LDRSBWpost: 1259 case AArch64::LDRSHWpost: 1260 case AArch64::STRBBpost: 1261 case AArch64::LDRBBpost: 1262 case AArch64::STRHHpost: 1263 case AArch64::LDRHHpost: 1264 case AArch64::STRWpost: 1265 case AArch64::LDRWpost: 1266 case AArch64::STLURBi: 1267 case AArch64::STLURHi: 1268 case AArch64::STLURWi: 1269 case AArch64::LDAPURBi: 1270 case AArch64::LDAPURSBWi: 1271 case AArch64::LDAPURHi: 1272 case AArch64::LDAPURSHWi: 1273 case AArch64::LDAPURi: 1274 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1275 break; 1276 case AArch64::LDURSBXi: 1277 case AArch64::LDURSHXi: 1278 case AArch64::LDURSWi: 1279 case AArch64::STURXi: 1280 case AArch64::LDURXi: 1281 case AArch64::LDTRSBXi: 1282 case AArch64::LDTRSHXi: 1283 case AArch64::LDTRSWi: 1284 case AArch64::STTRXi: 1285 case AArch64::LDTRXi: 1286 case AArch64::LDRSBXpre: 1287 case AArch64::LDRSHXpre: 1288 case AArch64::STRXpre: 1289 case AArch64::LDRSWpre: 1290 case AArch64::LDRXpre: 1291 case AArch64::LDRSBXpost: 1292 case AArch64::LDRSHXpost: 1293 case AArch64::STRXpost: 1294 case AArch64::LDRSWpost: 1295 case AArch64::LDRXpost: 1296 case AArch64::LDAPURSWi: 1297 case AArch64::LDAPURSHXi: 1298 case AArch64::LDAPURSBXi: 1299 case AArch64::STLURXi: 1300 case AArch64::LDAPURXi: 1301 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1302 break; 1303 case AArch64::LDURQi: 1304 case AArch64::STURQi: 1305 case AArch64::LDRQpre: 1306 case AArch64::STRQpre: 1307 case AArch64::LDRQpost: 1308 case AArch64::STRQpost: 1309 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1310 break; 1311 case AArch64::LDURDi: 1312 case AArch64::STURDi: 1313 case AArch64::LDRDpre: 1314 case AArch64::STRDpre: 1315 case AArch64::LDRDpost: 1316 case AArch64::STRDpost: 1317 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1318 break; 1319 case AArch64::LDURSi: 1320 case AArch64::STURSi: 1321 case AArch64::LDRSpre: 1322 case AArch64::STRSpre: 1323 case AArch64::LDRSpost: 1324 case AArch64::STRSpost: 1325 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1326 break; 1327 case AArch64::LDURHi: 1328 case AArch64::STURHi: 1329 case AArch64::LDRHpre: 1330 case AArch64::STRHpre: 1331 case AArch64::LDRHpost: 1332 case AArch64::STRHpost: 1333 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); 1334 break; 1335 case AArch64::LDURBi: 1336 case AArch64::STURBi: 1337 case AArch64::LDRBpre: 1338 case AArch64::STRBpre: 1339 case AArch64::LDRBpost: 1340 case AArch64::STRBpost: 1341 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); 1342 break; 1343 } 1344 1345 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1346 Inst.addOperand(MCOperand::createImm(offset)); 1347 1348 bool IsLoad = fieldFromInstruction(insn, 22, 1); 1349 bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0; 1350 bool IsFP = fieldFromInstruction(insn, 26, 1); 1351 1352 // Cannot write back to a transfer register (but xzr != sp). 1353 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn) 1354 return SoftFail; 1355 1356 return Success; 1357 } 1358 1359 static DecodeStatus 1360 DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, 1361 const MCDisassembler *Decoder) { 1362 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1363 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1364 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); 1365 unsigned Rs = fieldFromInstruction(insn, 16, 5); 1366 1367 unsigned Opcode = Inst.getOpcode(); 1368 switch (Opcode) { 1369 default: 1370 return Fail; 1371 case AArch64::STLXRW: 1372 case AArch64::STLXRB: 1373 case AArch64::STLXRH: 1374 case AArch64::STXRW: 1375 case AArch64::STXRB: 1376 case AArch64::STXRH: 1377 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1378 [[fallthrough]]; 1379 case AArch64::LDARW: 1380 case AArch64::LDARB: 1381 case AArch64::LDARH: 1382 case AArch64::LDAXRW: 1383 case AArch64::LDAXRB: 1384 case AArch64::LDAXRH: 1385 case AArch64::LDXRW: 1386 case AArch64::LDXRB: 1387 case AArch64::LDXRH: 1388 case AArch64::STLRW: 1389 case AArch64::STLRB: 1390 case AArch64::STLRH: 1391 case AArch64::STLLRW: 1392 case AArch64::STLLRB: 1393 case AArch64::STLLRH: 1394 case AArch64::LDLARW: 1395 case AArch64::LDLARB: 1396 case AArch64::LDLARH: 1397 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1398 break; 1399 case AArch64::STLXRX: 1400 case AArch64::STXRX: 1401 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1402 [[fallthrough]]; 1403 case AArch64::LDARX: 1404 case AArch64::LDAXRX: 1405 case AArch64::LDXRX: 1406 case AArch64::STLRX: 1407 case AArch64::LDLARX: 1408 case AArch64::STLLRX: 1409 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1410 break; 1411 case AArch64::STLXPW: 1412 case AArch64::STXPW: 1413 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1414 [[fallthrough]]; 1415 case AArch64::LDAXPW: 1416 case AArch64::LDXPW: 1417 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1418 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1419 break; 1420 case AArch64::STLXPX: 1421 case AArch64::STXPX: 1422 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1423 [[fallthrough]]; 1424 case AArch64::LDAXPX: 1425 case AArch64::LDXPX: 1426 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1427 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1428 break; 1429 } 1430 1431 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1432 1433 // You shouldn't load to the same register twice in an instruction... 1434 if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW || 1435 Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) && 1436 Rt == Rt2) 1437 return SoftFail; 1438 1439 return Success; 1440 } 1441 1442 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, 1443 uint64_t Addr, 1444 const MCDisassembler *Decoder) { 1445 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1446 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1447 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); 1448 int64_t offset = fieldFromInstruction(insn, 15, 7); 1449 bool IsLoad = fieldFromInstruction(insn, 22, 1); 1450 1451 // offset is a 7-bit signed immediate, so sign extend it to 1452 // fill the unsigned. 1453 if (offset & (1 << (7 - 1))) 1454 offset |= ~((1LL << 7) - 1); 1455 1456 unsigned Opcode = Inst.getOpcode(); 1457 bool NeedsDisjointWritebackTransfer = false; 1458 1459 // First operand is always writeback of base register. 1460 switch (Opcode) { 1461 default: 1462 break; 1463 case AArch64::LDPXpost: 1464 case AArch64::STPXpost: 1465 case AArch64::LDPSWpost: 1466 case AArch64::LDPXpre: 1467 case AArch64::STPXpre: 1468 case AArch64::LDPSWpre: 1469 case AArch64::LDPWpost: 1470 case AArch64::STPWpost: 1471 case AArch64::LDPWpre: 1472 case AArch64::STPWpre: 1473 case AArch64::LDPQpost: 1474 case AArch64::STPQpost: 1475 case AArch64::LDPQpre: 1476 case AArch64::STPQpre: 1477 case AArch64::LDPDpost: 1478 case AArch64::STPDpost: 1479 case AArch64::LDPDpre: 1480 case AArch64::STPDpre: 1481 case AArch64::LDPSpost: 1482 case AArch64::STPSpost: 1483 case AArch64::LDPSpre: 1484 case AArch64::STPSpre: 1485 case AArch64::STGPpre: 1486 case AArch64::STGPpost: 1487 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1488 break; 1489 } 1490 1491 switch (Opcode) { 1492 default: 1493 return Fail; 1494 case AArch64::LDPXpost: 1495 case AArch64::STPXpost: 1496 case AArch64::LDPSWpost: 1497 case AArch64::LDPXpre: 1498 case AArch64::STPXpre: 1499 case AArch64::LDPSWpre: 1500 case AArch64::STGPpre: 1501 case AArch64::STGPpost: 1502 NeedsDisjointWritebackTransfer = true; 1503 [[fallthrough]]; 1504 case AArch64::LDNPXi: 1505 case AArch64::STNPXi: 1506 case AArch64::LDPXi: 1507 case AArch64::STPXi: 1508 case AArch64::LDPSWi: 1509 case AArch64::STGPi: 1510 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1511 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1512 break; 1513 case AArch64::LDPWpost: 1514 case AArch64::STPWpost: 1515 case AArch64::LDPWpre: 1516 case AArch64::STPWpre: 1517 NeedsDisjointWritebackTransfer = true; 1518 [[fallthrough]]; 1519 case AArch64::LDNPWi: 1520 case AArch64::STNPWi: 1521 case AArch64::LDPWi: 1522 case AArch64::STPWi: 1523 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1524 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1525 break; 1526 case AArch64::LDNPQi: 1527 case AArch64::STNPQi: 1528 case AArch64::LDPQpost: 1529 case AArch64::STPQpost: 1530 case AArch64::LDPQi: 1531 case AArch64::STPQi: 1532 case AArch64::LDPQpre: 1533 case AArch64::STPQpre: 1534 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1535 DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder); 1536 break; 1537 case AArch64::LDNPDi: 1538 case AArch64::STNPDi: 1539 case AArch64::LDPDpost: 1540 case AArch64::STPDpost: 1541 case AArch64::LDPDi: 1542 case AArch64::STPDi: 1543 case AArch64::LDPDpre: 1544 case AArch64::STPDpre: 1545 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1546 DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1547 break; 1548 case AArch64::LDNPSi: 1549 case AArch64::STNPSi: 1550 case AArch64::LDPSpost: 1551 case AArch64::STPSpost: 1552 case AArch64::LDPSi: 1553 case AArch64::STPSi: 1554 case AArch64::LDPSpre: 1555 case AArch64::STPSpre: 1556 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1557 DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1558 break; 1559 } 1560 1561 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1562 Inst.addOperand(MCOperand::createImm(offset)); 1563 1564 // You shouldn't load to the same register twice in an instruction... 1565 if (IsLoad && Rt == Rt2) 1566 return SoftFail; 1567 1568 // ... or do any operation that writes-back to a transfer register. But note 1569 // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different. 1570 if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn)) 1571 return SoftFail; 1572 1573 return Success; 1574 } 1575 1576 static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn, 1577 uint64_t Addr, 1578 const MCDisassembler *Decoder) { 1579 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1580 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1581 uint64_t offset = fieldFromInstruction(insn, 22, 1) << 9 | 1582 fieldFromInstruction(insn, 12, 9); 1583 unsigned writeback = fieldFromInstruction(insn, 11, 1); 1584 1585 switch (Inst.getOpcode()) { 1586 default: 1587 return Fail; 1588 case AArch64::LDRAAwriteback: 1589 case AArch64::LDRABwriteback: 1590 DecodeGPR64spRegisterClass(Inst, Rn /* writeback register */, Addr, 1591 Decoder); 1592 break; 1593 case AArch64::LDRAAindexed: 1594 case AArch64::LDRABindexed: 1595 break; 1596 } 1597 1598 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1599 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1600 DecodeSImm<10>(Inst, offset, Addr, Decoder); 1601 1602 if (writeback && Rt == Rn && Rn != 31) { 1603 return SoftFail; 1604 } 1605 1606 return Success; 1607 } 1608 1609 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, 1610 uint64_t Addr, 1611 const MCDisassembler *Decoder) { 1612 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1613 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1614 unsigned Rm = fieldFromInstruction(insn, 16, 5); 1615 unsigned extend = fieldFromInstruction(insn, 10, 6); 1616 1617 unsigned shift = extend & 0x7; 1618 if (shift > 4) 1619 return Fail; 1620 1621 switch (Inst.getOpcode()) { 1622 default: 1623 return Fail; 1624 case AArch64::ADDWrx: 1625 case AArch64::SUBWrx: 1626 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1627 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1628 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1629 break; 1630 case AArch64::ADDSWrx: 1631 case AArch64::SUBSWrx: 1632 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1633 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1634 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1635 break; 1636 case AArch64::ADDXrx: 1637 case AArch64::SUBXrx: 1638 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1639 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1640 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1641 break; 1642 case AArch64::ADDSXrx: 1643 case AArch64::SUBSXrx: 1644 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1645 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1646 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1647 break; 1648 case AArch64::ADDXrx64: 1649 case AArch64::SUBXrx64: 1650 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1651 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1652 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1653 break; 1654 case AArch64::SUBSXrx64: 1655 case AArch64::ADDSXrx64: 1656 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1657 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1658 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1659 break; 1660 } 1661 1662 Inst.addOperand(MCOperand::createImm(extend)); 1663 return Success; 1664 } 1665 1666 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, 1667 uint64_t Addr, 1668 const MCDisassembler *Decoder) { 1669 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1670 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1671 unsigned Datasize = fieldFromInstruction(insn, 31, 1); 1672 unsigned imm; 1673 1674 if (Datasize) { 1675 if (Inst.getOpcode() == AArch64::ANDSXri) 1676 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1677 else 1678 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1679 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); 1680 imm = fieldFromInstruction(insn, 10, 13); 1681 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64)) 1682 return Fail; 1683 } else { 1684 if (Inst.getOpcode() == AArch64::ANDSWri) 1685 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1686 else 1687 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1688 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); 1689 imm = fieldFromInstruction(insn, 10, 12); 1690 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32)) 1691 return Fail; 1692 } 1693 Inst.addOperand(MCOperand::createImm(imm)); 1694 return Success; 1695 } 1696 1697 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, 1698 uint64_t Addr, 1699 const MCDisassembler *Decoder) { 1700 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1701 unsigned cmode = fieldFromInstruction(insn, 12, 4); 1702 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; 1703 imm |= fieldFromInstruction(insn, 5, 5); 1704 1705 if (Inst.getOpcode() == AArch64::MOVID) 1706 DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder); 1707 else 1708 DecodeFPR128RegisterClass(Inst, Rd, Addr, Decoder); 1709 1710 Inst.addOperand(MCOperand::createImm(imm)); 1711 1712 switch (Inst.getOpcode()) { 1713 default: 1714 break; 1715 case AArch64::MOVIv4i16: 1716 case AArch64::MOVIv8i16: 1717 case AArch64::MVNIv4i16: 1718 case AArch64::MVNIv8i16: 1719 case AArch64::MOVIv2i32: 1720 case AArch64::MOVIv4i32: 1721 case AArch64::MVNIv2i32: 1722 case AArch64::MVNIv4i32: 1723 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2)); 1724 break; 1725 case AArch64::MOVIv2s_msl: 1726 case AArch64::MOVIv4s_msl: 1727 case AArch64::MVNIv2s_msl: 1728 case AArch64::MVNIv4s_msl: 1729 Inst.addOperand(MCOperand::createImm((cmode & 1) ? 0x110 : 0x108)); 1730 break; 1731 } 1732 1733 return Success; 1734 } 1735 1736 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, 1737 uint64_t Addr, 1738 const MCDisassembler *Decoder) { 1739 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1740 unsigned cmode = fieldFromInstruction(insn, 12, 4); 1741 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; 1742 imm |= fieldFromInstruction(insn, 5, 5); 1743 1744 // Tied operands added twice. 1745 DecodeFPR128RegisterClass(Inst, Rd, Addr, Decoder); 1746 DecodeFPR128RegisterClass(Inst, Rd, Addr, Decoder); 1747 1748 Inst.addOperand(MCOperand::createImm(imm)); 1749 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2)); 1750 1751 return Success; 1752 } 1753 1754 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, 1755 uint64_t Addr, 1756 const MCDisassembler *Decoder) { 1757 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1758 int64_t imm = fieldFromInstruction(insn, 5, 19) << 2; 1759 imm |= fieldFromInstruction(insn, 29, 2); 1760 1761 // Sign-extend the 21-bit immediate. 1762 if (imm & (1 << (21 - 1))) 1763 imm |= ~((1LL << 21) - 1); 1764 1765 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1766 if (!Decoder->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 0, 4)) 1767 Inst.addOperand(MCOperand::createImm(imm)); 1768 1769 return Success; 1770 } 1771 1772 static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn, 1773 uint64_t Addr, 1774 const MCDisassembler *Decoder) { 1775 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1776 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1777 unsigned Imm = fieldFromInstruction(insn, 10, 14); 1778 unsigned S = fieldFromInstruction(insn, 29, 1); 1779 unsigned Datasize = fieldFromInstruction(insn, 31, 1); 1780 1781 unsigned ShifterVal = (Imm >> 12) & 3; 1782 unsigned ImmVal = Imm & 0xFFF; 1783 1784 if (ShifterVal != 0 && ShifterVal != 1) 1785 return Fail; 1786 1787 if (Datasize) { 1788 if (Rd == 31 && !S) 1789 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1790 else 1791 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1792 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1793 } else { 1794 if (Rd == 31 && !S) 1795 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1796 else 1797 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1798 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1799 } 1800 1801 if (!Decoder->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 0, 4)) 1802 Inst.addOperand(MCOperand::createImm(ImmVal)); 1803 Inst.addOperand(MCOperand::createImm(12 * ShifterVal)); 1804 return Success; 1805 } 1806 1807 static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, 1808 uint64_t Addr, 1809 const MCDisassembler *Decoder) { 1810 int64_t imm = fieldFromInstruction(insn, 0, 26); 1811 1812 // Sign-extend the 26-bit immediate. 1813 if (imm & (1 << (26 - 1))) 1814 imm |= ~((1LL << 26) - 1); 1815 1816 if (!Decoder->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 0, 4)) 1817 Inst.addOperand(MCOperand::createImm(imm)); 1818 1819 return Success; 1820 } 1821 1822 static bool isInvalidPState(uint64_t Op1, uint64_t Op2) { 1823 return Op1 == 0b000 && (Op2 == 0b000 || // CFINV 1824 Op2 == 0b001 || // XAFlag 1825 Op2 == 0b010); // AXFlag 1826 } 1827 1828 static DecodeStatus 1829 DecodeSystemPStateImm0_15Instruction(MCInst &Inst, uint32_t insn, uint64_t Addr, 1830 const MCDisassembler *Decoder) { 1831 uint64_t op1 = fieldFromInstruction(insn, 16, 3); 1832 uint64_t op2 = fieldFromInstruction(insn, 5, 3); 1833 uint64_t imm = fieldFromInstruction(insn, 8, 4); 1834 uint64_t pstate_field = (op1 << 3) | op2; 1835 1836 if (isInvalidPState(op1, op2)) 1837 return Fail; 1838 1839 Inst.addOperand(MCOperand::createImm(pstate_field)); 1840 Inst.addOperand(MCOperand::createImm(imm)); 1841 1842 auto PState = AArch64PState::lookupPStateImm0_15ByEncoding(pstate_field); 1843 if (PState && 1844 PState->haveFeatures(Decoder->getSubtargetInfo().getFeatureBits())) 1845 return Success; 1846 return Fail; 1847 } 1848 1849 static DecodeStatus 1850 DecodeSystemPStateImm0_1Instruction(MCInst &Inst, uint32_t insn, uint64_t Addr, 1851 const MCDisassembler *Decoder) { 1852 uint64_t op1 = fieldFromInstruction(insn, 16, 3); 1853 uint64_t op2 = fieldFromInstruction(insn, 5, 3); 1854 uint64_t crm_high = fieldFromInstruction(insn, 9, 3); 1855 uint64_t imm = fieldFromInstruction(insn, 8, 1); 1856 uint64_t pstate_field = (crm_high << 6) | (op1 << 3) | op2; 1857 1858 if (isInvalidPState(op1, op2)) 1859 return Fail; 1860 1861 Inst.addOperand(MCOperand::createImm(pstate_field)); 1862 Inst.addOperand(MCOperand::createImm(imm)); 1863 1864 auto PState = AArch64PState::lookupPStateImm0_1ByEncoding(pstate_field); 1865 if (PState && 1866 PState->haveFeatures(Decoder->getSubtargetInfo().getFeatureBits())) 1867 return Success; 1868 return Fail; 1869 } 1870 1871 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, 1872 uint64_t Addr, 1873 const MCDisassembler *Decoder) { 1874 uint64_t Rt = fieldFromInstruction(insn, 0, 5); 1875 uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5; 1876 bit |= fieldFromInstruction(insn, 19, 5); 1877 int64_t dst = fieldFromInstruction(insn, 5, 14); 1878 1879 // Sign-extend 14-bit immediate. 1880 if (dst & (1 << (14 - 1))) 1881 dst |= ~((1LL << 14) - 1); 1882 1883 if (fieldFromInstruction(insn, 31, 1) == 0) 1884 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1885 else 1886 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1887 Inst.addOperand(MCOperand::createImm(bit)); 1888 if (!Decoder->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 0, 4)) 1889 Inst.addOperand(MCOperand::createImm(dst)); 1890 1891 return Success; 1892 } 1893 1894 static DecodeStatus 1895 DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegClassID, 1896 unsigned RegNo, uint64_t Addr, 1897 const MCDisassembler *Decoder) { 1898 // Register number must be even (see CASP instruction) 1899 if (RegNo & 0x1) 1900 return Fail; 1901 1902 unsigned Reg = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo / 2); 1903 Inst.addOperand(MCOperand::createReg(Reg)); 1904 return Success; 1905 } 1906 1907 static DecodeStatus 1908 DecodeWSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, 1909 const MCDisassembler *Decoder) { 1910 return DecodeGPRSeqPairsClassRegisterClass(Inst, 1911 AArch64::WSeqPairsClassRegClassID, 1912 RegNo, Addr, Decoder); 1913 } 1914 1915 static DecodeStatus 1916 DecodeXSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, 1917 const MCDisassembler *Decoder) { 1918 return DecodeGPRSeqPairsClassRegisterClass(Inst, 1919 AArch64::XSeqPairsClassRegClassID, 1920 RegNo, Addr, Decoder); 1921 } 1922 1923 static DecodeStatus DecodeSyspXzrInstruction(MCInst &Inst, uint32_t insn, 1924 uint64_t Addr, 1925 const MCDisassembler *Decoder) { 1926 unsigned op1 = fieldFromInstruction(insn, 16, 3); 1927 unsigned CRn = fieldFromInstruction(insn, 12, 4); 1928 unsigned CRm = fieldFromInstruction(insn, 8, 4); 1929 unsigned op2 = fieldFromInstruction(insn, 5, 3); 1930 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1931 if (Rt != 0b11111) 1932 return Fail; 1933 1934 Inst.addOperand(MCOperand::createImm(op1)); 1935 Inst.addOperand(MCOperand::createImm(CRn)); 1936 Inst.addOperand(MCOperand::createImm(CRm)); 1937 Inst.addOperand(MCOperand::createImm(op2)); 1938 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1939 1940 return Success; 1941 } 1942 1943 static DecodeStatus 1944 DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, 1945 const MCDisassembler *Decoder) { 1946 unsigned Zdn = fieldFromInstruction(insn, 0, 5); 1947 unsigned imm = fieldFromInstruction(insn, 5, 13); 1948 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64)) 1949 return Fail; 1950 1951 // The same (tied) operand is added twice to the instruction. 1952 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); 1953 if (Inst.getOpcode() != AArch64::DUPM_ZI) 1954 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); 1955 Inst.addOperand(MCOperand::createImm(imm)); 1956 return Success; 1957 } 1958 1959 template <int Bits> 1960 static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address, 1961 const MCDisassembler *Decoder) { 1962 if (Imm & ~((1LL << Bits) - 1)) 1963 return Fail; 1964 1965 // Imm is a signed immediate, so sign extend it. 1966 if (Imm & (1 << (Bits - 1))) 1967 Imm |= ~((1LL << Bits) - 1); 1968 1969 Inst.addOperand(MCOperand::createImm(Imm)); 1970 return Success; 1971 } 1972 1973 // Decode 8-bit signed/unsigned immediate for a given element width. 1974 template <int ElementWidth> 1975 static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, uint64_t Addr, 1976 const MCDisassembler *Decoder) { 1977 unsigned Val = (uint8_t)Imm; 1978 unsigned Shift = (Imm & 0x100) ? 8 : 0; 1979 if (ElementWidth == 8 && Shift) 1980 return Fail; 1981 Inst.addOperand(MCOperand::createImm(Val)); 1982 Inst.addOperand(MCOperand::createImm(Shift)); 1983 return Success; 1984 } 1985 1986 // Decode uimm4 ranged from 1-16. 1987 static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, 1988 uint64_t Addr, 1989 const MCDisassembler *Decoder) { 1990 Inst.addOperand(MCOperand::createImm(Imm + 1)); 1991 return Success; 1992 } 1993 1994 static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address, 1995 const MCDisassembler *Decoder) { 1996 if (AArch64SVCR::lookupSVCRByEncoding(Imm)) { 1997 Inst.addOperand(MCOperand::createImm(Imm)); 1998 return Success; 1999 } 2000 return Fail; 2001 } 2002 2003 static DecodeStatus DecodeCPYMemOpInstruction(MCInst &Inst, uint32_t insn, 2004 uint64_t Addr, 2005 const MCDisassembler *Decoder) { 2006 unsigned Rd = fieldFromInstruction(insn, 0, 5); 2007 unsigned Rs = fieldFromInstruction(insn, 16, 5); 2008 unsigned Rn = fieldFromInstruction(insn, 5, 5); 2009 2010 // None of the registers may alias: if they do, then the instruction is not 2011 // merely unpredictable but actually entirely unallocated. 2012 if (Rd == Rs || Rs == Rn || Rd == Rn) 2013 return MCDisassembler::Fail; 2014 2015 // All three register operands are written back, so they all appear 2016 // twice in the operand list, once as outputs and once as inputs. 2017 if (!DecodeGPR64commonRegisterClass(Inst, Rd, Addr, Decoder) || 2018 !DecodeGPR64commonRegisterClass(Inst, Rs, Addr, Decoder) || 2019 !DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder) || 2020 !DecodeGPR64commonRegisterClass(Inst, Rd, Addr, Decoder) || 2021 !DecodeGPR64commonRegisterClass(Inst, Rs, Addr, Decoder) || 2022 !DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder)) 2023 return MCDisassembler::Fail; 2024 2025 return MCDisassembler::Success; 2026 } 2027 2028 static DecodeStatus DecodeSETMemOpInstruction(MCInst &Inst, uint32_t insn, 2029 uint64_t Addr, 2030 const MCDisassembler *Decoder) { 2031 unsigned Rd = fieldFromInstruction(insn, 0, 5); 2032 unsigned Rm = fieldFromInstruction(insn, 16, 5); 2033 unsigned Rn = fieldFromInstruction(insn, 5, 5); 2034 2035 // None of the registers may alias: if they do, then the instruction is not 2036 // merely unpredictable but actually entirely unallocated. 2037 if (Rd == Rm || Rm == Rn || Rd == Rn) 2038 return MCDisassembler::Fail; 2039 2040 // Rd and Rn (not Rm) register operands are written back, so they appear 2041 // twice in the operand list, once as outputs and once as inputs. 2042 if (!DecodeGPR64commonRegisterClass(Inst, Rd, Addr, Decoder) || 2043 !DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder) || 2044 !DecodeGPR64commonRegisterClass(Inst, Rd, Addr, Decoder) || 2045 !DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder) || 2046 !DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder)) 2047 return MCDisassembler::Fail; 2048 2049 return MCDisassembler::Success; 2050 } 2051 2052 static DecodeStatus DecodePRFMRegInstruction(MCInst &Inst, uint32_t insn, 2053 uint64_t Addr, 2054 const MCDisassembler *Decoder) { 2055 // PRFM with Rt = '11xxx' should be decoded as RPRFM. 2056 // Fail to decode and defer to fallback decoder table to decode RPRFM. 2057 unsigned Mask = 0x18; 2058 uint64_t Rt = fieldFromInstruction(insn, 0, 5); 2059 if ((Rt & Mask) == Mask) 2060 return Fail; 2061 2062 uint64_t Rn = fieldFromInstruction(insn, 5, 5); 2063 uint64_t Shift = fieldFromInstruction(insn, 12, 1); 2064 uint64_t Extend = fieldFromInstruction(insn, 15, 1); 2065 uint64_t Rm = fieldFromInstruction(insn, 16, 5); 2066 2067 Inst.addOperand(MCOperand::createImm(Rt)); 2068 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 2069 2070 switch (Inst.getOpcode()) { 2071 default: 2072 return Fail; 2073 case AArch64::PRFMroW: 2074 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 2075 break; 2076 case AArch64::PRFMroX: 2077 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 2078 break; 2079 } 2080 2081 DecodeMemExtend(Inst, (Extend << 1) | Shift, Addr, Decoder); 2082 2083 return Success; 2084 } 2085