1 //===-- AArch64InstPrinter.h - Convert AArch64 MCInst to assembly syntax --===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This class prints an AArch64 MCInst to a .s file. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64INSTPRINTER_H 14 #define LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64INSTPRINTER_H 15 16 #include "MCTargetDesc/AArch64MCTargetDesc.h" 17 #include "llvm/ADT/StringRef.h" 18 #include "llvm/MC/MCInstPrinter.h" 19 #include "../Utils/AArch64BaseInfo.h" 20 21 namespace llvm { 22 23 class AArch64InstPrinter : public MCInstPrinter { 24 public: 25 AArch64InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, 26 const MCRegisterInfo &MRI); 27 28 bool applyTargetSpecificCLOption(StringRef Opt) override; 29 30 void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, 31 const MCSubtargetInfo &STI, raw_ostream &O) override; 32 void printRegName(raw_ostream &OS, MCRegister Reg) const override; 33 void printRegName(raw_ostream &OS, MCRegister Reg, unsigned AltIdx) const; 34 35 // Autogenerated by tblgen. 36 std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override; 37 virtual void printInstruction(const MCInst *MI, uint64_t Address, 38 const MCSubtargetInfo &STI, raw_ostream &O); 39 virtual bool printAliasInstr(const MCInst *MI, uint64_t Address, 40 const MCSubtargetInfo &STI, raw_ostream &O); 41 virtual void printCustomAliasOperand(const MCInst *MI, uint64_t Address, 42 unsigned OpIdx, unsigned PrintMethodIdx, 43 const MCSubtargetInfo &STI, 44 raw_ostream &O); 45 46 virtual StringRef getRegName(MCRegister Reg) const; 47 48 static const char *getRegisterName(MCRegister Reg, 49 unsigned AltIdx = AArch64::NoRegAltName); 50 51 protected: 52 bool printSysAlias(const MCInst *MI, const MCSubtargetInfo &STI, 53 raw_ostream &O); 54 bool printSyspAlias(const MCInst *MI, const MCSubtargetInfo &STI, 55 raw_ostream &O); 56 bool printRangePrefetchAlias(const MCInst *MI, const MCSubtargetInfo &STI, 57 raw_ostream &O, StringRef Annot); 58 // Operand printers 59 void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, 60 raw_ostream &O); 61 void printImm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, 62 raw_ostream &O); 63 void printImmHex(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, 64 raw_ostream &O); 65 template <int Size> 66 void printSImm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, 67 raw_ostream &O); 68 template <typename T> void printImmSVE(T Value, raw_ostream &O); 69 void printPostIncOperand(const MCInst *MI, unsigned OpNo, unsigned Imm, 70 raw_ostream &O); 71 template <int Amount> printPostIncOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O)72 void printPostIncOperand(const MCInst *MI, unsigned OpNo, 73 const MCSubtargetInfo &STI, raw_ostream &O) { 74 printPostIncOperand(MI, OpNo, Amount, O); 75 } 76 77 void printVRegOperand(const MCInst *MI, unsigned OpNo, 78 const MCSubtargetInfo &STI, raw_ostream &O); 79 void printSysCROperand(const MCInst *MI, unsigned OpNo, 80 const MCSubtargetInfo &STI, raw_ostream &O); 81 void printAddSubImm(const MCInst *MI, unsigned OpNum, 82 const MCSubtargetInfo &STI, raw_ostream &O); 83 template <typename T> 84 void printLogicalImm(const MCInst *MI, unsigned OpNum, 85 const MCSubtargetInfo &STI, raw_ostream &O); 86 void printShifter(const MCInst *MI, unsigned OpNum, 87 const MCSubtargetInfo &STI, raw_ostream &O); 88 void printShiftedRegister(const MCInst *MI, unsigned OpNum, 89 const MCSubtargetInfo &STI, raw_ostream &O); 90 void printExtendedRegister(const MCInst *MI, unsigned OpNum, 91 const MCSubtargetInfo &STI, raw_ostream &O); 92 void printArithExtend(const MCInst *MI, unsigned OpNum, 93 const MCSubtargetInfo &STI, raw_ostream &O); 94 void printMemExtendImpl(bool SignExtend, bool DoShift, unsigned Width, 95 char SrcRegKind, raw_ostream &O); 96 void printMemExtend(const MCInst *MI, unsigned OpNum, raw_ostream &O, 97 char SrcRegKind, unsigned Width); 98 template <char SrcRegKind, unsigned Width> printMemExtend(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)99 void printMemExtend(const MCInst *MI, unsigned OpNum, 100 const MCSubtargetInfo &STI, raw_ostream &O) { 101 printMemExtend(MI, OpNum, O, SrcRegKind, Width); 102 } 103 template <bool SignedExtend, int ExtWidth, char SrcRegKind, char Suffix> 104 void printRegWithShiftExtend(const MCInst *MI, unsigned OpNum, 105 const MCSubtargetInfo &STI, raw_ostream &O); 106 void printCondCode(const MCInst *MI, unsigned OpNum, 107 const MCSubtargetInfo &STI, raw_ostream &O); 108 void printInverseCondCode(const MCInst *MI, unsigned OpNum, 109 const MCSubtargetInfo &STI, raw_ostream &O); 110 void printAlignedLabel(const MCInst *MI, uint64_t Address, unsigned OpNum, 111 const MCSubtargetInfo &STI, raw_ostream &O); 112 void printUImm12Offset(const MCInst *MI, unsigned OpNum, unsigned Scale, 113 raw_ostream &O); 114 void printAMIndexedWB(const MCInst *MI, unsigned OpNum, unsigned Scale, 115 raw_ostream &O); 116 117 template <int Scale> printUImm12Offset(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)118 void printUImm12Offset(const MCInst *MI, unsigned OpNum, 119 const MCSubtargetInfo &STI, raw_ostream &O) { 120 printUImm12Offset(MI, OpNum, Scale, O); 121 } 122 123 template <int BitWidth> printAMIndexedWB(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)124 void printAMIndexedWB(const MCInst *MI, unsigned OpNum, 125 const MCSubtargetInfo &STI, raw_ostream &O) { 126 printAMIndexedWB(MI, OpNum, BitWidth / 8, O); 127 } 128 129 void printAMNoIndex(const MCInst *MI, unsigned OpNum, 130 const MCSubtargetInfo &STI, raw_ostream &O); 131 132 template <int Scale> 133 void printImmScale(const MCInst *MI, unsigned OpNum, 134 const MCSubtargetInfo &STI, raw_ostream &O); 135 136 template <int Scale, int Offset> 137 void printImmRangeScale(const MCInst *MI, unsigned OpNum, 138 const MCSubtargetInfo &STI, raw_ostream &O); 139 140 template <bool IsSVEPrefetch = false> 141 void printPrefetchOp(const MCInst *MI, unsigned OpNum, 142 const MCSubtargetInfo &STI, raw_ostream &O); 143 144 void printRPRFMOperand(const MCInst *MI, unsigned OpNum, 145 const MCSubtargetInfo &STI, raw_ostream &O); 146 147 void printPSBHintOp(const MCInst *MI, unsigned OpNum, 148 const MCSubtargetInfo &STI, raw_ostream &O); 149 150 void printBTIHintOp(const MCInst *MI, unsigned OpNum, 151 const MCSubtargetInfo &STI, raw_ostream &O); 152 153 void printFPImmOperand(const MCInst *MI, unsigned OpNum, 154 const MCSubtargetInfo &STI, raw_ostream &O); 155 156 void printVectorList(const MCInst *MI, unsigned OpNum, 157 const MCSubtargetInfo &STI, raw_ostream &O, 158 StringRef LayoutSuffix); 159 160 void printMatrixTileList(const MCInst *MI, unsigned OpNum, 161 const MCSubtargetInfo &STI, raw_ostream &O); 162 163 /// Print a list of vector registers where the type suffix is implicit 164 /// (i.e. attached to the instruction rather than the registers). 165 void printImplicitlyTypedVectorList(const MCInst *MI, unsigned OpNum, 166 const MCSubtargetInfo &STI, 167 raw_ostream &O); 168 169 template <unsigned NumLanes, char LaneKind> 170 void printTypedVectorList(const MCInst *MI, unsigned OpNum, 171 const MCSubtargetInfo &STI, raw_ostream &O); 172 173 template <unsigned Scale = 1> 174 void printVectorIndex(const MCInst *MI, unsigned OpNum, 175 const MCSubtargetInfo &STI, raw_ostream &O); 176 template <unsigned Scale = 1> 177 void printMatrixIndex(const MCInst *MI, unsigned OpNum, 178 const MCSubtargetInfo &STI, raw_ostream &O); 179 void printAdrAdrpLabel(const MCInst *MI, uint64_t Address, unsigned OpNum, 180 const MCSubtargetInfo &STI, raw_ostream &O); 181 void printBarrierOption(const MCInst *MI, unsigned OpNum, 182 const MCSubtargetInfo &STI, raw_ostream &O); 183 void printBarriernXSOption(const MCInst *MI, unsigned OpNum, 184 const MCSubtargetInfo &STI, raw_ostream &O); 185 void printMSRSystemRegister(const MCInst *MI, unsigned OpNum, 186 const MCSubtargetInfo &STI, raw_ostream &O); 187 void printMRSSystemRegister(const MCInst *MI, unsigned OpNum, 188 const MCSubtargetInfo &STI, raw_ostream &O); 189 void printSystemPStateField(const MCInst *MI, unsigned OpNum, 190 const MCSubtargetInfo &STI, raw_ostream &O); 191 void printSIMDType10Operand(const MCInst *MI, unsigned OpNum, 192 const MCSubtargetInfo &STI, raw_ostream &O); 193 template <int EltSize> 194 void printPredicateAsCounter(const MCInst *MI, unsigned OpNum, 195 const MCSubtargetInfo &STI, raw_ostream &O); 196 template<int64_t Angle, int64_t Remainder> 197 void printComplexRotationOp(const MCInst *MI, unsigned OpNo, 198 const MCSubtargetInfo &STI, raw_ostream &O); 199 template<unsigned size> 200 void printGPRSeqPairsClassOperand(const MCInst *MI, unsigned OpNum, 201 const MCSubtargetInfo &STI, 202 raw_ostream &O); 203 template <typename T> 204 void printImm8OptLsl(const MCInst *MI, unsigned OpNum, 205 const MCSubtargetInfo &STI, raw_ostream &O); 206 template <typename T> 207 void printSVELogicalImm(const MCInst *MI, unsigned OpNum, 208 const MCSubtargetInfo &STI, raw_ostream &O); 209 void printSVEPattern(const MCInst *MI, unsigned OpNum, 210 const MCSubtargetInfo &STI, raw_ostream &O); 211 void printSVEVecLenSpecifier(const MCInst *MI, unsigned OpNum, 212 const MCSubtargetInfo &STI, raw_ostream &O); 213 214 template <bool IsVertical> 215 void printMatrixTileVector(const MCInst *MI, unsigned OpNum, 216 const MCSubtargetInfo &STI, raw_ostream &O); 217 void printMatrixTile(const MCInst *MI, unsigned OpNum, 218 const MCSubtargetInfo &STI, raw_ostream &O); 219 template <int EltSize> 220 void printMatrix(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, 221 raw_ostream &O); 222 void printSVCROp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, 223 raw_ostream &O); 224 template <char = 0> 225 void printSVERegOp(const MCInst *MI, unsigned OpNum, 226 const MCSubtargetInfo &STI, raw_ostream &O); 227 void printGPR64as32(const MCInst *MI, unsigned OpNum, 228 const MCSubtargetInfo &STI, raw_ostream &O); 229 void printGPR64x8(const MCInst *MI, unsigned OpNum, 230 const MCSubtargetInfo &STI, raw_ostream &O); 231 void printSyspXzrPair(const MCInst *MI, unsigned OpNum, 232 const MCSubtargetInfo &STI, raw_ostream &O); 233 template <int Width> 234 void printZPRasFPR(const MCInst *MI, unsigned OpNum, 235 const MCSubtargetInfo &STI, raw_ostream &O); 236 template <unsigned ImmIs0, unsigned ImmIs1> 237 void printExactFPImm(const MCInst *MI, unsigned OpNum, 238 const MCSubtargetInfo &STI, raw_ostream &O); 239 }; 240 241 class AArch64AppleInstPrinter : public AArch64InstPrinter { 242 public: 243 AArch64AppleInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, 244 const MCRegisterInfo &MRI); 245 246 void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, 247 const MCSubtargetInfo &STI, raw_ostream &O) override; 248 249 std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override; 250 void printInstruction(const MCInst *MI, uint64_t Address, 251 const MCSubtargetInfo &STI, raw_ostream &O) override; 252 bool printAliasInstr(const MCInst *MI, uint64_t Address, 253 const MCSubtargetInfo &STI, raw_ostream &O) override; 254 void printCustomAliasOperand(const MCInst *MI, uint64_t Address, 255 unsigned OpIdx, unsigned PrintMethodIdx, 256 const MCSubtargetInfo &STI, 257 raw_ostream &O) override; 258 259 StringRef getRegName(MCRegister Reg) const override; 260 261 static const char *getRegisterName(MCRegister Reg, 262 unsigned AltIdx = AArch64::NoRegAltName); 263 }; 264 265 } // end namespace llvm 266 267 #endif // LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64INSTPRINTER_H 268