1 //===-- AArch64MCTargetDesc.h - AArch64 Target Descriptions -----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides AArch64 specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64MCTARGETDESC_H
14 #define LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64MCTARGETDESC_H
15 
16 #include "llvm/MC/MCInstrDesc.h"
17 #include "llvm/Support/DataTypes.h"
18 
19 #include <memory>
20 
21 namespace llvm {
22 class formatted_raw_ostream;
23 class MCAsmBackend;
24 class MCCodeEmitter;
25 class MCContext;
26 class MCInst;
27 class MCInstrInfo;
28 class MCInstPrinter;
29 class MCRegisterInfo;
30 class MCObjectTargetWriter;
31 class MCStreamer;
32 class MCSubtargetInfo;
33 class MCTargetOptions;
34 class MCTargetStreamer;
35 class Target;
36 class FeatureBitset;
37 
38 MCCodeEmitter *createAArch64MCCodeEmitter(const MCInstrInfo &MCII,
39                                           MCContext &Ctx);
40 MCAsmBackend *createAArch64leAsmBackend(const Target &T,
41                                         const MCSubtargetInfo &STI,
42                                         const MCRegisterInfo &MRI,
43                                         const MCTargetOptions &Options);
44 MCAsmBackend *createAArch64beAsmBackend(const Target &T,
45                                         const MCSubtargetInfo &STI,
46                                         const MCRegisterInfo &MRI,
47                                         const MCTargetOptions &Options);
48 
49 std::unique_ptr<MCObjectTargetWriter>
50 createAArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32);
51 
52 std::unique_ptr<MCObjectTargetWriter>
53 createAArch64MachObjectWriter(uint32_t CPUType, uint32_t CPUSubtype,
54                               bool IsILP32);
55 
56 std::unique_ptr<MCObjectTargetWriter> createAArch64WinCOFFObjectWriter();
57 
58 MCTargetStreamer *createAArch64AsmTargetStreamer(MCStreamer &S,
59                                                  formatted_raw_ostream &OS,
60                                                  MCInstPrinter *InstPrint,
61                                                  bool isVerboseAsm);
62 
63 namespace AArch64_MC {
64 void initLLVMToCVRegMapping(MCRegisterInfo *MRI);
65 bool isQForm(const MCInst &MI, const MCInstrInfo *MCII);
66 bool isFpOrNEON(const MCInst &MI, const MCInstrInfo *MCII);
67 }
68 
69 namespace AArch64 {
70 enum OperandType {
71   OPERAND_IMPLICIT_IMM_0 = MCOI::OPERAND_FIRST_TARGET,
72 };
73 } // namespace AArch64
74 
75 } // End llvm namespace
76 
77 // Defines symbolic names for AArch64 registers.  This defines a mapping from
78 // register name to register number.
79 //
80 #define GET_REGINFO_ENUM
81 #include "AArch64GenRegisterInfo.inc"
82 
83 // Defines symbolic names for the AArch64 instructions.
84 //
85 #define GET_INSTRINFO_ENUM
86 #define GET_INSTRINFO_MC_HELPER_DECLS
87 #include "AArch64GenInstrInfo.inc"
88 
89 #define GET_SUBTARGETINFO_ENUM
90 #include "AArch64GenSubtargetInfo.inc"
91 
92 #endif
93