1 //===-- AArch64MCTargetDesc.h - AArch64 Target Descriptions -----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides AArch64 specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64MCTARGETDESC_H
14 #define LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64MCTARGETDESC_H
15 
16 #include "llvm/Support/DataTypes.h"
17 
18 #include <memory>
19 
20 namespace llvm {
21 class formatted_raw_ostream;
22 class MCAsmBackend;
23 class MCCodeEmitter;
24 class MCContext;
25 class MCInstrInfo;
26 class MCInstPrinter;
27 class MCRegisterInfo;
28 class MCObjectTargetWriter;
29 class MCStreamer;
30 class MCSubtargetInfo;
31 class MCTargetOptions;
32 class MCTargetStreamer;
33 class StringRef;
34 class Target;
35 class Triple;
36 class raw_ostream;
37 class raw_pwrite_stream;
38 
39 MCCodeEmitter *createAArch64MCCodeEmitter(const MCInstrInfo &MCII,
40                                           const MCRegisterInfo &MRI,
41                                           MCContext &Ctx);
42 MCAsmBackend *createAArch64leAsmBackend(const Target &T,
43                                         const MCSubtargetInfo &STI,
44                                         const MCRegisterInfo &MRI,
45                                         const MCTargetOptions &Options);
46 MCAsmBackend *createAArch64beAsmBackend(const Target &T,
47                                         const MCSubtargetInfo &STI,
48                                         const MCRegisterInfo &MRI,
49                                         const MCTargetOptions &Options);
50 
51 std::unique_ptr<MCObjectTargetWriter>
52 createAArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32);
53 
54 std::unique_ptr<MCObjectTargetWriter>
55 createAArch64MachObjectWriter(uint32_t CPUType, uint32_t CPUSubtype,
56                               bool IsILP32);
57 
58 std::unique_ptr<MCObjectTargetWriter> createAArch64WinCOFFObjectWriter();
59 
60 MCTargetStreamer *createAArch64AsmTargetStreamer(MCStreamer &S,
61                                                  formatted_raw_ostream &OS,
62                                                  MCInstPrinter *InstPrint,
63                                                  bool isVerboseAsm);
64 
65 MCTargetStreamer *createAArch64ObjectTargetStreamer(MCStreamer &S,
66                                                     const MCSubtargetInfo &STI);
67 
68 namespace AArch64_MC {
69 void initLLVMToCVRegMapping(MCRegisterInfo *MRI);
70 }
71 
72 } // End llvm namespace
73 
74 // Defines symbolic names for AArch64 registers.  This defines a mapping from
75 // register name to register number.
76 //
77 #define GET_REGINFO_ENUM
78 #include "AArch64GenRegisterInfo.inc"
79 
80 // Defines symbolic names for the AArch64 instructions.
81 //
82 #define GET_INSTRINFO_ENUM
83 #define GET_INSTRINFO_MC_HELPER_DECLS
84 #include "AArch64GenInstrInfo.inc"
85 
86 #define GET_SUBTARGETINFO_ENUM
87 #include "AArch64GenSubtargetInfo.inc"
88 
89 #endif
90