1 //===-- AArch64MCTargetDesc.h - AArch64 Target Descriptions -----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides AArch64 specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64MCTARGETDESC_H
14 #define LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64MCTARGETDESC_H
15 
16 #include "llvm/MC/MCInstrDesc.h"
17 #include "llvm/Support/DataTypes.h"
18 
19 #include <memory>
20 
21 namespace llvm {
22 class formatted_raw_ostream;
23 class MCAsmBackend;
24 class MCCodeEmitter;
25 class MCContext;
26 class MCInst;
27 class MCInstrInfo;
28 class MCInstPrinter;
29 class MCRegisterInfo;
30 class MCObjectTargetWriter;
31 class MCStreamer;
32 class MCSubtargetInfo;
33 class MCTargetOptions;
34 class MCTargetStreamer;
35 class Target;
36 
37 MCCodeEmitter *createAArch64MCCodeEmitter(const MCInstrInfo &MCII,
38                                           MCContext &Ctx);
39 MCAsmBackend *createAArch64leAsmBackend(const Target &T,
40                                         const MCSubtargetInfo &STI,
41                                         const MCRegisterInfo &MRI,
42                                         const MCTargetOptions &Options);
43 MCAsmBackend *createAArch64beAsmBackend(const Target &T,
44                                         const MCSubtargetInfo &STI,
45                                         const MCRegisterInfo &MRI,
46                                         const MCTargetOptions &Options);
47 
48 std::unique_ptr<MCObjectTargetWriter>
49 createAArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32);
50 
51 std::unique_ptr<MCObjectTargetWriter>
52 createAArch64MachObjectWriter(uint32_t CPUType, uint32_t CPUSubtype,
53                               bool IsILP32);
54 
55 std::unique_ptr<MCObjectTargetWriter> createAArch64WinCOFFObjectWriter();
56 
57 MCTargetStreamer *createAArch64AsmTargetStreamer(MCStreamer &S,
58                                                  formatted_raw_ostream &OS,
59                                                  MCInstPrinter *InstPrint,
60                                                  bool isVerboseAsm);
61 
62 namespace AArch64_MC {
63 void initLLVMToCVRegMapping(MCRegisterInfo *MRI);
64 bool isQForm(const MCInst &MI, const MCInstrInfo *MCII);
65 bool isFpOrNEON(const MCInst &MI, const MCInstrInfo *MCII);
66 }
67 
68 namespace AArch64 {
69 enum OperandType {
70   OPERAND_IMPLICIT_IMM_0 = MCOI::OPERAND_FIRST_TARGET,
71 };
72 } // namespace AArch64
73 
74 } // End llvm namespace
75 
76 // Defines symbolic names for AArch64 registers.  This defines a mapping from
77 // register name to register number.
78 //
79 #define GET_REGINFO_ENUM
80 #include "AArch64GenRegisterInfo.inc"
81 
82 // Defines symbolic names for the AArch64 instructions.
83 //
84 #define GET_INSTRINFO_ENUM
85 #define GET_INSTRINFO_MC_HELPER_DECLS
86 #include "AArch64GenInstrInfo.inc"
87 
88 #define GET_SUBTARGETINFO_ENUM
89 #include "AArch64GenSubtargetInfo.inc"
90 
91 #endif
92