10b57cec5SDimitry Andric //===-- AArch64BaseInfo.cpp - AArch64 Base encoding information------------===//
20b57cec5SDimitry Andric //
30b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
40b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information.
50b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
60b57cec5SDimitry Andric //
70b57cec5SDimitry Andric //===----------------------------------------------------------------------===//
80b57cec5SDimitry Andric //
90b57cec5SDimitry Andric // This file provides basic encoding and assembly information for AArch64.
100b57cec5SDimitry Andric //
110b57cec5SDimitry Andric //===----------------------------------------------------------------------===//
120b57cec5SDimitry Andric #include "AArch64BaseInfo.h"
130b57cec5SDimitry Andric #include "llvm/ADT/ArrayRef.h"
140b57cec5SDimitry Andric #include "llvm/ADT/SmallVector.h"
150b57cec5SDimitry Andric #include "llvm/ADT/StringExtras.h"
160b57cec5SDimitry Andric #include "llvm/Support/Regex.h"
170b57cec5SDimitry Andric 
180b57cec5SDimitry Andric using namespace llvm;
190b57cec5SDimitry Andric 
200b57cec5SDimitry Andric namespace llvm {
210b57cec5SDimitry Andric   namespace AArch64AT {
220b57cec5SDimitry Andric #define GET_AT_IMPL
230b57cec5SDimitry Andric #include "AArch64GenSystemOperands.inc"
240b57cec5SDimitry Andric   }
250b57cec5SDimitry Andric }
260b57cec5SDimitry Andric 
270b57cec5SDimitry Andric 
280b57cec5SDimitry Andric namespace llvm {
29e8d8bef9SDimitry Andric   namespace AArch64DBnXS {
30e8d8bef9SDimitry Andric #define GET_DBNXS_IMPL
31e8d8bef9SDimitry Andric #include "AArch64GenSystemOperands.inc"
32e8d8bef9SDimitry Andric   }
33e8d8bef9SDimitry Andric }
34e8d8bef9SDimitry Andric 
35e8d8bef9SDimitry Andric namespace llvm {
360b57cec5SDimitry Andric   namespace AArch64DB {
370b57cec5SDimitry Andric #define GET_DB_IMPL
380b57cec5SDimitry Andric #include "AArch64GenSystemOperands.inc"
390b57cec5SDimitry Andric   }
400b57cec5SDimitry Andric }
410b57cec5SDimitry Andric 
420b57cec5SDimitry Andric namespace llvm {
430b57cec5SDimitry Andric   namespace AArch64DC {
440b57cec5SDimitry Andric #define GET_DC_IMPL
450b57cec5SDimitry Andric #include "AArch64GenSystemOperands.inc"
460b57cec5SDimitry Andric   }
470b57cec5SDimitry Andric }
480b57cec5SDimitry Andric 
490b57cec5SDimitry Andric namespace llvm {
500b57cec5SDimitry Andric   namespace AArch64IC {
510b57cec5SDimitry Andric #define GET_IC_IMPL
520b57cec5SDimitry Andric #include "AArch64GenSystemOperands.inc"
530b57cec5SDimitry Andric   }
540b57cec5SDimitry Andric }
550b57cec5SDimitry Andric 
560b57cec5SDimitry Andric namespace llvm {
570b57cec5SDimitry Andric   namespace AArch64ISB {
580b57cec5SDimitry Andric #define GET_ISB_IMPL
590b57cec5SDimitry Andric #include "AArch64GenSystemOperands.inc"
600b57cec5SDimitry Andric   }
610b57cec5SDimitry Andric }
620b57cec5SDimitry Andric 
630b57cec5SDimitry Andric namespace llvm {
640b57cec5SDimitry Andric   namespace AArch64TSB {
650b57cec5SDimitry Andric #define GET_TSB_IMPL
660b57cec5SDimitry Andric #include "AArch64GenSystemOperands.inc"
670b57cec5SDimitry Andric   }
680b57cec5SDimitry Andric }
690b57cec5SDimitry Andric 
700b57cec5SDimitry Andric namespace llvm {
710b57cec5SDimitry Andric   namespace AArch64PRCTX {
720b57cec5SDimitry Andric #define GET_PRCTX_IMPL
730b57cec5SDimitry Andric #include "AArch64GenSystemOperands.inc"
740b57cec5SDimitry Andric   }
750b57cec5SDimitry Andric }
760b57cec5SDimitry Andric 
770b57cec5SDimitry Andric namespace llvm {
780b57cec5SDimitry Andric   namespace AArch64PRFM {
790b57cec5SDimitry Andric #define GET_PRFM_IMPL
800b57cec5SDimitry Andric #include "AArch64GenSystemOperands.inc"
810b57cec5SDimitry Andric   }
820b57cec5SDimitry Andric }
830b57cec5SDimitry Andric 
840b57cec5SDimitry Andric namespace llvm {
850b57cec5SDimitry Andric   namespace AArch64SVEPRFM {
860b57cec5SDimitry Andric #define GET_SVEPRFM_IMPL
870b57cec5SDimitry Andric #include "AArch64GenSystemOperands.inc"
880b57cec5SDimitry Andric   }
890b57cec5SDimitry Andric }
900b57cec5SDimitry Andric 
910b57cec5SDimitry Andric namespace llvm {
92bdd1243dSDimitry Andric   namespace AArch64RPRFM {
93bdd1243dSDimitry Andric #define GET_RPRFM_IMPL
94bdd1243dSDimitry Andric #include "AArch64GenSystemOperands.inc"
95bdd1243dSDimitry Andric   } // namespace AArch64RPRFM
96bdd1243dSDimitry Andric } // namespace llvm
97bdd1243dSDimitry Andric 
98bdd1243dSDimitry Andric namespace llvm {
990b57cec5SDimitry Andric   namespace AArch64SVEPredPattern {
1000b57cec5SDimitry Andric #define GET_SVEPREDPAT_IMPL
1010b57cec5SDimitry Andric #include "AArch64GenSystemOperands.inc"
1020b57cec5SDimitry Andric   }
1030b57cec5SDimitry Andric }
1040b57cec5SDimitry Andric 
1050b57cec5SDimitry Andric namespace llvm {
106bdd1243dSDimitry Andric namespace AArch64SVEVecLenSpecifier {
107bdd1243dSDimitry Andric #define GET_SVEVECLENSPECIFIER_IMPL
108bdd1243dSDimitry Andric #include "AArch64GenSystemOperands.inc"
109bdd1243dSDimitry Andric } // namespace AArch64SVEVecLenSpecifier
110bdd1243dSDimitry Andric } // namespace llvm
111bdd1243dSDimitry Andric 
112bdd1243dSDimitry Andric namespace llvm {
1130b57cec5SDimitry Andric   namespace AArch64ExactFPImm {
1140b57cec5SDimitry Andric #define GET_EXACTFPIMM_IMPL
1150b57cec5SDimitry Andric #include "AArch64GenSystemOperands.inc"
1160b57cec5SDimitry Andric   }
1170b57cec5SDimitry Andric }
1180b57cec5SDimitry Andric 
1190b57cec5SDimitry Andric namespace llvm {
1200b57cec5SDimitry Andric   namespace AArch64PState {
121bdd1243dSDimitry Andric #define GET_PSTATEIMM0_15_IMPL
122bdd1243dSDimitry Andric #include "AArch64GenSystemOperands.inc"
123bdd1243dSDimitry Andric #define GET_PSTATEIMM0_1_IMPL
1240b57cec5SDimitry Andric #include "AArch64GenSystemOperands.inc"
1250b57cec5SDimitry Andric   }
1260b57cec5SDimitry Andric }
1270b57cec5SDimitry Andric 
1280b57cec5SDimitry Andric namespace llvm {
1290b57cec5SDimitry Andric   namespace AArch64PSBHint {
1300b57cec5SDimitry Andric #define GET_PSB_IMPL
1310b57cec5SDimitry Andric #include "AArch64GenSystemOperands.inc"
1320b57cec5SDimitry Andric   }
1330b57cec5SDimitry Andric }
1340b57cec5SDimitry Andric 
1350b57cec5SDimitry Andric namespace llvm {
1360b57cec5SDimitry Andric   namespace AArch64BTIHint {
1370b57cec5SDimitry Andric #define GET_BTI_IMPL
1380b57cec5SDimitry Andric #include "AArch64GenSystemOperands.inc"
1390b57cec5SDimitry Andric   }
1400b57cec5SDimitry Andric }
1410b57cec5SDimitry Andric 
1420b57cec5SDimitry Andric namespace llvm {
1430b57cec5SDimitry Andric   namespace AArch64SysReg {
1440b57cec5SDimitry Andric #define GET_SYSREG_IMPL
1450b57cec5SDimitry Andric #include "AArch64GenSystemOperands.inc"
1460b57cec5SDimitry Andric   }
1470b57cec5SDimitry Andric }
1480b57cec5SDimitry Andric 
parseGenericRegister(StringRef Name)1490b57cec5SDimitry Andric uint32_t AArch64SysReg::parseGenericRegister(StringRef Name) {
1500b57cec5SDimitry Andric   // Try to parse an S<op0>_<op1>_<Cn>_<Cm>_<op2> register name
1518bcb0991SDimitry Andric   static const Regex GenericRegPattern("^S([0-3])_([0-7])_C([0-9]|1[0-5])_C([0-9]|1[0-5])_([0-7])$");
1520b57cec5SDimitry Andric 
1530b57cec5SDimitry Andric   std::string UpperName = Name.upper();
1540b57cec5SDimitry Andric   SmallVector<StringRef, 5> Ops;
1550b57cec5SDimitry Andric   if (!GenericRegPattern.match(UpperName, &Ops))
1560b57cec5SDimitry Andric     return -1;
1570b57cec5SDimitry Andric 
1580b57cec5SDimitry Andric   uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0;
1590b57cec5SDimitry Andric   uint32_t Bits;
1600b57cec5SDimitry Andric   Ops[1].getAsInteger(10, Op0);
1610b57cec5SDimitry Andric   Ops[2].getAsInteger(10, Op1);
1620b57cec5SDimitry Andric   Ops[3].getAsInteger(10, CRn);
1630b57cec5SDimitry Andric   Ops[4].getAsInteger(10, CRm);
1640b57cec5SDimitry Andric   Ops[5].getAsInteger(10, Op2);
1650b57cec5SDimitry Andric   Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2;
1660b57cec5SDimitry Andric 
1670b57cec5SDimitry Andric   return Bits;
1680b57cec5SDimitry Andric }
1690b57cec5SDimitry Andric 
genericRegisterString(uint32_t Bits)1700b57cec5SDimitry Andric std::string AArch64SysReg::genericRegisterString(uint32_t Bits) {
1710b57cec5SDimitry Andric   assert(Bits < 0x10000);
1720b57cec5SDimitry Andric   uint32_t Op0 = (Bits >> 14) & 0x3;
1730b57cec5SDimitry Andric   uint32_t Op1 = (Bits >> 11) & 0x7;
1740b57cec5SDimitry Andric   uint32_t CRn = (Bits >> 7) & 0xf;
1750b57cec5SDimitry Andric   uint32_t CRm = (Bits >> 3) & 0xf;
1760b57cec5SDimitry Andric   uint32_t Op2 = Bits & 0x7;
1770b57cec5SDimitry Andric 
1780b57cec5SDimitry Andric   return "S" + utostr(Op0) + "_" + utostr(Op1) + "_C" + utostr(CRn) + "_C" +
1790b57cec5SDimitry Andric          utostr(CRm) + "_" + utostr(Op2);
1800b57cec5SDimitry Andric }
1810b57cec5SDimitry Andric 
1820b57cec5SDimitry Andric namespace llvm {
1830b57cec5SDimitry Andric   namespace AArch64TLBI {
184e8d8bef9SDimitry Andric #define GET_TLBITable_IMPL
1850b57cec5SDimitry Andric #include "AArch64GenSystemOperands.inc"
1860b57cec5SDimitry Andric   }
1870b57cec5SDimitry Andric }
188fe6060f1SDimitry Andric 
189fe6060f1SDimitry Andric namespace llvm {
190fe6060f1SDimitry Andric   namespace AArch64SVCR {
191fe6060f1SDimitry Andric #define GET_SVCR_IMPL
192fe6060f1SDimitry Andric #include "AArch64GenSystemOperands.inc"
193fe6060f1SDimitry Andric   }
194fe6060f1SDimitry Andric }
195