1 //===-- AArch64BaseInfo.h - Top level definitions for AArch64 ---*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains small standalone helper functions and enum definitions for 10 // the AArch64 target useful for the compiler back-end and the MC libraries. 11 // As such, it deliberately does not include references to LLVM core 12 // code gen types, passes, etc.. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #ifndef LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H 17 #define LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H 18 19 // FIXME: Is it easiest to fix this layering violation by moving the .inc 20 // #includes from AArch64MCTargetDesc.h to here? 21 #include "MCTargetDesc/AArch64MCTargetDesc.h" // For AArch64::X0 and friends. 22 #include "llvm/ADT/STLExtras.h" 23 #include "llvm/ADT/StringSwitch.h" 24 #include "llvm/MC/SubtargetFeature.h" 25 #include "llvm/Support/ErrorHandling.h" 26 27 namespace llvm { 28 29 inline static unsigned getWRegFromXReg(unsigned Reg) { 30 switch (Reg) { 31 case AArch64::X0: return AArch64::W0; 32 case AArch64::X1: return AArch64::W1; 33 case AArch64::X2: return AArch64::W2; 34 case AArch64::X3: return AArch64::W3; 35 case AArch64::X4: return AArch64::W4; 36 case AArch64::X5: return AArch64::W5; 37 case AArch64::X6: return AArch64::W6; 38 case AArch64::X7: return AArch64::W7; 39 case AArch64::X8: return AArch64::W8; 40 case AArch64::X9: return AArch64::W9; 41 case AArch64::X10: return AArch64::W10; 42 case AArch64::X11: return AArch64::W11; 43 case AArch64::X12: return AArch64::W12; 44 case AArch64::X13: return AArch64::W13; 45 case AArch64::X14: return AArch64::W14; 46 case AArch64::X15: return AArch64::W15; 47 case AArch64::X16: return AArch64::W16; 48 case AArch64::X17: return AArch64::W17; 49 case AArch64::X18: return AArch64::W18; 50 case AArch64::X19: return AArch64::W19; 51 case AArch64::X20: return AArch64::W20; 52 case AArch64::X21: return AArch64::W21; 53 case AArch64::X22: return AArch64::W22; 54 case AArch64::X23: return AArch64::W23; 55 case AArch64::X24: return AArch64::W24; 56 case AArch64::X25: return AArch64::W25; 57 case AArch64::X26: return AArch64::W26; 58 case AArch64::X27: return AArch64::W27; 59 case AArch64::X28: return AArch64::W28; 60 case AArch64::FP: return AArch64::W29; 61 case AArch64::LR: return AArch64::W30; 62 case AArch64::SP: return AArch64::WSP; 63 case AArch64::XZR: return AArch64::WZR; 64 } 65 // For anything else, return it unchanged. 66 return Reg; 67 } 68 69 inline static unsigned getXRegFromWReg(unsigned Reg) { 70 switch (Reg) { 71 case AArch64::W0: return AArch64::X0; 72 case AArch64::W1: return AArch64::X1; 73 case AArch64::W2: return AArch64::X2; 74 case AArch64::W3: return AArch64::X3; 75 case AArch64::W4: return AArch64::X4; 76 case AArch64::W5: return AArch64::X5; 77 case AArch64::W6: return AArch64::X6; 78 case AArch64::W7: return AArch64::X7; 79 case AArch64::W8: return AArch64::X8; 80 case AArch64::W9: return AArch64::X9; 81 case AArch64::W10: return AArch64::X10; 82 case AArch64::W11: return AArch64::X11; 83 case AArch64::W12: return AArch64::X12; 84 case AArch64::W13: return AArch64::X13; 85 case AArch64::W14: return AArch64::X14; 86 case AArch64::W15: return AArch64::X15; 87 case AArch64::W16: return AArch64::X16; 88 case AArch64::W17: return AArch64::X17; 89 case AArch64::W18: return AArch64::X18; 90 case AArch64::W19: return AArch64::X19; 91 case AArch64::W20: return AArch64::X20; 92 case AArch64::W21: return AArch64::X21; 93 case AArch64::W22: return AArch64::X22; 94 case AArch64::W23: return AArch64::X23; 95 case AArch64::W24: return AArch64::X24; 96 case AArch64::W25: return AArch64::X25; 97 case AArch64::W26: return AArch64::X26; 98 case AArch64::W27: return AArch64::X27; 99 case AArch64::W28: return AArch64::X28; 100 case AArch64::W29: return AArch64::FP; 101 case AArch64::W30: return AArch64::LR; 102 case AArch64::WSP: return AArch64::SP; 103 case AArch64::WZR: return AArch64::XZR; 104 } 105 // For anything else, return it unchanged. 106 return Reg; 107 } 108 109 static inline unsigned getBRegFromDReg(unsigned Reg) { 110 switch (Reg) { 111 case AArch64::D0: return AArch64::B0; 112 case AArch64::D1: return AArch64::B1; 113 case AArch64::D2: return AArch64::B2; 114 case AArch64::D3: return AArch64::B3; 115 case AArch64::D4: return AArch64::B4; 116 case AArch64::D5: return AArch64::B5; 117 case AArch64::D6: return AArch64::B6; 118 case AArch64::D7: return AArch64::B7; 119 case AArch64::D8: return AArch64::B8; 120 case AArch64::D9: return AArch64::B9; 121 case AArch64::D10: return AArch64::B10; 122 case AArch64::D11: return AArch64::B11; 123 case AArch64::D12: return AArch64::B12; 124 case AArch64::D13: return AArch64::B13; 125 case AArch64::D14: return AArch64::B14; 126 case AArch64::D15: return AArch64::B15; 127 case AArch64::D16: return AArch64::B16; 128 case AArch64::D17: return AArch64::B17; 129 case AArch64::D18: return AArch64::B18; 130 case AArch64::D19: return AArch64::B19; 131 case AArch64::D20: return AArch64::B20; 132 case AArch64::D21: return AArch64::B21; 133 case AArch64::D22: return AArch64::B22; 134 case AArch64::D23: return AArch64::B23; 135 case AArch64::D24: return AArch64::B24; 136 case AArch64::D25: return AArch64::B25; 137 case AArch64::D26: return AArch64::B26; 138 case AArch64::D27: return AArch64::B27; 139 case AArch64::D28: return AArch64::B28; 140 case AArch64::D29: return AArch64::B29; 141 case AArch64::D30: return AArch64::B30; 142 case AArch64::D31: return AArch64::B31; 143 } 144 // For anything else, return it unchanged. 145 return Reg; 146 } 147 148 149 static inline unsigned getDRegFromBReg(unsigned Reg) { 150 switch (Reg) { 151 case AArch64::B0: return AArch64::D0; 152 case AArch64::B1: return AArch64::D1; 153 case AArch64::B2: return AArch64::D2; 154 case AArch64::B3: return AArch64::D3; 155 case AArch64::B4: return AArch64::D4; 156 case AArch64::B5: return AArch64::D5; 157 case AArch64::B6: return AArch64::D6; 158 case AArch64::B7: return AArch64::D7; 159 case AArch64::B8: return AArch64::D8; 160 case AArch64::B9: return AArch64::D9; 161 case AArch64::B10: return AArch64::D10; 162 case AArch64::B11: return AArch64::D11; 163 case AArch64::B12: return AArch64::D12; 164 case AArch64::B13: return AArch64::D13; 165 case AArch64::B14: return AArch64::D14; 166 case AArch64::B15: return AArch64::D15; 167 case AArch64::B16: return AArch64::D16; 168 case AArch64::B17: return AArch64::D17; 169 case AArch64::B18: return AArch64::D18; 170 case AArch64::B19: return AArch64::D19; 171 case AArch64::B20: return AArch64::D20; 172 case AArch64::B21: return AArch64::D21; 173 case AArch64::B22: return AArch64::D22; 174 case AArch64::B23: return AArch64::D23; 175 case AArch64::B24: return AArch64::D24; 176 case AArch64::B25: return AArch64::D25; 177 case AArch64::B26: return AArch64::D26; 178 case AArch64::B27: return AArch64::D27; 179 case AArch64::B28: return AArch64::D28; 180 case AArch64::B29: return AArch64::D29; 181 case AArch64::B30: return AArch64::D30; 182 case AArch64::B31: return AArch64::D31; 183 } 184 // For anything else, return it unchanged. 185 return Reg; 186 } 187 188 static inline bool atomicBarrierDroppedOnZero(unsigned Opcode) { 189 switch (Opcode) { 190 case AArch64::LDADDAB: case AArch64::LDADDAH: 191 case AArch64::LDADDAW: case AArch64::LDADDAX: 192 case AArch64::LDADDALB: case AArch64::LDADDALH: 193 case AArch64::LDADDALW: case AArch64::LDADDALX: 194 case AArch64::LDCLRAB: case AArch64::LDCLRAH: 195 case AArch64::LDCLRAW: case AArch64::LDCLRAX: 196 case AArch64::LDCLRALB: case AArch64::LDCLRALH: 197 case AArch64::LDCLRALW: case AArch64::LDCLRALX: 198 case AArch64::LDEORAB: case AArch64::LDEORAH: 199 case AArch64::LDEORAW: case AArch64::LDEORAX: 200 case AArch64::LDEORALB: case AArch64::LDEORALH: 201 case AArch64::LDEORALW: case AArch64::LDEORALX: 202 case AArch64::LDSETAB: case AArch64::LDSETAH: 203 case AArch64::LDSETAW: case AArch64::LDSETAX: 204 case AArch64::LDSETALB: case AArch64::LDSETALH: 205 case AArch64::LDSETALW: case AArch64::LDSETALX: 206 case AArch64::LDSMAXAB: case AArch64::LDSMAXAH: 207 case AArch64::LDSMAXAW: case AArch64::LDSMAXAX: 208 case AArch64::LDSMAXALB: case AArch64::LDSMAXALH: 209 case AArch64::LDSMAXALW: case AArch64::LDSMAXALX: 210 case AArch64::LDSMINAB: case AArch64::LDSMINAH: 211 case AArch64::LDSMINAW: case AArch64::LDSMINAX: 212 case AArch64::LDSMINALB: case AArch64::LDSMINALH: 213 case AArch64::LDSMINALW: case AArch64::LDSMINALX: 214 case AArch64::LDUMAXAB: case AArch64::LDUMAXAH: 215 case AArch64::LDUMAXAW: case AArch64::LDUMAXAX: 216 case AArch64::LDUMAXALB: case AArch64::LDUMAXALH: 217 case AArch64::LDUMAXALW: case AArch64::LDUMAXALX: 218 case AArch64::LDUMINAB: case AArch64::LDUMINAH: 219 case AArch64::LDUMINAW: case AArch64::LDUMINAX: 220 case AArch64::LDUMINALB: case AArch64::LDUMINALH: 221 case AArch64::LDUMINALW: case AArch64::LDUMINALX: 222 case AArch64::SWPAB: case AArch64::SWPAH: 223 case AArch64::SWPAW: case AArch64::SWPAX: 224 case AArch64::SWPALB: case AArch64::SWPALH: 225 case AArch64::SWPALW: case AArch64::SWPALX: 226 return true; 227 } 228 return false; 229 } 230 231 namespace AArch64CC { 232 233 // The CondCodes constants map directly to the 4-bit encoding of the condition 234 // field for predicated instructions. 235 enum CondCode { // Meaning (integer) Meaning (floating-point) 236 EQ = 0x0, // Equal Equal 237 NE = 0x1, // Not equal Not equal, or unordered 238 HS = 0x2, // Unsigned higher or same >, ==, or unordered 239 LO = 0x3, // Unsigned lower Less than 240 MI = 0x4, // Minus, negative Less than 241 PL = 0x5, // Plus, positive or zero >, ==, or unordered 242 VS = 0x6, // Overflow Unordered 243 VC = 0x7, // No overflow Not unordered 244 HI = 0x8, // Unsigned higher Greater than, or unordered 245 LS = 0x9, // Unsigned lower or same Less than or equal 246 GE = 0xa, // Greater than or equal Greater than or equal 247 LT = 0xb, // Less than Less than, or unordered 248 GT = 0xc, // Greater than Greater than 249 LE = 0xd, // Less than or equal <, ==, or unordered 250 AL = 0xe, // Always (unconditional) Always (unconditional) 251 NV = 0xf, // Always (unconditional) Always (unconditional) 252 // Note the NV exists purely to disassemble 0b1111. Execution is "always". 253 Invalid, 254 255 // Common aliases used for SVE. 256 ANY_ACTIVE = NE, // (!Z) 257 FIRST_ACTIVE = MI, // ( N) 258 LAST_ACTIVE = LO, // (!C) 259 NONE_ACTIVE = EQ // ( Z) 260 }; 261 262 inline static const char *getCondCodeName(CondCode Code) { 263 switch (Code) { 264 default: llvm_unreachable("Unknown condition code"); 265 case EQ: return "eq"; 266 case NE: return "ne"; 267 case HS: return "hs"; 268 case LO: return "lo"; 269 case MI: return "mi"; 270 case PL: return "pl"; 271 case VS: return "vs"; 272 case VC: return "vc"; 273 case HI: return "hi"; 274 case LS: return "ls"; 275 case GE: return "ge"; 276 case LT: return "lt"; 277 case GT: return "gt"; 278 case LE: return "le"; 279 case AL: return "al"; 280 case NV: return "nv"; 281 } 282 } 283 284 inline static CondCode getInvertedCondCode(CondCode Code) { 285 // To reverse a condition it's necessary to only invert the low bit: 286 287 return static_cast<CondCode>(static_cast<unsigned>(Code) ^ 0x1); 288 } 289 290 /// Given a condition code, return NZCV flags that would satisfy that condition. 291 /// The flag bits are in the format expected by the ccmp instructions. 292 /// Note that many different flag settings can satisfy a given condition code, 293 /// this function just returns one of them. 294 inline static unsigned getNZCVToSatisfyCondCode(CondCode Code) { 295 // NZCV flags encoded as expected by ccmp instructions, ARMv8 ISA 5.5.7. 296 enum { N = 8, Z = 4, C = 2, V = 1 }; 297 switch (Code) { 298 default: llvm_unreachable("Unknown condition code"); 299 case EQ: return Z; // Z == 1 300 case NE: return 0; // Z == 0 301 case HS: return C; // C == 1 302 case LO: return 0; // C == 0 303 case MI: return N; // N == 1 304 case PL: return 0; // N == 0 305 case VS: return V; // V == 1 306 case VC: return 0; // V == 0 307 case HI: return C; // C == 1 && Z == 0 308 case LS: return 0; // C == 0 || Z == 1 309 case GE: return 0; // N == V 310 case LT: return N; // N != V 311 case GT: return 0; // Z == 0 && N == V 312 case LE: return Z; // Z == 1 || N != V 313 } 314 } 315 } // end namespace AArch64CC 316 317 struct SysAlias { 318 const char *Name; 319 uint16_t Encoding; 320 FeatureBitset FeaturesRequired; 321 322 constexpr SysAlias(const char *N, uint16_t E) : Name(N), Encoding(E) {} 323 constexpr SysAlias(const char *N, uint16_t E, FeatureBitset F) 324 : Name(N), Encoding(E), FeaturesRequired(F) {} 325 326 bool haveFeatures(FeatureBitset ActiveFeatures) const { 327 return (FeaturesRequired & ActiveFeatures) == FeaturesRequired; 328 } 329 330 FeatureBitset getRequiredFeatures() const { return FeaturesRequired; } 331 }; 332 333 struct SysAliasReg : SysAlias { 334 bool NeedsReg; 335 constexpr SysAliasReg(const char *N, uint16_t E, bool R) 336 : SysAlias(N, E), NeedsReg(R) {} 337 constexpr SysAliasReg(const char *N, uint16_t E, bool R, FeatureBitset F) 338 : SysAlias(N, E, F), NeedsReg(R) {} 339 }; 340 341 namespace AArch64AT{ 342 struct AT : SysAlias { 343 using SysAlias::SysAlias; 344 }; 345 #define GET_AT_DECL 346 #include "AArch64GenSystemOperands.inc" 347 } 348 349 namespace AArch64DB { 350 struct DB : SysAlias { 351 using SysAlias::SysAlias; 352 }; 353 #define GET_DB_DECL 354 #include "AArch64GenSystemOperands.inc" 355 } 356 357 namespace AArch64DC { 358 struct DC : SysAlias { 359 using SysAlias::SysAlias; 360 }; 361 #define GET_DC_DECL 362 #include "AArch64GenSystemOperands.inc" 363 } 364 365 namespace AArch64IC { 366 struct IC : SysAliasReg { 367 using SysAliasReg::SysAliasReg; 368 }; 369 #define GET_IC_DECL 370 #include "AArch64GenSystemOperands.inc" 371 } 372 373 namespace AArch64ISB { 374 struct ISB : SysAlias { 375 using SysAlias::SysAlias; 376 }; 377 #define GET_ISB_DECL 378 #include "AArch64GenSystemOperands.inc" 379 } 380 381 namespace AArch64TSB { 382 struct TSB : SysAlias { 383 using SysAlias::SysAlias; 384 }; 385 #define GET_TSB_DECL 386 #include "AArch64GenSystemOperands.inc" 387 } 388 389 namespace AArch64PRFM { 390 struct PRFM : SysAlias { 391 using SysAlias::SysAlias; 392 }; 393 #define GET_PRFM_DECL 394 #include "AArch64GenSystemOperands.inc" 395 } 396 397 namespace AArch64SVEPRFM { 398 struct SVEPRFM : SysAlias { 399 using SysAlias::SysAlias; 400 }; 401 #define GET_SVEPRFM_DECL 402 #include "AArch64GenSystemOperands.inc" 403 } 404 405 namespace AArch64SVEPredPattern { 406 struct SVEPREDPAT { 407 const char *Name; 408 uint16_t Encoding; 409 }; 410 #define GET_SVEPREDPAT_DECL 411 #include "AArch64GenSystemOperands.inc" 412 } 413 414 namespace AArch64ExactFPImm { 415 struct ExactFPImm { 416 const char *Name; 417 int Enum; 418 const char *Repr; 419 }; 420 #define GET_EXACTFPIMM_DECL 421 #include "AArch64GenSystemOperands.inc" 422 } 423 424 namespace AArch64PState { 425 struct PState : SysAlias{ 426 using SysAlias::SysAlias; 427 }; 428 #define GET_PSTATE_DECL 429 #include "AArch64GenSystemOperands.inc" 430 } 431 432 namespace AArch64PSBHint { 433 struct PSB : SysAlias { 434 using SysAlias::SysAlias; 435 }; 436 #define GET_PSB_DECL 437 #include "AArch64GenSystemOperands.inc" 438 } 439 440 namespace AArch64BTIHint { 441 struct BTI : SysAlias { 442 using SysAlias::SysAlias; 443 }; 444 #define GET_BTI_DECL 445 #include "AArch64GenSystemOperands.inc" 446 } 447 448 namespace AArch64SE { 449 enum ShiftExtSpecifiers { 450 Invalid = -1, 451 LSL, 452 MSL, 453 LSR, 454 ASR, 455 ROR, 456 457 UXTB, 458 UXTH, 459 UXTW, 460 UXTX, 461 462 SXTB, 463 SXTH, 464 SXTW, 465 SXTX 466 }; 467 } 468 469 namespace AArch64Layout { 470 enum VectorLayout { 471 Invalid = -1, 472 VL_8B, 473 VL_4H, 474 VL_2S, 475 VL_1D, 476 477 VL_16B, 478 VL_8H, 479 VL_4S, 480 VL_2D, 481 482 // Bare layout for the 128-bit vector 483 // (only show ".b", ".h", ".s", ".d" without vector number) 484 VL_B, 485 VL_H, 486 VL_S, 487 VL_D 488 }; 489 } 490 491 inline static const char * 492 AArch64VectorLayoutToString(AArch64Layout::VectorLayout Layout) { 493 switch (Layout) { 494 case AArch64Layout::VL_8B: return ".8b"; 495 case AArch64Layout::VL_4H: return ".4h"; 496 case AArch64Layout::VL_2S: return ".2s"; 497 case AArch64Layout::VL_1D: return ".1d"; 498 case AArch64Layout::VL_16B: return ".16b"; 499 case AArch64Layout::VL_8H: return ".8h"; 500 case AArch64Layout::VL_4S: return ".4s"; 501 case AArch64Layout::VL_2D: return ".2d"; 502 case AArch64Layout::VL_B: return ".b"; 503 case AArch64Layout::VL_H: return ".h"; 504 case AArch64Layout::VL_S: return ".s"; 505 case AArch64Layout::VL_D: return ".d"; 506 default: llvm_unreachable("Unknown Vector Layout"); 507 } 508 } 509 510 inline static AArch64Layout::VectorLayout 511 AArch64StringToVectorLayout(StringRef LayoutStr) { 512 return StringSwitch<AArch64Layout::VectorLayout>(LayoutStr) 513 .Case(".8b", AArch64Layout::VL_8B) 514 .Case(".4h", AArch64Layout::VL_4H) 515 .Case(".2s", AArch64Layout::VL_2S) 516 .Case(".1d", AArch64Layout::VL_1D) 517 .Case(".16b", AArch64Layout::VL_16B) 518 .Case(".8h", AArch64Layout::VL_8H) 519 .Case(".4s", AArch64Layout::VL_4S) 520 .Case(".2d", AArch64Layout::VL_2D) 521 .Case(".b", AArch64Layout::VL_B) 522 .Case(".h", AArch64Layout::VL_H) 523 .Case(".s", AArch64Layout::VL_S) 524 .Case(".d", AArch64Layout::VL_D) 525 .Default(AArch64Layout::Invalid); 526 } 527 528 namespace AArch64SysReg { 529 struct SysReg { 530 const char *Name; 531 unsigned Encoding; 532 bool Readable; 533 bool Writeable; 534 FeatureBitset FeaturesRequired; 535 536 bool haveFeatures(FeatureBitset ActiveFeatures) const { 537 return (FeaturesRequired & ActiveFeatures) == FeaturesRequired; 538 } 539 }; 540 541 #define GET_SYSREG_DECL 542 #include "AArch64GenSystemOperands.inc" 543 544 const SysReg *lookupSysRegByName(StringRef); 545 const SysReg *lookupSysRegByEncoding(uint16_t); 546 547 uint32_t parseGenericRegister(StringRef Name); 548 std::string genericRegisterString(uint32_t Bits); 549 } 550 551 namespace AArch64TLBI { 552 struct TLBI : SysAliasReg { 553 using SysAliasReg::SysAliasReg; 554 }; 555 #define GET_TLBI_DECL 556 #include "AArch64GenSystemOperands.inc" 557 } 558 559 namespace AArch64PRCTX { 560 struct PRCTX : SysAliasReg { 561 using SysAliasReg::SysAliasReg; 562 }; 563 #define GET_PRCTX_DECL 564 #include "AArch64GenSystemOperands.inc" 565 } 566 567 namespace AArch64II { 568 /// Target Operand Flag enum. 569 enum TOF { 570 //===------------------------------------------------------------------===// 571 // AArch64 Specific MachineOperand flags. 572 573 MO_NO_FLAG, 574 575 MO_FRAGMENT = 0x7, 576 577 /// MO_PAGE - A symbol operand with this flag represents the pc-relative 578 /// offset of the 4K page containing the symbol. This is used with the 579 /// ADRP instruction. 580 MO_PAGE = 1, 581 582 /// MO_PAGEOFF - A symbol operand with this flag represents the offset of 583 /// that symbol within a 4K page. This offset is added to the page address 584 /// to produce the complete address. 585 MO_PAGEOFF = 2, 586 587 /// MO_G3 - A symbol operand with this flag (granule 3) represents the high 588 /// 16-bits of a 64-bit address, used in a MOVZ or MOVK instruction 589 MO_G3 = 3, 590 591 /// MO_G2 - A symbol operand with this flag (granule 2) represents the bits 592 /// 32-47 of a 64-bit address, used in a MOVZ or MOVK instruction 593 MO_G2 = 4, 594 595 /// MO_G1 - A symbol operand with this flag (granule 1) represents the bits 596 /// 16-31 of a 64-bit address, used in a MOVZ or MOVK instruction 597 MO_G1 = 5, 598 599 /// MO_G0 - A symbol operand with this flag (granule 0) represents the bits 600 /// 0-15 of a 64-bit address, used in a MOVZ or MOVK instruction 601 MO_G0 = 6, 602 603 /// MO_HI12 - This flag indicates that a symbol operand represents the bits 604 /// 13-24 of a 64-bit address, used in a arithmetic immediate-shifted-left- 605 /// by-12-bits instruction. 606 MO_HI12 = 7, 607 608 /// MO_COFFSTUB - On a symbol operand "FOO", this indicates that the 609 /// reference is actually to the ".refptrp.FOO" symbol. This is used for 610 /// stub symbols on windows. 611 MO_COFFSTUB = 0x8, 612 613 /// MO_GOT - This flag indicates that a symbol operand represents the 614 /// address of the GOT entry for the symbol, rather than the address of 615 /// the symbol itself. 616 MO_GOT = 0x10, 617 618 /// MO_NC - Indicates whether the linker is expected to check the symbol 619 /// reference for overflow. For example in an ADRP/ADD pair of relocations 620 /// the ADRP usually does check, but not the ADD. 621 MO_NC = 0x20, 622 623 /// MO_TLS - Indicates that the operand being accessed is some kind of 624 /// thread-local symbol. On Darwin, only one type of thread-local access 625 /// exists (pre linker-relaxation), but on ELF the TLSModel used for the 626 /// referee will affect interpretation. 627 MO_TLS = 0x40, 628 629 /// MO_DLLIMPORT - On a symbol operand, this represents that the reference 630 /// to the symbol is for an import stub. This is used for DLL import 631 /// storage class indication on Windows. 632 MO_DLLIMPORT = 0x80, 633 634 /// MO_S - Indicates that the bits of the symbol operand represented by 635 /// MO_G0 etc are signed. 636 MO_S = 0x100, 637 638 /// MO_PREL - Indicates that the bits of the symbol operand represented by 639 /// MO_G0 etc are PC relative. 640 MO_PREL = 0x200, 641 642 /// MO_TAGGED - With MO_PAGE, indicates that the page includes a memory tag 643 /// in bits 56-63. 644 /// On a FrameIndex operand, indicates that the underlying memory is tagged 645 /// with an unknown tag value (MTE); this needs to be lowered either to an 646 /// SP-relative load or store instruction (which do not check tags), or to 647 /// an LDG instruction to obtain the tag value. 648 MO_TAGGED = 0x400, 649 }; 650 } // end namespace AArch64II 651 652 namespace AArch64 { 653 // The number of bits in a SVE register is architecturally defined 654 // to be a multiple of this value. If <M x t> has this number of bits, 655 // a <n x M x t> vector can be stored in a SVE register without any 656 // redundant bits. If <M x t> has this number of bits divided by P, 657 // a <n x M x t> vector is stored in a SVE register by placing index i 658 // in index i*P of a <n x (M*P) x t> vector. The other elements of the 659 // <n x (M*P) x t> vector (such as index 1) are undefined. 660 static constexpr unsigned SVEBitsPerBlock = 128; 661 const unsigned NeonBitsPerVector = 128; 662 } // end namespace AArch64 663 } // end namespace llvm 664 665 #endif 666