1//===-- AMDGPU.td - AMDGPU Tablegen files --------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===------------------------------------------------------------===//
8
9include "llvm/TableGen/SearchableTable.td"
10include "llvm/Target/Target.td"
11include "AMDGPUFeatures.td"
12
13def p0 : PtrValueType<i64, 0>;
14def p1 : PtrValueType<i64, 1>;
15def p2 : PtrValueType<i32, 2>;
16def p3 : PtrValueType<i32, 3>;
17def p4 : PtrValueType<i64, 4>;
18def p5 : PtrValueType<i32, 5>;
19def p6 : PtrValueType<i32, 6>;
20
21
22class BoolToList<bit Value> {
23  list<int> ret = !if(Value, [1]<int>, []<int>);
24}
25
26//===------------------------------------------------------------===//
27// Subtarget Features (device properties)
28//===------------------------------------------------------------===//
29
30def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
31  "FastFMAF32",
32  "true",
33  "Assuming f32 fma is at least as fast as mul + add"
34>;
35
36def FeatureFastDenormalF32 : SubtargetFeature<"fast-denormal-f32",
37  "FastDenormalF32",
38  "true",
39  "Enabling denormals does not cause f32 instructions to run at f64 rates"
40>;
41
42def FeatureMIMG_R128 : SubtargetFeature<"mimg-r128",
43  "MIMG_R128",
44  "true",
45  "Support 128-bit texture resources"
46>;
47
48def HalfRate64Ops : SubtargetFeature<"half-rate-64-ops",
49  "HalfRate64Ops",
50  "true",
51  "Most fp64 instructions are half rate instead of quarter"
52>;
53
54def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
55  "FlatAddressSpace",
56  "true",
57  "Support flat address space"
58>;
59
60def FeatureFlatInstOffsets : SubtargetFeature<"flat-inst-offsets",
61  "FlatInstOffsets",
62  "true",
63  "Flat instructions have immediate offset addressing mode"
64>;
65
66def FeatureFlatGlobalInsts : SubtargetFeature<"flat-global-insts",
67  "FlatGlobalInsts",
68  "true",
69  "Have global_* flat memory instructions"
70>;
71
72def FeatureFlatScratchInsts : SubtargetFeature<"flat-scratch-insts",
73  "FlatScratchInsts",
74  "true",
75  "Have scratch_* flat memory instructions"
76>;
77
78def FeatureScalarFlatScratchInsts : SubtargetFeature<"scalar-flat-scratch-insts",
79  "ScalarFlatScratchInsts",
80  "true",
81  "Have s_scratch_* flat memory instructions"
82>;
83
84def FeatureAddNoCarryInsts : SubtargetFeature<"add-no-carry-insts",
85  "AddNoCarryInsts",
86  "true",
87  "Have VALU add/sub instructions without carry out"
88>;
89
90def FeatureUnalignedBufferAccess : SubtargetFeature<"unaligned-buffer-access",
91  "UnalignedBufferAccess",
92  "true",
93  "Hardware supports unaligned global loads and stores"
94>;
95
96def FeatureTrapHandler: SubtargetFeature<"trap-handler",
97  "TrapHandler",
98  "true",
99  "Trap handler support"
100>;
101
102def FeatureUnalignedScratchAccess : SubtargetFeature<"unaligned-scratch-access",
103  "UnalignedScratchAccess",
104  "true",
105  "Support unaligned scratch loads and stores"
106>;
107
108def FeatureUnalignedDSAccess : SubtargetFeature<"unaligned-ds-access",
109  "UnalignedDSAccess",
110  "true",
111  "Hardware supports unaligned local and region loads and stores"
112>;
113
114def FeatureApertureRegs : SubtargetFeature<"aperture-regs",
115  "HasApertureRegs",
116  "true",
117  "Has Memory Aperture Base and Size Registers"
118>;
119
120def FeatureMadMixInsts : SubtargetFeature<"mad-mix-insts",
121  "HasMadMixInsts",
122  "true",
123  "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions"
124>;
125
126def FeatureFmaMixInsts : SubtargetFeature<"fma-mix-insts",
127  "HasFmaMixInsts",
128  "true",
129  "Has v_fma_mix_f32, v_fma_mixlo_f16, v_fma_mixhi_f16 instructions"
130>;
131
132def FeatureSupportsXNACK : SubtargetFeature<"xnack-support",
133  "SupportsXNACK",
134  "true",
135  "Hardware supports XNACK"
136>;
137
138// XNACK is disabled if SH_MEM_CONFIG.ADDRESS_MODE = GPUVM on chips that support
139// XNACK. The current default kernel driver setting is:
140// - graphics ring: XNACK disabled
141// - compute ring: XNACK enabled
142//
143// If XNACK is enabled, the VMEM latency can be worse.
144// If XNACK is disabled, the 2 SGPRs can be used for general purposes.
145def FeatureXNACK : SubtargetFeature<"xnack",
146  "EnableXNACK",
147  "true",
148  "Enable XNACK support"
149>;
150
151def FeatureCuMode : SubtargetFeature<"cumode",
152  "EnableCuMode",
153  "true",
154  "Enable CU wavefront execution mode"
155>;
156
157def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
158  "SGPRInitBug",
159  "true",
160  "VI SGPR initialization bug requiring a fixed SGPR allocation size"
161>;
162
163def FeatureLdsMisalignedBug : SubtargetFeature<"lds-misaligned-bug",
164  "LDSMisalignedBug",
165  "true",
166  "Some GFX10 bug with multi-dword LDS and flat access that is not naturally aligned in WGP mode"
167>;
168
169def FeatureMFMAInlineLiteralBug : SubtargetFeature<"mfma-inline-literal-bug",
170  "HasMFMAInlineLiteralBug",
171  "true",
172  "MFMA cannot use inline literal as SrcC"
173>;
174
175def FeatureVcmpxPermlaneHazard : SubtargetFeature<"vcmpx-permlane-hazard",
176  "HasVcmpxPermlaneHazard",
177  "true",
178  "TODO: describe me"
179>;
180
181def FeatureVMEMtoScalarWriteHazard : SubtargetFeature<"vmem-to-scalar-write-hazard",
182  "HasVMEMtoScalarWriteHazard",
183  "true",
184  "VMEM instruction followed by scalar writing to EXEC mask, M0 or SGPR leads to incorrect execution."
185>;
186
187def FeatureSMEMtoVectorWriteHazard : SubtargetFeature<"smem-to-vector-write-hazard",
188  "HasSMEMtoVectorWriteHazard",
189  "true",
190  "s_load_dword followed by v_cmp page faults"
191>;
192
193def FeatureInstFwdPrefetchBug : SubtargetFeature<"inst-fwd-prefetch-bug",
194  "HasInstFwdPrefetchBug",
195  "true",
196  "S_INST_PREFETCH instruction causes shader to hang"
197>;
198
199def FeatureVcmpxExecWARHazard : SubtargetFeature<"vcmpx-exec-war-hazard",
200  "HasVcmpxExecWARHazard",
201  "true",
202  "V_CMPX WAR hazard on EXEC (V_CMPX issue ONLY)"
203>;
204
205def FeatureLdsBranchVmemWARHazard : SubtargetFeature<"lds-branch-vmem-war-hazard",
206  "HasLdsBranchVmemWARHazard",
207  "true",
208  "Switching between LDS and VMEM-tex not waiting VM_VSRC=0"
209>;
210
211def FeatureNSAtoVMEMBug : SubtargetFeature<"nsa-to-vmem-bug",
212  "HasNSAtoVMEMBug",
213  "true",
214  "MIMG-NSA followed by VMEM fail if EXEC_LO or EXEC_HI equals zero"
215>;
216
217def FeatureFlatSegmentOffsetBug : SubtargetFeature<"flat-segment-offset-bug",
218  "HasFlatSegmentOffsetBug",
219  "true",
220  "GFX10 bug, inst_offset ignored in flat segment"
221>;
222
223def FeatureOffset3fBug : SubtargetFeature<"offset-3f-bug",
224  "HasOffset3fBug",
225  "true",
226  "Branch offset of 3f hardware bug"
227>;
228
229def FeatureImageStoreD16Bug : SubtargetFeature<"image-store-d16-bug",
230  "HasImageStoreD16Bug",
231  "true",
232  "Image Store D16 hardware bug"
233>;
234
235def FeatureImageGather4D16Bug : SubtargetFeature<"image-gather4-d16-bug",
236  "HasImageGather4D16Bug",
237  "true",
238  "Image Gather4 D16 hardware bug"
239>;
240
241class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
242  "ldsbankcount"#Value,
243  "LDSBankCount",
244  !cast<string>(Value),
245  "The number of LDS banks per compute unit."
246>;
247
248def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;
249def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>;
250
251def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
252  "GCN3Encoding",
253  "true",
254  "Encoding format for VI"
255>;
256
257def FeatureCIInsts : SubtargetFeature<"ci-insts",
258  "CIInsts",
259  "true",
260  "Additional instructions for CI+"
261>;
262
263def FeatureGFX8Insts : SubtargetFeature<"gfx8-insts",
264  "GFX8Insts",
265  "true",
266  "Additional instructions for GFX8+"
267>;
268
269def FeatureGFX9Insts : SubtargetFeature<"gfx9-insts",
270  "GFX9Insts",
271  "true",
272  "Additional instructions for GFX9+"
273>;
274
275def FeatureGFX10Insts : SubtargetFeature<"gfx10-insts",
276  "GFX10Insts",
277  "true",
278  "Additional instructions for GFX10+"
279>;
280
281def FeatureGFX10_3Insts : SubtargetFeature<"gfx10-3-insts",
282  "GFX10_3Insts",
283  "true",
284  "Additional instructions for GFX10.3"
285>;
286
287def FeatureGFX7GFX8GFX9Insts : SubtargetFeature<"gfx7-gfx8-gfx9-insts",
288  "GFX7GFX8GFX9Insts",
289  "true",
290  "Instructions shared in GFX7, GFX8, GFX9"
291>;
292
293def FeatureSMemRealTime : SubtargetFeature<"s-memrealtime",
294  "HasSMemRealTime",
295  "true",
296  "Has s_memrealtime instruction"
297>;
298
299def FeatureInv2PiInlineImm : SubtargetFeature<"inv-2pi-inline-imm",
300  "HasInv2PiInlineImm",
301  "true",
302  "Has 1 / (2 * pi) as inline immediate"
303>;
304
305def Feature16BitInsts : SubtargetFeature<"16-bit-insts",
306  "Has16BitInsts",
307  "true",
308  "Has i16/f16 instructions"
309>;
310
311def FeatureVOP3P : SubtargetFeature<"vop3p",
312  "HasVOP3PInsts",
313  "true",
314  "Has VOP3P packed instructions"
315>;
316
317def FeatureMovrel : SubtargetFeature<"movrel",
318  "HasMovrel",
319  "true",
320  "Has v_movrel*_b32 instructions"
321>;
322
323def FeatureVGPRIndexMode : SubtargetFeature<"vgpr-index-mode",
324  "HasVGPRIndexMode",
325  "true",
326  "Has VGPR mode register indexing"
327>;
328
329def FeatureScalarStores : SubtargetFeature<"scalar-stores",
330  "HasScalarStores",
331  "true",
332  "Has store scalar memory instructions"
333>;
334
335def FeatureScalarAtomics : SubtargetFeature<"scalar-atomics",
336  "HasScalarAtomics",
337  "true",
338  "Has atomic scalar memory instructions"
339>;
340
341def FeatureSDWA : SubtargetFeature<"sdwa",
342  "HasSDWA",
343  "true",
344  "Support SDWA (Sub-DWORD Addressing) extension"
345>;
346
347def FeatureSDWAOmod : SubtargetFeature<"sdwa-omod",
348  "HasSDWAOmod",
349  "true",
350  "Support OMod with SDWA (Sub-DWORD Addressing) extension"
351>;
352
353def FeatureSDWAScalar : SubtargetFeature<"sdwa-scalar",
354  "HasSDWAScalar",
355  "true",
356  "Support scalar register with SDWA (Sub-DWORD Addressing) extension"
357>;
358
359def FeatureSDWASdst : SubtargetFeature<"sdwa-sdst",
360  "HasSDWASdst",
361  "true",
362  "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension"
363>;
364
365def FeatureSDWAMac : SubtargetFeature<"sdwa-mav",
366  "HasSDWAMac",
367  "true",
368  "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension"
369>;
370
371def FeatureSDWAOutModsVOPC : SubtargetFeature<"sdwa-out-mods-vopc",
372  "HasSDWAOutModsVOPC",
373  "true",
374  "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension"
375>;
376
377def FeatureDPP : SubtargetFeature<"dpp",
378  "HasDPP",
379  "true",
380  "Support DPP (Data Parallel Primitives) extension"
381>;
382
383// DPP8 allows arbitrary cross-lane swizzling withing groups of 8 lanes.
384def FeatureDPP8 : SubtargetFeature<"dpp8",
385  "HasDPP8",
386  "true",
387  "Support DPP8 (Data Parallel Primitives) extension"
388>;
389
390def FeatureR128A16 : SubtargetFeature<"r128-a16",
391  "HasR128A16",
392  "true",
393  "Support gfx9-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands, where a16 is aliased with r128"
394>;
395
396def FeatureGFX10A16 : SubtargetFeature<"a16",
397  "HasGFX10A16",
398  "true",
399  "Support gfx10-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands"
400>;
401
402def FeatureG16 : SubtargetFeature<"g16",
403  "HasG16",
404  "true",
405  "Support G16 for 16-bit gradient image operands"
406>;
407
408def FeatureNSAEncoding : SubtargetFeature<"nsa-encoding",
409  "HasNSAEncoding",
410  "true",
411  "Support NSA encoding for image instructions"
412>;
413
414def FeatureGFX10_BEncoding : SubtargetFeature<"gfx10_b-encoding",
415  "GFX10_BEncoding",
416  "true",
417  "Encoding format GFX10_B"
418>;
419
420def FeatureIntClamp : SubtargetFeature<"int-clamp-insts",
421  "HasIntClamp",
422  "true",
423  "Support clamp for integer destination"
424>;
425
426def FeatureUnpackedD16VMem : SubtargetFeature<"unpacked-d16-vmem",
427  "HasUnpackedD16VMem",
428  "true",
429  "Has unpacked d16 vmem instructions"
430>;
431
432def FeatureDLInsts : SubtargetFeature<"dl-insts",
433  "HasDLInsts",
434  "true",
435  "Has v_fmac_f32 and v_xnor_b32 instructions"
436>;
437
438def FeatureDot1Insts : SubtargetFeature<"dot1-insts",
439  "HasDot1Insts",
440  "true",
441  "Has v_dot4_i32_i8 and v_dot8_i32_i4 instructions"
442>;
443
444def FeatureDot2Insts : SubtargetFeature<"dot2-insts",
445  "HasDot2Insts",
446  "true",
447  "Has v_dot2_f32_f16, v_dot2_i32_i16, v_dot2_u32_u16, v_dot4_u32_u8, v_dot8_u32_u4 instructions"
448>;
449
450def FeatureDot3Insts : SubtargetFeature<"dot3-insts",
451  "HasDot3Insts",
452  "true",
453  "Has v_dot8c_i32_i4 instruction"
454>;
455
456def FeatureDot4Insts : SubtargetFeature<"dot4-insts",
457  "HasDot4Insts",
458  "true",
459  "Has v_dot2c_i32_i16 instruction"
460>;
461
462def FeatureDot5Insts : SubtargetFeature<"dot5-insts",
463  "HasDot5Insts",
464  "true",
465  "Has v_dot2c_f32_f16 instruction"
466>;
467
468def FeatureDot6Insts : SubtargetFeature<"dot6-insts",
469  "HasDot6Insts",
470  "true",
471  "Has v_dot4c_i32_i8 instruction"
472>;
473
474def FeatureMAIInsts : SubtargetFeature<"mai-insts",
475  "HasMAIInsts",
476  "true",
477  "Has mAI instructions"
478>;
479
480def FeaturePkFmacF16Inst : SubtargetFeature<"pk-fmac-f16-inst",
481  "HasPkFmacF16Inst",
482  "true",
483  "Has v_pk_fmac_f16 instruction"
484>;
485
486def FeatureAtomicFaddInsts : SubtargetFeature<"atomic-fadd-insts",
487  "HasAtomicFaddInsts",
488  "true",
489  "Has buffer_atomic_add_f32, buffer_atomic_pk_add_f16, global_atomic_add_f32, "
490  "global_atomic_pk_add_f16 instructions",
491  [FeatureFlatGlobalInsts]
492>;
493
494def FeatureSupportsSRAMECC : SubtargetFeature<"sramecc-support",
495  "SupportsSRAMECC",
496  "true",
497  "Hardware supports SRAMECC"
498>;
499
500def FeatureSRAMECC : SubtargetFeature<"sramecc",
501  "EnableSRAMECC",
502  "true",
503  "Enable SRAMECC"
504>;
505
506def FeatureNoSdstCMPX : SubtargetFeature<"no-sdst-cmpx",
507  "HasNoSdstCMPX",
508  "true",
509  "V_CMPX does not write VCC/SGPR in addition to EXEC"
510>;
511
512def FeatureVscnt : SubtargetFeature<"vscnt",
513  "HasVscnt",
514  "true",
515  "Has separate store vscnt counter"
516>;
517
518def FeatureGetWaveIdInst : SubtargetFeature<"get-wave-id-inst",
519  "HasGetWaveIdInst",
520  "true",
521  "Has s_get_waveid_in_workgroup instruction"
522>;
523
524def FeatureSMemTimeInst : SubtargetFeature<"s-memtime-inst",
525  "HasSMemTimeInst",
526  "true",
527  "Has s_memtime instruction"
528>;
529
530def FeatureMadMacF32Insts : SubtargetFeature<"mad-mac-f32-insts",
531  "HasMadMacF32Insts",
532  "true",
533  "Has v_mad_f32/v_mac_f32/v_madak_f32/v_madmk_f32 instructions"
534>;
535
536def FeatureDsSrc2Insts : SubtargetFeature<"ds-src2-insts",
537  "HasDsSrc2Insts",
538  "true",
539  "Has ds_*_src2 instructions"
540>;
541
542def FeatureRegisterBanking : SubtargetFeature<"register-banking",
543  "HasRegisterBanking",
544  "true",
545  "Has register banking"
546>;
547
548def FeatureVOP3Literal : SubtargetFeature<"vop3-literal",
549  "HasVOP3Literal",
550  "true",
551  "Can use one literal in VOP3"
552>;
553
554def FeatureNoDataDepHazard : SubtargetFeature<"no-data-dep-hazard",
555  "HasNoDataDepHazard",
556  "true",
557  "Does not need SW waitstates"
558>;
559
560//===------------------------------------------------------------===//
561// Subtarget Features (options and debugging)
562//===------------------------------------------------------------===//
563
564class FeatureMaxPrivateElementSize<int size> : SubtargetFeature<
565  "max-private-element-size-"#size,
566  "MaxPrivateElementSize",
567  !cast<string>(size),
568  "Maximum private access size may be "#size
569>;
570
571def FeatureMaxPrivateElementSize4 : FeatureMaxPrivateElementSize<4>;
572def FeatureMaxPrivateElementSize8 : FeatureMaxPrivateElementSize<8>;
573def FeatureMaxPrivateElementSize16 : FeatureMaxPrivateElementSize<16>;
574
575def FeatureDumpCode : SubtargetFeature <"DumpCode",
576  "DumpCode",
577  "true",
578  "Dump MachineInstrs in the CodeEmitter"
579>;
580
581def FeatureDumpCodeLower : SubtargetFeature <"dumpcode",
582  "DumpCode",
583  "true",
584  "Dump MachineInstrs in the CodeEmitter"
585>;
586
587// XXX - This should probably be removed once enabled by default
588def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
589  "EnableLoadStoreOpt",
590  "true",
591  "Enable SI load/store optimizer pass"
592>;
593
594// Performance debugging feature. Allow using DS instruction immediate
595// offsets even if the base pointer can't be proven to be base. On SI,
596// base pointer values that won't give the same result as a 16-bit add
597// are not safe to fold, but this will override the conservative test
598// for the base pointer.
599def FeatureEnableUnsafeDSOffsetFolding : SubtargetFeature <
600  "unsafe-ds-offset-folding",
601  "EnableUnsafeDSOffsetFolding",
602  "true",
603  "Force using DS instruction immediate offsets on SI"
604>;
605
606def FeatureEnableSIScheduler : SubtargetFeature<"si-scheduler",
607  "EnableSIScheduler",
608  "true",
609  "Enable SI Machine Scheduler"
610>;
611
612def FeatureEnableDS128 : SubtargetFeature<"enable-ds128",
613  "EnableDS128",
614  "true",
615  "Use ds_{read|write}_b128"
616>;
617
618// Sparse texture support requires that all result registers are zeroed when
619// PRTStrictNull is set to true. This feature is turned on for all architectures
620// but is enabled as a feature in case there are situations where PRTStrictNull
621// is disabled by the driver.
622def FeatureEnablePRTStrictNull : SubtargetFeature<"enable-prt-strict-null",
623  "EnablePRTStrictNull",
624  "true",
625  "Enable zeroing of result registers for sparse texture fetches"
626>;
627
628// Unless +-flat-for-global is specified, turn on FlatForGlobal for
629// all OS-es on VI and newer hardware to avoid assertion failures due
630// to missing ADDR64 variants of MUBUF instructions.
631// FIXME: moveToVALU should be able to handle converting addr64 MUBUF
632// instructions.
633
634def FeatureFlatForGlobal : SubtargetFeature<"flat-for-global",
635  "FlatForGlobal",
636  "true",
637  "Force to generate flat instruction for global"
638>;
639
640def FeatureAutoWaitcntBeforeBarrier : SubtargetFeature <
641  "auto-waitcnt-before-barrier",
642  "AutoWaitcntBeforeBarrier",
643  "true",
644  "Hardware automatically inserts waitcnt before barrier"
645>;
646
647def FeatureTrigReducedRange : SubtargetFeature<"trig-reduced-range",
648  "HasTrigReducedRange",
649  "true",
650  "Requires use of fract on arguments to trig instructions"
651>;
652
653// Alignment enforcement is controlled by a configuration register:
654// SH_MEM_CONFIG.alignment_mode
655def FeatureUnalignedAccessMode : SubtargetFeature<"unaligned-access-mode",
656  "UnalignedAccessMode",
657  "true",
658  "Enable unaligned global, local and region loads and stores if the hardware"
659  " supports it"
660>;
661
662// Dummy feature used to disable assembler instructions.
663def FeatureDisable : SubtargetFeature<"",
664  "FeatureDisable","true",
665  "Dummy feature to disable assembler instructions"
666>;
667
668class GCNSubtargetFeatureGeneration <string Value,
669                                     string FeatureName,
670                                     list<SubtargetFeature> Implies> :
671        SubtargetFeatureGeneration <Value, FeatureName, "GCNSubtarget", Implies>;
672
673def FeatureSouthernIslands : GCNSubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
674    "southern-islands",
675  [FeatureFP64, FeatureLocalMemorySize32768, FeatureMIMG_R128,
676  FeatureWavefrontSize64, FeatureSMemTimeInst, FeatureMadMacF32Insts,
677  FeatureDsSrc2Insts, FeatureLDSBankCount32, FeatureMovrel,
678  FeatureTrigReducedRange]
679>;
680
681def FeatureSeaIslands : GCNSubtargetFeatureGeneration<"SEA_ISLANDS",
682    "sea-islands",
683  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
684  FeatureWavefrontSize64, FeatureFlatAddressSpace,
685  FeatureCIInsts, FeatureMovrel, FeatureTrigReducedRange,
686  FeatureGFX7GFX8GFX9Insts, FeatureSMemTimeInst, FeatureMadMacF32Insts,
687  FeatureDsSrc2Insts, FeatureUnalignedBufferAccess]
688>;
689
690def FeatureVolcanicIslands : GCNSubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
691  "volcanic-islands",
692  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
693   FeatureWavefrontSize64, FeatureFlatAddressSpace,
694   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
695   FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel,
696   FeatureScalarStores, FeatureInv2PiInlineImm,
697   FeatureSDWA, FeatureSDWAOutModsVOPC, FeatureSDWAMac, FeatureDPP,
698   FeatureIntClamp, FeatureTrigReducedRange, FeatureGFX8Insts,
699   FeatureGFX7GFX8GFX9Insts, FeatureSMemTimeInst, FeatureMadMacF32Insts,
700   FeatureDsSrc2Insts, FeatureFastDenormalF32, FeatureUnalignedBufferAccess]
701>;
702
703def FeatureGFX9 : GCNSubtargetFeatureGeneration<"GFX9",
704  "gfx9",
705  [FeatureFP64, FeatureLocalMemorySize65536,
706   FeatureWavefrontSize64, FeatureFlatAddressSpace,
707   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
708   FeatureSMemRealTime, FeatureScalarStores, FeatureInv2PiInlineImm,
709   FeatureApertureRegs, FeatureGFX9Insts, FeatureVOP3P, FeatureVGPRIndexMode,
710   FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
711   FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
712   FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
713   FeatureAddNoCarryInsts, FeatureGFX8Insts, FeatureGFX7GFX8GFX9Insts,
714   FeatureScalarFlatScratchInsts, FeatureScalarAtomics, FeatureR128A16,
715   FeatureSMemTimeInst, FeatureMadMacF32Insts, FeatureDsSrc2Insts,
716   FeatureFastDenormalF32, FeatureUnalignedBufferAccess, FeatureUnalignedDSAccess,
717   FeatureSupportsXNACK]
718>;
719
720def FeatureGFX10 : GCNSubtargetFeatureGeneration<"GFX10",
721  "gfx10",
722  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
723   FeatureFlatAddressSpace,
724   FeatureCIInsts, Feature16BitInsts,
725   FeatureSMemRealTime, FeatureInv2PiInlineImm,
726   FeatureApertureRegs, FeatureGFX9Insts, FeatureGFX10Insts, FeatureVOP3P,
727   FeatureMovrel, FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
728   FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
729   FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
730   FeatureAddNoCarryInsts, FeatureFmaMixInsts, FeatureGFX8Insts,
731   FeatureNoSdstCMPX, FeatureVscnt, FeatureRegisterBanking,
732   FeatureVOP3Literal, FeatureDPP8,
733   FeatureNoDataDepHazard, FeaturePkFmacF16Inst,
734   FeatureGFX10A16, FeatureFastDenormalF32, FeatureG16,
735   FeatureUnalignedBufferAccess, FeatureUnalignedDSAccess
736  ]
737>;
738
739class FeatureSet<list<SubtargetFeature> Features_> {
740  list<SubtargetFeature> Features = Features_;
741}
742
743def FeatureISAVersion6_0_0 : FeatureSet<[FeatureSouthernIslands,
744   FeatureFastFMAF32,
745   HalfRate64Ops,
746   FeatureLDSBankCount32]>;
747
748def FeatureISAVersion6_0_1 : FeatureSet<
749  [FeatureSouthernIslands,
750   FeatureLDSBankCount32]>;
751
752def FeatureISAVersion6_0_2 : FeatureSet<
753  [FeatureSouthernIslands,
754   FeatureLDSBankCount32]>;
755
756def FeatureISAVersion7_0_0 : FeatureSet<
757  [FeatureSeaIslands,
758   FeatureLDSBankCount32]>;
759
760def FeatureISAVersion7_0_1 : FeatureSet<
761  [FeatureSeaIslands,
762   HalfRate64Ops,
763   FeatureLDSBankCount32,
764   FeatureFastFMAF32]>;
765
766def FeatureISAVersion7_0_2 : FeatureSet<
767  [FeatureSeaIslands,
768   FeatureLDSBankCount16,
769   FeatureFastFMAF32]>;
770
771def FeatureISAVersion7_0_3 : FeatureSet<
772  [FeatureSeaIslands,
773   FeatureLDSBankCount16]>;
774
775def FeatureISAVersion7_0_4 : FeatureSet<
776  [FeatureSeaIslands,
777   FeatureLDSBankCount32]>;
778
779def FeatureISAVersion7_0_5 : FeatureSet<
780  [FeatureSeaIslands,
781   FeatureLDSBankCount16]>;
782
783def FeatureISAVersion8_0_1 : FeatureSet<
784  [FeatureVolcanicIslands,
785   FeatureFastFMAF32,
786   HalfRate64Ops,
787   FeatureLDSBankCount32,
788   FeatureSupportsXNACK,
789   FeatureUnpackedD16VMem]>;
790
791def FeatureISAVersion8_0_2 : FeatureSet<
792  [FeatureVolcanicIslands,
793   FeatureLDSBankCount32,
794   FeatureSGPRInitBug,
795   FeatureUnpackedD16VMem]>;
796
797def FeatureISAVersion8_0_3 : FeatureSet<
798  [FeatureVolcanicIslands,
799   FeatureLDSBankCount32,
800   FeatureUnpackedD16VMem]>;
801
802def FeatureISAVersion8_0_5 : FeatureSet<
803  [FeatureVolcanicIslands,
804   FeatureLDSBankCount32,
805   FeatureSGPRInitBug,
806   FeatureUnpackedD16VMem]>;
807
808def FeatureISAVersion8_1_0 : FeatureSet<
809  [FeatureVolcanicIslands,
810   FeatureLDSBankCount16,
811   FeatureSupportsXNACK,
812   FeatureImageStoreD16Bug,
813   FeatureImageGather4D16Bug]>;
814
815def FeatureISAVersion9_0_0 : FeatureSet<
816  [FeatureGFX9,
817   FeatureMadMixInsts,
818   FeatureLDSBankCount32,
819   FeatureImageGather4D16Bug]>;
820
821def FeatureISAVersion9_0_2 : FeatureSet<
822  [FeatureGFX9,
823   FeatureMadMixInsts,
824   FeatureLDSBankCount32,
825   FeatureImageGather4D16Bug]>;
826
827def FeatureISAVersion9_0_4 : FeatureSet<
828  [FeatureGFX9,
829   FeatureLDSBankCount32,
830   FeatureFmaMixInsts,
831   FeatureImageGather4D16Bug]>;
832
833def FeatureISAVersion9_0_6 : FeatureSet<
834  [FeatureGFX9,
835   HalfRate64Ops,
836   FeatureFmaMixInsts,
837   FeatureLDSBankCount32,
838   FeatureDLInsts,
839   FeatureDot1Insts,
840   FeatureDot2Insts,
841   FeatureSupportsSRAMECC,
842   FeatureImageGather4D16Bug]>;
843
844def FeatureISAVersion9_0_8 : FeatureSet<
845  [FeatureGFX9,
846   HalfRate64Ops,
847   FeatureFmaMixInsts,
848   FeatureLDSBankCount32,
849   FeatureDLInsts,
850   FeatureDot1Insts,
851   FeatureDot2Insts,
852   FeatureDot3Insts,
853   FeatureDot4Insts,
854   FeatureDot5Insts,
855   FeatureDot6Insts,
856   FeatureMAIInsts,
857   FeaturePkFmacF16Inst,
858   FeatureAtomicFaddInsts,
859   FeatureSupportsSRAMECC,
860   FeatureMFMAInlineLiteralBug,
861   FeatureImageGather4D16Bug]>;
862
863def FeatureISAVersion9_0_9 : FeatureSet<
864  [FeatureGFX9,
865   FeatureMadMixInsts,
866   FeatureLDSBankCount32,
867   FeatureImageGather4D16Bug]>;
868
869def FeatureISAVersion9_0_C : FeatureSet<
870  [FeatureGFX9,
871   FeatureMadMixInsts,
872   FeatureLDSBankCount32,
873   FeatureXNACK,
874   FeatureImageGather4D16Bug]>;
875
876// TODO: Organize more features into groups.
877def FeatureGroup {
878  // Bugs present on gfx10.1.
879  list<SubtargetFeature> GFX10_1_Bugs = [
880    FeatureVcmpxPermlaneHazard,
881    FeatureVMEMtoScalarWriteHazard,
882    FeatureSMEMtoVectorWriteHazard,
883    FeatureInstFwdPrefetchBug,
884    FeatureVcmpxExecWARHazard,
885    FeatureLdsBranchVmemWARHazard,
886    FeatureNSAtoVMEMBug,
887    FeatureOffset3fBug,
888    FeatureFlatSegmentOffsetBug
889   ];
890}
891
892def FeatureISAVersion10_1_0 : FeatureSet<
893  !listconcat(FeatureGroup.GFX10_1_Bugs,
894    [FeatureGFX10,
895     FeatureLDSBankCount32,
896     FeatureDLInsts,
897     FeatureNSAEncoding,
898     FeatureWavefrontSize32,
899     FeatureScalarStores,
900     FeatureScalarAtomics,
901     FeatureScalarFlatScratchInsts,
902     FeatureGetWaveIdInst,
903     FeatureSMemTimeInst,
904     FeatureMadMacF32Insts,
905     FeatureDsSrc2Insts,
906     FeatureLdsMisalignedBug,
907     FeatureSupportsXNACK])>;
908
909def FeatureISAVersion10_1_1 : FeatureSet<
910  !listconcat(FeatureGroup.GFX10_1_Bugs,
911    [FeatureGFX10,
912     FeatureLDSBankCount32,
913     FeatureDLInsts,
914     FeatureDot1Insts,
915     FeatureDot2Insts,
916     FeatureDot5Insts,
917     FeatureDot6Insts,
918     FeatureNSAEncoding,
919     FeatureWavefrontSize32,
920     FeatureScalarStores,
921     FeatureScalarAtomics,
922     FeatureScalarFlatScratchInsts,
923     FeatureGetWaveIdInst,
924     FeatureSMemTimeInst,
925     FeatureMadMacF32Insts,
926     FeatureDsSrc2Insts,
927     FeatureLdsMisalignedBug,
928     FeatureSupportsXNACK])>;
929
930def FeatureISAVersion10_1_2 : FeatureSet<
931  !listconcat(FeatureGroup.GFX10_1_Bugs,
932    [FeatureGFX10,
933     FeatureLDSBankCount32,
934     FeatureDLInsts,
935     FeatureDot1Insts,
936     FeatureDot2Insts,
937     FeatureDot5Insts,
938     FeatureDot6Insts,
939     FeatureNSAEncoding,
940     FeatureWavefrontSize32,
941     FeatureScalarStores,
942     FeatureScalarAtomics,
943     FeatureScalarFlatScratchInsts,
944     FeatureGetWaveIdInst,
945     FeatureSMemTimeInst,
946     FeatureMadMacF32Insts,
947     FeatureDsSrc2Insts,
948     FeatureLdsMisalignedBug,
949     FeatureSupportsXNACK])>;
950
951def FeatureISAVersion10_3_0 : FeatureSet<
952  [FeatureGFX10,
953   FeatureGFX10_BEncoding,
954   FeatureGFX10_3Insts,
955   FeatureLDSBankCount32,
956   FeatureDLInsts,
957   FeatureDot1Insts,
958   FeatureDot2Insts,
959   FeatureDot5Insts,
960   FeatureDot6Insts,
961   FeatureNSAEncoding,
962   FeatureWavefrontSize32]>;
963
964//===----------------------------------------------------------------------===//
965
966def AMDGPUInstrInfo : InstrInfo {
967  let guessInstructionProperties = 1;
968  let noNamedPositionallyEncodedOperands = 1;
969}
970
971def AMDGPUAsmParser : AsmParser {
972  // Some of the R600 registers have the same name, so this crashes.
973  // For example T0_XYZW and T0_XY both have the asm name T0.
974  let ShouldEmitMatchRegisterName = 0;
975}
976
977def AMDGPUAsmWriter : AsmWriter {
978  int PassSubtarget = 1;
979}
980
981def AMDGPUAsmVariants {
982  string Default = "Default";
983  int Default_ID = 0;
984  string VOP3 = "VOP3";
985  int VOP3_ID = 1;
986  string SDWA = "SDWA";
987  int SDWA_ID = 2;
988  string SDWA9 = "SDWA9";
989  int SDWA9_ID = 3;
990  string DPP = "DPP";
991  int DPP_ID = 4;
992  string Disable = "Disable";
993  int Disable_ID = 5;
994}
995
996def DefaultAMDGPUAsmParserVariant : AsmParserVariant {
997  let Variant = AMDGPUAsmVariants.Default_ID;
998  let Name = AMDGPUAsmVariants.Default;
999}
1000
1001def VOP3AsmParserVariant : AsmParserVariant {
1002  let Variant = AMDGPUAsmVariants.VOP3_ID;
1003  let Name = AMDGPUAsmVariants.VOP3;
1004}
1005
1006def SDWAAsmParserVariant : AsmParserVariant {
1007  let Variant = AMDGPUAsmVariants.SDWA_ID;
1008  let Name = AMDGPUAsmVariants.SDWA;
1009}
1010
1011def SDWA9AsmParserVariant : AsmParserVariant {
1012  let Variant = AMDGPUAsmVariants.SDWA9_ID;
1013  let Name = AMDGPUAsmVariants.SDWA9;
1014}
1015
1016
1017def DPPAsmParserVariant : AsmParserVariant {
1018  let Variant = AMDGPUAsmVariants.DPP_ID;
1019  let Name = AMDGPUAsmVariants.DPP;
1020}
1021
1022def AMDGPU : Target {
1023  // Pull in Instruction Info:
1024  let InstructionSet = AMDGPUInstrInfo;
1025  let AssemblyParsers = [AMDGPUAsmParser];
1026  let AssemblyParserVariants = [DefaultAMDGPUAsmParserVariant,
1027                                VOP3AsmParserVariant,
1028                                SDWAAsmParserVariant,
1029                                SDWA9AsmParserVariant,
1030                                DPPAsmParserVariant];
1031  let AssemblyWriters = [AMDGPUAsmWriter];
1032  let AllowRegisterRenaming = 1;
1033}
1034
1035// Dummy Instruction itineraries for pseudo instructions
1036def ALU_NULL : FuncUnit;
1037def NullALU : InstrItinClass;
1038
1039//===----------------------------------------------------------------------===//
1040// Predicate helper class
1041//===----------------------------------------------------------------------===//
1042
1043def isGFX6 :
1044  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS">,
1045  AssemblerPredicate<(all_of FeatureSouthernIslands)>;
1046
1047def isGFX6GFX7 :
1048  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1049            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">,
1050  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), (not FeatureGFX10Insts))>;
1051
1052def isGFX6GFX7GFX10 :
1053  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1054            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1055            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
1056  AssemblerPredicate<(all_of (not FeatureGCN3Encoding))>;
1057
1058def isGFX7Only :
1059  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">,
1060  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureCIInsts, (not FeatureGFX10Insts))>;
1061
1062def isGFX7GFX10 :
1063  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1064            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
1065  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureCIInsts)>;
1066
1067def isGFX7GFX8GFX9 :
1068  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1069            "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1070            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1071  AssemblerPredicate<(all_of FeatureGFX7GFX8GFX9Insts)>;
1072
1073def isGFX6GFX7GFX8GFX9 :
1074  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1075            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1076            "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1077            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1078  AssemblerPredicate<(all_of (not FeatureGFX10Insts))>;
1079
1080def isGFX7Plus :
1081  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS">,
1082  AssemblerPredicate<(all_of FeatureCIInsts)>;
1083
1084def isGFX8Plus :
1085  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
1086  AssemblerPredicate<(all_of FeatureGFX8Insts)>;
1087
1088def isGFX8Only : Predicate<"Subtarget->getGeneration() =="
1089                           "AMDGPUSubtarget::VOLCANIC_ISLANDS">,
1090  AssemblerPredicate <(all_of FeatureVolcanicIslands)>;
1091
1092def isGFX9Plus :
1093  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
1094  AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1095
1096def isGFX9Only : Predicate <
1097  "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1098  AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureGFX9Insts)>;
1099
1100def isGFX8GFX9 :
1101  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1102            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1103  AssemblerPredicate<(all_of FeatureGFX8Insts, FeatureGCN3Encoding)>;
1104
1105def isGFX10Plus :
1106  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10">,
1107  AssemblerPredicate<(all_of FeatureGFX10Insts)>;
1108
1109def isGFX10Before1030 :
1110  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::GFX10 &&"
1111            "!Subtarget->hasGFX10_3Insts()">,
1112  AssemblerPredicate<(all_of FeatureGFX10Insts,(not FeatureGFX10_3Insts))>;
1113
1114def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">,
1115  AssemblerPredicate<(all_of FeatureFlatAddressSpace)>;
1116
1117def HasFlatGlobalInsts : Predicate<"Subtarget->hasFlatGlobalInsts()">,
1118  AssemblerPredicate<(all_of FeatureFlatGlobalInsts)>;
1119def HasFlatScratchInsts : Predicate<"Subtarget->hasFlatScratchInsts()">,
1120  AssemblerPredicate<(all_of FeatureFlatScratchInsts)>;
1121def HasScalarFlatScratchInsts : Predicate<"Subtarget->hasScalarFlatScratchInsts()">,
1122  AssemblerPredicate<(all_of FeatureScalarFlatScratchInsts)>;
1123def HasD16LoadStore : Predicate<"Subtarget->hasD16LoadStore()">,
1124  AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1125
1126def HasFlatScratchSTMode : Predicate<"Subtarget->hasFlatScratchSTMode()">,
1127  AssemblerPredicate<(any_of FeatureGFX10_3Insts)>;
1128
1129def HasGFX10_BEncoding : Predicate<"Subtarget->hasGFX10_BEncoding()">,
1130  AssemblerPredicate<(all_of FeatureGFX10_BEncoding)>;
1131
1132def HasUnpackedD16VMem : Predicate<"Subtarget->hasUnpackedD16VMem()">,
1133  AssemblerPredicate<(all_of FeatureUnpackedD16VMem)>;
1134def HasPackedD16VMem : Predicate<"!Subtarget->hasUnpackedD16VMem()">,
1135  AssemblerPredicate<(all_of (not FeatureUnpackedD16VMem))>;
1136
1137def D16PreservesUnusedBits :
1138  Predicate<"Subtarget->d16PreservesUnusedBits()">,
1139  AssemblerPredicate<(all_of FeatureGFX9Insts, (not FeatureSRAMECC))>;
1140
1141def LDSRequiresM0Init : Predicate<"Subtarget->ldsRequiresM0Init()">;
1142def NotLDSRequiresM0Init : Predicate<"!Subtarget->ldsRequiresM0Init()">;
1143
1144def HasDSAddTid : Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
1145  AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1146
1147def HasLDSFPAtomics : Predicate<"Subtarget->hasLDSFPAtomics()">,
1148  AssemblerPredicate<(all_of FeatureGFX8Insts)>;
1149
1150def HasAddNoCarryInsts : Predicate<"Subtarget->hasAddNoCarry()">,
1151  AssemblerPredicate<(all_of FeatureAddNoCarryInsts)>;
1152
1153def NotHasAddNoCarryInsts : Predicate<"!Subtarget->hasAddNoCarry()">;
1154
1155def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">,
1156  AssemblerPredicate<(all_of Feature16BitInsts)>;
1157def HasVOP3PInsts : Predicate<"Subtarget->hasVOP3PInsts()">,
1158  AssemblerPredicate<(all_of FeatureVOP3P)>;
1159
1160def HasMinMaxDenormModes : Predicate<"Subtarget->supportsMinMaxDenormModes()">;
1161def NotHasMinMaxDenormModes : Predicate<"!Subtarget->supportsMinMaxDenormModes()">;
1162
1163def HasSDWA : Predicate<"Subtarget->hasSDWA()">,
1164  AssemblerPredicate<(all_of FeatureSDWA, FeatureVolcanicIslands)>;
1165
1166def HasSDWA9 :
1167  Predicate<"Subtarget->hasSDWA()">,
1168  AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureGFX9Insts,FeatureSDWA)>;
1169
1170def HasSDWA10 :
1171  Predicate<"Subtarget->hasSDWA()">,
1172  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureSDWA)>;
1173
1174def HasDPP : Predicate<"Subtarget->hasDPP()">,
1175  AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureDPP)>;
1176
1177def HasDPP8 : Predicate<"Subtarget->hasDPP8()">,
1178  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureDPP8)>;
1179
1180def HasR128A16 : Predicate<"Subtarget->hasR128A16()">,
1181  AssemblerPredicate<(all_of FeatureR128A16)>;
1182
1183def HasGFX10A16 : Predicate<"Subtarget->hasGFX10A16()">,
1184  AssemblerPredicate<(all_of FeatureGFX10A16)>;
1185
1186def HasG16 : Predicate<"Subtarget->hasG16()">,
1187  AssemblerPredicate<(all_of FeatureG16)>;
1188
1189def HasDPP16 : Predicate<"Subtarget->hasDPP()">,
1190  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureDPP)>;
1191
1192def HasIntClamp : Predicate<"Subtarget->hasIntClamp()">,
1193  AssemblerPredicate<(all_of FeatureIntClamp)>;
1194
1195def HasMadMixInsts : Predicate<"Subtarget->hasMadMixInsts()">,
1196  AssemblerPredicate<(all_of FeatureMadMixInsts)>;
1197
1198def HasScalarStores : Predicate<"Subtarget->hasScalarStores()">,
1199  AssemblerPredicate<(all_of FeatureScalarStores)>;
1200
1201def HasScalarAtomics : Predicate<"Subtarget->hasScalarAtomics()">,
1202  AssemblerPredicate<(all_of FeatureScalarAtomics)>;
1203
1204def HasNoSdstCMPX : Predicate<"Subtarget->hasNoSdstCMPX()">,
1205  AssemblerPredicate<(all_of FeatureNoSdstCMPX)>;
1206
1207def HasSdstCMPX : Predicate<"!Subtarget->hasNoSdstCMPX()">,
1208  AssemblerPredicate<(all_of (not FeatureNoSdstCMPX))>;
1209
1210def has16BankLDS : Predicate<"Subtarget->getLDSBankCount() == 16">;
1211def has32BankLDS : Predicate<"Subtarget->getLDSBankCount() == 32">;
1212def HasVGPRIndexMode : Predicate<"Subtarget->hasVGPRIndexMode()">,
1213                      AssemblerPredicate<(all_of FeatureVGPRIndexMode)>;
1214def HasMovrel : Predicate<"Subtarget->hasMovrel()">,
1215                AssemblerPredicate<(all_of FeatureMovrel)>;
1216
1217def HasFmaMixInsts : Predicate<"Subtarget->hasFmaMixInsts()">,
1218  AssemblerPredicate<(all_of FeatureFmaMixInsts)>;
1219
1220def HasDLInsts : Predicate<"Subtarget->hasDLInsts()">,
1221  AssemblerPredicate<(all_of FeatureDLInsts)>;
1222
1223def HasDot1Insts : Predicate<"Subtarget->hasDot1Insts()">,
1224  AssemblerPredicate<(all_of FeatureDot1Insts)>;
1225
1226def HasDot2Insts : Predicate<"Subtarget->hasDot2Insts()">,
1227  AssemblerPredicate<(all_of FeatureDot2Insts)>;
1228
1229def HasDot3Insts : Predicate<"Subtarget->hasDot3Insts()">,
1230  AssemblerPredicate<(all_of FeatureDot3Insts)>;
1231
1232def HasDot4Insts : Predicate<"Subtarget->hasDot4Insts()">,
1233  AssemblerPredicate<(all_of FeatureDot4Insts)>;
1234
1235def HasDot5Insts : Predicate<"Subtarget->hasDot5Insts()">,
1236  AssemblerPredicate<(all_of FeatureDot5Insts)>;
1237
1238def HasDot6Insts : Predicate<"Subtarget->hasDot6Insts()">,
1239  AssemblerPredicate<(all_of FeatureDot6Insts)>;
1240
1241def HasGetWaveIdInst : Predicate<"Subtarget->hasGetWaveIdInst()">,
1242  AssemblerPredicate<(all_of FeatureGetWaveIdInst)>;
1243
1244def HasMAIInsts : Predicate<"Subtarget->hasMAIInsts()">,
1245  AssemblerPredicate<(all_of FeatureMAIInsts)>;
1246
1247def HasSMemRealTime : Predicate<"Subtarget->hasSMemRealTime()">,
1248  AssemblerPredicate<(all_of FeatureSMemRealTime)>;
1249
1250def HasSMemTimeInst : Predicate<"Subtarget->hasSMemTimeInst()">,
1251  AssemblerPredicate<(all_of FeatureSMemTimeInst)>;
1252
1253def HasNoSMemTimeInst : Predicate<"!Subtarget->hasSMemTimeInst()">;
1254
1255def HasPkFmacF16Inst : Predicate<"Subtarget->hasPkFmacF16Inst()">,
1256  AssemblerPredicate<(all_of FeaturePkFmacF16Inst)>;
1257
1258def HasMadMacF32Insts : Predicate<"Subtarget->hasMadMacF32Insts()">,
1259  AssemblerPredicate<(all_of FeatureMadMacF32Insts)>;
1260
1261def HasFmaLegacy32 : Predicate<"Subtarget->hasGFX10_3Insts()">,
1262  AssemblerPredicate<(any_of FeatureGFX10_3Insts)>;
1263
1264def HasAtomicFaddInsts : Predicate<"Subtarget->hasAtomicFaddInsts()">,
1265  AssemblerPredicate<(all_of FeatureAtomicFaddInsts)>;
1266
1267def HasDsSrc2Insts : Predicate<"!Subtarget->hasDsSrc2Insts()">,
1268  AssemblerPredicate<(all_of FeatureDsSrc2Insts)>;
1269
1270def HasOffset3fBug : Predicate<"!Subtarget->hasOffset3fBug()">,
1271  AssemblerPredicate<(all_of FeatureOffset3fBug)>;
1272
1273def EnableLateCFGStructurize : Predicate<
1274  "EnableLateStructurizeCFG">;
1275
1276def EnableFlatScratch : Predicate<"Subtarget->enableFlatScratch()">;
1277
1278def DisableFlatScratch : Predicate<"!Subtarget->enableFlatScratch()">;
1279
1280def HasUnalignedAccessMode : Predicate<"Subtarget->hasUnalignedAccessMode()">,
1281  AssemblerPredicate<(all_of FeatureUnalignedAccessMode)>;
1282
1283// Include AMDGPU TD files
1284include "SISchedule.td"
1285include "GCNProcessors.td"
1286include "AMDGPUInstrInfo.td"
1287include "SIRegisterInfo.td"
1288include "AMDGPURegisterBanks.td"
1289include "AMDGPUInstructions.td"
1290include "SIInstrInfo.td"
1291include "AMDGPUCallingConv.td"
1292include "AMDGPUSearchableTables.td"
1293