1//===- AMDGPUGenRegisterBankInfo.def -----------------------------*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file defines all the static objects used by AMDGPURegisterBankInfo.
10/// \todo This should be generated by TableGen.
11//===----------------------------------------------------------------------===//
12
13namespace llvm {
14namespace AMDGPU {
15
16enum PartialMappingIdx {
17  None = - 1,
18  PM_SGPR1  = 1,
19  PM_SGPR16 = 5,
20  PM_SGPR32 = 6,
21  PM_SGPR64 = 7,
22  PM_SGPR128 = 8,
23  PM_SGPR256 = 9,
24  PM_SGPR512 = 10,
25  PM_SGPR1024 = 11,
26  PM_VGPR1  = 12,
27  PM_VGPR16 = 16,
28  PM_VGPR32 = 17,
29  PM_VGPR64 = 18,
30  PM_VGPR128 = 19,
31  PM_VGPR256 = 20,
32  PM_VGPR512 = 21,
33  PM_VGPR1024 = 22,
34  PM_SGPR96 = 23,
35  PM_VGPR96 = 24,
36  PM_AGPR96 = 25,
37  PM_AGPR32 = 31,
38  PM_AGPR64 = 32,
39  PM_AGPR128 = 33,
40  PM_AGPR256 = 34,
41  PM_AGPR512 = 35,
42  PM_AGPR1024 = 36
43};
44
45const RegisterBankInfo::PartialMapping PartMappings[] {
46  // StartIdx, Length, RegBank
47  {0, 1,  VCCRegBank},
48
49  {0, 1,  SGPRRegBank}, // SGPR begin
50  {0, 16, SGPRRegBank},
51  {0, 32, SGPRRegBank},
52  {0, 64, SGPRRegBank},
53  {0, 128, SGPRRegBank},
54  {0, 256, SGPRRegBank},
55  {0, 512, SGPRRegBank},
56  {0, 1024, SGPRRegBank},
57
58  {0, 1,  VGPRRegBank}, // VGPR begin
59  {0, 16, VGPRRegBank},
60  {0, 32, VGPRRegBank},
61  {0, 64, VGPRRegBank},
62  {0, 128, VGPRRegBank},
63  {0, 256, VGPRRegBank},
64  {0, 512, VGPRRegBank},
65  {0, 1024, VGPRRegBank},
66  {0, 96, SGPRRegBank},
67  {0, 96, VGPRRegBank},
68  {0, 96, AGPRRegBank},
69
70  {0, 32, AGPRRegBank}, // AGPR begin
71  {0, 64, AGPRRegBank},
72  {0, 128, AGPRRegBank},
73  {0, 256, AGPRRegBank},
74  {0, 512, AGPRRegBank},
75  {0, 1024, AGPRRegBank}
76};
77
78const RegisterBankInfo::ValueMapping ValMappings[] {
79  // VCC
80  {&PartMappings[0], 1},
81
82  // SGPRs
83  {&PartMappings[1], 1}, // 1
84  {nullptr, 0}, // Illegal power of 2 sizes
85  {nullptr, 0},
86  {nullptr, 0},
87  {&PartMappings[2], 1}, // 16
88  {&PartMappings[3], 1}, // 32
89  {&PartMappings[4], 1}, // 64
90  {&PartMappings[5], 1}, // 128
91  {&PartMappings[6], 1}, // 256
92  {&PartMappings[7], 1}, // 512
93  {&PartMappings[8], 1}, // 1024
94
95  // VGPRs
96  {&PartMappings[9], 1}, // 1
97  {nullptr, 0},
98  {nullptr, 0},
99  {nullptr, 0},
100  {&PartMappings[10], 1}, // 16
101  {&PartMappings[11], 1}, // 32
102  {&PartMappings[12], 1}, // 64
103  {&PartMappings[13], 1}, // 128
104  {&PartMappings[14], 1}, // 256
105  {&PartMappings[15], 1}, // 512
106  {&PartMappings[16], 1}, // 1024
107  {&PartMappings[17], 1},
108  {&PartMappings[18], 1},
109  {&PartMappings[19], 1},
110
111  // AGPRs
112  {nullptr, 0},
113  {nullptr, 0},
114  {nullptr, 0},
115  {nullptr, 0},
116  {nullptr, 0},
117  {&PartMappings[20], 1}, // 32
118  {&PartMappings[21], 1}, // 64
119  {&PartMappings[22], 1}, // 128
120  {&PartMappings[23], 1}, // 256
121  {&PartMappings[24], 1}, // 512
122  {&PartMappings[25], 1}  // 1024
123};
124
125const RegisterBankInfo::PartialMapping SGPROnly64BreakDown[] {
126  {0, 32, SGPRRegBank}, // 32-bit op
127  {0, 32, SGPRRegBank}, // 2x32-bit op
128  {32, 32, SGPRRegBank},
129  {0, 64, SGPRRegBank}, // <2x32-bit> op
130
131  {0, 32, VGPRRegBank}, // 32-bit op
132  {0, 32, VGPRRegBank}, // 2x32-bit op
133  {32, 32, VGPRRegBank},
134};
135
136
137// For some instructions which can operate 64-bit only for the scalar
138// version. Otherwise, these need to be split into 2 32-bit operations.
139const RegisterBankInfo::ValueMapping ValMappingsSGPR64OnlyVGPR32[] {
140  /*32-bit sgpr*/     {&SGPROnly64BreakDown[0], 1},
141  /*2 x 32-bit sgpr*/ {&SGPROnly64BreakDown[1], 2},
142  /*64-bit sgpr */    {&SGPROnly64BreakDown[3], 1},
143
144  /*32-bit vgpr*/     {&SGPROnly64BreakDown[4], 1},
145  /*2 x 32-bit vgpr*/ {&SGPROnly64BreakDown[5], 2}
146};
147
148enum ValueMappingIdx {
149  SGPRStartIdx = 1,
150  VGPRStartIdx = 12,
151  AGPRStartIdx = 26
152};
153
154const RegisterBankInfo::ValueMapping *getValueMapping(unsigned BankID,
155                                                      unsigned Size) {
156  unsigned Idx;
157  switch (Size) {
158  case 1:
159    if (BankID == AMDGPU::VCCRegBankID)
160      return &ValMappings[0];
161
162    Idx = BankID == AMDGPU::SGPRRegBankID ? PM_SGPR1 : PM_VGPR1;
163    break;
164  case 96:
165    switch (BankID) {
166      case AMDGPU::VGPRRegBankID:
167        Idx = PM_VGPR96;
168        break;
169      case AMDGPU::SGPRRegBankID:
170        Idx = PM_SGPR96;
171        break;
172      case AMDGPU::AGPRRegBankID:
173        Idx = PM_AGPR96;
174        break;
175      default: llvm_unreachable("Invalid register bank");
176    }
177    break;
178  default:
179    switch (BankID) {
180      case AMDGPU::VGPRRegBankID:
181        Idx = VGPRStartIdx;
182        break;
183      case AMDGPU::SGPRRegBankID:
184        Idx = SGPRStartIdx;
185        break;
186      case AMDGPU::AGPRRegBankID:
187        Idx = AGPRStartIdx;
188        break;
189      default: llvm_unreachable("Invalid register bank");
190    }
191    Idx += Log2_32_Ceil(Size);
192    break;
193  }
194
195  assert(Log2_32_Ceil(Size) == Log2_32_Ceil(ValMappings[Idx].BreakDown->Length));
196  assert(BankID == ValMappings[Idx].BreakDown->RegBank->getID());
197
198  return &ValMappings[Idx];
199}
200
201const RegisterBankInfo::ValueMapping *getValueMappingSGPR64Only(unsigned BankID,
202                                                                unsigned Size) {
203  if (Size != 64)
204    return getValueMapping(BankID, Size);
205
206  if (BankID == AMDGPU::VGPRRegBankID)
207    return &ValMappingsSGPR64OnlyVGPR32[4];
208
209  assert(BankID == AMDGPU::SGPRRegBankID);
210  return &ValMappingsSGPR64OnlyVGPR32[2];
211}
212
213/// Split any 64-bit value into 2 32-bit pieces. Unlike
214/// getValueMappingSGPR64Only, this splits both VGPRs and SGPRs.
215const RegisterBankInfo::ValueMapping *getValueMappingSplit64(unsigned BankID,
216                                                             unsigned Size) {
217  assert(Size == 64);
218  if (BankID == AMDGPU::VGPRRegBankID)
219    return &ValMappingsSGPR64OnlyVGPR32[4];
220
221  assert(BankID == AMDGPU::SGPRRegBankID);
222  return &ValMappingsSGPR64OnlyVGPR32[1];
223}
224
225
226} // End AMDGPU namespace.
227} // End llvm namespace.
228