1 //===- AMDGPUGlobalISelUtils -------------------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUGLOBALISELUTILS_H
10 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUGLOBALISELUTILS_H
11 
12 #include "llvm/ADT/ArrayRef.h"
13 #include "llvm/CodeGen/Register.h"
14 #include <utility>
15 
16 namespace llvm {
17 
18 class MachineRegisterInfo;
19 class GCNSubtarget;
20 class GISelKnownBits;
21 class LLT;
22 
23 namespace AMDGPU {
24 
25 /// Returns base register and constant offset.
26 std::pair<Register, unsigned>
27 getBaseWithConstantOffset(MachineRegisterInfo &MRI, Register Reg,
28                           GISelKnownBits *KnownBits = nullptr);
29 
30 bool hasAtomicFaddRtnForTy(const GCNSubtarget &Subtarget, const LLT &Ty);
31 }
32 }
33 
34 #endif
35