1 //===- AMDGPULegalizerInfo ---------------------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file declares the targeting of the Machinelegalizer class for
10 /// AMDGPU.
11 /// \todo This should be generated by TableGen.
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUMACHINELEGALIZER_H
15 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUMACHINELEGALIZER_H
16 
17 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
18 #include "AMDGPUArgumentUsageInfo.h"
19 #include "SIInstrInfo.h"
20 
21 namespace llvm {
22 
23 class GCNTargetMachine;
24 class LLVMContext;
25 class GCNSubtarget;
26 class MachineIRBuilder;
27 
28 namespace AMDGPU {
29 struct ImageDimIntrinsicInfo;
30 }
31 /// This class provides the information for the target register banks.
32 class AMDGPULegalizerInfo final : public LegalizerInfo {
33   const GCNSubtarget &ST;
34 
35 public:
36   AMDGPULegalizerInfo(const GCNSubtarget &ST,
37                       const GCNTargetMachine &TM);
38 
39   bool legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI) const override;
40 
41   Register getSegmentAperture(unsigned AddrSpace,
42                               MachineRegisterInfo &MRI,
43                               MachineIRBuilder &B) const;
44 
45   bool legalizeAddrSpaceCast(MachineInstr &MI, MachineRegisterInfo &MRI,
46                              MachineIRBuilder &B) const;
47   bool legalizeFrint(MachineInstr &MI, MachineRegisterInfo &MRI,
48                      MachineIRBuilder &B) const;
49   bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI,
50                      MachineIRBuilder &B) const;
51   bool legalizeFrem(MachineInstr &MI, MachineRegisterInfo &MRI,
52                     MachineIRBuilder &B) const;
53   bool legalizeIntrinsicTrunc(MachineInstr &MI, MachineRegisterInfo &MRI,
54                               MachineIRBuilder &B) const;
55   bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI,
56                      MachineIRBuilder &B, bool Signed) const;
57   bool legalizeFPTOI(MachineInstr &MI, MachineRegisterInfo &MRI,
58                      MachineIRBuilder &B, bool Signed) const;
59   bool legalizeMinNumMaxNum(LegalizerHelper &Helper, MachineInstr &MI) const;
60   bool legalizeExtractVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
61                                 MachineIRBuilder &B) const;
62   bool legalizeInsertVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
63                                MachineIRBuilder &B) const;
64   bool legalizeShuffleVector(MachineInstr &MI, MachineRegisterInfo &MRI,
65                              MachineIRBuilder &B) const;
66 
67   bool legalizeSinCos(MachineInstr &MI, MachineRegisterInfo &MRI,
68                       MachineIRBuilder &B) const;
69 
70   bool buildPCRelGlobalAddress(Register DstReg, LLT PtrTy, MachineIRBuilder &B,
71                                const GlobalValue *GV, int64_t Offset,
72                                unsigned GAFlags = SIInstrInfo::MO_NONE) const;
73 
74   bool legalizeGlobalValue(MachineInstr &MI, MachineRegisterInfo &MRI,
75                            MachineIRBuilder &B) const;
76   bool legalizeLoad(LegalizerHelper &Helper, MachineInstr &MI) const;
77 
78   bool legalizeFMad(MachineInstr &MI, MachineRegisterInfo &MRI,
79                     MachineIRBuilder &B) const;
80 
81   bool legalizeAtomicCmpXChg(MachineInstr &MI, MachineRegisterInfo &MRI,
82                              MachineIRBuilder &B) const;
83   bool legalizeFlog(MachineInstr &MI, MachineIRBuilder &B,
84                     double Log2BaseInverted) const;
85   bool legalizeFExp(MachineInstr &MI, MachineIRBuilder &B) const;
86   bool legalizeFPow(MachineInstr &MI, MachineIRBuilder &B) const;
87   bool legalizeFFloor(MachineInstr &MI, MachineRegisterInfo &MRI,
88                       MachineIRBuilder &B) const;
89 
90   bool legalizeBuildVector(MachineInstr &MI, MachineRegisterInfo &MRI,
91                            MachineIRBuilder &B) const;
92 
93   bool loadInputValue(Register DstReg, MachineIRBuilder &B,
94                       const ArgDescriptor *Arg,
95                       const TargetRegisterClass *ArgRC, LLT ArgTy) const;
96   bool loadInputValue(Register DstReg, MachineIRBuilder &B,
97                       AMDGPUFunctionArgInfo::PreloadedValue ArgType) const;
98   bool legalizePreloadedArgIntrin(
99     MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B,
100     AMDGPUFunctionArgInfo::PreloadedValue ArgType) const;
101 
102   bool legalizeUDIV_UREM(MachineInstr &MI, MachineRegisterInfo &MRI,
103                          MachineIRBuilder &B) const;
104 
105   void legalizeUDIV_UREM32Impl(MachineIRBuilder &B,
106                                Register DstReg, Register Num, Register Den,
107                                bool IsRem) const;
108   bool legalizeUDIV_UREM32(MachineInstr &MI, MachineRegisterInfo &MRI,
109                            MachineIRBuilder &B) const;
110   bool legalizeSDIV_SREM32(MachineInstr &MI, MachineRegisterInfo &MRI,
111                            MachineIRBuilder &B) const;
112 
113   void legalizeUDIV_UREM64Impl(MachineIRBuilder &B,
114                                Register DstReg, Register Numer, Register Denom,
115                                bool IsDiv) const;
116 
117   bool legalizeUDIV_UREM64(MachineInstr &MI, MachineRegisterInfo &MRI,
118                            MachineIRBuilder &B) const;
119   bool legalizeSDIV_SREM(MachineInstr &MI, MachineRegisterInfo &MRI,
120                          MachineIRBuilder &B) const;
121 
122   bool legalizeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI,
123                     MachineIRBuilder &B) const;
124   bool legalizeFDIV16(MachineInstr &MI, MachineRegisterInfo &MRI,
125                       MachineIRBuilder &B) const;
126   bool legalizeFDIV32(MachineInstr &MI, MachineRegisterInfo &MRI,
127                       MachineIRBuilder &B) const;
128   bool legalizeFDIV64(MachineInstr &MI, MachineRegisterInfo &MRI,
129                       MachineIRBuilder &B) const;
130   bool legalizeFastUnsafeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI,
131                               MachineIRBuilder &B) const;
132   bool legalizeFastUnsafeFDIV64(MachineInstr &MI, MachineRegisterInfo &MRI,
133                                 MachineIRBuilder &B) const;
134   bool legalizeFDIVFastIntrin(MachineInstr &MI, MachineRegisterInfo &MRI,
135                               MachineIRBuilder &B) const;
136 
137   bool legalizeRsqClampIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI,
138                                  MachineIRBuilder &B) const;
139 
140   bool legalizeDSAtomicFPIntrinsic(LegalizerHelper &Helper,
141                                    MachineInstr &MI, Intrinsic::ID IID) const;
142 
143   bool getImplicitArgPtr(Register DstReg, MachineRegisterInfo &MRI,
144                          MachineIRBuilder &B) const;
145 
146   bool legalizeImplicitArgPtr(MachineInstr &MI, MachineRegisterInfo &MRI,
147                               MachineIRBuilder &B) const;
148   bool legalizeIsAddrSpace(MachineInstr &MI, MachineRegisterInfo &MRI,
149                            MachineIRBuilder &B, unsigned AddrSpace) const;
150 
151   std::tuple<Register, unsigned, unsigned>
152   splitBufferOffsets(MachineIRBuilder &B, Register OrigOffset) const;
153 
154   Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI,
155                           Register Reg, bool ImageStore = false) const;
156   bool legalizeRawBufferStore(MachineInstr &MI, MachineRegisterInfo &MRI,
157                               MachineIRBuilder &B, bool IsFormat) const;
158   bool legalizeRawBufferLoad(MachineInstr &MI, MachineRegisterInfo &MRI,
159                              MachineIRBuilder &B, bool IsFormat) const;
160   Register fixStoreSourceType(MachineIRBuilder &B, Register VData,
161                               bool IsFormat) const;
162 
163   bool legalizeBufferStore(MachineInstr &MI, MachineRegisterInfo &MRI,
164                            MachineIRBuilder &B, bool IsTyped,
165                            bool IsFormat) const;
166   bool legalizeBufferLoad(MachineInstr &MI, MachineRegisterInfo &MRI,
167                           MachineIRBuilder &B, bool IsFormat,
168                           bool IsTyped) const;
169   bool legalizeBufferAtomic(MachineInstr &MI, MachineIRBuilder &B,
170                             Intrinsic::ID IID) const;
171 
172   bool legalizeBVHIntrinsic(MachineInstr &MI, MachineIRBuilder &B) const;
173 
174   bool legalizeImageIntrinsic(
175       MachineInstr &MI, MachineIRBuilder &B,
176       GISelChangeObserver &Observer,
177       const AMDGPU::ImageDimIntrinsicInfo *ImageDimIntr) const;
178 
179   bool legalizeSBufferLoad(LegalizerHelper &Helper, MachineInstr &MI) const;
180 
181   bool legalizeAtomicIncDec(MachineInstr &MI,  MachineIRBuilder &B,
182                             bool IsInc) const;
183 
184   bool legalizeTrapIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI,
185                              MachineIRBuilder &B) const;
186   bool legalizeDebugTrapIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI,
187                                   MachineIRBuilder &B) const;
188 
189   bool legalizeIntrinsic(LegalizerHelper &Helper,
190                          MachineInstr &MI) const override;
191 };
192 } // End llvm namespace.
193 #endif
194