1 //===- AMDGPULegalizerInfo ---------------------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file declares the targeting of the Machinelegalizer class for
10 /// AMDGPU.
11 /// \todo This should be generated by TableGen.
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUMACHINELEGALIZER_H
15 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUMACHINELEGALIZER_H
16 
17 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
18 #include "AMDGPUArgumentUsageInfo.h"
19 #include "SIInstrInfo.h"
20 
21 namespace llvm {
22 
23 class GCNTargetMachine;
24 class GCNSubtarget;
25 class MachineIRBuilder;
26 
27 namespace AMDGPU {
28 struct ImageDimIntrinsicInfo;
29 }
30 /// This class provides the information for the target register banks.
31 class AMDGPULegalizerInfo final : public LegalizerInfo {
32   const GCNSubtarget &ST;
33 
34 public:
35   AMDGPULegalizerInfo(const GCNSubtarget &ST,
36                       const GCNTargetMachine &TM);
37 
38   bool legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI) const override;
39 
40   Register getSegmentAperture(unsigned AddrSpace,
41                               MachineRegisterInfo &MRI,
42                               MachineIRBuilder &B) const;
43 
44   bool legalizeAddrSpaceCast(MachineInstr &MI, MachineRegisterInfo &MRI,
45                              MachineIRBuilder &B) const;
46   bool legalizeFroundeven(MachineInstr &MI, MachineRegisterInfo &MRI,
47                           MachineIRBuilder &B) const;
48   bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI,
49                      MachineIRBuilder &B) const;
50   bool legalizeFrem(MachineInstr &MI, MachineRegisterInfo &MRI,
51                     MachineIRBuilder &B) const;
52   bool legalizeIntrinsicTrunc(MachineInstr &MI, MachineRegisterInfo &MRI,
53                               MachineIRBuilder &B) const;
54   bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI,
55                      MachineIRBuilder &B, bool Signed) const;
56   bool legalizeFPTOI(MachineInstr &MI, MachineRegisterInfo &MRI,
57                      MachineIRBuilder &B, bool Signed) const;
58   bool legalizeMinNumMaxNum(LegalizerHelper &Helper, MachineInstr &MI) const;
59   bool legalizeExtractVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
60                                 MachineIRBuilder &B) const;
61   bool legalizeInsertVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
62                                MachineIRBuilder &B) const;
63 
64   bool legalizeSinCos(MachineInstr &MI, MachineRegisterInfo &MRI,
65                       MachineIRBuilder &B) const;
66 
67   bool buildPCRelGlobalAddress(Register DstReg, LLT PtrTy, MachineIRBuilder &B,
68                                const GlobalValue *GV, int64_t Offset,
69                                unsigned GAFlags = SIInstrInfo::MO_NONE) const;
70 
71   void buildAbsGlobalAddress(Register DstReg, LLT PtrTy, MachineIRBuilder &B,
72                              const GlobalValue *GV,
73                              MachineRegisterInfo &MRI) const;
74 
75   bool legalizeGlobalValue(MachineInstr &MI, MachineRegisterInfo &MRI,
76                            MachineIRBuilder &B) const;
77   bool legalizeLoad(LegalizerHelper &Helper, MachineInstr &MI) const;
78   bool legalizeStore(LegalizerHelper &Helper, MachineInstr &MI) const;
79 
80   bool legalizeFMad(MachineInstr &MI, MachineRegisterInfo &MRI,
81                     MachineIRBuilder &B) const;
82 
83   bool legalizeAtomicCmpXChg(MachineInstr &MI, MachineRegisterInfo &MRI,
84                              MachineIRBuilder &B) const;
85 
86   std::pair<Register, Register>
87   getScaledLogInput(MachineIRBuilder &B, Register Src, unsigned Flags) const;
88 
89   bool legalizeFlog2(MachineInstr &MI, MachineIRBuilder &B) const;
90   bool legalizeFlogCommon(MachineInstr &MI, MachineIRBuilder &B) const;
91   bool legalizeFlogUnsafe(MachineIRBuilder &B, Register Dst, Register Src,
92                           bool IsLog10, unsigned Flags) const;
93   bool legalizeFExp2(MachineInstr &MI, MachineIRBuilder &B) const;
94   bool legalizeFExpUnsafe(MachineIRBuilder &B, Register Dst, Register Src,
95                           unsigned Flags) const;
96   bool legalizeFExp(MachineInstr &MI, MachineIRBuilder &B) const;
97   bool legalizeFPow(MachineInstr &MI, MachineIRBuilder &B) const;
98   bool legalizeFFloor(MachineInstr &MI, MachineRegisterInfo &MRI,
99                       MachineIRBuilder &B) const;
100 
101   bool legalizeBuildVector(MachineInstr &MI, MachineRegisterInfo &MRI,
102                            MachineIRBuilder &B) const;
103 
104   void buildMultiply(LegalizerHelper &Helper, MutableArrayRef<Register> Accum,
105                      ArrayRef<Register> Src0, ArrayRef<Register> Src1,
106                      bool UsePartialMad64_32,
107                      bool SeparateOddAlignedProducts) const;
108   bool legalizeMul(LegalizerHelper &Helper, MachineInstr &MI) const;
109   bool legalizeCTLZ_CTTZ(MachineInstr &MI, MachineRegisterInfo &MRI,
110                          MachineIRBuilder &B) const;
111 
112   bool loadInputValue(Register DstReg, MachineIRBuilder &B,
113                       const ArgDescriptor *Arg,
114                       const TargetRegisterClass *ArgRC, LLT ArgTy) const;
115   bool loadInputValue(Register DstReg, MachineIRBuilder &B,
116                       AMDGPUFunctionArgInfo::PreloadedValue ArgType) const;
117 
118   bool legalizePointerAsRsrcIntrin(MachineInstr &MI, MachineRegisterInfo &MRI,
119                                    MachineIRBuilder &B) const;
120 
121   bool legalizePreloadedArgIntrin(
122     MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B,
123     AMDGPUFunctionArgInfo::PreloadedValue ArgType) const;
124   bool legalizeWorkitemIDIntrinsic(
125       MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B,
126       unsigned Dim, AMDGPUFunctionArgInfo::PreloadedValue ArgType) const;
127 
128   Register getKernargParameterPtr(MachineIRBuilder &B, int64_t Offset) const;
129   bool legalizeKernargMemParameter(MachineInstr &MI, MachineIRBuilder &B,
130                                    uint64_t Offset,
131                                    Align Alignment = Align(4)) const;
132 
133   bool legalizeUnsignedDIV_REM(MachineInstr &MI, MachineRegisterInfo &MRI,
134                                MachineIRBuilder &B) const;
135 
136   void legalizeUnsignedDIV_REM32Impl(MachineIRBuilder &B, Register DstDivReg,
137                                      Register DstRemReg, Register Num,
138                                      Register Den) const;
139 
140   void legalizeUnsignedDIV_REM64Impl(MachineIRBuilder &B, Register DstDivReg,
141                                      Register DstRemReg, Register Num,
142                                      Register Den) const;
143 
144   bool legalizeSignedDIV_REM(MachineInstr &MI, MachineRegisterInfo &MRI,
145                              MachineIRBuilder &B) const;
146 
147   bool legalizeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI,
148                     MachineIRBuilder &B) const;
149   bool legalizeFDIV16(MachineInstr &MI, MachineRegisterInfo &MRI,
150                       MachineIRBuilder &B) const;
151   bool legalizeFDIV32(MachineInstr &MI, MachineRegisterInfo &MRI,
152                       MachineIRBuilder &B) const;
153   bool legalizeFDIV64(MachineInstr &MI, MachineRegisterInfo &MRI,
154                       MachineIRBuilder &B) const;
155   bool legalizeFFREXP(MachineInstr &MI, MachineRegisterInfo &MRI,
156                       MachineIRBuilder &B) const;
157   bool legalizeFastUnsafeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI,
158                               MachineIRBuilder &B) const;
159   bool legalizeFastUnsafeFDIV64(MachineInstr &MI, MachineRegisterInfo &MRI,
160                                 MachineIRBuilder &B) const;
161   bool legalizeFDIVFastIntrin(MachineInstr &MI, MachineRegisterInfo &MRI,
162                               MachineIRBuilder &B) const;
163 
164   bool legalizeFSQRTF16(MachineInstr &MI, MachineRegisterInfo &MRI,
165                         MachineIRBuilder &B) const;
166   bool legalizeFSQRTF32(MachineInstr &MI, MachineRegisterInfo &MRI,
167                         MachineIRBuilder &B) const;
168   bool legalizeFSQRTF64(MachineInstr &MI, MachineRegisterInfo &MRI,
169                         MachineIRBuilder &B) const;
170   bool legalizeFSQRT(MachineInstr &MI, MachineRegisterInfo &MRI,
171                      MachineIRBuilder &B) const;
172 
173   bool legalizeRsqClampIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI,
174                                  MachineIRBuilder &B) const;
175 
176   bool legalizeDSAtomicFPIntrinsic(LegalizerHelper &Helper,
177                                    MachineInstr &MI, Intrinsic::ID IID) const;
178 
179   bool getImplicitArgPtr(Register DstReg, MachineRegisterInfo &MRI,
180                          MachineIRBuilder &B) const;
181 
182   bool legalizeImplicitArgPtr(MachineInstr &MI, MachineRegisterInfo &MRI,
183                               MachineIRBuilder &B) const;
184 
185   bool getLDSKernelId(Register DstReg, MachineRegisterInfo &MRI,
186                       MachineIRBuilder &B) const;
187 
188   bool legalizeLDSKernelId(MachineInstr &MI, MachineRegisterInfo &MRI,
189                            MachineIRBuilder &B) const;
190 
191   bool legalizeIsAddrSpace(MachineInstr &MI, MachineRegisterInfo &MRI,
192                            MachineIRBuilder &B, unsigned AddrSpace) const;
193 
194   std::pair<Register, unsigned> splitBufferOffsets(MachineIRBuilder &B,
195                                                    Register OrigOffset) const;
196 
197   Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI,
198                           Register Reg, bool ImageStore = false) const;
199   Register fixStoreSourceType(MachineIRBuilder &B, Register VData,
200                               bool IsFormat) const;
201 
202   bool legalizeBufferStore(MachineInstr &MI, MachineRegisterInfo &MRI,
203                            MachineIRBuilder &B, bool IsTyped,
204                            bool IsFormat) const;
205   bool legalizeBufferLoad(MachineInstr &MI, MachineRegisterInfo &MRI,
206                           MachineIRBuilder &B, bool IsFormat,
207                           bool IsTyped) const;
208   bool legalizeBufferAtomic(MachineInstr &MI, MachineIRBuilder &B,
209                             Intrinsic::ID IID) const;
210 
211   bool legalizeBVHIntrinsic(MachineInstr &MI, MachineIRBuilder &B) const;
212 
213   bool legalizeFPTruncRound(MachineInstr &MI, MachineIRBuilder &B) const;
214   bool legalizeStackSave(MachineInstr &MI, MachineIRBuilder &B) const;
215 
216   bool legalizeImageIntrinsic(
217       MachineInstr &MI, MachineIRBuilder &B,
218       GISelChangeObserver &Observer,
219       const AMDGPU::ImageDimIntrinsicInfo *ImageDimIntr) const;
220 
221   bool legalizeSBufferLoad(LegalizerHelper &Helper, MachineInstr &MI) const;
222 
223   bool legalizeTrapIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI,
224                              MachineIRBuilder &B) const;
225   bool legalizeTrapEndpgm(MachineInstr &MI, MachineRegisterInfo &MRI,
226                           MachineIRBuilder &B) const;
227   bool legalizeTrapHsaQueuePtr(MachineInstr &MI, MachineRegisterInfo &MRI,
228                                MachineIRBuilder &B) const;
229   bool legalizeTrapHsa(MachineInstr &MI, MachineRegisterInfo &MRI,
230                        MachineIRBuilder &B) const;
231   bool legalizeDebugTrapIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI,
232                                   MachineIRBuilder &B) const;
233 
234   bool legalizeIntrinsic(LegalizerHelper &Helper,
235                          MachineInstr &MI) const override;
236 };
237 } // End llvm namespace.
238 #endif
239