1 //===- AMDGPURegBankSelect.cpp -----------------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Use MachineUniformityAnalysis as the primary basis for making SGPR vs. VGPR
10 // register bank selection. Use/def analysis as in the default RegBankSelect can
11 // be useful in narrower circumstances (e.g. choosing AGPR vs. VGPR for gfx908).
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AMDGPURegBankSelect.h"
16 #include "AMDGPU.h"
17 #include "GCNSubtarget.h"
18 #include "llvm/CodeGen/MachineUniformityAnalysis.h"
19 #include "llvm/InitializePasses.h"
20 
21 #define DEBUG_TYPE "regbankselect"
22 
23 using namespace llvm;
24 
25 AMDGPURegBankSelect::AMDGPURegBankSelect(Mode RunningMode)
26     : RegBankSelect(AMDGPURegBankSelect::ID, RunningMode) {}
27 
28 char AMDGPURegBankSelect::ID = 0;
29 
30 StringRef AMDGPURegBankSelect::getPassName() const {
31   return "AMDGPURegBankSelect";
32 }
33 
34 void AMDGPURegBankSelect::getAnalysisUsage(AnalysisUsage &AU) const {
35   AU.addRequired<MachineCycleInfoWrapperPass>();
36   AU.addRequired<MachineDominatorTree>();
37   // TODO: Preserve DomTree
38   RegBankSelect::getAnalysisUsage(AU);
39 }
40 
41 INITIALIZE_PASS_BEGIN(AMDGPURegBankSelect, "amdgpu-" DEBUG_TYPE,
42                       "AMDGPU Register Bank Select", false, false)
43 INITIALIZE_PASS_DEPENDENCY(MachineCycleInfoWrapperPass)
44 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
45 INITIALIZE_PASS_END(AMDGPURegBankSelect, "amdgpu-" DEBUG_TYPE,
46                     "AMDGPU Register Bank Select", false, false)
47 
48 bool AMDGPURegBankSelect::runOnMachineFunction(MachineFunction &MF) {
49   // If the ISel pipeline failed, do not bother running that pass.
50   if (MF.getProperties().hasProperty(
51           MachineFunctionProperties::Property::FailedISel))
52     return false;
53 
54   LLVM_DEBUG(dbgs() << "Assign register banks for: " << MF.getName() << '\n');
55   const Function &F = MF.getFunction();
56   Mode SaveOptMode = OptMode;
57   if (F.hasOptNone())
58     OptMode = Mode::Fast;
59   init(MF);
60 
61   assert(checkFunctionIsLegal(MF));
62 
63   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
64   MachineCycleInfo &CycleInfo =
65       getAnalysis<MachineCycleInfoWrapperPass>().getCycleInfo();
66   MachineDominatorTree &DomTree = getAnalysis<MachineDominatorTree>();
67 
68   MachineUniformityInfo Uniformity =
69       computeMachineUniformityInfo(MF, CycleInfo, DomTree.getBase(),
70                                    !ST.isSingleLaneExecution(F));
71   (void)Uniformity; // TODO: Use this
72 
73   assignRegisterBanks(MF);
74 
75   OptMode = SaveOptMode;
76   return false;
77 }
78