1 //===- AMDGPURegisterBankInfo -----------------------------------*- C++ -*-==// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file declares the targeting of the RegisterBankInfo class for AMDGPU. 10 /// \todo This should be generated by TableGen. 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERBANKINFO_H 14 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERBANKINFO_H 15 16 #include "llvm/ADT/SmallSet.h" 17 #include "llvm/CodeGen/MachineBasicBlock.h" 18 #include "llvm/CodeGen/Register.h" 19 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h" 20 21 #define GET_REGBANK_DECLARATIONS 22 #include "AMDGPUGenRegisterBank.inc" 23 24 namespace llvm { 25 26 class LLT; 27 class GCNSubtarget; 28 class MachineIRBuilder; 29 class SIInstrInfo; 30 class SIRegisterInfo; 31 class TargetRegisterInfo; 32 33 /// This class provides the information for the target register banks. 34 class AMDGPUGenRegisterBankInfo : public RegisterBankInfo { 35 36 protected: 37 38 #define GET_TARGET_REGBANK_CLASS 39 #include "AMDGPUGenRegisterBank.inc" 40 }; 41 42 class AMDGPURegisterBankInfo final : public AMDGPUGenRegisterBankInfo { 43 public: 44 const GCNSubtarget &Subtarget; 45 const SIRegisterInfo *TRI; 46 const SIInstrInfo *TII; 47 48 bool buildVCopy(MachineIRBuilder &B, Register DstReg, Register SrcReg) const; 49 50 bool collectWaterfallOperands( 51 SmallSet<Register, 4> &SGPROperandRegs, 52 MachineInstr &MI, 53 MachineRegisterInfo &MRI, 54 ArrayRef<unsigned> OpIndices) const; 55 56 bool executeInWaterfallLoop( 57 MachineIRBuilder &B, 58 iterator_range<MachineBasicBlock::iterator> Range, 59 SmallSet<Register, 4> &SGPROperandRegs, 60 MachineRegisterInfo &MRI) const; 61 62 bool executeInWaterfallLoop(MachineIRBuilder &B, 63 MachineInstr &MI, 64 MachineRegisterInfo &MRI, 65 ArrayRef<unsigned> OpIndices) const; 66 bool executeInWaterfallLoop(MachineInstr &MI, 67 MachineRegisterInfo &MRI, 68 ArrayRef<unsigned> OpIndices) const; 69 70 void constrainOpWithReadfirstlane(MachineInstr &MI, MachineRegisterInfo &MRI, 71 unsigned OpIdx) const; 72 bool applyMappingDynStackAlloc(MachineInstr &MI, 73 const OperandsMapper &OpdMapper, 74 MachineRegisterInfo &MRI) const; 75 bool applyMappingLoad(MachineInstr &MI, 76 const OperandsMapper &OpdMapper, 77 MachineRegisterInfo &MRI) const; 78 bool 79 applyMappingImage(MachineInstr &MI, 80 const OperandsMapper &OpdMapper, 81 MachineRegisterInfo &MRI, int RSrcIdx) const; 82 bool applyMappingSBufferLoad(const OperandsMapper &OpdMapper) const; 83 84 bool applyMappingBFE(const OperandsMapper &OpdMapper, bool Signed) const; 85 86 Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI, 87 Register Reg) const; 88 89 std::pair<Register, unsigned> 90 splitBufferOffsets(MachineIRBuilder &B, Register Offset) const; 91 92 MachineInstr *selectStoreIntrinsic(MachineIRBuilder &B, 93 MachineInstr &MI) const; 94 95 /// See RegisterBankInfo::applyMapping. 96 void applyMappingImpl(const OperandsMapper &OpdMapper) const override; 97 98 const ValueMapping *getValueMappingForPtr(const MachineRegisterInfo &MRI, 99 Register Ptr) const; 100 101 const RegisterBankInfo::InstructionMapping & 102 getInstrMappingForLoad(const MachineInstr &MI) const; 103 104 unsigned getRegBankID(Register Reg, const MachineRegisterInfo &MRI, 105 unsigned Default = AMDGPU::VGPRRegBankID) const; 106 107 // Return a value mapping for an operand that is required to be an SGPR. 108 const ValueMapping *getSGPROpMapping(Register Reg, 109 const MachineRegisterInfo &MRI, 110 const TargetRegisterInfo &TRI) const; 111 112 // Return a value mapping for an operand that is required to be a VGPR. 113 const ValueMapping *getVGPROpMapping(Register Reg, 114 const MachineRegisterInfo &MRI, 115 const TargetRegisterInfo &TRI) const; 116 117 // Return a value mapping for an operand that is required to be a AGPR. 118 const ValueMapping *getAGPROpMapping(Register Reg, 119 const MachineRegisterInfo &MRI, 120 const TargetRegisterInfo &TRI) const; 121 122 /// Split 64-bit value \p Reg into two 32-bit halves and populate them into \p 123 /// Regs. This appropriately sets the regbank of the new registers. 124 void split64BitValueForMapping(MachineIRBuilder &B, 125 SmallVector<Register, 2> &Regs, 126 LLT HalfTy, 127 Register Reg) const; 128 129 template <unsigned NumOps> 130 struct OpRegBankEntry { 131 int8_t RegBanks[NumOps]; 132 int16_t Cost; 133 }; 134 135 template <unsigned NumOps> 136 InstructionMappings 137 addMappingFromTable(const MachineInstr &MI, const MachineRegisterInfo &MRI, 138 const std::array<unsigned, NumOps> RegSrcOpIdx, 139 ArrayRef<OpRegBankEntry<NumOps>> Table) const; 140 141 RegisterBankInfo::InstructionMappings 142 getInstrAlternativeMappingsIntrinsic( 143 const MachineInstr &MI, const MachineRegisterInfo &MRI) const; 144 145 RegisterBankInfo::InstructionMappings 146 getInstrAlternativeMappingsIntrinsicWSideEffects( 147 const MachineInstr &MI, const MachineRegisterInfo &MRI) const; 148 149 unsigned getMappingType(const MachineRegisterInfo &MRI, 150 const MachineInstr &MI) const; 151 152 bool isSALUMapping(const MachineInstr &MI) const; 153 154 const InstructionMapping &getDefaultMappingSOP(const MachineInstr &MI) const; 155 const InstructionMapping &getDefaultMappingVOP(const MachineInstr &MI) const; 156 const InstructionMapping &getDefaultMappingAllVGPR( 157 const MachineInstr &MI) const; 158 159 const InstructionMapping &getImageMapping(const MachineRegisterInfo &MRI, 160 const MachineInstr &MI, 161 int RsrcIdx) const; 162 163 public: 164 AMDGPURegisterBankInfo(const GCNSubtarget &STI); 165 166 unsigned copyCost(const RegisterBank &A, const RegisterBank &B, 167 unsigned Size) const override; 168 169 unsigned getBreakDownCost(const ValueMapping &ValMapping, 170 const RegisterBank *CurBank = nullptr) const override; 171 172 const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC, 173 LLT) const override; 174 175 InstructionMappings 176 getInstrAlternativeMappings(const MachineInstr &MI) const override; 177 178 const InstructionMapping & 179 getInstrMapping(const MachineInstr &MI) const override; 180 181 private: 182 183 bool foldExtractEltToCmpSelect(MachineInstr &MI, 184 MachineRegisterInfo &MRI, 185 const OperandsMapper &OpdMapper) const; 186 bool foldInsertEltToCmpSelect(MachineInstr &MI, 187 MachineRegisterInfo &MRI, 188 const OperandsMapper &OpdMapper) const; 189 }; 190 } // End llvm namespace. 191 #endif 192