1 //===- AMDGPURegisterBankInfo -----------------------------------*- C++ -*-==// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file declares the targeting of the RegisterBankInfo class for AMDGPU. 10 /// \todo This should be generated by TableGen. 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERBANKINFO_H 14 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERBANKINFO_H 15 16 #include "llvm/ADT/SmallSet.h" 17 #include "llvm/CodeGen/MachineBasicBlock.h" 18 #include "llvm/CodeGen/Register.h" 19 #include "llvm/CodeGen/RegisterBankInfo.h" 20 21 #define GET_REGBANK_DECLARATIONS 22 #include "AMDGPUGenRegisterBank.inc" 23 24 namespace llvm { 25 26 class LLT; 27 class GCNSubtarget; 28 class MachineIRBuilder; 29 class SIInstrInfo; 30 class SIRegisterInfo; 31 class TargetRegisterInfo; 32 33 /// This class provides the information for the target register banks. 34 class AMDGPUGenRegisterBankInfo : public RegisterBankInfo { 35 36 protected: 37 38 #define GET_TARGET_REGBANK_CLASS 39 #include "AMDGPUGenRegisterBank.inc" 40 }; 41 42 class AMDGPURegisterBankInfo final : public AMDGPUGenRegisterBankInfo { 43 public: 44 const GCNSubtarget &Subtarget; 45 const SIRegisterInfo *TRI; 46 const SIInstrInfo *TII; 47 48 bool buildVCopy(MachineIRBuilder &B, Register DstReg, Register SrcReg) const; 49 50 bool collectWaterfallOperands( 51 SmallSet<Register, 4> &SGPROperandRegs, 52 MachineInstr &MI, 53 MachineRegisterInfo &MRI, 54 ArrayRef<unsigned> OpIndices) const; 55 56 bool executeInWaterfallLoop( 57 MachineIRBuilder &B, 58 iterator_range<MachineBasicBlock::iterator> Range, 59 SmallSet<Register, 4> &SGPROperandRegs, 60 MachineRegisterInfo &MRI) const; 61 62 Register buildReadFirstLane(MachineIRBuilder &B, MachineRegisterInfo &MRI, 63 Register Src) const; 64 65 bool executeInWaterfallLoop(MachineIRBuilder &B, 66 MachineInstr &MI, 67 MachineRegisterInfo &MRI, 68 ArrayRef<unsigned> OpIndices) const; 69 bool executeInWaterfallLoop(MachineInstr &MI, 70 MachineRegisterInfo &MRI, 71 ArrayRef<unsigned> OpIndices) const; 72 73 void constrainOpWithReadfirstlane(MachineInstr &MI, MachineRegisterInfo &MRI, 74 unsigned OpIdx) const; 75 bool applyMappingDynStackAlloc(MachineInstr &MI, 76 const OperandsMapper &OpdMapper, 77 MachineRegisterInfo &MRI) const; 78 bool applyMappingLoad(MachineInstr &MI, 79 const OperandsMapper &OpdMapper, 80 MachineRegisterInfo &MRI) const; 81 bool 82 applyMappingImage(MachineInstr &MI, 83 const OperandsMapper &OpdMapper, 84 MachineRegisterInfo &MRI, int RSrcIdx) const; 85 bool applyMappingSBufferLoad(const OperandsMapper &OpdMapper) const; 86 87 bool applyMappingBFE(const OperandsMapper &OpdMapper, bool Signed) const; 88 89 bool applyMappingMAD_64_32(const OperandsMapper &OpdMapper) const; 90 91 Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI, 92 Register Reg) const; 93 94 std::pair<Register, unsigned> 95 splitBufferOffsets(MachineIRBuilder &B, Register Offset) const; 96 97 /// See RegisterBankInfo::applyMapping. 98 void applyMappingImpl(const OperandsMapper &OpdMapper) const override; 99 100 const ValueMapping *getValueMappingForPtr(const MachineRegisterInfo &MRI, 101 Register Ptr) const; 102 103 const RegisterBankInfo::InstructionMapping & 104 getInstrMappingForLoad(const MachineInstr &MI) const; 105 106 unsigned getRegBankID(Register Reg, const MachineRegisterInfo &MRI, 107 unsigned Default = AMDGPU::VGPRRegBankID) const; 108 109 // Return a value mapping for an operand that is required to be an SGPR. 110 const ValueMapping *getSGPROpMapping(Register Reg, 111 const MachineRegisterInfo &MRI, 112 const TargetRegisterInfo &TRI) const; 113 114 // Return a value mapping for an operand that is required to be a VGPR. 115 const ValueMapping *getVGPROpMapping(Register Reg, 116 const MachineRegisterInfo &MRI, 117 const TargetRegisterInfo &TRI) const; 118 119 // Return a value mapping for an operand that is required to be a AGPR. 120 const ValueMapping *getAGPROpMapping(Register Reg, 121 const MachineRegisterInfo &MRI, 122 const TargetRegisterInfo &TRI) const; 123 124 /// Split 64-bit value \p Reg into two 32-bit halves and populate them into \p 125 /// Regs. This appropriately sets the regbank of the new registers. 126 void split64BitValueForMapping(MachineIRBuilder &B, 127 SmallVector<Register, 2> &Regs, 128 LLT HalfTy, 129 Register Reg) const; 130 131 template <unsigned NumOps> 132 struct OpRegBankEntry { 133 int8_t RegBanks[NumOps]; 134 int16_t Cost; 135 }; 136 137 template <unsigned NumOps> 138 InstructionMappings 139 addMappingFromTable(const MachineInstr &MI, const MachineRegisterInfo &MRI, 140 const std::array<unsigned, NumOps> RegSrcOpIdx, 141 ArrayRef<OpRegBankEntry<NumOps>> Table) const; 142 143 RegisterBankInfo::InstructionMappings 144 getInstrAlternativeMappingsIntrinsic( 145 const MachineInstr &MI, const MachineRegisterInfo &MRI) const; 146 147 RegisterBankInfo::InstructionMappings 148 getInstrAlternativeMappingsIntrinsicWSideEffects( 149 const MachineInstr &MI, const MachineRegisterInfo &MRI) const; 150 151 unsigned getMappingType(const MachineRegisterInfo &MRI, 152 const MachineInstr &MI) const; 153 154 bool isSALUMapping(const MachineInstr &MI) const; 155 156 const InstructionMapping &getDefaultMappingSOP(const MachineInstr &MI) const; 157 const InstructionMapping &getDefaultMappingVOP(const MachineInstr &MI) const; 158 const InstructionMapping &getDefaultMappingAllVGPR( 159 const MachineInstr &MI) const; 160 161 const InstructionMapping &getImageMapping(const MachineRegisterInfo &MRI, 162 const MachineInstr &MI, 163 int RsrcIdx) const; 164 165 public: 166 AMDGPURegisterBankInfo(const GCNSubtarget &STI); 167 168 unsigned copyCost(const RegisterBank &A, const RegisterBank &B, 169 unsigned Size) const override; 170 171 unsigned getBreakDownCost(const ValueMapping &ValMapping, 172 const RegisterBank *CurBank = nullptr) const override; 173 174 const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC, 175 LLT) const override; 176 177 InstructionMappings 178 getInstrAlternativeMappings(const MachineInstr &MI) const override; 179 180 const InstructionMapping & 181 getInstrMapping(const MachineInstr &MI) const override; 182 183 private: 184 185 bool foldExtractEltToCmpSelect(MachineInstr &MI, 186 MachineRegisterInfo &MRI, 187 const OperandsMapper &OpdMapper) const; 188 bool foldInsertEltToCmpSelect(MachineInstr &MI, 189 MachineRegisterInfo &MRI, 190 const OperandsMapper &OpdMapper) const; 191 }; 192 } // End llvm namespace. 193 #endif 194