1 //===- AMDGPURegisterBankInfo -----------------------------------*- C++ -*-==// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file declares the targeting of the RegisterBankInfo class for AMDGPU. 10 /// \todo This should be generated by TableGen. 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERBANKINFO_H 14 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERBANKINFO_H 15 16 #include "llvm/ADT/SmallSet.h" 17 #include "llvm/CodeGen/MachineBasicBlock.h" 18 #include "llvm/CodeGen/Register.h" 19 #include "llvm/CodeGen/RegisterBankInfo.h" 20 21 #define GET_REGBANK_DECLARATIONS 22 #include "AMDGPUGenRegisterBank.inc" 23 24 namespace llvm { 25 26 class LLT; 27 class GCNSubtarget; 28 class MachineIRBuilder; 29 class SIInstrInfo; 30 class SIRegisterInfo; 31 class TargetRegisterInfo; 32 33 /// This class provides the information for the target register banks. 34 class AMDGPUGenRegisterBankInfo : public RegisterBankInfo { 35 36 protected: 37 38 #define GET_TARGET_REGBANK_CLASS 39 #include "AMDGPUGenRegisterBank.inc" 40 }; 41 42 class AMDGPURegisterBankInfo final : public AMDGPUGenRegisterBankInfo { 43 public: 44 const GCNSubtarget &Subtarget; 45 const SIRegisterInfo *TRI; 46 const SIInstrInfo *TII; 47 48 bool buildVCopy(MachineIRBuilder &B, Register DstReg, Register SrcReg) const; 49 50 bool collectWaterfallOperands( 51 SmallSet<Register, 4> &SGPROperandRegs, 52 MachineInstr &MI, 53 MachineRegisterInfo &MRI, 54 ArrayRef<unsigned> OpIndices) const; 55 56 bool executeInWaterfallLoop( 57 MachineIRBuilder &B, 58 iterator_range<MachineBasicBlock::iterator> Range, 59 SmallSet<Register, 4> &SGPROperandRegs, 60 MachineRegisterInfo &MRI) const; 61 62 Register buildReadFirstLane(MachineIRBuilder &B, MachineRegisterInfo &MRI, 63 Register Src) const; 64 65 bool executeInWaterfallLoop(MachineIRBuilder &B, 66 MachineInstr &MI, 67 MachineRegisterInfo &MRI, 68 ArrayRef<unsigned> OpIndices) const; 69 bool executeInWaterfallLoop(MachineInstr &MI, 70 MachineRegisterInfo &MRI, 71 ArrayRef<unsigned> OpIndices) const; 72 73 void constrainOpWithReadfirstlane(MachineInstr &MI, MachineRegisterInfo &MRI, 74 unsigned OpIdx) const; 75 bool applyMappingDynStackAlloc(MachineInstr &MI, 76 const OperandsMapper &OpdMapper, 77 MachineRegisterInfo &MRI) const; 78 bool applyMappingLoad(MachineInstr &MI, 79 const OperandsMapper &OpdMapper, 80 MachineRegisterInfo &MRI) const; 81 bool 82 applyMappingImage(MachineInstr &MI, 83 const OperandsMapper &OpdMapper, 84 MachineRegisterInfo &MRI, int RSrcIdx) const; 85 unsigned setBufferOffsets(MachineIRBuilder &B, Register CombinedOffset, 86 Register &VOffsetReg, Register &SOffsetReg, 87 int64_t &InstOffsetVal, Align Alignment) const; 88 bool applyMappingSBufferLoad(const OperandsMapper &OpdMapper) const; 89 90 bool applyMappingBFE(const OperandsMapper &OpdMapper, bool Signed) const; 91 92 bool applyMappingMAD_64_32(const OperandsMapper &OpdMapper) const; 93 94 Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI, 95 Register Reg) const; 96 97 std::pair<Register, unsigned> 98 splitBufferOffsets(MachineIRBuilder &B, Register Offset) const; 99 100 /// See RegisterBankInfo::applyMapping. 101 void applyMappingImpl(const OperandsMapper &OpdMapper) const override; 102 103 const ValueMapping *getValueMappingForPtr(const MachineRegisterInfo &MRI, 104 Register Ptr) const; 105 106 const RegisterBankInfo::InstructionMapping & 107 getInstrMappingForLoad(const MachineInstr &MI) const; 108 109 unsigned getRegBankID(Register Reg, const MachineRegisterInfo &MRI, 110 unsigned Default = AMDGPU::VGPRRegBankID) const; 111 112 // Return a value mapping for an operand that is required to be an SGPR. 113 const ValueMapping *getSGPROpMapping(Register Reg, 114 const MachineRegisterInfo &MRI, 115 const TargetRegisterInfo &TRI) const; 116 117 // Return a value mapping for an operand that is required to be a VGPR. 118 const ValueMapping *getVGPROpMapping(Register Reg, 119 const MachineRegisterInfo &MRI, 120 const TargetRegisterInfo &TRI) const; 121 122 // Return a value mapping for an operand that is required to be a AGPR. 123 const ValueMapping *getAGPROpMapping(Register Reg, 124 const MachineRegisterInfo &MRI, 125 const TargetRegisterInfo &TRI) const; 126 127 /// Split 64-bit value \p Reg into two 32-bit halves and populate them into \p 128 /// Regs. This appropriately sets the regbank of the new registers. 129 void split64BitValueForMapping(MachineIRBuilder &B, 130 SmallVector<Register, 2> &Regs, 131 LLT HalfTy, 132 Register Reg) const; 133 134 template <unsigned NumOps> 135 struct OpRegBankEntry { 136 int8_t RegBanks[NumOps]; 137 int16_t Cost; 138 }; 139 140 template <unsigned NumOps> 141 InstructionMappings 142 addMappingFromTable(const MachineInstr &MI, const MachineRegisterInfo &MRI, 143 const std::array<unsigned, NumOps> RegSrcOpIdx, 144 ArrayRef<OpRegBankEntry<NumOps>> Table) const; 145 146 RegisterBankInfo::InstructionMappings 147 getInstrAlternativeMappingsIntrinsic( 148 const MachineInstr &MI, const MachineRegisterInfo &MRI) const; 149 150 RegisterBankInfo::InstructionMappings 151 getInstrAlternativeMappingsIntrinsicWSideEffects( 152 const MachineInstr &MI, const MachineRegisterInfo &MRI) const; 153 154 unsigned getMappingType(const MachineRegisterInfo &MRI, 155 const MachineInstr &MI) const; 156 157 bool isSALUMapping(const MachineInstr &MI) const; 158 159 const InstructionMapping &getDefaultMappingSOP(const MachineInstr &MI) const; 160 const InstructionMapping &getDefaultMappingVOP(const MachineInstr &MI) const; 161 const InstructionMapping &getDefaultMappingAllVGPR( 162 const MachineInstr &MI) const; 163 164 const InstructionMapping &getImageMapping(const MachineRegisterInfo &MRI, 165 const MachineInstr &MI, 166 int RsrcIdx) const; 167 168 public: 169 AMDGPURegisterBankInfo(const GCNSubtarget &STI); 170 171 bool isDivergentRegBank(const RegisterBank *RB) const override; 172 173 unsigned copyCost(const RegisterBank &A, const RegisterBank &B, 174 unsigned Size) const override; 175 176 unsigned getBreakDownCost(const ValueMapping &ValMapping, 177 const RegisterBank *CurBank = nullptr) const override; 178 179 const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC, 180 LLT) const override; 181 182 InstructionMappings 183 getInstrAlternativeMappings(const MachineInstr &MI) const override; 184 185 const InstructionMapping & 186 getInstrMapping(const MachineInstr &MI) const override; 187 188 private: 189 190 bool foldExtractEltToCmpSelect(MachineInstr &MI, 191 MachineRegisterInfo &MRI, 192 const OperandsMapper &OpdMapper) const; 193 bool foldInsertEltToCmpSelect(MachineInstr &MI, 194 MachineRegisterInfo &MRI, 195 const OperandsMapper &OpdMapper) const; 196 }; 197 } // End llvm namespace. 198 #endif 199