1 //===-- AMDGPUTargetMachine.h - AMDGPU TargetMachine Interface --*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// The AMDGPU TargetMachine interface definition for hw codegen targets.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETMACHINE_H
15 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETMACHINE_H
16 
17 #include "GCNSubtarget.h"
18 #include "llvm/CodeGen/TargetPassConfig.h"
19 #include "llvm/Target/TargetMachine.h"
20 #include <optional>
21 #include <utility>
22 
23 namespace llvm {
24 
25 //===----------------------------------------------------------------------===//
26 // AMDGPU Target Machine (R600+)
27 //===----------------------------------------------------------------------===//
28 
29 class AMDGPUTargetMachine : public LLVMTargetMachine {
30 protected:
31   std::unique_ptr<TargetLoweringObjectFile> TLOF;
32 
33   StringRef getGPUName(const Function &F) const;
34   StringRef getFeatureString(const Function &F) const;
35 
36 public:
37   static bool EnableLateStructurizeCFG;
38   static bool EnableFunctionCalls;
39   static bool EnableLowerModuleLDS;
40 
41   AMDGPUTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
42                       StringRef FS, TargetOptions Options,
43                       std::optional<Reloc::Model> RM,
44                       std::optional<CodeModel::Model> CM, CodeGenOptLevel OL);
45   ~AMDGPUTargetMachine() override;
46 
47   const TargetSubtargetInfo *getSubtargetImpl() const;
48   const TargetSubtargetInfo *getSubtargetImpl(const Function &) const override = 0;
49 
50   TargetLoweringObjectFile *getObjFileLowering() const override {
51     return TLOF.get();
52   }
53 
54   void registerPassBuilderCallbacks(PassBuilder &PB,
55                                     bool PopulateClassToPassNames) override;
56   void registerDefaultAliasAnalyses(AAManager &) override;
57 
58   /// Get the integer value of a null pointer in the given address space.
59   static int64_t getNullPointerValue(unsigned AddrSpace);
60 
61   bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
62 
63   unsigned getAssumedAddrSpace(const Value *V) const override;
64 
65   std::pair<const Value *, unsigned>
66   getPredicatedAddrSpace(const Value *V) const override;
67 
68   unsigned getAddressSpaceForPseudoSourceKind(unsigned Kind) const override;
69 };
70 
71 //===----------------------------------------------------------------------===//
72 // GCN Target Machine (SI+)
73 //===----------------------------------------------------------------------===//
74 
75 class GCNTargetMachine final : public AMDGPUTargetMachine {
76 private:
77   mutable StringMap<std::unique_ptr<GCNSubtarget>> SubtargetMap;
78 
79 public:
80   GCNTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
81                    StringRef FS, TargetOptions Options,
82                    std::optional<Reloc::Model> RM,
83                    std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
84                    bool JIT);
85 
86   TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
87 
88   const TargetSubtargetInfo *getSubtargetImpl(const Function &) const override;
89 
90   TargetTransformInfo getTargetTransformInfo(const Function &F) const override;
91 
92   bool useIPRA() const override {
93     return true;
94   }
95 
96   void registerMachineRegisterInfoCallback(MachineFunction &MF) const override;
97 
98   MachineFunctionInfo *
99   createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
100                             const TargetSubtargetInfo *STI) const override;
101 
102   yaml::MachineFunctionInfo *createDefaultFuncInfoYAML() const override;
103   yaml::MachineFunctionInfo *
104   convertFuncInfoToYAML(const MachineFunction &MF) const override;
105   bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &,
106                                 PerFunctionMIParsingState &PFS,
107                                 SMDiagnostic &Error,
108                                 SMRange &SourceRange) const override;
109 };
110 
111 //===----------------------------------------------------------------------===//
112 // AMDGPU Pass Setup
113 //===----------------------------------------------------------------------===//
114 
115 class AMDGPUPassConfig : public TargetPassConfig {
116 public:
117   AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM);
118 
119   AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
120     return getTM<AMDGPUTargetMachine>();
121   }
122 
123   ScheduleDAGInstrs *
124   createMachineScheduler(MachineSchedContext *C) const override;
125 
126   void addEarlyCSEOrGVNPass();
127   void addStraightLineScalarOptimizationPasses();
128   void addIRPasses() override;
129   void addCodeGenPrepare() override;
130   bool addPreISel() override;
131   bool addInstSelector() override;
132   bool addGCPasses() override;
133 
134   std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
135 
136   /// Check if a pass is enabled given \p Opt option. The option always
137   /// overrides defaults if explicitly used. Otherwise its default will
138   /// be used given that a pass shall work at an optimization \p Level
139   /// minimum.
140   bool isPassEnabled(const cl::opt<bool> &Opt,
141                      CodeGenOptLevel Level = CodeGenOptLevel::Default) const {
142     if (Opt.getNumOccurrences())
143       return Opt;
144     if (TM->getOptLevel() < Level)
145       return false;
146     return Opt;
147   }
148 };
149 
150 } // end namespace llvm
151 
152 #endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETMACHINE_H
153