1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 //===----------------------------------------------------------------------===// 10 // 11 /// \file 12 /// 13 /// This file contains definition for AMDGPU ISA disassembler 14 // 15 //===----------------------------------------------------------------------===// 16 17 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)? 18 19 #include "Disassembler/AMDGPUDisassembler.h" 20 #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 21 #include "SIDefines.h" 22 #include "SIRegisterInfo.h" 23 #include "TargetInfo/AMDGPUTargetInfo.h" 24 #include "Utils/AMDGPUBaseInfo.h" 25 #include "llvm-c/DisassemblerTypes.h" 26 #include "llvm/BinaryFormat/ELF.h" 27 #include "llvm/MC/MCAsmInfo.h" 28 #include "llvm/MC/MCContext.h" 29 #include "llvm/MC/MCDecoderOps.h" 30 #include "llvm/MC/MCExpr.h" 31 #include "llvm/MC/MCInstrDesc.h" 32 #include "llvm/MC/MCRegisterInfo.h" 33 #include "llvm/MC/MCSubtargetInfo.h" 34 #include "llvm/MC/TargetRegistry.h" 35 #include "llvm/Support/AMDHSAKernelDescriptor.h" 36 37 using namespace llvm; 38 39 #define DEBUG_TYPE "amdgpu-disassembler" 40 41 #define SGPR_MAX \ 42 (isGFX10Plus() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \ 43 : AMDGPU::EncValues::SGPR_MAX_SI) 44 45 using DecodeStatus = llvm::MCDisassembler::DecodeStatus; 46 47 AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI, 48 MCContext &Ctx, 49 MCInstrInfo const *MCII) : 50 MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()), 51 TargetMaxInstBytes(Ctx.getAsmInfo()->getMaxInstLength(&STI)) { 52 53 // ToDo: AMDGPUDisassembler supports only VI ISA. 54 if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding] && !isGFX10Plus()) 55 report_fatal_error("Disassembly not yet supported for subtarget"); 56 } 57 58 inline static MCDisassembler::DecodeStatus 59 addOperand(MCInst &Inst, const MCOperand& Opnd) { 60 Inst.addOperand(Opnd); 61 return Opnd.isValid() ? 62 MCDisassembler::Success : 63 MCDisassembler::Fail; 64 } 65 66 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, 67 uint16_t NameIdx) { 68 int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx); 69 if (OpIdx != -1) { 70 auto I = MI.begin(); 71 std::advance(I, OpIdx); 72 MI.insert(I, Op); 73 } 74 return OpIdx; 75 } 76 77 static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm, 78 uint64_t Addr, 79 const MCDisassembler *Decoder) { 80 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 81 82 // Our branches take a simm16, but we need two extra bits to account for the 83 // factor of 4. 84 APInt SignedOffset(18, Imm * 4, true); 85 int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue(); 86 87 if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2, 0)) 88 return MCDisassembler::Success; 89 return addOperand(Inst, MCOperand::createImm(Imm)); 90 } 91 92 static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, uint64_t Addr, 93 const MCDisassembler *Decoder) { 94 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 95 int64_t Offset; 96 if (DAsm->isVI()) { // VI supports 20-bit unsigned offsets. 97 Offset = Imm & 0xFFFFF; 98 } else { // GFX9+ supports 21-bit signed offsets. 99 Offset = SignExtend64<21>(Imm); 100 } 101 return addOperand(Inst, MCOperand::createImm(Offset)); 102 } 103 104 static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, uint64_t Addr, 105 const MCDisassembler *Decoder) { 106 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 107 return addOperand(Inst, DAsm->decodeBoolReg(Val)); 108 } 109 110 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \ 111 static DecodeStatus StaticDecoderName(MCInst &Inst, unsigned Imm, \ 112 uint64_t /*Addr*/, \ 113 const MCDisassembler *Decoder) { \ 114 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 115 return addOperand(Inst, DAsm->DecoderName(Imm)); \ 116 } 117 118 #define DECODE_OPERAND_REG(RegClass) \ 119 DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass) 120 121 DECODE_OPERAND_REG(VGPR_32) 122 DECODE_OPERAND_REG(VRegOrLds_32) 123 DECODE_OPERAND_REG(VS_32) 124 DECODE_OPERAND_REG(VS_64) 125 DECODE_OPERAND_REG(VS_128) 126 127 DECODE_OPERAND_REG(VReg_64) 128 DECODE_OPERAND_REG(VReg_96) 129 DECODE_OPERAND_REG(VReg_128) 130 DECODE_OPERAND_REG(VReg_256) 131 DECODE_OPERAND_REG(VReg_512) 132 DECODE_OPERAND_REG(VReg_1024) 133 134 DECODE_OPERAND_REG(SReg_32) 135 DECODE_OPERAND_REG(SReg_32_XM0_XEXEC) 136 DECODE_OPERAND_REG(SReg_32_XEXEC_HI) 137 DECODE_OPERAND_REG(SRegOrLds_32) 138 DECODE_OPERAND_REG(SReg_64) 139 DECODE_OPERAND_REG(SReg_64_XEXEC) 140 DECODE_OPERAND_REG(SReg_128) 141 DECODE_OPERAND_REG(SReg_256) 142 DECODE_OPERAND_REG(SReg_512) 143 144 DECODE_OPERAND_REG(AGPR_32) 145 DECODE_OPERAND_REG(AReg_64) 146 DECODE_OPERAND_REG(AReg_128) 147 DECODE_OPERAND_REG(AReg_256) 148 DECODE_OPERAND_REG(AReg_512) 149 DECODE_OPERAND_REG(AReg_1024) 150 DECODE_OPERAND_REG(AV_32) 151 DECODE_OPERAND_REG(AV_64) 152 DECODE_OPERAND_REG(AV_128) 153 DECODE_OPERAND_REG(AVDst_128) 154 DECODE_OPERAND_REG(AVDst_512) 155 156 static DecodeStatus decodeOperand_VSrc16(MCInst &Inst, unsigned Imm, 157 uint64_t Addr, 158 const MCDisassembler *Decoder) { 159 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 160 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); 161 } 162 163 static DecodeStatus decodeOperand_VSrcV216(MCInst &Inst, unsigned Imm, 164 uint64_t Addr, 165 const MCDisassembler *Decoder) { 166 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 167 return addOperand(Inst, DAsm->decodeOperand_VSrcV216(Imm)); 168 } 169 170 static DecodeStatus decodeOperand_VSrcV232(MCInst &Inst, unsigned Imm, 171 uint64_t Addr, 172 const MCDisassembler *Decoder) { 173 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 174 return addOperand(Inst, DAsm->decodeOperand_VSrcV232(Imm)); 175 } 176 177 static DecodeStatus decodeOperand_VS_16(MCInst &Inst, unsigned Imm, 178 uint64_t Addr, 179 const MCDisassembler *Decoder) { 180 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 181 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); 182 } 183 184 static DecodeStatus decodeOperand_VS_32(MCInst &Inst, unsigned Imm, 185 uint64_t Addr, 186 const MCDisassembler *Decoder) { 187 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 188 return addOperand(Inst, DAsm->decodeOperand_VS_32(Imm)); 189 } 190 191 static DecodeStatus decodeOperand_AReg_64(MCInst &Inst, unsigned Imm, 192 uint64_t Addr, 193 const MCDisassembler *Decoder) { 194 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 195 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm | 512)); 196 } 197 198 static DecodeStatus decodeOperand_AReg_128(MCInst &Inst, unsigned Imm, 199 uint64_t Addr, 200 const MCDisassembler *Decoder) { 201 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 202 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm | 512)); 203 } 204 205 static DecodeStatus decodeOperand_AReg_256(MCInst &Inst, unsigned Imm, 206 uint64_t Addr, 207 const MCDisassembler *Decoder) { 208 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 209 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW256, Imm | 512)); 210 } 211 212 static DecodeStatus decodeOperand_AReg_512(MCInst &Inst, unsigned Imm, 213 uint64_t Addr, 214 const MCDisassembler *Decoder) { 215 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 216 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm | 512)); 217 } 218 219 static DecodeStatus decodeOperand_AReg_1024(MCInst &Inst, unsigned Imm, 220 uint64_t Addr, 221 const MCDisassembler *Decoder) { 222 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 223 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm | 512)); 224 } 225 226 static DecodeStatus decodeOperand_VReg_64(MCInst &Inst, unsigned Imm, 227 uint64_t Addr, 228 const MCDisassembler *Decoder) { 229 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 230 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm)); 231 } 232 233 static DecodeStatus decodeOperand_VReg_128(MCInst &Inst, unsigned Imm, 234 uint64_t Addr, 235 const MCDisassembler *Decoder) { 236 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 237 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm)); 238 } 239 240 static DecodeStatus decodeOperand_VReg_256(MCInst &Inst, unsigned Imm, 241 uint64_t Addr, 242 const MCDisassembler *Decoder) { 243 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 244 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW256, Imm)); 245 } 246 247 static DecodeStatus decodeOperand_VReg_512(MCInst &Inst, unsigned Imm, 248 uint64_t Addr, 249 const MCDisassembler *Decoder) { 250 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 251 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm)); 252 } 253 254 static DecodeStatus decodeOperand_VReg_1024(MCInst &Inst, unsigned Imm, 255 uint64_t Addr, 256 const MCDisassembler *Decoder) { 257 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 258 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm)); 259 } 260 261 static DecodeStatus decodeOperand_f32kimm(MCInst &Inst, unsigned Imm, 262 uint64_t Addr, 263 const MCDisassembler *Decoder) { 264 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 265 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm)); 266 } 267 268 static DecodeStatus decodeOperand_f16kimm(MCInst &Inst, unsigned Imm, 269 uint64_t Addr, 270 const MCDisassembler *Decoder) { 271 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 272 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm)); 273 } 274 275 static DecodeStatus 276 decodeOperand_VS_16_Deferred(MCInst &Inst, unsigned Imm, uint64_t Addr, 277 const MCDisassembler *Decoder) { 278 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 279 return addOperand( 280 Inst, DAsm->decodeSrcOp(llvm::AMDGPUDisassembler::OPW16, Imm, true)); 281 } 282 283 static DecodeStatus 284 decodeOperand_VS_32_Deferred(MCInst &Inst, unsigned Imm, uint64_t Addr, 285 const MCDisassembler *Decoder) { 286 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 287 return addOperand( 288 Inst, DAsm->decodeSrcOp(llvm::AMDGPUDisassembler::OPW32, Imm, true)); 289 } 290 291 static DecodeStatus decodeOperandVOPDDstY(MCInst &Inst, unsigned Val, 292 uint64_t Addr, const void *Decoder) { 293 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 294 return addOperand(Inst, DAsm->decodeVOPDDstYOp(Inst, Val)); 295 } 296 297 static bool IsAGPROperand(const MCInst &Inst, int OpIdx, 298 const MCRegisterInfo *MRI) { 299 if (OpIdx < 0) 300 return false; 301 302 const MCOperand &Op = Inst.getOperand(OpIdx); 303 if (!Op.isReg()) 304 return false; 305 306 unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0); 307 auto Reg = Sub ? Sub : Op.getReg(); 308 return Reg >= AMDGPU::AGPR0 && Reg <= AMDGPU::AGPR255; 309 } 310 311 static DecodeStatus decodeOperand_AVLdSt_Any(MCInst &Inst, unsigned Imm, 312 AMDGPUDisassembler::OpWidthTy Opw, 313 const MCDisassembler *Decoder) { 314 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 315 if (!DAsm->isGFX90A()) { 316 Imm &= 511; 317 } else { 318 // If atomic has both vdata and vdst their register classes are tied. 319 // The bit is decoded along with the vdst, first operand. We need to 320 // change register class to AGPR if vdst was AGPR. 321 // If a DS instruction has both data0 and data1 their register classes 322 // are also tied. 323 unsigned Opc = Inst.getOpcode(); 324 uint64_t TSFlags = DAsm->getMCII()->get(Opc).TSFlags; 325 uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0 326 : AMDGPU::OpName::vdata; 327 const MCRegisterInfo *MRI = DAsm->getContext().getRegisterInfo(); 328 int DataIdx = AMDGPU::getNamedOperandIdx(Opc, DataNameIdx); 329 if ((int)Inst.getNumOperands() == DataIdx) { 330 int DstIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst); 331 if (IsAGPROperand(Inst, DstIdx, MRI)) 332 Imm |= 512; 333 } 334 335 if (TSFlags & SIInstrFlags::DS) { 336 int Data2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data1); 337 if ((int)Inst.getNumOperands() == Data2Idx && 338 IsAGPROperand(Inst, DataIdx, MRI)) 339 Imm |= 512; 340 } 341 } 342 return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256)); 343 } 344 345 static DecodeStatus 346 DecodeAVLdSt_32RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 347 const MCDisassembler *Decoder) { 348 return decodeOperand_AVLdSt_Any(Inst, Imm, 349 AMDGPUDisassembler::OPW32, Decoder); 350 } 351 352 static DecodeStatus 353 DecodeAVLdSt_64RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 354 const MCDisassembler *Decoder) { 355 return decodeOperand_AVLdSt_Any(Inst, Imm, 356 AMDGPUDisassembler::OPW64, Decoder); 357 } 358 359 static DecodeStatus 360 DecodeAVLdSt_96RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 361 const MCDisassembler *Decoder) { 362 return decodeOperand_AVLdSt_Any(Inst, Imm, 363 AMDGPUDisassembler::OPW96, Decoder); 364 } 365 366 static DecodeStatus 367 DecodeAVLdSt_128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 368 const MCDisassembler *Decoder) { 369 return decodeOperand_AVLdSt_Any(Inst, Imm, 370 AMDGPUDisassembler::OPW128, Decoder); 371 } 372 373 static DecodeStatus decodeOperand_SReg_32(MCInst &Inst, unsigned Imm, 374 uint64_t Addr, 375 const MCDisassembler *Decoder) { 376 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 377 return addOperand(Inst, DAsm->decodeOperand_SReg_32(Imm)); 378 } 379 380 #define DECODE_SDWA(DecName) \ 381 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName) 382 383 DECODE_SDWA(Src32) 384 DECODE_SDWA(Src16) 385 DECODE_SDWA(VopcDst) 386 387 #include "AMDGPUGenDisassemblerTables.inc" 388 389 //===----------------------------------------------------------------------===// 390 // 391 //===----------------------------------------------------------------------===// 392 393 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) { 394 assert(Bytes.size() >= sizeof(T)); 395 const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data()); 396 Bytes = Bytes.slice(sizeof(T)); 397 return Res; 398 } 399 400 static inline DecoderUInt128 eat12Bytes(ArrayRef<uint8_t> &Bytes) { 401 assert(Bytes.size() >= 12); 402 uint64_t Lo = support::endian::read<uint64_t, support::endianness::little>( 403 Bytes.data()); 404 Bytes = Bytes.slice(8); 405 uint64_t Hi = support::endian::read<uint32_t, support::endianness::little>( 406 Bytes.data()); 407 Bytes = Bytes.slice(4); 408 return DecoderUInt128(Lo, Hi); 409 } 410 411 // The disassembler is greedy, so we need to check FI operand value to 412 // not parse a dpp if the correct literal is not set. For dpp16 the 413 // autogenerated decoder checks the dpp literal 414 static bool isValidDPP8(const MCInst &MI) { 415 using namespace llvm::AMDGPU::DPP; 416 int FiIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::fi); 417 assert(FiIdx != -1); 418 if ((unsigned)FiIdx >= MI.getNumOperands()) 419 return false; 420 unsigned Fi = MI.getOperand(FiIdx).getImm(); 421 return Fi == DPP8_FI_0 || Fi == DPP8_FI_1; 422 } 423 424 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 425 ArrayRef<uint8_t> Bytes_, 426 uint64_t Address, 427 raw_ostream &CS) const { 428 CommentStream = &CS; 429 bool IsSDWA = false; 430 431 unsigned MaxInstBytesNum = std::min((size_t)TargetMaxInstBytes, Bytes_.size()); 432 Bytes = Bytes_.slice(0, MaxInstBytesNum); 433 434 DecodeStatus Res = MCDisassembler::Fail; 435 do { 436 // ToDo: better to switch encoding length using some bit predicate 437 // but it is unknown yet, so try all we can 438 439 // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2 440 // encodings 441 if (isGFX11Plus() && Bytes.size() >= 12 ) { 442 DecoderUInt128 DecW = eat12Bytes(Bytes); 443 Res = tryDecodeInst(DecoderTableDPP8GFX1196, MI, DecW, 444 Address); 445 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 446 break; 447 MI = MCInst(); // clear 448 Res = tryDecodeInst(DecoderTableDPPGFX1196, MI, DecW, 449 Address); 450 if (Res) { 451 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3P) 452 convertVOP3PDPPInst(MI); 453 else if (AMDGPU::isVOPC64DPP(MI.getOpcode())) 454 convertVOPCDPPInst(MI); // Special VOP3 case 455 else { 456 assert(MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3); 457 convertVOP3DPPInst(MI); // Regular VOP3 case 458 } 459 break; 460 } 461 Res = tryDecodeInst(DecoderTableGFX1196, MI, DecW, Address); 462 if (Res) 463 break; 464 } 465 // Reinitialize Bytes 466 Bytes = Bytes_.slice(0, MaxInstBytesNum); 467 468 if (Bytes.size() >= 8) { 469 const uint64_t QW = eatBytes<uint64_t>(Bytes); 470 471 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) { 472 Res = tryDecodeInst(DecoderTableGFX10_B64, MI, QW, Address); 473 if (Res) { 474 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dpp8) 475 == -1) 476 break; 477 if (convertDPP8Inst(MI) == MCDisassembler::Success) 478 break; 479 MI = MCInst(); // clear 480 } 481 } 482 483 Res = tryDecodeInst(DecoderTableDPP864, MI, QW, Address); 484 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 485 break; 486 MI = MCInst(); // clear 487 488 Res = tryDecodeInst(DecoderTableDPP8GFX1164, MI, QW, Address); 489 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 490 break; 491 MI = MCInst(); // clear 492 493 Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address); 494 if (Res) break; 495 496 Res = tryDecodeInst(DecoderTableDPPGFX1164, MI, QW, Address); 497 if (Res) { 498 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOPC) 499 convertVOPCDPPInst(MI); 500 break; 501 } 502 503 Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address); 504 if (Res) { IsSDWA = true; break; } 505 506 Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address); 507 if (Res) { IsSDWA = true; break; } 508 509 Res = tryDecodeInst(DecoderTableSDWA1064, MI, QW, Address); 510 if (Res) { IsSDWA = true; break; } 511 512 if (STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem]) { 513 Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address); 514 if (Res) 515 break; 516 } 517 518 // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and 519 // v_mad_mixhi_f16 for FMA variants. Try to decode using this special 520 // table first so we print the correct name. 521 if (STI.getFeatureBits()[AMDGPU::FeatureFmaMixInsts]) { 522 Res = tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address); 523 if (Res) 524 break; 525 } 526 } 527 528 // Reinitialize Bytes as DPP64 could have eaten too much 529 Bytes = Bytes_.slice(0, MaxInstBytesNum); 530 531 // Try decode 32-bit instruction 532 if (Bytes.size() < 4) break; 533 const uint32_t DW = eatBytes<uint32_t>(Bytes); 534 Res = tryDecodeInst(DecoderTableGFX832, MI, DW, Address); 535 if (Res) break; 536 537 Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address); 538 if (Res) break; 539 540 Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address); 541 if (Res) break; 542 543 if (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]) { 544 Res = tryDecodeInst(DecoderTableGFX90A32, MI, DW, Address); 545 if (Res) 546 break; 547 } 548 549 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) { 550 Res = tryDecodeInst(DecoderTableGFX10_B32, MI, DW, Address); 551 if (Res) break; 552 } 553 554 Res = tryDecodeInst(DecoderTableGFX1032, MI, DW, Address); 555 if (Res) break; 556 557 Res = tryDecodeInst(DecoderTableGFX1132, MI, DW, Address); 558 if (Res) break; 559 560 if (Bytes.size() < 4) break; 561 const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW; 562 563 if (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]) { 564 Res = tryDecodeInst(DecoderTableGFX90A64, MI, QW, Address); 565 if (Res) 566 break; 567 } 568 569 Res = tryDecodeInst(DecoderTableGFX864, MI, QW, Address); 570 if (Res) break; 571 572 Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address); 573 if (Res) break; 574 575 Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address); 576 if (Res) break; 577 578 Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address); 579 if (Res) break; 580 581 Res = tryDecodeInst(DecoderTableGFX1164, MI, QW, Address); 582 if (Res) 583 break; 584 585 Res = tryDecodeInst(DecoderTableWMMAGFX1164, MI, QW, Address); 586 } while (false); 587 588 if (Res && (MI.getOpcode() == AMDGPU::V_MAC_F32_e64_vi || 589 MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx6_gfx7 || 590 MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx10 || 591 MI.getOpcode() == AMDGPU::V_MAC_LEGACY_F32_e64_gfx6_gfx7 || 592 MI.getOpcode() == AMDGPU::V_MAC_LEGACY_F32_e64_gfx10 || 593 MI.getOpcode() == AMDGPU::V_MAC_F16_e64_vi || 594 MI.getOpcode() == AMDGPU::V_FMAC_F64_e64_gfx90a || 595 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_vi || 596 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_gfx10 || 597 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_gfx11 || 598 MI.getOpcode() == AMDGPU::V_FMAC_LEGACY_F32_e64_gfx10 || 599 MI.getOpcode() == AMDGPU::V_FMAC_DX9_ZERO_F32_e64_gfx11 || 600 MI.getOpcode() == AMDGPU::V_FMAC_F16_e64_gfx10 || 601 MI.getOpcode() == AMDGPU::V_FMAC_F16_e64_gfx11)) { 602 // Insert dummy unused src2_modifiers. 603 insertNamedMCOperand(MI, MCOperand::createImm(0), 604 AMDGPU::OpName::src2_modifiers); 605 } 606 607 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 608 (SIInstrFlags::MUBUF | SIInstrFlags::FLAT | SIInstrFlags::SMRD))) { 609 int CPolPos = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 610 AMDGPU::OpName::cpol); 611 if (CPolPos != -1) { 612 unsigned CPol = 613 (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::IsAtomicRet) ? 614 AMDGPU::CPol::GLC : 0; 615 if (MI.getNumOperands() <= (unsigned)CPolPos) { 616 insertNamedMCOperand(MI, MCOperand::createImm(CPol), 617 AMDGPU::OpName::cpol); 618 } else if (CPol) { 619 MI.getOperand(CPolPos).setImm(MI.getOperand(CPolPos).getImm() | CPol); 620 } 621 } 622 } 623 624 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 625 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF)) && 626 (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts])) { 627 // GFX90A lost TFE, its place is occupied by ACC. 628 int TFEOpIdx = 629 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::tfe); 630 if (TFEOpIdx != -1) { 631 auto TFEIter = MI.begin(); 632 std::advance(TFEIter, TFEOpIdx); 633 MI.insert(TFEIter, MCOperand::createImm(0)); 634 } 635 } 636 637 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 638 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF))) { 639 int SWZOpIdx = 640 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::swz); 641 if (SWZOpIdx != -1) { 642 auto SWZIter = MI.begin(); 643 std::advance(SWZIter, SWZOpIdx); 644 MI.insert(SWZIter, MCOperand::createImm(0)); 645 } 646 } 647 648 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) { 649 int VAddr0Idx = 650 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 651 int RsrcIdx = 652 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc); 653 unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1; 654 if (VAddr0Idx >= 0 && NSAArgs > 0) { 655 unsigned NSAWords = (NSAArgs + 3) / 4; 656 if (Bytes.size() < 4 * NSAWords) { 657 Res = MCDisassembler::Fail; 658 } else { 659 for (unsigned i = 0; i < NSAArgs; ++i) { 660 const unsigned VAddrIdx = VAddr0Idx + 1 + i; 661 auto VAddrRCID = MCII->get(MI.getOpcode()).OpInfo[VAddrIdx].RegClass; 662 MI.insert(MI.begin() + VAddrIdx, 663 createRegOperand(VAddrRCID, Bytes[i])); 664 } 665 Bytes = Bytes.slice(4 * NSAWords); 666 } 667 } 668 669 if (Res) 670 Res = convertMIMGInst(MI); 671 } 672 673 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::EXP)) 674 Res = convertEXPInst(MI); 675 676 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VINTERP)) 677 Res = convertVINTERPInst(MI); 678 679 if (Res && IsSDWA) 680 Res = convertSDWAInst(MI); 681 682 int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 683 AMDGPU::OpName::vdst_in); 684 if (VDstIn_Idx != -1) { 685 int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx, 686 MCOI::OperandConstraint::TIED_TO); 687 if (Tied != -1 && (MI.getNumOperands() <= (unsigned)VDstIn_Idx || 688 !MI.getOperand(VDstIn_Idx).isReg() || 689 MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) { 690 if (MI.getNumOperands() > (unsigned)VDstIn_Idx) 691 MI.erase(&MI.getOperand(VDstIn_Idx)); 692 insertNamedMCOperand(MI, 693 MCOperand::createReg(MI.getOperand(Tied).getReg()), 694 AMDGPU::OpName::vdst_in); 695 } 696 } 697 698 int ImmLitIdx = 699 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::imm); 700 if (Res && ImmLitIdx != -1) 701 Res = convertFMAanyK(MI, ImmLitIdx); 702 703 // if the opcode was not recognized we'll assume a Size of 4 bytes 704 // (unless there are fewer bytes left) 705 Size = Res ? (MaxInstBytesNum - Bytes.size()) 706 : std::min((size_t)4, Bytes_.size()); 707 return Res; 708 } 709 710 DecodeStatus AMDGPUDisassembler::convertEXPInst(MCInst &MI) const { 711 if (STI.getFeatureBits()[AMDGPU::FeatureGFX11]) { 712 // The MCInst still has these fields even though they are no longer encoded 713 // in the GFX11 instruction. 714 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vm); 715 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::compr); 716 } 717 return MCDisassembler::Success; 718 } 719 720 DecodeStatus AMDGPUDisassembler::convertVINTERPInst(MCInst &MI) const { 721 if (MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_gfx11 || 722 MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_gfx11 || 723 MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_gfx11 || 724 MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_gfx11) { 725 // The MCInst has this field that is not directly encoded in the 726 // instruction. 727 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::op_sel); 728 } 729 return MCDisassembler::Success; 730 } 731 732 DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const { 733 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 734 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 735 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst) != -1) 736 // VOPC - insert clamp 737 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp); 738 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 739 int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst); 740 if (SDst != -1) { 741 // VOPC - insert VCC register as sdst 742 insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC), 743 AMDGPU::OpName::sdst); 744 } else { 745 // VOP1/2 - insert omod if present in instruction 746 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod); 747 } 748 } 749 return MCDisassembler::Success; 750 } 751 752 struct VOPModifiers { 753 unsigned OpSel = 0; 754 unsigned OpSelHi = 0; 755 unsigned NegLo = 0; 756 unsigned NegHi = 0; 757 }; 758 759 // Reconstruct values of VOP3/VOP3P operands such as op_sel. 760 // Note that these values do not affect disassembler output, 761 // so this is only necessary for consistency with src_modifiers. 762 static VOPModifiers collectVOPModifiers(const MCInst &MI, 763 bool IsVOP3P = false) { 764 VOPModifiers Modifiers; 765 unsigned Opc = MI.getOpcode(); 766 const int ModOps[] = {AMDGPU::OpName::src0_modifiers, 767 AMDGPU::OpName::src1_modifiers, 768 AMDGPU::OpName::src2_modifiers}; 769 for (int J = 0; J < 3; ++J) { 770 int OpIdx = AMDGPU::getNamedOperandIdx(Opc, ModOps[J]); 771 if (OpIdx == -1) 772 continue; 773 774 unsigned Val = MI.getOperand(OpIdx).getImm(); 775 776 Modifiers.OpSel |= !!(Val & SISrcMods::OP_SEL_0) << J; 777 if (IsVOP3P) { 778 Modifiers.OpSelHi |= !!(Val & SISrcMods::OP_SEL_1) << J; 779 Modifiers.NegLo |= !!(Val & SISrcMods::NEG) << J; 780 Modifiers.NegHi |= !!(Val & SISrcMods::NEG_HI) << J; 781 } else if (J == 0) { 782 Modifiers.OpSel |= !!(Val & SISrcMods::DST_OP_SEL) << 3; 783 } 784 } 785 786 return Modifiers; 787 } 788 789 // We must check FI == literal to reject not genuine dpp8 insts, and we must 790 // first add optional MI operands to check FI 791 DecodeStatus AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const { 792 unsigned Opc = MI.getOpcode(); 793 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 794 if (MCII->get(Opc).TSFlags & SIInstrFlags::VOP3P) { 795 convertVOP3PDPPInst(MI); 796 } else if ((MCII->get(Opc).TSFlags & SIInstrFlags::VOPC) || 797 AMDGPU::isVOPC64DPP(Opc)) { 798 convertVOPCDPPInst(MI); 799 } else if (MI.getNumOperands() < DescNumOps && 800 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel) != -1) { 801 auto Mods = collectVOPModifiers(MI); 802 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 803 AMDGPU::OpName::op_sel); 804 } else { 805 // Insert dummy unused src modifiers. 806 if (MI.getNumOperands() < DescNumOps && 807 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1) 808 insertNamedMCOperand(MI, MCOperand::createImm(0), 809 AMDGPU::OpName::src0_modifiers); 810 811 if (MI.getNumOperands() < DescNumOps && 812 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers) != -1) 813 insertNamedMCOperand(MI, MCOperand::createImm(0), 814 AMDGPU::OpName::src1_modifiers); 815 } 816 return isValidDPP8(MI) ? MCDisassembler::Success : MCDisassembler::SoftFail; 817 } 818 819 DecodeStatus AMDGPUDisassembler::convertVOP3DPPInst(MCInst &MI) const { 820 unsigned Opc = MI.getOpcode(); 821 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 822 if (MI.getNumOperands() < DescNumOps && 823 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel) != -1) { 824 auto Mods = collectVOPModifiers(MI); 825 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 826 AMDGPU::OpName::op_sel); 827 } 828 return MCDisassembler::Success; 829 } 830 831 // Note that before gfx10, the MIMG encoding provided no information about 832 // VADDR size. Consequently, decoded instructions always show address as if it 833 // has 1 dword, which could be not really so. 834 DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const { 835 836 int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 837 AMDGPU::OpName::vdst); 838 839 int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 840 AMDGPU::OpName::vdata); 841 int VAddr0Idx = 842 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 843 int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 844 AMDGPU::OpName::dmask); 845 846 int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 847 AMDGPU::OpName::tfe); 848 int D16Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 849 AMDGPU::OpName::d16); 850 851 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode()); 852 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = 853 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode); 854 855 assert(VDataIdx != -1); 856 if (BaseOpcode->BVH) { 857 // Add A16 operand for intersect_ray instructions 858 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16) > -1) { 859 addOperand(MI, MCOperand::createImm(1)); 860 } 861 return MCDisassembler::Success; 862 } 863 864 bool IsAtomic = (VDstIdx != -1); 865 bool IsGather4 = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::Gather4; 866 bool IsNSA = false; 867 unsigned AddrSize = Info->VAddrDwords; 868 869 if (isGFX10Plus()) { 870 unsigned DimIdx = 871 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim); 872 int A16Idx = 873 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16); 874 const AMDGPU::MIMGDimInfo *Dim = 875 AMDGPU::getMIMGDimInfoByEncoding(MI.getOperand(DimIdx).getImm()); 876 const bool IsA16 = (A16Idx != -1 && MI.getOperand(A16Idx).getImm()); 877 878 AddrSize = 879 AMDGPU::getAddrSizeMIMGOp(BaseOpcode, Dim, IsA16, AMDGPU::hasG16(STI)); 880 881 IsNSA = Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA || 882 Info->MIMGEncoding == AMDGPU::MIMGEncGfx11NSA; 883 if (!IsNSA) { 884 if (AddrSize > 8) 885 AddrSize = 16; 886 } else { 887 if (AddrSize > Info->VAddrDwords) { 888 // The NSA encoding does not contain enough operands for the combination 889 // of base opcode / dimension. Should this be an error? 890 return MCDisassembler::Success; 891 } 892 } 893 } 894 895 unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf; 896 unsigned DstSize = IsGather4 ? 4 : std::max(countPopulation(DMask), 1u); 897 898 bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm(); 899 if (D16 && AMDGPU::hasPackedD16(STI)) { 900 DstSize = (DstSize + 1) / 2; 901 } 902 903 if (TFEIdx != -1 && MI.getOperand(TFEIdx).getImm()) 904 DstSize += 1; 905 906 if (DstSize == Info->VDataDwords && AddrSize == Info->VAddrDwords) 907 return MCDisassembler::Success; 908 909 int NewOpcode = 910 AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize); 911 if (NewOpcode == -1) 912 return MCDisassembler::Success; 913 914 // Widen the register to the correct number of enabled channels. 915 unsigned NewVdata = AMDGPU::NoRegister; 916 if (DstSize != Info->VDataDwords) { 917 auto DataRCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass; 918 919 // Get first subregister of VData 920 unsigned Vdata0 = MI.getOperand(VDataIdx).getReg(); 921 unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0); 922 Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0; 923 924 NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0, 925 &MRI.getRegClass(DataRCID)); 926 if (NewVdata == AMDGPU::NoRegister) { 927 // It's possible to encode this such that the low register + enabled 928 // components exceeds the register count. 929 return MCDisassembler::Success; 930 } 931 } 932 933 // If not using NSA on GFX10+, widen address register to correct size. 934 unsigned NewVAddr0 = AMDGPU::NoRegister; 935 if (isGFX10Plus() && !IsNSA && AddrSize != Info->VAddrDwords) { 936 unsigned VAddr0 = MI.getOperand(VAddr0Idx).getReg(); 937 unsigned VAddrSub0 = MRI.getSubReg(VAddr0, AMDGPU::sub0); 938 VAddr0 = (VAddrSub0 != 0) ? VAddrSub0 : VAddr0; 939 940 auto AddrRCID = MCII->get(NewOpcode).OpInfo[VAddr0Idx].RegClass; 941 NewVAddr0 = MRI.getMatchingSuperReg(VAddr0, AMDGPU::sub0, 942 &MRI.getRegClass(AddrRCID)); 943 if (NewVAddr0 == AMDGPU::NoRegister) 944 return MCDisassembler::Success; 945 } 946 947 MI.setOpcode(NewOpcode); 948 949 if (NewVdata != AMDGPU::NoRegister) { 950 MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata); 951 952 if (IsAtomic) { 953 // Atomic operations have an additional operand (a copy of data) 954 MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata); 955 } 956 } 957 958 if (NewVAddr0 != AMDGPU::NoRegister) { 959 MI.getOperand(VAddr0Idx) = MCOperand::createReg(NewVAddr0); 960 } else if (IsNSA) { 961 assert(AddrSize <= Info->VAddrDwords); 962 MI.erase(MI.begin() + VAddr0Idx + AddrSize, 963 MI.begin() + VAddr0Idx + Info->VAddrDwords); 964 } 965 966 return MCDisassembler::Success; 967 } 968 969 // Opsel and neg bits are used in src_modifiers and standalone operands. Autogen 970 // decoder only adds to src_modifiers, so manually add the bits to the other 971 // operands. 972 DecodeStatus AMDGPUDisassembler::convertVOP3PDPPInst(MCInst &MI) const { 973 unsigned Opc = MI.getOpcode(); 974 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 975 auto Mods = collectVOPModifiers(MI, true); 976 977 if (MI.getNumOperands() < DescNumOps && 978 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst_in) != -1) 979 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vdst_in); 980 981 if (MI.getNumOperands() < DescNumOps && 982 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel) != -1) 983 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 984 AMDGPU::OpName::op_sel); 985 if (MI.getNumOperands() < DescNumOps && 986 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel_hi) != -1) 987 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSelHi), 988 AMDGPU::OpName::op_sel_hi); 989 if (MI.getNumOperands() < DescNumOps && 990 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::neg_lo) != -1) 991 insertNamedMCOperand(MI, MCOperand::createImm(Mods.NegLo), 992 AMDGPU::OpName::neg_lo); 993 if (MI.getNumOperands() < DescNumOps && 994 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::neg_hi) != -1) 995 insertNamedMCOperand(MI, MCOperand::createImm(Mods.NegHi), 996 AMDGPU::OpName::neg_hi); 997 998 return MCDisassembler::Success; 999 } 1000 1001 // Create dummy old operand and insert optional operands 1002 DecodeStatus AMDGPUDisassembler::convertVOPCDPPInst(MCInst &MI) const { 1003 unsigned Opc = MI.getOpcode(); 1004 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 1005 1006 if (MI.getNumOperands() < DescNumOps && 1007 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::old) != -1) 1008 insertNamedMCOperand(MI, MCOperand::createReg(0), AMDGPU::OpName::old); 1009 1010 if (MI.getNumOperands() < DescNumOps && 1011 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1) 1012 insertNamedMCOperand(MI, MCOperand::createImm(0), 1013 AMDGPU::OpName::src0_modifiers); 1014 1015 if (MI.getNumOperands() < DescNumOps && 1016 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers) != -1) 1017 insertNamedMCOperand(MI, MCOperand::createImm(0), 1018 AMDGPU::OpName::src1_modifiers); 1019 return MCDisassembler::Success; 1020 } 1021 1022 DecodeStatus AMDGPUDisassembler::convertFMAanyK(MCInst &MI, 1023 int ImmLitIdx) const { 1024 assert(HasLiteral && "Should have decoded a literal"); 1025 const MCInstrDesc &Desc = MCII->get(MI.getOpcode()); 1026 unsigned DescNumOps = Desc.getNumOperands(); 1027 insertNamedMCOperand(MI, MCOperand::createImm(Literal), 1028 AMDGPU::OpName::immDeferred); 1029 assert(DescNumOps == MI.getNumOperands()); 1030 for (unsigned I = 0; I < DescNumOps; ++I) { 1031 auto &Op = MI.getOperand(I); 1032 auto OpType = Desc.OpInfo[I].OperandType; 1033 bool IsDeferredOp = (OpType == AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED || 1034 OpType == AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED); 1035 if (Op.isImm() && Op.getImm() == AMDGPU::EncValues::LITERAL_CONST && 1036 IsDeferredOp) 1037 Op.setImm(Literal); 1038 } 1039 return MCDisassembler::Success; 1040 } 1041 1042 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { 1043 return getContext().getRegisterInfo()-> 1044 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); 1045 } 1046 1047 inline 1048 MCOperand AMDGPUDisassembler::errOperand(unsigned V, 1049 const Twine& ErrMsg) const { 1050 *CommentStream << "Error: " + ErrMsg; 1051 1052 // ToDo: add support for error operands to MCInst.h 1053 // return MCOperand::createError(V); 1054 return MCOperand(); 1055 } 1056 1057 inline 1058 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const { 1059 return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI)); 1060 } 1061 1062 inline 1063 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, 1064 unsigned Val) const { 1065 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; 1066 if (Val >= RegCl.getNumRegs()) 1067 return errOperand(Val, Twine(getRegClassName(RegClassID)) + 1068 ": unknown register " + Twine(Val)); 1069 return createRegOperand(RegCl.getRegister(Val)); 1070 } 1071 1072 inline 1073 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID, 1074 unsigned Val) const { 1075 // ToDo: SI/CI have 104 SGPRs, VI - 102 1076 // Valery: here we accepting as much as we can, let assembler sort it out 1077 int shift = 0; 1078 switch (SRegClassID) { 1079 case AMDGPU::SGPR_32RegClassID: 1080 case AMDGPU::TTMP_32RegClassID: 1081 break; 1082 case AMDGPU::SGPR_64RegClassID: 1083 case AMDGPU::TTMP_64RegClassID: 1084 shift = 1; 1085 break; 1086 case AMDGPU::SGPR_128RegClassID: 1087 case AMDGPU::TTMP_128RegClassID: 1088 // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in 1089 // this bundle? 1090 case AMDGPU::SGPR_256RegClassID: 1091 case AMDGPU::TTMP_256RegClassID: 1092 // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in 1093 // this bundle? 1094 case AMDGPU::SGPR_512RegClassID: 1095 case AMDGPU::TTMP_512RegClassID: 1096 shift = 2; 1097 break; 1098 // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in 1099 // this bundle? 1100 default: 1101 llvm_unreachable("unhandled register class"); 1102 } 1103 1104 if (Val % (1 << shift)) { 1105 *CommentStream << "Warning: " << getRegClassName(SRegClassID) 1106 << ": scalar reg isn't aligned " << Val; 1107 } 1108 1109 return createRegOperand(SRegClassID, Val >> shift); 1110 } 1111 1112 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const { 1113 return decodeSrcOp(OPW32, Val); 1114 } 1115 1116 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const { 1117 return decodeSrcOp(OPW64, Val); 1118 } 1119 1120 MCOperand AMDGPUDisassembler::decodeOperand_VS_128(unsigned Val) const { 1121 return decodeSrcOp(OPW128, Val); 1122 } 1123 1124 MCOperand AMDGPUDisassembler::decodeOperand_VSrc16(unsigned Val) const { 1125 return decodeSrcOp(OPW16, Val); 1126 } 1127 1128 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV216(unsigned Val) const { 1129 return decodeSrcOp(OPWV216, Val); 1130 } 1131 1132 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV232(unsigned Val) const { 1133 return decodeSrcOp(OPWV232, Val); 1134 } 1135 1136 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const { 1137 // Some instructions have operand restrictions beyond what the encoding 1138 // allows. Some ordinarily VSrc_32 operands are VGPR_32, so clear the extra 1139 // high bit. 1140 Val &= 255; 1141 1142 return createRegOperand(AMDGPU::VGPR_32RegClassID, Val); 1143 } 1144 1145 MCOperand AMDGPUDisassembler::decodeOperand_VRegOrLds_32(unsigned Val) const { 1146 return decodeSrcOp(OPW32, Val); 1147 } 1148 1149 MCOperand AMDGPUDisassembler::decodeOperand_AGPR_32(unsigned Val) const { 1150 return createRegOperand(AMDGPU::AGPR_32RegClassID, Val & 255); 1151 } 1152 1153 MCOperand AMDGPUDisassembler::decodeOperand_AReg_64(unsigned Val) const { 1154 return createRegOperand(AMDGPU::AReg_64RegClassID, Val & 255); 1155 } 1156 1157 MCOperand AMDGPUDisassembler::decodeOperand_AReg_128(unsigned Val) const { 1158 return createRegOperand(AMDGPU::AReg_128RegClassID, Val & 255); 1159 } 1160 1161 MCOperand AMDGPUDisassembler::decodeOperand_AReg_256(unsigned Val) const { 1162 return createRegOperand(AMDGPU::AReg_256RegClassID, Val & 255); 1163 } 1164 1165 MCOperand AMDGPUDisassembler::decodeOperand_AReg_512(unsigned Val) const { 1166 return createRegOperand(AMDGPU::AReg_512RegClassID, Val & 255); 1167 } 1168 1169 MCOperand AMDGPUDisassembler::decodeOperand_AReg_1024(unsigned Val) const { 1170 return createRegOperand(AMDGPU::AReg_1024RegClassID, Val & 255); 1171 } 1172 1173 MCOperand AMDGPUDisassembler::decodeOperand_AV_32(unsigned Val) const { 1174 return decodeSrcOp(OPW32, Val); 1175 } 1176 1177 MCOperand AMDGPUDisassembler::decodeOperand_AV_64(unsigned Val) const { 1178 return decodeSrcOp(OPW64, Val); 1179 } 1180 1181 MCOperand AMDGPUDisassembler::decodeOperand_AV_128(unsigned Val) const { 1182 return decodeSrcOp(OPW128, Val); 1183 } 1184 1185 MCOperand AMDGPUDisassembler::decodeOperand_AVDst_128(unsigned Val) const { 1186 using namespace AMDGPU::EncValues; 1187 assert((Val & IS_VGPR) == 0); // Val{8} is not encoded but assumed to be 1. 1188 return decodeSrcOp(OPW128, Val | IS_VGPR); 1189 } 1190 1191 MCOperand AMDGPUDisassembler::decodeOperand_AVDst_512(unsigned Val) const { 1192 using namespace AMDGPU::EncValues; 1193 assert((Val & IS_VGPR) == 0); // Val{8} is not encoded but assumed to be 1. 1194 return decodeSrcOp(OPW512, Val | IS_VGPR); 1195 } 1196 1197 MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const { 1198 return createRegOperand(AMDGPU::VReg_64RegClassID, Val); 1199 } 1200 1201 MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const { 1202 return createRegOperand(AMDGPU::VReg_96RegClassID, Val); 1203 } 1204 1205 MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const { 1206 return createRegOperand(AMDGPU::VReg_128RegClassID, Val); 1207 } 1208 1209 MCOperand AMDGPUDisassembler::decodeOperand_VReg_256(unsigned Val) const { 1210 return createRegOperand(AMDGPU::VReg_256RegClassID, Val); 1211 } 1212 1213 MCOperand AMDGPUDisassembler::decodeOperand_VReg_512(unsigned Val) const { 1214 return createRegOperand(AMDGPU::VReg_512RegClassID, Val); 1215 } 1216 1217 MCOperand AMDGPUDisassembler::decodeOperand_VReg_1024(unsigned Val) const { 1218 return createRegOperand(AMDGPU::VReg_1024RegClassID, Val); 1219 } 1220 1221 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const { 1222 // table-gen generated disassembler doesn't care about operand types 1223 // leaving only registry class so SSrc_32 operand turns into SReg_32 1224 // and therefore we accept immediates and literals here as well 1225 return decodeSrcOp(OPW32, Val); 1226 } 1227 1228 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0_XEXEC( 1229 unsigned Val) const { 1230 // SReg_32_XM0 is SReg_32 without M0 or EXEC_LO/EXEC_HI 1231 return decodeOperand_SReg_32(Val); 1232 } 1233 1234 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XEXEC_HI( 1235 unsigned Val) const { 1236 // SReg_32_XM0 is SReg_32 without EXEC_HI 1237 return decodeOperand_SReg_32(Val); 1238 } 1239 1240 MCOperand AMDGPUDisassembler::decodeOperand_SRegOrLds_32(unsigned Val) const { 1241 // table-gen generated disassembler doesn't care about operand types 1242 // leaving only registry class so SSrc_32 operand turns into SReg_32 1243 // and therefore we accept immediates and literals here as well 1244 return decodeSrcOp(OPW32, Val); 1245 } 1246 1247 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const { 1248 return decodeSrcOp(OPW64, Val); 1249 } 1250 1251 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64_XEXEC(unsigned Val) const { 1252 return decodeSrcOp(OPW64, Val); 1253 } 1254 1255 MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const { 1256 return decodeSrcOp(OPW128, Val); 1257 } 1258 1259 MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const { 1260 return decodeDstOp(OPW256, Val); 1261 } 1262 1263 MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const { 1264 return decodeDstOp(OPW512, Val); 1265 } 1266 1267 // Decode Literals for insts which always have a literal in the encoding 1268 MCOperand 1269 AMDGPUDisassembler::decodeMandatoryLiteralConstant(unsigned Val) const { 1270 if (HasLiteral) { 1271 assert( 1272 AMDGPU::hasVOPD(STI) && 1273 "Should only decode multiple kimm with VOPD, check VSrc operand types"); 1274 if (Literal != Val) 1275 return errOperand(Val, "More than one unique literal is illegal"); 1276 } 1277 HasLiteral = true; 1278 Literal = Val; 1279 return MCOperand::createImm(Literal); 1280 } 1281 1282 MCOperand AMDGPUDisassembler::decodeLiteralConstant() const { 1283 // For now all literal constants are supposed to be unsigned integer 1284 // ToDo: deal with signed/unsigned 64-bit integer constants 1285 // ToDo: deal with float/double constants 1286 if (!HasLiteral) { 1287 if (Bytes.size() < 4) { 1288 return errOperand(0, "cannot read literal, inst bytes left " + 1289 Twine(Bytes.size())); 1290 } 1291 HasLiteral = true; 1292 Literal = eatBytes<uint32_t>(Bytes); 1293 } 1294 return MCOperand::createImm(Literal); 1295 } 1296 1297 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) { 1298 using namespace AMDGPU::EncValues; 1299 1300 assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX); 1301 return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ? 1302 (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) : 1303 (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm))); 1304 // Cast prevents negative overflow. 1305 } 1306 1307 static int64_t getInlineImmVal32(unsigned Imm) { 1308 switch (Imm) { 1309 case 240: 1310 return FloatToBits(0.5f); 1311 case 241: 1312 return FloatToBits(-0.5f); 1313 case 242: 1314 return FloatToBits(1.0f); 1315 case 243: 1316 return FloatToBits(-1.0f); 1317 case 244: 1318 return FloatToBits(2.0f); 1319 case 245: 1320 return FloatToBits(-2.0f); 1321 case 246: 1322 return FloatToBits(4.0f); 1323 case 247: 1324 return FloatToBits(-4.0f); 1325 case 248: // 1 / (2 * PI) 1326 return 0x3e22f983; 1327 default: 1328 llvm_unreachable("invalid fp inline imm"); 1329 } 1330 } 1331 1332 static int64_t getInlineImmVal64(unsigned Imm) { 1333 switch (Imm) { 1334 case 240: 1335 return DoubleToBits(0.5); 1336 case 241: 1337 return DoubleToBits(-0.5); 1338 case 242: 1339 return DoubleToBits(1.0); 1340 case 243: 1341 return DoubleToBits(-1.0); 1342 case 244: 1343 return DoubleToBits(2.0); 1344 case 245: 1345 return DoubleToBits(-2.0); 1346 case 246: 1347 return DoubleToBits(4.0); 1348 case 247: 1349 return DoubleToBits(-4.0); 1350 case 248: // 1 / (2 * PI) 1351 return 0x3fc45f306dc9c882; 1352 default: 1353 llvm_unreachable("invalid fp inline imm"); 1354 } 1355 } 1356 1357 static int64_t getInlineImmVal16(unsigned Imm) { 1358 switch (Imm) { 1359 case 240: 1360 return 0x3800; 1361 case 241: 1362 return 0xB800; 1363 case 242: 1364 return 0x3C00; 1365 case 243: 1366 return 0xBC00; 1367 case 244: 1368 return 0x4000; 1369 case 245: 1370 return 0xC000; 1371 case 246: 1372 return 0x4400; 1373 case 247: 1374 return 0xC400; 1375 case 248: // 1 / (2 * PI) 1376 return 0x3118; 1377 default: 1378 llvm_unreachable("invalid fp inline imm"); 1379 } 1380 } 1381 1382 MCOperand AMDGPUDisassembler::decodeFPImmed(OpWidthTy Width, unsigned Imm) { 1383 assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN 1384 && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX); 1385 1386 // ToDo: case 248: 1/(2*PI) - is allowed only on VI 1387 switch (Width) { 1388 case OPW32: 1389 case OPW128: // splat constants 1390 case OPW512: 1391 case OPW1024: 1392 case OPWV232: 1393 return MCOperand::createImm(getInlineImmVal32(Imm)); 1394 case OPW64: 1395 case OPW256: 1396 return MCOperand::createImm(getInlineImmVal64(Imm)); 1397 case OPW16: 1398 case OPWV216: 1399 return MCOperand::createImm(getInlineImmVal16(Imm)); 1400 default: 1401 llvm_unreachable("implement me"); 1402 } 1403 } 1404 1405 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const { 1406 using namespace AMDGPU; 1407 1408 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1409 switch (Width) { 1410 default: // fall 1411 case OPW32: 1412 case OPW16: 1413 case OPWV216: 1414 return VGPR_32RegClassID; 1415 case OPW64: 1416 case OPWV232: return VReg_64RegClassID; 1417 case OPW96: return VReg_96RegClassID; 1418 case OPW128: return VReg_128RegClassID; 1419 case OPW160: return VReg_160RegClassID; 1420 case OPW256: return VReg_256RegClassID; 1421 case OPW512: return VReg_512RegClassID; 1422 case OPW1024: return VReg_1024RegClassID; 1423 } 1424 } 1425 1426 unsigned AMDGPUDisassembler::getAgprClassId(const OpWidthTy Width) const { 1427 using namespace AMDGPU; 1428 1429 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1430 switch (Width) { 1431 default: // fall 1432 case OPW32: 1433 case OPW16: 1434 case OPWV216: 1435 return AGPR_32RegClassID; 1436 case OPW64: 1437 case OPWV232: return AReg_64RegClassID; 1438 case OPW96: return AReg_96RegClassID; 1439 case OPW128: return AReg_128RegClassID; 1440 case OPW160: return AReg_160RegClassID; 1441 case OPW256: return AReg_256RegClassID; 1442 case OPW512: return AReg_512RegClassID; 1443 case OPW1024: return AReg_1024RegClassID; 1444 } 1445 } 1446 1447 1448 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const { 1449 using namespace AMDGPU; 1450 1451 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1452 switch (Width) { 1453 default: // fall 1454 case OPW32: 1455 case OPW16: 1456 case OPWV216: 1457 return SGPR_32RegClassID; 1458 case OPW64: 1459 case OPWV232: return SGPR_64RegClassID; 1460 case OPW96: return SGPR_96RegClassID; 1461 case OPW128: return SGPR_128RegClassID; 1462 case OPW160: return SGPR_160RegClassID; 1463 case OPW256: return SGPR_256RegClassID; 1464 case OPW512: return SGPR_512RegClassID; 1465 } 1466 } 1467 1468 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const { 1469 using namespace AMDGPU; 1470 1471 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1472 switch (Width) { 1473 default: // fall 1474 case OPW32: 1475 case OPW16: 1476 case OPWV216: 1477 return TTMP_32RegClassID; 1478 case OPW64: 1479 case OPWV232: return TTMP_64RegClassID; 1480 case OPW128: return TTMP_128RegClassID; 1481 case OPW256: return TTMP_256RegClassID; 1482 case OPW512: return TTMP_512RegClassID; 1483 } 1484 } 1485 1486 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const { 1487 using namespace AMDGPU::EncValues; 1488 1489 unsigned TTmpMin = isGFX9Plus() ? TTMP_GFX9PLUS_MIN : TTMP_VI_MIN; 1490 unsigned TTmpMax = isGFX9Plus() ? TTMP_GFX9PLUS_MAX : TTMP_VI_MAX; 1491 1492 return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1; 1493 } 1494 1495 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val, 1496 bool MandatoryLiteral) const { 1497 using namespace AMDGPU::EncValues; 1498 1499 assert(Val < 1024); // enum10 1500 1501 bool IsAGPR = Val & 512; 1502 Val &= 511; 1503 1504 if (VGPR_MIN <= Val && Val <= VGPR_MAX) { 1505 return createRegOperand(IsAGPR ? getAgprClassId(Width) 1506 : getVgprClassId(Width), Val - VGPR_MIN); 1507 } 1508 if (Val <= SGPR_MAX) { 1509 // "SGPR_MIN <= Val" is always true and causes compilation warning. 1510 static_assert(SGPR_MIN == 0, ""); 1511 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1512 } 1513 1514 int TTmpIdx = getTTmpIdx(Val); 1515 if (TTmpIdx >= 0) { 1516 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1517 } 1518 1519 if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX) 1520 return decodeIntImmed(Val); 1521 1522 if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX) 1523 return decodeFPImmed(Width, Val); 1524 1525 if (Val == LITERAL_CONST) { 1526 if (MandatoryLiteral) 1527 // Keep a sentinel value for deferred setting 1528 return MCOperand::createImm(LITERAL_CONST); 1529 else 1530 return decodeLiteralConstant(); 1531 } 1532 1533 switch (Width) { 1534 case OPW32: 1535 case OPW16: 1536 case OPWV216: 1537 return decodeSpecialReg32(Val); 1538 case OPW64: 1539 case OPWV232: 1540 return decodeSpecialReg64(Val); 1541 default: 1542 llvm_unreachable("unexpected immediate type"); 1543 } 1544 } 1545 1546 MCOperand AMDGPUDisassembler::decodeDstOp(const OpWidthTy Width, unsigned Val) const { 1547 using namespace AMDGPU::EncValues; 1548 1549 assert(Val < 128); 1550 assert(Width == OPW256 || Width == OPW512); 1551 1552 if (Val <= SGPR_MAX) { 1553 // "SGPR_MIN <= Val" is always true and causes compilation warning. 1554 static_assert(SGPR_MIN == 0, ""); 1555 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1556 } 1557 1558 int TTmpIdx = getTTmpIdx(Val); 1559 if (TTmpIdx >= 0) { 1560 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1561 } 1562 1563 llvm_unreachable("unknown dst register"); 1564 } 1565 1566 // Bit 0 of DstY isn't stored in the instruction, because it's always the 1567 // opposite of bit 0 of DstX. 1568 MCOperand AMDGPUDisassembler::decodeVOPDDstYOp(MCInst &Inst, 1569 unsigned Val) const { 1570 int VDstXInd = 1571 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::vdstX); 1572 assert(VDstXInd != -1); 1573 assert(Inst.getOperand(VDstXInd).isReg()); 1574 unsigned XDstReg = MRI.getEncodingValue(Inst.getOperand(VDstXInd).getReg()); 1575 Val |= ~XDstReg & 1; 1576 auto Width = llvm::AMDGPUDisassembler::OPW32; 1577 return createRegOperand(getVgprClassId(Width), Val); 1578 } 1579 1580 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { 1581 using namespace AMDGPU; 1582 1583 switch (Val) { 1584 case 102: return createRegOperand(FLAT_SCR_LO); 1585 case 103: return createRegOperand(FLAT_SCR_HI); 1586 case 104: return createRegOperand(XNACK_MASK_LO); 1587 case 105: return createRegOperand(XNACK_MASK_HI); 1588 case 106: return createRegOperand(VCC_LO); 1589 case 107: return createRegOperand(VCC_HI); 1590 case 108: return createRegOperand(TBA_LO); 1591 case 109: return createRegOperand(TBA_HI); 1592 case 110: return createRegOperand(TMA_LO); 1593 case 111: return createRegOperand(TMA_HI); 1594 case 124: 1595 return isGFX11Plus() ? createRegOperand(SGPR_NULL) : createRegOperand(M0); 1596 case 125: 1597 return isGFX11Plus() ? createRegOperand(M0) : createRegOperand(SGPR_NULL); 1598 case 126: return createRegOperand(EXEC_LO); 1599 case 127: return createRegOperand(EXEC_HI); 1600 case 235: return createRegOperand(SRC_SHARED_BASE); 1601 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1602 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1603 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1604 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1605 case 251: return createRegOperand(SRC_VCCZ); 1606 case 252: return createRegOperand(SRC_EXECZ); 1607 case 253: return createRegOperand(SRC_SCC); 1608 case 254: return createRegOperand(LDS_DIRECT); 1609 default: break; 1610 } 1611 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1612 } 1613 1614 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const { 1615 using namespace AMDGPU; 1616 1617 switch (Val) { 1618 case 102: return createRegOperand(FLAT_SCR); 1619 case 104: return createRegOperand(XNACK_MASK); 1620 case 106: return createRegOperand(VCC); 1621 case 108: return createRegOperand(TBA); 1622 case 110: return createRegOperand(TMA); 1623 case 124: 1624 if (isGFX11Plus()) 1625 return createRegOperand(SGPR_NULL); 1626 break; 1627 case 125: 1628 if (!isGFX11Plus()) 1629 return createRegOperand(SGPR_NULL); 1630 break; 1631 case 126: return createRegOperand(EXEC); 1632 case 235: return createRegOperand(SRC_SHARED_BASE); 1633 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1634 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1635 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1636 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1637 case 251: return createRegOperand(SRC_VCCZ); 1638 case 252: return createRegOperand(SRC_EXECZ); 1639 case 253: return createRegOperand(SRC_SCC); 1640 default: break; 1641 } 1642 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1643 } 1644 1645 MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width, 1646 const unsigned Val) const { 1647 using namespace AMDGPU::SDWA; 1648 using namespace AMDGPU::EncValues; 1649 1650 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 1651 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 1652 // XXX: cast to int is needed to avoid stupid warning: 1653 // compare with unsigned is always true 1654 if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) && 1655 Val <= SDWA9EncValues::SRC_VGPR_MAX) { 1656 return createRegOperand(getVgprClassId(Width), 1657 Val - SDWA9EncValues::SRC_VGPR_MIN); 1658 } 1659 if (SDWA9EncValues::SRC_SGPR_MIN <= Val && 1660 Val <= (isGFX10Plus() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10 1661 : SDWA9EncValues::SRC_SGPR_MAX_SI)) { 1662 return createSRegOperand(getSgprClassId(Width), 1663 Val - SDWA9EncValues::SRC_SGPR_MIN); 1664 } 1665 if (SDWA9EncValues::SRC_TTMP_MIN <= Val && 1666 Val <= SDWA9EncValues::SRC_TTMP_MAX) { 1667 return createSRegOperand(getTtmpClassId(Width), 1668 Val - SDWA9EncValues::SRC_TTMP_MIN); 1669 } 1670 1671 const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN; 1672 1673 if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX) 1674 return decodeIntImmed(SVal); 1675 1676 if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX) 1677 return decodeFPImmed(Width, SVal); 1678 1679 return decodeSpecialReg32(SVal); 1680 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 1681 return createRegOperand(getVgprClassId(Width), Val); 1682 } 1683 llvm_unreachable("unsupported target"); 1684 } 1685 1686 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const { 1687 return decodeSDWASrc(OPW16, Val); 1688 } 1689 1690 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const { 1691 return decodeSDWASrc(OPW32, Val); 1692 } 1693 1694 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const { 1695 using namespace AMDGPU::SDWA; 1696 1697 assert((STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 1698 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) && 1699 "SDWAVopcDst should be present only on GFX9+"); 1700 1701 bool IsWave64 = STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64]; 1702 1703 if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) { 1704 Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK; 1705 1706 int TTmpIdx = getTTmpIdx(Val); 1707 if (TTmpIdx >= 0) { 1708 auto TTmpClsId = getTtmpClassId(IsWave64 ? OPW64 : OPW32); 1709 return createSRegOperand(TTmpClsId, TTmpIdx); 1710 } else if (Val > SGPR_MAX) { 1711 return IsWave64 ? decodeSpecialReg64(Val) 1712 : decodeSpecialReg32(Val); 1713 } else { 1714 return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val); 1715 } 1716 } else { 1717 return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO); 1718 } 1719 } 1720 1721 MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const { 1722 return STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ? 1723 decodeOperand_SReg_64(Val) : decodeOperand_SReg_32(Val); 1724 } 1725 1726 bool AMDGPUDisassembler::isVI() const { 1727 return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]; 1728 } 1729 1730 bool AMDGPUDisassembler::isGFX9() const { return AMDGPU::isGFX9(STI); } 1731 1732 bool AMDGPUDisassembler::isGFX90A() const { 1733 return STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]; 1734 } 1735 1736 bool AMDGPUDisassembler::isGFX9Plus() const { return AMDGPU::isGFX9Plus(STI); } 1737 1738 bool AMDGPUDisassembler::isGFX10() const { return AMDGPU::isGFX10(STI); } 1739 1740 bool AMDGPUDisassembler::isGFX10Plus() const { 1741 return AMDGPU::isGFX10Plus(STI); 1742 } 1743 1744 bool AMDGPUDisassembler::isGFX11() const { 1745 return STI.getFeatureBits()[AMDGPU::FeatureGFX11]; 1746 } 1747 1748 bool AMDGPUDisassembler::isGFX11Plus() const { 1749 return AMDGPU::isGFX11Plus(STI); 1750 } 1751 1752 1753 bool AMDGPUDisassembler::hasArchitectedFlatScratch() const { 1754 return STI.getFeatureBits()[AMDGPU::FeatureArchitectedFlatScratch]; 1755 } 1756 1757 //===----------------------------------------------------------------------===// 1758 // AMDGPU specific symbol handling 1759 //===----------------------------------------------------------------------===// 1760 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1761 do { \ 1762 KdStream << Indent << DIRECTIVE " " \ 1763 << ((FourByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 1764 } while (0) 1765 1766 // NOLINTNEXTLINE(readability-identifier-naming) 1767 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1( 1768 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1769 using namespace amdhsa; 1770 StringRef Indent = "\t"; 1771 1772 // We cannot accurately backward compute #VGPRs used from 1773 // GRANULATED_WORKITEM_VGPR_COUNT. But we are concerned with getting the same 1774 // value of GRANULATED_WORKITEM_VGPR_COUNT in the reassembled binary. So we 1775 // simply calculate the inverse of what the assembler does. 1776 1777 uint32_t GranulatedWorkitemVGPRCount = 1778 (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT) >> 1779 COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT_SHIFT; 1780 1781 uint32_t NextFreeVGPR = (GranulatedWorkitemVGPRCount + 1) * 1782 AMDGPU::IsaInfo::getVGPREncodingGranule(&STI); 1783 1784 KdStream << Indent << ".amdhsa_next_free_vgpr " << NextFreeVGPR << '\n'; 1785 1786 // We cannot backward compute values used to calculate 1787 // GRANULATED_WAVEFRONT_SGPR_COUNT. Hence the original values for following 1788 // directives can't be computed: 1789 // .amdhsa_reserve_vcc 1790 // .amdhsa_reserve_flat_scratch 1791 // .amdhsa_reserve_xnack_mask 1792 // They take their respective default values if not specified in the assembly. 1793 // 1794 // GRANULATED_WAVEFRONT_SGPR_COUNT 1795 // = f(NEXT_FREE_SGPR + VCC + FLAT_SCRATCH + XNACK_MASK) 1796 // 1797 // We compute the inverse as though all directives apart from NEXT_FREE_SGPR 1798 // are set to 0. So while disassembling we consider that: 1799 // 1800 // GRANULATED_WAVEFRONT_SGPR_COUNT 1801 // = f(NEXT_FREE_SGPR + 0 + 0 + 0) 1802 // 1803 // The disassembler cannot recover the original values of those 3 directives. 1804 1805 uint32_t GranulatedWavefrontSGPRCount = 1806 (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT) >> 1807 COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT_SHIFT; 1808 1809 if (isGFX10Plus() && GranulatedWavefrontSGPRCount) 1810 return MCDisassembler::Fail; 1811 1812 uint32_t NextFreeSGPR = (GranulatedWavefrontSGPRCount + 1) * 1813 AMDGPU::IsaInfo::getSGPREncodingGranule(&STI); 1814 1815 KdStream << Indent << ".amdhsa_reserve_vcc " << 0 << '\n'; 1816 if (!hasArchitectedFlatScratch()) 1817 KdStream << Indent << ".amdhsa_reserve_flat_scratch " << 0 << '\n'; 1818 KdStream << Indent << ".amdhsa_reserve_xnack_mask " << 0 << '\n'; 1819 KdStream << Indent << ".amdhsa_next_free_sgpr " << NextFreeSGPR << "\n"; 1820 1821 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIORITY) 1822 return MCDisassembler::Fail; 1823 1824 PRINT_DIRECTIVE(".amdhsa_float_round_mode_32", 1825 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32); 1826 PRINT_DIRECTIVE(".amdhsa_float_round_mode_16_64", 1827 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64); 1828 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_32", 1829 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32); 1830 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_16_64", 1831 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); 1832 1833 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIV) 1834 return MCDisassembler::Fail; 1835 1836 PRINT_DIRECTIVE(".amdhsa_dx10_clamp", COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP); 1837 1838 if (FourByteBuffer & COMPUTE_PGM_RSRC1_DEBUG_MODE) 1839 return MCDisassembler::Fail; 1840 1841 PRINT_DIRECTIVE(".amdhsa_ieee_mode", COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE); 1842 1843 if (FourByteBuffer & COMPUTE_PGM_RSRC1_BULKY) 1844 return MCDisassembler::Fail; 1845 1846 if (FourByteBuffer & COMPUTE_PGM_RSRC1_CDBG_USER) 1847 return MCDisassembler::Fail; 1848 1849 PRINT_DIRECTIVE(".amdhsa_fp16_overflow", COMPUTE_PGM_RSRC1_FP16_OVFL); 1850 1851 if (FourByteBuffer & COMPUTE_PGM_RSRC1_RESERVED0) 1852 return MCDisassembler::Fail; 1853 1854 if (isGFX10Plus()) { 1855 PRINT_DIRECTIVE(".amdhsa_workgroup_processor_mode", 1856 COMPUTE_PGM_RSRC1_WGP_MODE); 1857 PRINT_DIRECTIVE(".amdhsa_memory_ordered", COMPUTE_PGM_RSRC1_MEM_ORDERED); 1858 PRINT_DIRECTIVE(".amdhsa_forward_progress", COMPUTE_PGM_RSRC1_FWD_PROGRESS); 1859 } 1860 return MCDisassembler::Success; 1861 } 1862 1863 // NOLINTNEXTLINE(readability-identifier-naming) 1864 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2( 1865 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1866 using namespace amdhsa; 1867 StringRef Indent = "\t"; 1868 if (hasArchitectedFlatScratch()) 1869 PRINT_DIRECTIVE(".amdhsa_enable_private_segment", 1870 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1871 else 1872 PRINT_DIRECTIVE(".amdhsa_system_sgpr_private_segment_wavefront_offset", 1873 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1874 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_x", 1875 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X); 1876 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_y", 1877 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y); 1878 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_z", 1879 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z); 1880 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_info", 1881 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO); 1882 PRINT_DIRECTIVE(".amdhsa_system_vgpr_workitem_id", 1883 COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID); 1884 1885 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_ADDRESS_WATCH) 1886 return MCDisassembler::Fail; 1887 1888 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_MEMORY) 1889 return MCDisassembler::Fail; 1890 1891 if (FourByteBuffer & COMPUTE_PGM_RSRC2_GRANULATED_LDS_SIZE) 1892 return MCDisassembler::Fail; 1893 1894 PRINT_DIRECTIVE( 1895 ".amdhsa_exception_fp_ieee_invalid_op", 1896 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION); 1897 PRINT_DIRECTIVE(".amdhsa_exception_fp_denorm_src", 1898 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE); 1899 PRINT_DIRECTIVE( 1900 ".amdhsa_exception_fp_ieee_div_zero", 1901 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO); 1902 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_overflow", 1903 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW); 1904 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_underflow", 1905 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW); 1906 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_inexact", 1907 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT); 1908 PRINT_DIRECTIVE(".amdhsa_exception_int_div_zero", 1909 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO); 1910 1911 if (FourByteBuffer & COMPUTE_PGM_RSRC2_RESERVED0) 1912 return MCDisassembler::Fail; 1913 1914 return MCDisassembler::Success; 1915 } 1916 1917 #undef PRINT_DIRECTIVE 1918 1919 MCDisassembler::DecodeStatus 1920 AMDGPUDisassembler::decodeKernelDescriptorDirective( 1921 DataExtractor::Cursor &Cursor, ArrayRef<uint8_t> Bytes, 1922 raw_string_ostream &KdStream) const { 1923 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1924 do { \ 1925 KdStream << Indent << DIRECTIVE " " \ 1926 << ((TwoByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 1927 } while (0) 1928 1929 uint16_t TwoByteBuffer = 0; 1930 uint32_t FourByteBuffer = 0; 1931 1932 StringRef ReservedBytes; 1933 StringRef Indent = "\t"; 1934 1935 assert(Bytes.size() == 64); 1936 DataExtractor DE(Bytes, /*IsLittleEndian=*/true, /*AddressSize=*/8); 1937 1938 switch (Cursor.tell()) { 1939 case amdhsa::GROUP_SEGMENT_FIXED_SIZE_OFFSET: 1940 FourByteBuffer = DE.getU32(Cursor); 1941 KdStream << Indent << ".amdhsa_group_segment_fixed_size " << FourByteBuffer 1942 << '\n'; 1943 return MCDisassembler::Success; 1944 1945 case amdhsa::PRIVATE_SEGMENT_FIXED_SIZE_OFFSET: 1946 FourByteBuffer = DE.getU32(Cursor); 1947 KdStream << Indent << ".amdhsa_private_segment_fixed_size " 1948 << FourByteBuffer << '\n'; 1949 return MCDisassembler::Success; 1950 1951 case amdhsa::KERNARG_SIZE_OFFSET: 1952 FourByteBuffer = DE.getU32(Cursor); 1953 KdStream << Indent << ".amdhsa_kernarg_size " 1954 << FourByteBuffer << '\n'; 1955 return MCDisassembler::Success; 1956 1957 case amdhsa::RESERVED0_OFFSET: 1958 // 4 reserved bytes, must be 0. 1959 ReservedBytes = DE.getBytes(Cursor, 4); 1960 for (int I = 0; I < 4; ++I) { 1961 if (ReservedBytes[I] != 0) { 1962 return MCDisassembler::Fail; 1963 } 1964 } 1965 return MCDisassembler::Success; 1966 1967 case amdhsa::KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET: 1968 // KERNEL_CODE_ENTRY_BYTE_OFFSET 1969 // So far no directive controls this for Code Object V3, so simply skip for 1970 // disassembly. 1971 DE.skip(Cursor, 8); 1972 return MCDisassembler::Success; 1973 1974 case amdhsa::RESERVED1_OFFSET: 1975 // 20 reserved bytes, must be 0. 1976 ReservedBytes = DE.getBytes(Cursor, 20); 1977 for (int I = 0; I < 20; ++I) { 1978 if (ReservedBytes[I] != 0) { 1979 return MCDisassembler::Fail; 1980 } 1981 } 1982 return MCDisassembler::Success; 1983 1984 case amdhsa::COMPUTE_PGM_RSRC3_OFFSET: 1985 // COMPUTE_PGM_RSRC3 1986 // - Only set for GFX10, GFX6-9 have this to be 0. 1987 // - Currently no directives directly control this. 1988 FourByteBuffer = DE.getU32(Cursor); 1989 if (!isGFX10Plus() && FourByteBuffer) { 1990 return MCDisassembler::Fail; 1991 } 1992 return MCDisassembler::Success; 1993 1994 case amdhsa::COMPUTE_PGM_RSRC1_OFFSET: 1995 FourByteBuffer = DE.getU32(Cursor); 1996 if (decodeCOMPUTE_PGM_RSRC1(FourByteBuffer, KdStream) == 1997 MCDisassembler::Fail) { 1998 return MCDisassembler::Fail; 1999 } 2000 return MCDisassembler::Success; 2001 2002 case amdhsa::COMPUTE_PGM_RSRC2_OFFSET: 2003 FourByteBuffer = DE.getU32(Cursor); 2004 if (decodeCOMPUTE_PGM_RSRC2(FourByteBuffer, KdStream) == 2005 MCDisassembler::Fail) { 2006 return MCDisassembler::Fail; 2007 } 2008 return MCDisassembler::Success; 2009 2010 case amdhsa::KERNEL_CODE_PROPERTIES_OFFSET: 2011 using namespace amdhsa; 2012 TwoByteBuffer = DE.getU16(Cursor); 2013 2014 if (!hasArchitectedFlatScratch()) 2015 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_buffer", 2016 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER); 2017 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_ptr", 2018 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR); 2019 PRINT_DIRECTIVE(".amdhsa_user_sgpr_queue_ptr", 2020 KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR); 2021 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_segment_ptr", 2022 KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR); 2023 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_id", 2024 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID); 2025 if (!hasArchitectedFlatScratch()) 2026 PRINT_DIRECTIVE(".amdhsa_user_sgpr_flat_scratch_init", 2027 KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT); 2028 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_size", 2029 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE); 2030 2031 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED0) 2032 return MCDisassembler::Fail; 2033 2034 // Reserved for GFX9 2035 if (isGFX9() && 2036 (TwoByteBuffer & KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32)) { 2037 return MCDisassembler::Fail; 2038 } else if (isGFX10Plus()) { 2039 PRINT_DIRECTIVE(".amdhsa_wavefront_size32", 2040 KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 2041 } 2042 2043 PRINT_DIRECTIVE(".amdhsa_uses_dynamic_stack", 2044 KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK); 2045 2046 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED1) 2047 return MCDisassembler::Fail; 2048 2049 return MCDisassembler::Success; 2050 2051 case amdhsa::RESERVED2_OFFSET: 2052 // 6 bytes from here are reserved, must be 0. 2053 ReservedBytes = DE.getBytes(Cursor, 6); 2054 for (int I = 0; I < 6; ++I) { 2055 if (ReservedBytes[I] != 0) 2056 return MCDisassembler::Fail; 2057 } 2058 return MCDisassembler::Success; 2059 2060 default: 2061 llvm_unreachable("Unhandled index. Case statements cover everything."); 2062 return MCDisassembler::Fail; 2063 } 2064 #undef PRINT_DIRECTIVE 2065 } 2066 2067 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeKernelDescriptor( 2068 StringRef KdName, ArrayRef<uint8_t> Bytes, uint64_t KdAddress) const { 2069 // CP microcode requires the kernel descriptor to be 64 aligned. 2070 if (Bytes.size() != 64 || KdAddress % 64 != 0) 2071 return MCDisassembler::Fail; 2072 2073 std::string Kd; 2074 raw_string_ostream KdStream(Kd); 2075 KdStream << ".amdhsa_kernel " << KdName << '\n'; 2076 2077 DataExtractor::Cursor C(0); 2078 while (C && C.tell() < Bytes.size()) { 2079 MCDisassembler::DecodeStatus Status = 2080 decodeKernelDescriptorDirective(C, Bytes, KdStream); 2081 2082 cantFail(C.takeError()); 2083 2084 if (Status == MCDisassembler::Fail) 2085 return MCDisassembler::Fail; 2086 } 2087 KdStream << ".end_amdhsa_kernel\n"; 2088 outs() << KdStream.str(); 2089 return MCDisassembler::Success; 2090 } 2091 2092 Optional<MCDisassembler::DecodeStatus> 2093 AMDGPUDisassembler::onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, 2094 ArrayRef<uint8_t> Bytes, uint64_t Address, 2095 raw_ostream &CStream) const { 2096 // Right now only kernel descriptor needs to be handled. 2097 // We ignore all other symbols for target specific handling. 2098 // TODO: 2099 // Fix the spurious symbol issue for AMDGPU kernels. Exists for both Code 2100 // Object V2 and V3 when symbols are marked protected. 2101 2102 // amd_kernel_code_t for Code Object V2. 2103 if (Symbol.Type == ELF::STT_AMDGPU_HSA_KERNEL) { 2104 Size = 256; 2105 return MCDisassembler::Fail; 2106 } 2107 2108 // Code Object V3 kernel descriptors. 2109 StringRef Name = Symbol.Name; 2110 if (Symbol.Type == ELF::STT_OBJECT && Name.endswith(StringRef(".kd"))) { 2111 Size = 64; // Size = 64 regardless of success or failure. 2112 return decodeKernelDescriptor(Name.drop_back(3), Bytes, Address); 2113 } 2114 return None; 2115 } 2116 2117 //===----------------------------------------------------------------------===// 2118 // AMDGPUSymbolizer 2119 //===----------------------------------------------------------------------===// 2120 2121 // Try to find symbol name for specified label 2122 bool AMDGPUSymbolizer::tryAddingSymbolicOperand( 2123 MCInst &Inst, raw_ostream & /*cStream*/, int64_t Value, 2124 uint64_t /*Address*/, bool IsBranch, uint64_t /*Offset*/, 2125 uint64_t /*OpSize*/, uint64_t /*InstSize*/) { 2126 2127 if (!IsBranch) { 2128 return false; 2129 } 2130 2131 auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo); 2132 if (!Symbols) 2133 return false; 2134 2135 auto Result = llvm::find_if(*Symbols, [Value](const SymbolInfoTy &Val) { 2136 return Val.Addr == static_cast<uint64_t>(Value) && 2137 Val.Type == ELF::STT_NOTYPE; 2138 }); 2139 if (Result != Symbols->end()) { 2140 auto *Sym = Ctx.getOrCreateSymbol(Result->Name); 2141 const auto *Add = MCSymbolRefExpr::create(Sym, Ctx); 2142 Inst.addOperand(MCOperand::createExpr(Add)); 2143 return true; 2144 } 2145 // Add to list of referenced addresses, so caller can synthesize a label. 2146 ReferencedAddresses.push_back(static_cast<uint64_t>(Value)); 2147 return false; 2148 } 2149 2150 void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream, 2151 int64_t Value, 2152 uint64_t Address) { 2153 llvm_unreachable("unimplemented"); 2154 } 2155 2156 //===----------------------------------------------------------------------===// 2157 // Initialization 2158 //===----------------------------------------------------------------------===// 2159 2160 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/, 2161 LLVMOpInfoCallback /*GetOpInfo*/, 2162 LLVMSymbolLookupCallback /*SymbolLookUp*/, 2163 void *DisInfo, 2164 MCContext *Ctx, 2165 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 2166 return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo); 2167 } 2168 2169 static MCDisassembler *createAMDGPUDisassembler(const Target &T, 2170 const MCSubtargetInfo &STI, 2171 MCContext &Ctx) { 2172 return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo()); 2173 } 2174 2175 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler() { 2176 TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(), 2177 createAMDGPUDisassembler); 2178 TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(), 2179 createAMDGPUSymbolizer); 2180 } 2181