1 //===- AMDGPUDisassembler.hpp - Disassembler for AMDGPU ISA -----*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 /// \file 10 /// 11 /// This file contains declaration for AMDGPU ISA disassembler 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H 16 #define LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H 17 18 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 19 #include "llvm/MC/MCInstrInfo.h" 20 #include "llvm/Support/DataExtractor.h" 21 #include <memory> 22 23 namespace llvm { 24 25 class MCInst; 26 class MCOperand; 27 class MCSubtargetInfo; 28 class Twine; 29 30 //===----------------------------------------------------------------------===// 31 // AMDGPUDisassembler 32 //===----------------------------------------------------------------------===// 33 34 class AMDGPUDisassembler : public MCDisassembler { 35 private: 36 std::unique_ptr<MCInstrInfo const> const MCII; 37 const MCRegisterInfo &MRI; 38 const unsigned TargetMaxInstBytes; 39 mutable ArrayRef<uint8_t> Bytes; 40 mutable uint32_t Literal; 41 mutable bool HasLiteral; 42 43 public: 44 AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, 45 MCInstrInfo const *MCII); 46 ~AMDGPUDisassembler() override = default; 47 48 DecodeStatus getInstruction(MCInst &MI, uint64_t &Size, 49 ArrayRef<uint8_t> Bytes, uint64_t Address, 50 raw_ostream &CS) const override; 51 52 const char* getRegClassName(unsigned RegClassID) const; 53 54 MCOperand createRegOperand(unsigned int RegId) const; 55 MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const; 56 MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const; 57 58 MCOperand errOperand(unsigned V, const Twine& ErrMsg) const; 59 60 DecodeStatus tryDecodeInst(const uint8_t* Table, MCInst &MI, uint64_t Inst, 61 uint64_t Address) const; 62 63 Optional<DecodeStatus> onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, 64 ArrayRef<uint8_t> Bytes, 65 uint64_t Address, 66 raw_ostream &CStream) const override; 67 68 DecodeStatus decodeKernelDescriptor(StringRef KdName, ArrayRef<uint8_t> Bytes, 69 uint64_t KdAddress) const; 70 71 DecodeStatus 72 decodeKernelDescriptorDirective(DataExtractor::Cursor &Cursor, 73 ArrayRef<uint8_t> Bytes, 74 raw_string_ostream &KdStream) const; 75 76 /// Decode as directives that handle COMPUTE_PGM_RSRC1. 77 /// \param FourByteBuffer - Bytes holding contents of COMPUTE_PGM_RSRC1. 78 /// \param KdStream - Stream to write the disassembled directives to. 79 // NOLINTNEXTLINE(readability-identifier-naming) 80 DecodeStatus decodeCOMPUTE_PGM_RSRC1(uint32_t FourByteBuffer, 81 raw_string_ostream &KdStream) const; 82 83 /// Decode as directives that handle COMPUTE_PGM_RSRC2. 84 /// \param FourByteBuffer - Bytes holding contents of COMPUTE_PGM_RSRC2. 85 /// \param KdStream - Stream to write the disassembled directives to. 86 // NOLINTNEXTLINE(readability-identifier-naming) 87 DecodeStatus decodeCOMPUTE_PGM_RSRC2(uint32_t FourByteBuffer, 88 raw_string_ostream &KdStream) const; 89 90 DecodeStatus convertFMAanyK(MCInst &MI, int ImmLitIdx) const; 91 DecodeStatus convertSDWAInst(MCInst &MI) const; 92 DecodeStatus convertDPP8Inst(MCInst &MI) const; 93 DecodeStatus convertMIMGInst(MCInst &MI) const; 94 95 MCOperand decodeOperand_VGPR_32(unsigned Val) const; 96 MCOperand decodeOperand_VRegOrLds_32(unsigned Val) const; 97 98 MCOperand decodeOperand_VS_32(unsigned Val) const; 99 MCOperand decodeOperand_VS_64(unsigned Val) const; 100 MCOperand decodeOperand_VS_128(unsigned Val) const; 101 MCOperand decodeOperand_VSrc16(unsigned Val) const; 102 MCOperand decodeOperand_VSrcV216(unsigned Val) const; 103 MCOperand decodeOperand_VSrcV232(unsigned Val) const; 104 105 MCOperand decodeOperand_VReg_64(unsigned Val) const; 106 MCOperand decodeOperand_VReg_96(unsigned Val) const; 107 MCOperand decodeOperand_VReg_128(unsigned Val) const; 108 MCOperand decodeOperand_VReg_256(unsigned Val) const; 109 MCOperand decodeOperand_VReg_512(unsigned Val) const; 110 MCOperand decodeOperand_VReg_1024(unsigned Val) const; 111 112 MCOperand decodeOperand_SReg_32(unsigned Val) const; 113 MCOperand decodeOperand_SReg_32_XM0_XEXEC(unsigned Val) const; 114 MCOperand decodeOperand_SReg_32_XEXEC_HI(unsigned Val) const; 115 MCOperand decodeOperand_SRegOrLds_32(unsigned Val) const; 116 MCOperand decodeOperand_SReg_64(unsigned Val) const; 117 MCOperand decodeOperand_SReg_64_XEXEC(unsigned Val) const; 118 MCOperand decodeOperand_SReg_128(unsigned Val) const; 119 MCOperand decodeOperand_SReg_256(unsigned Val) const; 120 MCOperand decodeOperand_SReg_512(unsigned Val) const; 121 122 MCOperand decodeOperand_AGPR_32(unsigned Val) const; 123 MCOperand decodeOperand_AReg_64(unsigned Val) const; 124 MCOperand decodeOperand_AReg_128(unsigned Val) const; 125 MCOperand decodeOperand_AReg_256(unsigned Val) const; 126 MCOperand decodeOperand_AReg_512(unsigned Val) const; 127 MCOperand decodeOperand_AReg_1024(unsigned Val) const; 128 MCOperand decodeOperand_AV_32(unsigned Val) const; 129 MCOperand decodeOperand_AV_64(unsigned Val) const; 130 131 enum OpWidthTy { 132 OPW32, 133 OPW64, 134 OPW96, 135 OPW128, 136 OPW160, 137 OPW256, 138 OPW512, 139 OPW1024, 140 OPW16, 141 OPWV216, 142 OPWV232, 143 OPW_LAST_, 144 OPW_FIRST_ = OPW32 145 }; 146 147 unsigned getVgprClassId(const OpWidthTy Width) const; 148 unsigned getAgprClassId(const OpWidthTy Width) const; 149 unsigned getSgprClassId(const OpWidthTy Width) const; 150 unsigned getTtmpClassId(const OpWidthTy Width) const; 151 152 static MCOperand decodeIntImmed(unsigned Imm); 153 static MCOperand decodeFPImmed(OpWidthTy Width, unsigned Imm); 154 MCOperand decodeMandatoryLiteralConstant(unsigned Imm) const; 155 MCOperand decodeLiteralConstant() const; 156 157 MCOperand decodeSrcOp(const OpWidthTy Width, unsigned Val, 158 bool MandatoryLiteral = false) const; 159 MCOperand decodeDstOp(const OpWidthTy Width, unsigned Val) const; 160 MCOperand decodeSpecialReg32(unsigned Val) const; 161 MCOperand decodeSpecialReg64(unsigned Val) const; 162 163 MCOperand decodeSDWASrc(const OpWidthTy Width, unsigned Val) const; 164 MCOperand decodeSDWASrc16(unsigned Val) const; 165 MCOperand decodeSDWASrc32(unsigned Val) const; 166 MCOperand decodeSDWAVopcDst(unsigned Val) const; 167 168 MCOperand decodeBoolReg(unsigned Val) const; 169 170 int getTTmpIdx(unsigned Val) const; 171 172 const MCInstrInfo *getMCII() const { return MCII.get(); } 173 174 bool isVI() const; 175 bool isGFX9() const; 176 bool isGFX90A() const; 177 bool isGFX9Plus() const; 178 bool isGFX10() const; 179 bool isGFX10Plus() const; 180 181 bool hasArchitectedFlatScratch() const; 182 }; 183 184 //===----------------------------------------------------------------------===// 185 // AMDGPUSymbolizer 186 //===----------------------------------------------------------------------===// 187 188 class AMDGPUSymbolizer : public MCSymbolizer { 189 private: 190 void *DisInfo; 191 std::vector<uint64_t> ReferencedAddresses; 192 193 public: 194 AMDGPUSymbolizer(MCContext &Ctx, std::unique_ptr<MCRelocationInfo> &&RelInfo, 195 void *disInfo) 196 : MCSymbolizer(Ctx, std::move(RelInfo)), DisInfo(disInfo) {} 197 198 bool tryAddingSymbolicOperand(MCInst &Inst, raw_ostream &cStream, 199 int64_t Value, uint64_t Address, 200 bool IsBranch, uint64_t Offset, 201 uint64_t InstSize) override; 202 203 void tryAddingPcLoadReferenceComment(raw_ostream &cStream, 204 int64_t Value, 205 uint64_t Address) override; 206 207 ArrayRef<uint64_t> getReferencedAddresses() const override { 208 return ReferencedAddresses; 209 } 210 }; 211 212 } // end namespace llvm 213 214 #endif // LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H 215