1//===-- EvergreenInstructions.td - EG Instruction defs ----*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// TableGen definitions for instructions which are: 10// - Available to Evergreen and newer VLIW4/VLIW5 GPUs 11// - Available only on Evergreen family GPUs. 12// 13//===----------------------------------------------------------------------===// 14 15def isEG : Predicate< 16 "Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && " 17 "!Subtarget->hasCaymanISA()" 18>; 19 20def isEGorCayman : Predicate< 21 "Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||" 22 "Subtarget->getGeneration() == AMDGPUSubtarget::NORTHERN_ISLANDS" 23>; 24 25class EGPat<dag pattern, dag result> : AMDGPUPat<pattern, result> { 26 let SubtargetPredicate = isEG; 27} 28 29class EGOrCaymanPat<dag pattern, dag result> : AMDGPUPat<pattern, result> { 30 let SubtargetPredicate = isEGorCayman; 31} 32 33def IMMZeroBasedBitfieldMask : ImmLeaf <i32, [{ 34 return isMask_32(Imm); 35}]>; 36 37def IMMPopCount : SDNodeXForm<imm, [{ 38 return CurDAG->getTargetConstant(countPopulation(N->getZExtValue()), SDLoc(N), 39 MVT::i32); 40}]>; 41 42//===----------------------------------------------------------------------===// 43// Evergreen / Cayman store instructions 44//===----------------------------------------------------------------------===// 45 46let SubtargetPredicate = isEGorCayman in { 47 48class CF_MEM_RAT_CACHELESS <bits<6> rat_inst, bits<4> rat_id, bits<4> mask, dag ins, 49 string name, list<dag> pattern> 50 : EG_CF_RAT <0x57, rat_inst, rat_id, mask, (outs), ins, 51 "MEM_RAT_CACHELESS "#name, pattern>; 52 53class CF_MEM_RAT <bits<6> rat_inst, bits<4> rat_id, bits<4> mask, dag ins, 54 dag outs, string name, list<dag> pattern> 55 : EG_CF_RAT <0x56, rat_inst, rat_id, mask, outs, ins, 56 "MEM_RAT "#name, pattern>; 57 58class CF_MEM_RAT_STORE_TYPED<bits<1> has_eop> 59 : CF_MEM_RAT <0x1, ?, 0xf, (ins R600_Reg128:$rw_gpr, R600_Reg128:$index_gpr, 60 i32imm:$rat_id, InstFlag:$eop), (outs), 61 "STORE_TYPED RAT($rat_id) $rw_gpr, $index_gpr" 62 #!if(has_eop, ", $eop", ""), 63 [(int_r600_rat_store_typed R600_Reg128:$rw_gpr, 64 R600_Reg128:$index_gpr, 65 (i32 imm:$rat_id))]>; 66 67def RAT_MSKOR : CF_MEM_RAT <0x11, 0, 0xf, 68 (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr), (outs), 69 "MSKOR $rw_gpr.XW, $index_gpr", 70 [(mskor_global v4i32:$rw_gpr, i32:$index_gpr)] 71> { 72 let eop = 0; 73} 74 75 76multiclass RAT_ATOMIC<bits<6> op_ret, bits<6> op_noret, string name> { 77 let Constraints = "$rw_gpr = $out_gpr", eop = 0, mayStore = 1 in { 78 def _RTN: CF_MEM_RAT <op_ret, 0, 0xf, 79 (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr), 80 (outs R600_Reg128:$out_gpr), 81 name # "_RTN $rw_gpr, $index_gpr", [] >; 82 def _NORET: CF_MEM_RAT <op_noret, 0, 0xf, 83 (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr), 84 (outs R600_Reg128:$out_gpr), 85 name # " $rw_gpr, $index_gpr", [] >; 86 } 87} 88 89// Swap no-ret is just store. Raw store to cached target 90// can only store on dword, which exactly matches swap_no_ret. 91defm RAT_ATOMIC_XCHG_INT : RAT_ATOMIC<1, 34, "ATOMIC_XCHG_INT">; 92defm RAT_ATOMIC_CMPXCHG_INT : RAT_ATOMIC<4, 36, "ATOMIC_CMPXCHG_INT">; 93defm RAT_ATOMIC_ADD : RAT_ATOMIC<7, 39, "ATOMIC_ADD">; 94defm RAT_ATOMIC_SUB : RAT_ATOMIC<8, 40, "ATOMIC_SUB">; 95defm RAT_ATOMIC_RSUB : RAT_ATOMIC<9, 41, "ATOMIC_RSUB">; 96defm RAT_ATOMIC_MIN_INT : RAT_ATOMIC<10, 42, "ATOMIC_MIN_INT">; 97defm RAT_ATOMIC_MIN_UINT : RAT_ATOMIC<11, 43, "ATOMIC_MIN_UINT">; 98defm RAT_ATOMIC_MAX_INT : RAT_ATOMIC<12, 44, "ATOMIC_MAX_INT">; 99defm RAT_ATOMIC_MAX_UINT : RAT_ATOMIC<13, 45, "ATOMIC_MAX_UINT">; 100defm RAT_ATOMIC_AND : RAT_ATOMIC<14, 46, "ATOMIC_AND">; 101defm RAT_ATOMIC_OR : RAT_ATOMIC<15, 47, "ATOMIC_OR">; 102defm RAT_ATOMIC_XOR : RAT_ATOMIC<16, 48, "ATOMIC_XOR">; 103defm RAT_ATOMIC_INC_UINT : RAT_ATOMIC<18, 50, "ATOMIC_INC_UINT">; 104defm RAT_ATOMIC_DEC_UINT : RAT_ATOMIC<19, 51, "ATOMIC_DEC_UINT">; 105 106} // End SubtargetPredicate = isEGorCayman 107 108//===----------------------------------------------------------------------===// 109// Evergreen Only instructions 110//===----------------------------------------------------------------------===// 111 112let SubtargetPredicate = isEG in { 113 114def RECIP_IEEE_eg : RECIP_IEEE_Common<0x86>; 115defm DIV_eg : DIV_Common<RECIP_IEEE_eg>; 116 117def MULLO_INT_eg : MULLO_INT_Common<0x8F>; 118def MULHI_INT_eg : MULHI_INT_Common<0x90>; 119def MULLO_UINT_eg : MULLO_UINT_Common<0x91>; 120def MULHI_UINT_eg : MULHI_UINT_Common<0x92>; 121def MULHI_UINT24_eg : MULHI_UINT24_Common<0xb2>; 122 123def RECIP_UINT_eg : RECIP_UINT_Common<0x94>; 124def RECIPSQRT_CLAMPED_eg : RECIPSQRT_CLAMPED_Common<0x87>; 125def EXP_IEEE_eg : EXP_IEEE_Common<0x81>; 126def LOG_IEEE_eg : LOG_IEEE_Common<0x83>; 127def RECIP_CLAMPED_eg : RECIP_CLAMPED_Common<0x84>; 128def RECIPSQRT_IEEE_eg : RECIPSQRT_IEEE_Common<0x89>; 129def : RsqPat<RECIPSQRT_IEEE_eg, f32>; 130def : SqrtPat<RECIPSQRT_IEEE_eg, RECIP_IEEE_eg>; 131 132def SIN_eg : SIN_Common<0x8D>; 133def COS_eg : COS_Common<0x8E>; 134 135def : POW_Common <LOG_IEEE_eg, EXP_IEEE_eg, MUL>; 136} // End SubtargetPredicate = isEG 137 138//===----------------------------------------------------------------------===// 139// Memory read/write instructions 140//===----------------------------------------------------------------------===// 141 142let usesCustomInserter = 1 in { 143 144// 32-bit store 145def RAT_WRITE_CACHELESS_32_eg : CF_MEM_RAT_CACHELESS <0x2, 0, 0x1, 146 (ins R600_TReg32_X:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop), 147 "STORE_RAW $rw_gpr, $index_gpr, $eop", 148 [(store_global i32:$rw_gpr, i32:$index_gpr)] 149>; 150 151// 64-bit store 152def RAT_WRITE_CACHELESS_64_eg : CF_MEM_RAT_CACHELESS <0x2, 0, 0x3, 153 (ins R600_Reg64:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop), 154 "STORE_RAW $rw_gpr.XY, $index_gpr, $eop", 155 [(store_global v2i32:$rw_gpr, i32:$index_gpr)] 156>; 157 158//128-bit store 159def RAT_WRITE_CACHELESS_128_eg : CF_MEM_RAT_CACHELESS <0x2, 0, 0xf, 160 (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop), 161 "STORE_RAW $rw_gpr.XYZW, $index_gpr, $eop", 162 [(store_global v4i32:$rw_gpr, i32:$index_gpr)] 163>; 164 165def RAT_STORE_TYPED_eg: CF_MEM_RAT_STORE_TYPED<1>; 166 167} // End usesCustomInserter = 1 168 169class VTX_READ_eg <string name, dag outs> 170 : VTX_WORD0_eg, VTX_READ<name, outs, []> { 171 172 // Static fields 173 let VC_INST = 0; 174 let FETCH_TYPE = 2; 175 let FETCH_WHOLE_QUAD = 0; 176 let SRC_REL = 0; 177 // XXX: We can infer this field based on the SRC_GPR. This would allow us 178 // to store vertex addresses in any channel, not just X. 179 let SRC_SEL_X = 0; 180 181 let Inst{31-0} = Word0; 182} 183 184def VTX_READ_8_eg 185 : VTX_READ_eg <"VTX_READ_8 $dst_gpr, $src_gpr", 186 (outs R600_TReg32_X:$dst_gpr)> { 187 188 let MEGA_FETCH_COUNT = 1; 189 let DST_SEL_X = 0; 190 let DST_SEL_Y = 7; // Masked 191 let DST_SEL_Z = 7; // Masked 192 let DST_SEL_W = 7; // Masked 193 let DATA_FORMAT = 1; // FMT_8 194} 195 196def VTX_READ_16_eg 197 : VTX_READ_eg <"VTX_READ_16 $dst_gpr, $src_gpr", 198 (outs R600_TReg32_X:$dst_gpr)> { 199 let MEGA_FETCH_COUNT = 2; 200 let DST_SEL_X = 0; 201 let DST_SEL_Y = 7; // Masked 202 let DST_SEL_Z = 7; // Masked 203 let DST_SEL_W = 7; // Masked 204 let DATA_FORMAT = 5; // FMT_16 205 206} 207 208def VTX_READ_32_eg 209 : VTX_READ_eg <"VTX_READ_32 $dst_gpr, $src_gpr", 210 (outs R600_TReg32_X:$dst_gpr)> { 211 212 let MEGA_FETCH_COUNT = 4; 213 let DST_SEL_X = 0; 214 let DST_SEL_Y = 7; // Masked 215 let DST_SEL_Z = 7; // Masked 216 let DST_SEL_W = 7; // Masked 217 let DATA_FORMAT = 0xD; // COLOR_32 218 219 // This is not really necessary, but there were some GPU hangs that appeared 220 // to be caused by ALU instructions in the next instruction group that wrote 221 // to the $src_gpr registers of the VTX_READ. 222 // e.g. 223 // %t3_x = VTX_READ_PARAM_32_eg killed %t2_x, 24 224 // %t2_x = MOV %zero 225 //Adding this constraint prevents this from happening. 226 let Constraints = "$src_gpr.ptr = $dst_gpr"; 227} 228 229def VTX_READ_64_eg 230 : VTX_READ_eg <"VTX_READ_64 $dst_gpr.XY, $src_gpr", 231 (outs R600_Reg64:$dst_gpr)> { 232 233 let MEGA_FETCH_COUNT = 8; 234 let DST_SEL_X = 0; 235 let DST_SEL_Y = 1; 236 let DST_SEL_Z = 7; 237 let DST_SEL_W = 7; 238 let DATA_FORMAT = 0x1D; // COLOR_32_32 239} 240 241def VTX_READ_128_eg 242 : VTX_READ_eg <"VTX_READ_128 $dst_gpr.XYZW, $src_gpr", 243 (outs R600_Reg128:$dst_gpr)> { 244 245 let MEGA_FETCH_COUNT = 16; 246 let DST_SEL_X = 0; 247 let DST_SEL_Y = 1; 248 let DST_SEL_Z = 2; 249 let DST_SEL_W = 3; 250 let DATA_FORMAT = 0x22; // COLOR_32_32_32_32 251 252 // XXX: Need to force VTX_READ_128 instructions to write to the same register 253 // that holds its buffer address to avoid potential hangs. We can't use 254 // the same constraint as VTX_READ_32_eg, because the $src_gpr.ptr and $dst 255 // registers are different sizes. 256} 257 258//===----------------------------------------------------------------------===// 259// VTX Read from parameter memory space 260//===----------------------------------------------------------------------===// 261def : EGPat<(i32:$dst_gpr (vtx_id3_az_extloadi8 ADDRVTX_READ:$src_gpr)), 262 (VTX_READ_8_eg MEMxi:$src_gpr, 3)>; 263def : EGPat<(i32:$dst_gpr (vtx_id3_az_extloadi16 ADDRVTX_READ:$src_gpr)), 264 (VTX_READ_16_eg MEMxi:$src_gpr, 3)>; 265def : EGPat<(i32:$dst_gpr (vtx_id3_load ADDRVTX_READ:$src_gpr)), 266 (VTX_READ_32_eg MEMxi:$src_gpr, 3)>; 267def : EGPat<(v2i32:$dst_gpr (vtx_id3_load ADDRVTX_READ:$src_gpr)), 268 (VTX_READ_64_eg MEMxi:$src_gpr, 3)>; 269def : EGPat<(v4i32:$dst_gpr (vtx_id3_load ADDRVTX_READ:$src_gpr)), 270 (VTX_READ_128_eg MEMxi:$src_gpr, 3)>; 271 272//===----------------------------------------------------------------------===// 273// VTX Read from constant memory space 274//===----------------------------------------------------------------------===// 275def : EGPat<(i32:$dst_gpr (vtx_id2_az_extloadi8 ADDRVTX_READ:$src_gpr)), 276 (VTX_READ_8_eg MEMxi:$src_gpr, 2)>; 277def : EGPat<(i32:$dst_gpr (vtx_id2_az_extloadi16 ADDRVTX_READ:$src_gpr)), 278 (VTX_READ_16_eg MEMxi:$src_gpr, 2)>; 279def : EGPat<(i32:$dst_gpr (vtx_id2_load ADDRVTX_READ:$src_gpr)), 280 (VTX_READ_32_eg MEMxi:$src_gpr, 2)>; 281def : EGPat<(v2i32:$dst_gpr (vtx_id2_load ADDRVTX_READ:$src_gpr)), 282 (VTX_READ_64_eg MEMxi:$src_gpr, 2)>; 283def : EGPat<(v4i32:$dst_gpr (vtx_id2_load ADDRVTX_READ:$src_gpr)), 284 (VTX_READ_128_eg MEMxi:$src_gpr, 2)>; 285 286//===----------------------------------------------------------------------===// 287// VTX Read from global memory space 288//===----------------------------------------------------------------------===// 289def : EGPat<(i32:$dst_gpr (vtx_id1_az_extloadi8 ADDRVTX_READ:$src_gpr)), 290 (VTX_READ_8_eg MEMxi:$src_gpr, 1)>; 291def : EGPat<(i32:$dst_gpr (vtx_id1_az_extloadi16 ADDRVTX_READ:$src_gpr)), 292 (VTX_READ_16_eg MEMxi:$src_gpr, 1)>; 293def : EGPat<(i32:$dst_gpr (vtx_id1_load ADDRVTX_READ:$src_gpr)), 294 (VTX_READ_32_eg MEMxi:$src_gpr, 1)>; 295def : EGPat<(v2i32:$dst_gpr (vtx_id1_load ADDRVTX_READ:$src_gpr)), 296 (VTX_READ_64_eg MEMxi:$src_gpr, 1)>; 297def : EGPat<(v4i32:$dst_gpr (vtx_id1_load ADDRVTX_READ:$src_gpr)), 298 (VTX_READ_128_eg MEMxi:$src_gpr, 1)>; 299 300//===----------------------------------------------------------------------===// 301// Evergreen / Cayman Instructions 302//===----------------------------------------------------------------------===// 303 304let SubtargetPredicate = isEGorCayman in { 305 306multiclass AtomicPat<Instruction inst_ret, Instruction inst_noret, 307 SDPatternOperator node_ret, SDPatternOperator node_noret> { 308 // FIXME: Add _RTN version. We need per WI scratch location to store the old value 309 // EXTRACT_SUBREG here is dummy, we know the node has no uses 310 def : EGOrCaymanPat<(i32 (node_noret i32:$ptr, i32:$data)), 311 (EXTRACT_SUBREG (inst_noret 312 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), $data, sub0), $ptr), sub1)>; 313} 314multiclass AtomicIncDecPat<Instruction inst_ret, Instruction inst_noret, 315 SDPatternOperator node_ret, SDPatternOperator node_noret, int C> { 316 // FIXME: Add _RTN version. We need per WI scratch location to store the old value 317 // EXTRACT_SUBREG here is dummy, we know the node has no uses 318 def : EGOrCaymanPat<(i32 (node_noret i32:$ptr, C)), 319 (EXTRACT_SUBREG (inst_noret 320 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), (MOV_IMM_I32 -1), sub0), $ptr), sub1)>; 321} 322 323// CMPSWAP is pattern is special 324// EXTRACT_SUBREG here is dummy, we know the node has no uses 325// FIXME: Add _RTN version. We need per WI scratch location to store the old value 326def : EGOrCaymanPat<(i32 (atomic_cmp_swap_global_noret i32:$ptr, i32:$cmp, i32:$data)), 327 (EXTRACT_SUBREG (RAT_ATOMIC_CMPXCHG_INT_NORET 328 (INSERT_SUBREG 329 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), $cmp, sub3), 330 $data, sub0), 331 $ptr), sub1)>; 332 333defm AtomicSwapPat : AtomicPat <RAT_ATOMIC_XCHG_INT_RTN, 334 RAT_ATOMIC_XCHG_INT_NORET, 335 atomic_swap_global_ret_32, 336 atomic_swap_global_noret_32>; 337defm AtomicAddPat : AtomicPat <RAT_ATOMIC_ADD_RTN, RAT_ATOMIC_ADD_NORET, 338 atomic_load_add_global_ret_32, atomic_load_add_global_noret_32>; 339defm AtomicSubPat : AtomicPat <RAT_ATOMIC_SUB_RTN, RAT_ATOMIC_SUB_NORET, 340 atomic_load_sub_global_ret_32, atomic_load_sub_global_noret_32>; 341defm AtomicMinPat : AtomicPat <RAT_ATOMIC_MIN_INT_RTN, 342 RAT_ATOMIC_MIN_INT_NORET, 343 atomic_load_min_global_ret_32, atomic_load_min_global_noret_32>; 344defm AtomicUMinPat : AtomicPat <RAT_ATOMIC_MIN_UINT_RTN, 345 RAT_ATOMIC_MIN_UINT_NORET, 346 atomic_load_umin_global_ret_32, atomic_load_umin_global_noret_32>; 347defm AtomicMaxPat : AtomicPat <RAT_ATOMIC_MAX_INT_RTN, 348 RAT_ATOMIC_MAX_INT_NORET, 349 atomic_load_max_global_ret_32, atomic_load_max_global_noret_32>; 350defm AtomicUMaxPat : AtomicPat <RAT_ATOMIC_MAX_UINT_RTN, 351 RAT_ATOMIC_MAX_UINT_NORET, 352 atomic_load_umax_global_ret_32, atomic_load_umax_global_noret_32>; 353defm AtomicAndPat : AtomicPat <RAT_ATOMIC_AND_RTN, RAT_ATOMIC_AND_NORET, 354 atomic_load_and_global_ret_32, atomic_load_and_global_noret_32>; 355defm AtomicOrPat : AtomicPat <RAT_ATOMIC_OR_RTN, RAT_ATOMIC_OR_NORET, 356 atomic_load_or_global_ret_32, atomic_load_or_global_noret_32>; 357defm AtomicXorPat : AtomicPat <RAT_ATOMIC_XOR_RTN, RAT_ATOMIC_XOR_NORET, 358 atomic_load_xor_global_ret_32, atomic_load_xor_global_noret_32>; 359defm AtomicIncAddPat : AtomicIncDecPat <RAT_ATOMIC_INC_UINT_RTN, 360 RAT_ATOMIC_INC_UINT_NORET, 361 atomic_load_add_global_ret_32, 362 atomic_load_add_global_noret_32, 1>; 363defm AtomicIncSubPat : AtomicIncDecPat <RAT_ATOMIC_INC_UINT_RTN, 364 RAT_ATOMIC_INC_UINT_NORET, 365 atomic_load_sub_global_ret_32, 366 atomic_load_sub_global_noret_32, -1>; 367defm AtomicDecAddPat : AtomicIncDecPat <RAT_ATOMIC_DEC_UINT_RTN, 368 RAT_ATOMIC_DEC_UINT_NORET, 369 atomic_load_add_global_ret_32, 370 atomic_load_add_global_noret_32, -1>; 371defm AtomicDecSubPat : AtomicIncDecPat <RAT_ATOMIC_DEC_UINT_RTN, 372 RAT_ATOMIC_DEC_UINT_NORET, 373 atomic_load_sub_global_ret_32, 374 atomic_load_sub_global_noret_32, 1>; 375 376// Should be predicated on FeatureFP64 377// def FMA_64 : R600_3OP < 378// 0xA, "FMA_64", 379// [(set f64:$dst, (fma f64:$src0, f64:$src1, f64:$src2))] 380// >; 381 382// BFE_UINT - bit_extract, an optimization for mask and shift 383// Src0 = Input 384// Src1 = Offset 385// Src2 = Width 386// 387// bit_extract = (Input << (32 - Offset - Width)) >> (32 - Width) 388// 389// Example Usage: 390// (Offset, Width) 391// 392// (0, 8) = (Input << 24) >> 24 = (Input & 0xff) >> 0 393// (8, 8) = (Input << 16) >> 24 = (Input & 0xffff) >> 8 394// (16, 8) = (Input << 8) >> 24 = (Input & 0xffffff) >> 16 395// (24, 8) = (Input << 0) >> 24 = (Input & 0xffffffff) >> 24 396def BFE_UINT_eg : R600_3OP <0x4, "BFE_UINT", 397 [(set i32:$dst, (AMDGPUbfe_u32 i32:$src0, i32:$src1, i32:$src2))], 398 VecALU 399>; 400 401def BFE_INT_eg : R600_3OP <0x5, "BFE_INT", 402 [(set i32:$dst, (AMDGPUbfe_i32 i32:$src0, i32:$src1, i32:$src2))], 403 VecALU 404>; 405 406// Bitfield extract patterns 407 408def : AMDGPUPat < 409 (and (i32 (srl i32:$src, i32:$rshift)), IMMZeroBasedBitfieldMask:$mask), 410 (BFE_UINT_eg $src, $rshift, (MOV_IMM_I32 (i32 (IMMPopCount $mask)))) 411>; 412 413// x & ((1 << y) - 1) 414def : AMDGPUPat < 415 (and i32:$src, (add_oneuse (shl_oneuse 1, i32:$width), -1)), 416 (BFE_UINT_eg $src, (MOV_IMM_I32 (i32 0)), $width) 417>; 418 419// x & ~(-1 << y) 420def : AMDGPUPat < 421 (and i32:$src, (xor_oneuse (shl_oneuse -1, i32:$width), -1)), 422 (BFE_UINT_eg $src, (MOV_IMM_I32 (i32 0)), $width) 423>; 424 425// x & (-1 >> (bitwidth - y)) 426def : AMDGPUPat < 427 (and i32:$src, (srl_oneuse -1, (sub 32, i32:$width))), 428 (BFE_UINT_eg $src, (MOV_IMM_I32 (i32 0)), $width) 429>; 430 431// x << (bitwidth - y) >> (bitwidth - y) 432def : AMDGPUPat < 433 (srl (shl_oneuse i32:$src, (sub 32, i32:$width)), (sub 32, i32:$width)), 434 (BFE_UINT_eg $src, (MOV_IMM_I32 (i32 0)), $width) 435>; 436 437def : AMDGPUPat < 438 (sra (shl_oneuse i32:$src, (sub 32, i32:$width)), (sub 32, i32:$width)), 439 (BFE_INT_eg $src, (MOV_IMM_I32 (i32 0)), $width) 440>; 441 442def BFI_INT_eg : R600_3OP <0x06, "BFI_INT", 443 [(set i32:$dst, (AMDGPUbfi i32:$src0, i32:$src1, i32:$src2))], 444 VecALU 445>; 446 447def : EGOrCaymanPat<(i32 (sext_inreg i32:$src, i1)), 448 (BFE_INT_eg i32:$src, (i32 ZERO), (i32 ONE_INT))>; 449def : EGOrCaymanPat<(i32 (sext_inreg i32:$src, i8)), 450 (BFE_INT_eg i32:$src, (i32 ZERO), (MOV_IMM_I32 8))>; 451def : EGOrCaymanPat<(i32 (sext_inreg i32:$src, i16)), 452 (BFE_INT_eg i32:$src, (i32 ZERO), (MOV_IMM_I32 16))>; 453 454// BFI patterns 455 456// Definition from ISA doc: 457// (y & x) | (z & ~x) 458def : AMDGPUPat < 459 (or (and i32:$y, i32:$x), (and i32:$z, (not i32:$x))), 460 (BFI_INT_eg $x, $y, $z) 461>; 462 463// 64-bit version 464def : AMDGPUPat < 465 (or (and i64:$y, i64:$x), (and i64:$z, (not i64:$x))), 466 (REG_SEQUENCE R600_Reg64, 467 (BFI_INT_eg (i32 (EXTRACT_SUBREG R600_Reg64:$x, sub0)), 468 (i32 (EXTRACT_SUBREG R600_Reg64:$y, sub0)), 469 (i32 (EXTRACT_SUBREG R600_Reg64:$z, sub0))), sub0, 470 (BFI_INT_eg (i32 (EXTRACT_SUBREG R600_Reg64:$x, sub1)), 471 (i32 (EXTRACT_SUBREG R600_Reg64:$y, sub1)), 472 (i32 (EXTRACT_SUBREG R600_Reg64:$z, sub1))), sub1) 473>; 474 475// SHA-256 Ch function 476// z ^ (x & (y ^ z)) 477def : AMDGPUPat < 478 (xor i32:$z, (and i32:$x, (xor i32:$y, i32:$z))), 479 (BFI_INT_eg $x, $y, $z) 480>; 481 482// 64-bit version 483def : AMDGPUPat < 484 (xor i64:$z, (and i64:$x, (xor i64:$y, i64:$z))), 485 (REG_SEQUENCE R600_Reg64, 486 (BFI_INT_eg (i32 (EXTRACT_SUBREG R600_Reg64:$x, sub0)), 487 (i32 (EXTRACT_SUBREG R600_Reg64:$y, sub0)), 488 (i32 (EXTRACT_SUBREG R600_Reg64:$z, sub0))), sub0, 489 (BFI_INT_eg (i32 (EXTRACT_SUBREG R600_Reg64:$x, sub1)), 490 (i32 (EXTRACT_SUBREG R600_Reg64:$y, sub1)), 491 (i32 (EXTRACT_SUBREG R600_Reg64:$z, sub1))), sub1) 492>; 493 494def : AMDGPUPat < 495 (fcopysign f32:$src0, f32:$src1), 496 (BFI_INT_eg (MOV_IMM_I32 (i32 0x7fffffff)), $src0, $src1) 497>; 498 499def : AMDGPUPat < 500 (fcopysign f32:$src0, f64:$src1), 501 (BFI_INT_eg (MOV_IMM_I32 (i32 0x7fffffff)), $src0, 502 (i32 (EXTRACT_SUBREG R600_Reg64:$src1, sub1))) 503>; 504 505def : AMDGPUPat < 506 (fcopysign f64:$src0, f64:$src1), 507 (REG_SEQUENCE R600_Reg64, 508 (i32 (EXTRACT_SUBREG $src0, sub0)), sub0, 509 (BFI_INT_eg (MOV_IMM_I32 (i32 0x7fffffff)), 510 (i32 (EXTRACT_SUBREG R600_Reg64:$src0, sub1)), 511 (i32 (EXTRACT_SUBREG R600_Reg64:$src1, sub1))), sub1) 512>; 513 514def : AMDGPUPat < 515 (fcopysign f64:$src0, f32:$src1), 516 (REG_SEQUENCE R600_Reg64, 517 (i32 (EXTRACT_SUBREG $src0, sub0)), sub0, 518 (BFI_INT_eg (MOV_IMM_I32 (i32 0x7fffffff)), 519 (i32 (EXTRACT_SUBREG R600_Reg64:$src0, sub1)), 520 $src1), sub1) 521>; 522 523def BFM_INT_eg : R600_2OP <0xA0, "BFM_INT", 524 [(set i32:$dst, (AMDGPUbfm i32:$src0, i32:$src1))], 525 VecALU 526>; 527 528def MULADD_UINT24_eg : R600_3OP <0x10, "MULADD_UINT24", 529 [(set i32:$dst, (AMDGPUmad_u24 i32:$src0, i32:$src1, i32:$src2))], VecALU 530>; 531 532def : UMad24Pat<MULADD_UINT24_eg>; 533 534def BIT_ALIGN_INT_eg : R600_3OP <0xC, "BIT_ALIGN_INT", [], VecALU>; 535def : AMDGPUPat < 536 (fshr i32:$src0, i32:$src1, i32:$src2), 537 (BIT_ALIGN_INT_eg $src0, $src1, $src2) 538>; 539def : ROTRPattern <BIT_ALIGN_INT_eg>; 540def MULADD_eg : MULADD_Common<0x14>; 541def MULADD_IEEE_eg : MULADD_IEEE_Common<0x18>; 542def FMA_eg : FMA_Common<0x7>; 543def ASHR_eg : ASHR_Common<0x15>; 544def LSHR_eg : LSHR_Common<0x16>; 545def LSHL_eg : LSHL_Common<0x17>; 546def CNDE_eg : CNDE_Common<0x19>; 547def CNDGT_eg : CNDGT_Common<0x1A>; 548def CNDGE_eg : CNDGE_Common<0x1B>; 549def MUL_LIT_eg : MUL_LIT_Common<0x1F>; 550def LOG_CLAMPED_eg : LOG_CLAMPED_Common<0x82>; 551def MUL_UINT24_eg : R600_2OP <0xB5, "MUL_UINT24", 552 [(set i32:$dst, (AMDGPUmul_u24 i32:$src0, i32:$src1))], VecALU 553>; 554def DOT4_eg : DOT4_Common<0xBE>; 555defm CUBE_eg : CUBE_Common<0xC0>; 556 557 558def ADDC_UINT : R600_2OP_Helper <0x52, "ADDC_UINT", AMDGPUcarry>; 559def SUBB_UINT : R600_2OP_Helper <0x53, "SUBB_UINT", AMDGPUborrow>; 560 561def FLT32_TO_FLT16 : R600_1OP_Helper <0xA2, "FLT32_TO_FLT16", AMDGPUfp_to_f16, VecALU>; 562def FLT16_TO_FLT32 : R600_1OP_Helper <0xA3, "FLT16_TO_FLT32", f16_to_fp, VecALU>; 563def BCNT_INT : R600_1OP_Helper <0xAA, "BCNT_INT", ctpop, VecALU>; 564def FFBH_UINT : R600_1OP_Helper <0xAB, "FFBH_UINT", AMDGPUffbh_u32, VecALU>; 565def FFBL_INT : R600_1OP_Helper <0xAC, "FFBL_INT", AMDGPUffbl_b32, VecALU>; 566 567let hasSideEffects = 1 in { 568 def MOVA_INT_eg : R600_1OP <0xCC, "MOVA_INT", [], VecALU>; 569} 570 571def FLT_TO_INT_eg : FLT_TO_INT_Common<0x50> { 572 let Pattern = []; 573 let Itinerary = AnyALU; 574} 575 576def INT_TO_FLT_eg : INT_TO_FLT_Common<0x9B>; 577 578def FLT_TO_UINT_eg : FLT_TO_UINT_Common<0x9A> { 579 let Pattern = []; 580} 581 582def UINT_TO_FLT_eg : UINT_TO_FLT_Common<0x9C>; 583 584def GROUP_BARRIER : InstR600 < 585 (outs), (ins), " GROUP_BARRIER", [(int_r600_group_barrier)], AnyALU>, 586 R600ALU_Word0, 587 R600ALU_Word1_OP2 <0x54> { 588 589 let dst = 0; 590 let dst_rel = 0; 591 let src0 = 0; 592 let src0_rel = 0; 593 let src0_neg = 0; 594 let src0_abs = 0; 595 let src1 = 0; 596 let src1_rel = 0; 597 let src1_neg = 0; 598 let src1_abs = 0; 599 let write = 0; 600 let omod = 0; 601 let clamp = 0; 602 let last = 1; 603 let bank_swizzle = 0; 604 let pred_sel = 0; 605 let update_exec_mask = 0; 606 let update_pred = 0; 607 608 let Inst{31-0} = Word0; 609 let Inst{63-32} = Word1; 610 611 let ALUInst = 1; 612} 613 614//===----------------------------------------------------------------------===// 615// LDS Instructions 616//===----------------------------------------------------------------------===// 617class R600_LDS <bits<6> op, dag outs, dag ins, string asm, 618 list<dag> pattern = []> : 619 620 InstR600 <outs, ins, asm, pattern, XALU>, 621 R600_ALU_LDS_Word0, 622 R600LDS_Word1 { 623 624 bits<6> offset = 0; 625 let lds_op = op; 626 627 let Word1{27} = offset{0}; 628 let Word1{12} = offset{1}; 629 let Word1{28} = offset{2}; 630 let Word1{31} = offset{3}; 631 let Word0{12} = offset{4}; 632 let Word0{25} = offset{5}; 633 634 635 let Inst{31-0} = Word0; 636 let Inst{63-32} = Word1; 637 638 let ALUInst = 1; 639 let HasNativeOperands = 1; 640 let UseNamedOperandTable = 1; 641} 642 643class R600_LDS_1A <bits<6> lds_op, string name, list<dag> pattern> : R600_LDS < 644 lds_op, 645 (outs R600_Reg32:$dst), 646 (ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel, 647 LAST:$last, R600_Pred:$pred_sel, 648 BANK_SWIZZLE:$bank_swizzle), 649 " "#name#" $last OQAP, $src0$src0_rel $pred_sel", 650 pattern 651 > { 652 653 let src1 = 0; 654 let src1_rel = 0; 655 let src2 = 0; 656 let src2_rel = 0; 657 658 let usesCustomInserter = 1; 659 let LDS_1A = 1; 660 let DisableEncoding = "$dst"; 661} 662 663class R600_LDS_1A1D <bits<6> lds_op, dag outs, string name, list<dag> pattern, 664 string dst =""> : 665 R600_LDS < 666 lds_op, outs, 667 (ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel, 668 R600_Reg32:$src1, REL:$src1_rel, SEL:$src1_sel, 669 LAST:$last, R600_Pred:$pred_sel, 670 BANK_SWIZZLE:$bank_swizzle), 671 " "#name#" $last "#dst#"$src0$src0_rel, $src1$src1_rel, $pred_sel", 672 pattern 673 > { 674 675 field string BaseOp; 676 677 let src2 = 0; 678 let src2_rel = 0; 679 let LDS_1A1D = 1; 680} 681 682class R600_LDS_1A1D_NORET <bits<6> lds_op, string name, list<dag> pattern> : 683 R600_LDS_1A1D <lds_op, (outs), name, pattern> { 684 let BaseOp = name; 685} 686 687class R600_LDS_1A1D_RET <bits<6> lds_op, string name, list<dag> pattern> : 688 R600_LDS_1A1D <lds_op, (outs R600_Reg32:$dst), name#"_RET", pattern, "OQAP, "> { 689 690 let BaseOp = name; 691 let usesCustomInserter = 1; 692 let DisableEncoding = "$dst"; 693} 694 695class R600_LDS_1A2D <bits<6> lds_op, dag outs, string name, list<dag> pattern, 696 string dst =""> : 697 R600_LDS < 698 lds_op, outs, 699 (ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel, 700 R600_Reg32:$src1, REL:$src1_rel, SEL:$src1_sel, 701 R600_Reg32:$src2, REL:$src2_rel, SEL:$src2_sel, 702 LAST:$last, R600_Pred:$pred_sel, BANK_SWIZZLE:$bank_swizzle), 703 " "#name# "$last "#dst#"$src0$src0_rel, $src1$src1_rel, $src2$src2_rel, $pred_sel", 704 pattern> { 705 706 field string BaseOp; 707 708 let LDS_1A1D = 0; 709 let LDS_1A2D = 1; 710} 711 712class R600_LDS_1A2D_NORET <bits<6> lds_op, string name, list<dag> pattern> : 713 R600_LDS_1A2D <lds_op, (outs), name, pattern> { 714 let BaseOp = name; 715} 716 717class R600_LDS_1A2D_RET <bits<6> lds_op, string name, list<dag> pattern> : 718 R600_LDS_1A2D <lds_op, (outs R600_Reg32:$dst), name, pattern> { 719 720 let BaseOp = name; 721 let usesCustomInserter = 1; 722 let DisableEncoding = "$dst"; 723} 724 725def LDS_ADD : R600_LDS_1A1D_NORET <0x0, "LDS_ADD", [] >; 726def LDS_SUB : R600_LDS_1A1D_NORET <0x1, "LDS_SUB", [] >; 727def LDS_AND : R600_LDS_1A1D_NORET <0x9, "LDS_AND", [] >; 728def LDS_OR : R600_LDS_1A1D_NORET <0xa, "LDS_OR", [] >; 729def LDS_XOR : R600_LDS_1A1D_NORET <0xb, "LDS_XOR", [] >; 730def LDS_WRXCHG: R600_LDS_1A1D_NORET <0xd, "LDS_WRXCHG", [] >; 731def LDS_CMPST: R600_LDS_1A2D_NORET <0x10, "LDS_CMPST", [] >; 732def LDS_MIN_INT : R600_LDS_1A1D_NORET <0x5, "LDS_MIN_INT", [] >; 733def LDS_MAX_INT : R600_LDS_1A1D_NORET <0x6, "LDS_MAX_INT", [] >; 734def LDS_MIN_UINT : R600_LDS_1A1D_NORET <0x7, "LDS_MIN_UINT", [] >; 735def LDS_MAX_UINT : R600_LDS_1A1D_NORET <0x8, "LDS_MAX_UINT", [] >; 736def LDS_WRITE : R600_LDS_1A1D_NORET <0xD, "LDS_WRITE", 737 [(store_local (i32 R600_Reg32:$src1), R600_Reg32:$src0)] 738>; 739def LDS_BYTE_WRITE : R600_LDS_1A1D_NORET<0x12, "LDS_BYTE_WRITE", 740 [(truncstorei8_local i32:$src1, i32:$src0)] 741>; 742def LDS_SHORT_WRITE : R600_LDS_1A1D_NORET<0x13, "LDS_SHORT_WRITE", 743 [(truncstorei16_local i32:$src1, i32:$src0)] 744>; 745def LDS_ADD_RET : R600_LDS_1A1D_RET <0x20, "LDS_ADD", 746 [(set i32:$dst, (atomic_load_add_local_32 i32:$src0, i32:$src1))] 747>; 748def LDS_SUB_RET : R600_LDS_1A1D_RET <0x21, "LDS_SUB", 749 [(set i32:$dst, (atomic_load_sub_local_32 i32:$src0, i32:$src1))] 750>; 751def LDS_AND_RET : R600_LDS_1A1D_RET <0x29, "LDS_AND", 752 [(set i32:$dst, (atomic_load_and_local_32 i32:$src0, i32:$src1))] 753>; 754def LDS_OR_RET : R600_LDS_1A1D_RET <0x2a, "LDS_OR", 755 [(set i32:$dst, (atomic_load_or_local_32 i32:$src0, i32:$src1))] 756>; 757def LDS_XOR_RET : R600_LDS_1A1D_RET <0x2b, "LDS_XOR", 758 [(set i32:$dst, (atomic_load_xor_local_32 i32:$src0, i32:$src1))] 759>; 760def LDS_MIN_INT_RET : R600_LDS_1A1D_RET <0x25, "LDS_MIN_INT", 761 [(set i32:$dst, (atomic_load_min_local_32 i32:$src0, i32:$src1))] 762>; 763def LDS_MAX_INT_RET : R600_LDS_1A1D_RET <0x26, "LDS_MAX_INT", 764 [(set i32:$dst, (atomic_load_max_local_32 i32:$src0, i32:$src1))] 765>; 766def LDS_MIN_UINT_RET : R600_LDS_1A1D_RET <0x27, "LDS_MIN_UINT", 767 [(set i32:$dst, (atomic_load_umin_local_32 i32:$src0, i32:$src1))] 768>; 769def LDS_MAX_UINT_RET : R600_LDS_1A1D_RET <0x28, "LDS_MAX_UINT", 770 [(set i32:$dst, (atomic_load_umax_local_32 i32:$src0, i32:$src1))] 771>; 772def LDS_WRXCHG_RET : R600_LDS_1A1D_RET <0x2d, "LDS_WRXCHG", 773 [(set i32:$dst, (atomic_swap_local_32 i32:$src0, i32:$src1))] 774>; 775def LDS_CMPST_RET : R600_LDS_1A2D_RET <0x30, "LDS_CMPST", 776 [(set i32:$dst, (atomic_cmp_swap_local_32 i32:$src0, i32:$src1, i32:$src2))] 777>; 778def LDS_READ_RET : R600_LDS_1A <0x32, "LDS_READ_RET", 779 [(set (i32 R600_Reg32:$dst), (load_local R600_Reg32:$src0))] 780>; 781def LDS_BYTE_READ_RET : R600_LDS_1A <0x36, "LDS_BYTE_READ_RET", 782 [(set i32:$dst, (sextloadi8_local i32:$src0))] 783>; 784def LDS_UBYTE_READ_RET : R600_LDS_1A <0x37, "LDS_UBYTE_READ_RET", 785 [(set i32:$dst, (az_extloadi8_local i32:$src0))] 786>; 787def LDS_SHORT_READ_RET : R600_LDS_1A <0x38, "LDS_SHORT_READ_RET", 788 [(set i32:$dst, (sextloadi16_local i32:$src0))] 789>; 790def LDS_USHORT_READ_RET : R600_LDS_1A <0x39, "LDS_USHORT_READ_RET", 791 [(set i32:$dst, (az_extloadi16_local i32:$src0))] 792>; 793 794// TRUNC is used for the FLT_TO_INT instructions to work around a 795// perceived problem where the rounding modes are applied differently 796// depending on the instruction and the slot they are in. 797// See: 798// https://bugs.freedesktop.org/show_bug.cgi?id=50232 799// Mesa commit: a1a0974401c467cb86ef818f22df67c21774a38c 800// 801// XXX: Lowering SELECT_CC will sometimes generate fp_to_[su]int nodes, 802// which do not need to be truncated since the fp values are 0.0f or 1.0f. 803// We should look into handling these cases separately. 804def : EGOrCaymanPat<(fp_to_sint f32:$src0), (FLT_TO_INT_eg (TRUNC $src0))>; 805 806def : EGOrCaymanPat<(fp_to_uint f32:$src0), (FLT_TO_UINT_eg (TRUNC $src0))>; 807 808// SHA-256 Ma patterns 809 810// ((x & z) | (y & (x | z))) -> BFI (XOR x, y), z, y 811def : AMDGPUPat < 812 (or (and i32:$x, i32:$z), (and i32:$y, (or i32:$x, i32:$z))), 813 (BFI_INT_eg (XOR_INT i32:$x, i32:$y), i32:$z, i32:$y) 814>; 815 816def : AMDGPUPat < 817 (or (and i64:$x, i64:$z), (and i64:$y, (or i64:$x, i64:$z))), 818 (REG_SEQUENCE R600_Reg64, 819 (BFI_INT_eg (XOR_INT (i32 (EXTRACT_SUBREG R600_Reg64:$x, sub0)), 820 (i32 (EXTRACT_SUBREG R600_Reg64:$y, sub0))), 821 (i32 (EXTRACT_SUBREG R600_Reg64:$z, sub0)), 822 (i32 (EXTRACT_SUBREG R600_Reg64:$y, sub0))), sub0, 823 (BFI_INT_eg (XOR_INT (i32 (EXTRACT_SUBREG R600_Reg64:$x, sub1)), 824 (i32 (EXTRACT_SUBREG R600_Reg64:$y, sub1))), 825 (i32 (EXTRACT_SUBREG R600_Reg64:$z, sub1)), 826 (i32 (EXTRACT_SUBREG R600_Reg64:$y, sub1))), sub1) 827>; 828 829def EG_ExportSwz : ExportSwzInst { 830 let Word1{19-16} = 0; // BURST_COUNT 831 let Word1{20} = 0; // VALID_PIXEL_MODE 832 let Word1{21} = eop; 833 let Word1{29-22} = inst; 834 let Word1{30} = 0; // MARK 835 let Word1{31} = 1; // BARRIER 836} 837defm : ExportPattern<EG_ExportSwz, 83>; 838 839def EG_ExportBuf : ExportBufInst { 840 let Word1{19-16} = 0; // BURST_COUNT 841 let Word1{20} = 0; // VALID_PIXEL_MODE 842 let Word1{21} = eop; 843 let Word1{29-22} = inst; 844 let Word1{30} = 0; // MARK 845 let Word1{31} = 1; // BARRIER 846} 847defm : SteamOutputExportPattern<EG_ExportBuf, 0x40, 0x41, 0x42, 0x43>; 848 849def CF_TC_EG : CF_CLAUSE_EG<1, (ins i32imm:$ADDR, i32imm:$COUNT), 850 "TEX $COUNT @$ADDR"> { 851 let POP_COUNT = 0; 852} 853def CF_VC_EG : CF_CLAUSE_EG<2, (ins i32imm:$ADDR, i32imm:$COUNT), 854 "VTX $COUNT @$ADDR"> { 855 let POP_COUNT = 0; 856} 857def WHILE_LOOP_EG : CF_CLAUSE_EG<6, (ins i32imm:$ADDR), 858 "LOOP_START_DX10 @$ADDR"> { 859 let POP_COUNT = 0; 860 let COUNT = 0; 861} 862def END_LOOP_EG : CF_CLAUSE_EG<5, (ins i32imm:$ADDR), "END_LOOP @$ADDR"> { 863 let POP_COUNT = 0; 864 let COUNT = 0; 865} 866def LOOP_BREAK_EG : CF_CLAUSE_EG<9, (ins i32imm:$ADDR), 867 "LOOP_BREAK @$ADDR"> { 868 let POP_COUNT = 0; 869 let COUNT = 0; 870} 871def CF_CONTINUE_EG : CF_CLAUSE_EG<8, (ins i32imm:$ADDR), 872 "CONTINUE @$ADDR"> { 873 let POP_COUNT = 0; 874 let COUNT = 0; 875} 876def CF_JUMP_EG : CF_CLAUSE_EG<10, (ins i32imm:$ADDR, i32imm:$POP_COUNT), 877 "JUMP @$ADDR POP:$POP_COUNT"> { 878 let COUNT = 0; 879} 880def CF_PUSH_EG : CF_CLAUSE_EG<11, (ins i32imm:$ADDR, i32imm:$POP_COUNT), 881 "PUSH @$ADDR POP:$POP_COUNT"> { 882 let COUNT = 0; 883} 884def CF_ELSE_EG : CF_CLAUSE_EG<13, (ins i32imm:$ADDR, i32imm:$POP_COUNT), 885 "ELSE @$ADDR POP:$POP_COUNT"> { 886 let COUNT = 0; 887} 888def CF_CALL_FS_EG : CF_CLAUSE_EG<19, (ins), "CALL_FS"> { 889 let ADDR = 0; 890 let COUNT = 0; 891 let POP_COUNT = 0; 892} 893def POP_EG : CF_CLAUSE_EG<14, (ins i32imm:$ADDR, i32imm:$POP_COUNT), 894 "POP @$ADDR POP:$POP_COUNT"> { 895 let COUNT = 0; 896} 897def CF_END_EG : CF_CLAUSE_EG<0, (ins), "CF_END"> { 898 let COUNT = 0; 899 let POP_COUNT = 0; 900 let ADDR = 0; 901 let END_OF_PROGRAM = 1; 902} 903 904} // End Predicates = [isEGorCayman] 905