1 //===-- AMDGPUMCTargetDesc.h - AMDGPU Target Descriptions -----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// Provides AMDGPU specific target descriptions.
11 //
12 //===----------------------------------------------------------------------===//
13 //
14 
15 #ifndef LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUMCTARGETDESC_H
16 #define LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUMCTARGETDESC_H
17 
18 #include <memory>
19 
20 namespace llvm {
21 class Target;
22 class MCAsmBackend;
23 class MCCodeEmitter;
24 class MCContext;
25 class MCInstrInfo;
26 class MCObjectTargetWriter;
27 class MCRegisterInfo;
28 class MCSubtargetInfo;
29 class MCTargetOptions;
30 
31 enum AMDGPUDwarfFlavour : unsigned { Wave64 = 0, Wave32 = 1 };
32 
33 MCRegisterInfo *createGCNMCRegisterInfo(AMDGPUDwarfFlavour DwarfFlavour);
34 
35 MCCodeEmitter *createAMDGPUMCCodeEmitter(const MCInstrInfo &MCII,
36                                          MCContext &Ctx);
37 
38 MCAsmBackend *createAMDGPUAsmBackend(const Target &T,
39                                      const MCSubtargetInfo &STI,
40                                      const MCRegisterInfo &MRI,
41                                      const MCTargetOptions &Options);
42 
43 std::unique_ptr<MCObjectTargetWriter>
44 createAMDGPUELFObjectWriter(bool Is64Bit, uint8_t OSABI,
45                             bool HasRelocationAddend);
46 } // namespace llvm
47 
48 #define GET_REGINFO_ENUM
49 #include "AMDGPUGenRegisterInfo.inc"
50 
51 #define GET_INSTRINFO_ENUM
52 #define GET_INSTRINFO_OPERAND_ENUM
53 #define GET_INSTRINFO_MC_HELPER_DECLS
54 #include "AMDGPUGenInstrInfo.inc"
55 
56 #define GET_SUBTARGETINFO_ENUM
57 #include "AMDGPUGenSubtargetInfo.inc"
58 
59 #endif
60