1//===-- MIMGInstructions.td - MIMG Instruction Definitions ----------------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9// MIMG-specific encoding families to distinguish between semantically 10// equivalent machine instructions with different encoding. 11// 12// - MIMGEncGfx6: encoding introduced with gfx6 (obsoleted for atomics in gfx8) 13// - MIMGEncGfx8: encoding introduced with gfx8 for atomics 14// - MIMGEncGfx10Default: gfx default (non-NSA) encoding 15// - MIMGEncGfx10NSA: gfx10 NSA encoding 16class MIMGEncoding; 17 18def MIMGEncGfx6 : MIMGEncoding; 19def MIMGEncGfx8 : MIMGEncoding; 20def MIMGEncGfx10Default : MIMGEncoding; 21def MIMGEncGfx10NSA : MIMGEncoding; 22 23def MIMGEncoding : GenericEnum { 24 let FilterClass = "MIMGEncoding"; 25} 26 27// Represent an ISA-level opcode, independent of the encoding and the 28// vdata/vaddr size. 29class MIMGBaseOpcode : PredicateControl { 30 MIMGBaseOpcode BaseOpcode = !cast<MIMGBaseOpcode>(NAME); 31 bit Store = 0; 32 bit Atomic = 0; 33 bit AtomicX2 = 0; // (f)cmpswap 34 bit Sampler = 0; 35 bit Gather4 = 0; 36 bits<8> NumExtraArgs = 0; 37 bit Gradients = 0; 38 bit G16 = 0; 39 bit Coordinates = 1; 40 bit LodOrClampOrMip = 0; 41 bit HasD16 = 0; 42} 43 44def MIMGBaseOpcode : GenericEnum { 45 let FilterClass = "MIMGBaseOpcode"; 46} 47 48def MIMGBaseOpcodesTable : GenericTable { 49 let FilterClass = "MIMGBaseOpcode"; 50 let CppTypeName = "MIMGBaseOpcodeInfo"; 51 let Fields = ["BaseOpcode", "Store", "Atomic", "AtomicX2", "Sampler", 52 "Gather4", "NumExtraArgs", "Gradients", "G16", "Coordinates", 53 "LodOrClampOrMip", "HasD16"]; 54 string TypeOf_BaseOpcode = "MIMGBaseOpcode"; 55 56 let PrimaryKey = ["BaseOpcode"]; 57 let PrimaryKeyName = "getMIMGBaseOpcodeInfo"; 58} 59 60def MIMGDim : GenericEnum { 61 let FilterClass = "AMDGPUDimProps"; 62} 63 64def MIMGDimInfoTable : GenericTable { 65 let FilterClass = "AMDGPUDimProps"; 66 let CppTypeName = "MIMGDimInfo"; 67 let Fields = ["Dim", "NumCoords", "NumGradients", "DA", "Encoding", "AsmSuffix"]; 68 string TypeOf_Dim = "MIMGDim"; 69 70 let PrimaryKey = ["Dim"]; 71 let PrimaryKeyName = "getMIMGDimInfo"; 72} 73 74def getMIMGDimInfoByEncoding : SearchIndex { 75 let Table = MIMGDimInfoTable; 76 let Key = ["Encoding"]; 77} 78 79def getMIMGDimInfoByAsmSuffix : SearchIndex { 80 let Table = MIMGDimInfoTable; 81 let Key = ["AsmSuffix"]; 82} 83 84class mimg <bits<8> si_gfx10, bits<8> vi = si_gfx10> { 85 field bits<8> SI_GFX10 = si_gfx10; 86 field bits<8> VI = vi; 87} 88 89class MIMGLZMapping<MIMGBaseOpcode l, MIMGBaseOpcode lz> { 90 MIMGBaseOpcode L = l; 91 MIMGBaseOpcode LZ = lz; 92} 93 94def MIMGLZMappingTable : GenericTable { 95 let FilterClass = "MIMGLZMapping"; 96 let CppTypeName = "MIMGLZMappingInfo"; 97 let Fields = ["L", "LZ"]; 98 string TypeOf_L = "MIMGBaseOpcode"; 99 string TypeOf_LZ = "MIMGBaseOpcode"; 100 101 let PrimaryKey = ["L"]; 102 let PrimaryKeyName = "getMIMGLZMappingInfo"; 103} 104 105class MIMGMIPMapping<MIMGBaseOpcode mip, MIMGBaseOpcode nonmip> { 106 MIMGBaseOpcode MIP = mip; 107 MIMGBaseOpcode NONMIP = nonmip; 108} 109 110def MIMGMIPMappingTable : GenericTable { 111 let FilterClass = "MIMGMIPMapping"; 112 let CppTypeName = "MIMGMIPMappingInfo"; 113 let Fields = ["MIP", "NONMIP"]; 114 string TypeOf_MIP = "MIMGBaseOpcode"; 115 string TypeOf_NONMIP = "MIMGBaseOpcode"; 116 117 let PrimaryKey = ["MIP"]; 118 let PrimaryKeyName = "getMIMGMIPMappingInfo"; 119} 120 121class MIMGG16Mapping<MIMGBaseOpcode g, MIMGBaseOpcode g16> { 122 MIMGBaseOpcode G = g; 123 MIMGBaseOpcode G16 = g16; 124} 125 126def MIMGG16MappingTable : GenericTable { 127 let FilterClass = "MIMGG16Mapping"; 128 let CppTypeName = "MIMGG16MappingInfo"; 129 let Fields = ["G", "G16"]; 130 string TypeOf_G = "MIMGBaseOpcode"; 131 string TypeOf_G16 = "MIMGBaseOpcode"; 132 133 let PrimaryKey = ["G"]; 134 let PrimaryKeyName = "getMIMGG16MappingInfo"; 135} 136 137class MIMG_Base <dag outs, string dns = ""> 138 : InstSI <outs, (ins), "", []> { 139 140 let VM_CNT = 1; 141 let EXP_CNT = 1; 142 let MIMG = 1; 143 let Uses = [EXEC]; 144 let mayLoad = 1; 145 let mayStore = 0; 146 let SchedRW = [WriteVMEM]; 147 let UseNamedOperandTable = 1; 148 let hasSideEffects = 0; // XXX ???? 149 150 let DecoderNamespace = dns; 151 let isAsmParserOnly = !eq(dns, ""); 152} 153 154class MIMG <dag outs, string dns = ""> 155 : MIMG_Base <outs, dns> { 156 157 let hasPostISelHook = 1; 158 let AsmMatchConverter = "cvtMIMG"; 159 160 Instruction Opcode = !cast<Instruction>(NAME); 161 MIMGBaseOpcode BaseOpcode; 162 MIMGEncoding MIMGEncoding; 163 bits<8> VDataDwords; 164 bits<8> VAddrDwords; 165} 166 167def MIMGInfoTable : GenericTable { 168 let FilterClass = "MIMG"; 169 let CppTypeName = "MIMGInfo"; 170 let Fields = ["Opcode", "BaseOpcode", "MIMGEncoding", "VDataDwords", "VAddrDwords"]; 171 string TypeOf_BaseOpcode = "MIMGBaseOpcode"; 172 string TypeOf_MIMGEncoding = "MIMGEncoding"; 173 174 let PrimaryKey = ["BaseOpcode", "MIMGEncoding", "VDataDwords", "VAddrDwords"]; 175 let PrimaryKeyName = "getMIMGOpcodeHelper"; 176} 177 178def getMIMGInfo : SearchIndex { 179 let Table = MIMGInfoTable; 180 let Key = ["Opcode"]; 181} 182 183// This class used to use !foldl to memoize the AddrAsmNames list. 184// It turned out that that was much slower than using !filter. 185class MIMGNSAHelper<int num_addrs> { 186 list<string> AddrAsmNames = 187 !foreach(i, !filter(i, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11], 188 !lt(i, num_addrs)), "vaddr" # i); 189 dag AddrIns = !dag(ins, !foreach(arg, AddrAsmNames, VGPR_32), AddrAsmNames); 190 string AddrAsm = "[$" # !interleave(AddrAsmNames, ", $") # "]"; 191 192 int NSA = !if(!le(num_addrs, 1), ?, 193 !if(!le(num_addrs, 5), 1, 194 !if(!le(num_addrs, 9), 2, 195 !if(!le(num_addrs, 13), 3, ?)))); 196} 197 198// Base class of all pre-gfx10 MIMG instructions. 199class MIMG_gfx6789<bits<8> op, dag outs, string dns = ""> 200 : MIMG<outs, dns>, MIMGe_gfx6789<op> { 201 let SubtargetPredicate = isGFX6GFX7GFX8GFX9; 202 let AssemblerPredicate = isGFX6GFX7GFX8GFX9; 203 204 let MIMGEncoding = MIMGEncGfx6; 205 206 let d16 = !if(BaseOpcode.HasD16, ?, 0); 207} 208 209// Base class of all non-NSA gfx10 MIMG instructions. 210class MIMG_gfx10<int op, dag outs, string dns = ""> 211 : MIMG<outs, dns>, MIMGe_gfx10<op> { 212 let SubtargetPredicate = isGFX10Plus; 213 let AssemblerPredicate = isGFX10Plus; 214 215 let MIMGEncoding = MIMGEncGfx10Default; 216 217 let d16 = !if(BaseOpcode.HasD16, ?, 0); 218 let nsa = 0; 219} 220 221// Base class for all NSA MIMG instructions. Note that 1-dword addresses always 222// use non-NSA variants. 223class MIMG_nsa_gfx10<int op, dag outs, int num_addrs, string dns=""> 224 : MIMG<outs, dns>, MIMGe_gfx10<op> { 225 let SubtargetPredicate = isGFX10Plus; 226 let AssemblerPredicate = isGFX10Plus; 227 228 let MIMGEncoding = MIMGEncGfx10NSA; 229 230 MIMGNSAHelper nsah = MIMGNSAHelper<num_addrs>; 231 dag AddrIns = nsah.AddrIns; 232 string AddrAsm = nsah.AddrAsm; 233 234 let d16 = !if(BaseOpcode.HasD16, ?, 0); 235 let nsa = nsah.NSA; 236} 237 238class MIMG_NoSampler_Helper <bits<8> op, string asm, 239 RegisterClass dst_rc, 240 RegisterClass addr_rc, 241 string dns=""> 242 : MIMG_gfx6789 <op, (outs dst_rc:$vdata), dns> { 243 let InOperandList = !con((ins addr_rc:$vaddr, SReg_256:$srsrc, 244 DMask:$dmask, UNorm:$unorm, GLC:$glc, SLC:$slc, 245 R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da), 246 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 247 let AsmString = asm#" $vdata, $vaddr, $srsrc$dmask$unorm$glc$slc$r128$tfe$lwe$da" 248 #!if(BaseOpcode.HasD16, "$d16", ""); 249} 250 251class MIMG_NoSampler_gfx10<int op, string opcode, 252 RegisterClass DataRC, RegisterClass AddrRC, 253 string dns=""> 254 : MIMG_gfx10<op, (outs DataRC:$vdata), dns> { 255 let InOperandList = !con((ins AddrRC:$vaddr0, SReg_256:$srsrc, DMask:$dmask, 256 Dim:$dim, UNorm:$unorm, DLC:$dlc, GLC:$glc, 257 SLC:$slc, R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe), 258 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 259 let AsmString = opcode#" $vdata, $vaddr0, $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$a16$tfe$lwe" 260 #!if(BaseOpcode.HasD16, "$d16", ""); 261} 262 263class MIMG_NoSampler_nsa_gfx10<int op, string opcode, 264 RegisterClass DataRC, int num_addrs, 265 string dns=""> 266 : MIMG_nsa_gfx10<op, (outs DataRC:$vdata), num_addrs, dns> { 267 let InOperandList = !con(AddrIns, 268 (ins SReg_256:$srsrc, DMask:$dmask, 269 Dim:$dim, UNorm:$unorm, DLC:$dlc, GLC:$glc, 270 SLC:$slc, R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe), 271 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 272 let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$a16$tfe$lwe" 273 #!if(BaseOpcode.HasD16, "$d16", ""); 274} 275 276multiclass MIMG_NoSampler_Src_Helper <bits<8> op, string asm, 277 RegisterClass dst_rc, 278 bit enableDisasm> { 279 let ssamp = 0 in { 280 let VAddrDwords = 1 in { 281 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32, 282 !if(enableDisasm, "AMDGPU", "")>; 283 def _V1_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VGPR_32, 284 !if(enableDisasm, "AMDGPU", "")>; 285 } 286 287 let VAddrDwords = 2 in { 288 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>; 289 def _V2_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VReg_64>; 290 def _V2_nsa_gfx10 : MIMG_NoSampler_nsa_gfx10<op, asm, dst_rc, 2>; 291 } 292 293 let VAddrDwords = 3 in { 294 def _V3 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_96>; 295 def _V3_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VReg_96>; 296 def _V3_nsa_gfx10 : MIMG_NoSampler_nsa_gfx10<op, asm, dst_rc, 3>; 297 } 298 299 let VAddrDwords = 4 in { 300 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>; 301 def _V4_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VReg_128>; 302 def _V4_nsa_gfx10 : MIMG_NoSampler_nsa_gfx10<op, asm, dst_rc, 4, 303 !if(enableDisasm, "AMDGPU", "")>; 304 } 305 } 306} 307 308multiclass MIMG_NoSampler <bits<8> op, string asm, bit has_d16, bit mip = 0, 309 bit isResInfo = 0> { 310 def "" : MIMGBaseOpcode { 311 let Coordinates = !not(isResInfo); 312 let LodOrClampOrMip = mip; 313 let HasD16 = has_d16; 314 } 315 316 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME), 317 mayLoad = !not(isResInfo) in { 318 let VDataDwords = 1 in 319 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VGPR_32, 1>; 320 let VDataDwords = 2 in 321 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 0>; 322 let VDataDwords = 3 in 323 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 0>; 324 let VDataDwords = 4 in 325 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 0>; 326 let VDataDwords = 5 in 327 defm _V5 : MIMG_NoSampler_Src_Helper <op, asm, VReg_160, 0>; 328 } 329} 330 331class MIMG_Store_Helper <bits<8> op, string asm, 332 RegisterClass data_rc, 333 RegisterClass addr_rc, 334 string dns = ""> 335 : MIMG_gfx6789<op, (outs), dns> { 336 let InOperandList = !con((ins data_rc:$vdata, addr_rc:$vaddr, SReg_256:$srsrc, 337 DMask:$dmask, UNorm:$unorm, GLC:$glc, SLC:$slc, 338 R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da), 339 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 340 let AsmString = asm#" $vdata, $vaddr, $srsrc$dmask$unorm$glc$slc$r128$tfe$lwe$da" 341 #!if(BaseOpcode.HasD16, "$d16", ""); 342} 343 344class MIMG_Store_gfx10<int op, string opcode, 345 RegisterClass DataRC, RegisterClass AddrRC, 346 string dns=""> 347 : MIMG_gfx10<op, (outs), dns> { 348 let InOperandList = !con((ins DataRC:$vdata, AddrRC:$vaddr0, SReg_256:$srsrc, 349 DMask:$dmask, Dim:$dim, UNorm:$unorm, DLC:$dlc, 350 GLC:$glc, SLC:$slc, R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe), 351 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 352 let AsmString = opcode#" $vdata, $vaddr0, $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$a16$tfe$lwe" 353 #!if(BaseOpcode.HasD16, "$d16", ""); 354} 355 356class MIMG_Store_nsa_gfx10<int op, string opcode, 357 RegisterClass DataRC, int num_addrs, 358 string dns=""> 359 : MIMG_nsa_gfx10<op, (outs), num_addrs, dns> { 360 let InOperandList = !con((ins DataRC:$vdata), 361 AddrIns, 362 (ins SReg_256:$srsrc, DMask:$dmask, 363 Dim:$dim, UNorm:$unorm, DLC:$dlc, GLC:$glc, 364 SLC:$slc, R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe), 365 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 366 let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$a16$tfe$lwe" 367 #!if(BaseOpcode.HasD16, "$d16", ""); 368} 369 370multiclass MIMG_Store_Addr_Helper <int op, string asm, 371 RegisterClass data_rc, 372 bit enableDisasm> { 373 let mayLoad = 0, mayStore = 1, hasSideEffects = 0, hasPostISelHook = 0, 374 DisableWQM = 1, ssamp = 0 in { 375 let VAddrDwords = 1 in { 376 def _V1 : MIMG_Store_Helper <op, asm, data_rc, VGPR_32, 377 !if(enableDisasm, "AMDGPU", "")>; 378 def _V1_gfx10 : MIMG_Store_gfx10 <op, asm, data_rc, VGPR_32, 379 !if(enableDisasm, "AMDGPU", "")>; 380 } 381 let VAddrDwords = 2 in { 382 def _V2 : MIMG_Store_Helper <op, asm, data_rc, VReg_64>; 383 def _V2_gfx10 : MIMG_Store_gfx10 <op, asm, data_rc, VReg_64>; 384 def _V2_nsa_gfx10 : MIMG_Store_nsa_gfx10 <op, asm, data_rc, 2>; 385 } 386 let VAddrDwords = 3 in { 387 def _V3 : MIMG_Store_Helper <op, asm, data_rc, VReg_96>; 388 def _V3_gfx10 : MIMG_Store_gfx10 <op, asm, data_rc, VReg_96>; 389 def _V3_nsa_gfx10 : MIMG_Store_nsa_gfx10 <op, asm, data_rc, 3>; 390 } 391 let VAddrDwords = 4 in { 392 def _V4 : MIMG_Store_Helper <op, asm, data_rc, VReg_128>; 393 def _V4_gfx10 : MIMG_Store_gfx10 <op, asm, data_rc, VReg_128>; 394 def _V4_nsa_gfx10 : MIMG_Store_nsa_gfx10 <op, asm, data_rc, 4, 395 !if(enableDisasm, "AMDGPU", "")>; 396 } 397 } 398} 399 400multiclass MIMG_Store <bits<8> op, string asm, bit has_d16, bit mip = 0> { 401 def "" : MIMGBaseOpcode { 402 let Store = 1; 403 let LodOrClampOrMip = mip; 404 let HasD16 = has_d16; 405 } 406 407 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME) in { 408 let VDataDwords = 1 in 409 defm _V1 : MIMG_Store_Addr_Helper <op, asm, VGPR_32, 1>; 410 let VDataDwords = 2 in 411 defm _V2 : MIMG_Store_Addr_Helper <op, asm, VReg_64, 0>; 412 let VDataDwords = 3 in 413 defm _V3 : MIMG_Store_Addr_Helper <op, asm, VReg_96, 0>; 414 let VDataDwords = 4 in 415 defm _V4 : MIMG_Store_Addr_Helper <op, asm, VReg_128, 0>; 416 let VDataDwords = 5 in 417 defm _V5 : MIMG_Store_Addr_Helper <op, asm, VReg_160, 0>; 418 } 419} 420 421class MIMG_Atomic_gfx6789_base <bits<8> op, string asm, RegisterClass data_rc, 422 RegisterClass addr_rc, string dns=""> 423 : MIMG_gfx6789 <op, (outs data_rc:$vdst), dns> { 424 let Constraints = "$vdst = $vdata"; 425 let AsmMatchConverter = "cvtMIMGAtomic"; 426 427 let InOperandList = (ins data_rc:$vdata, addr_rc:$vaddr, SReg_256:$srsrc, 428 DMask:$dmask, UNorm:$unorm, GLC:$glc, SLC:$slc, 429 R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da); 430 let AsmString = asm#" $vdst, $vaddr, $srsrc$dmask$unorm$glc$slc$r128$tfe$lwe$da"; 431} 432 433class MIMG_Atomic_si<mimg op, string asm, RegisterClass data_rc, 434 RegisterClass addr_rc, bit enableDasm = 0> 435 : MIMG_Atomic_gfx6789_base<op.SI_GFX10, asm, data_rc, addr_rc, 436 !if(enableDasm, "GFX6GFX7", "")> { 437 let AssemblerPredicate = isGFX6GFX7; 438} 439 440class MIMG_Atomic_vi<mimg op, string asm, RegisterClass data_rc, 441 RegisterClass addr_rc, bit enableDasm = 0> 442 : MIMG_Atomic_gfx6789_base<op.VI, asm, data_rc, addr_rc, !if(enableDasm, "GFX8", "")> { 443 let AssemblerPredicate = isGFX8GFX9; 444 let MIMGEncoding = MIMGEncGfx8; 445} 446 447class MIMG_Atomic_gfx10<mimg op, string opcode, 448 RegisterClass DataRC, RegisterClass AddrRC, 449 bit enableDisasm = 0> 450 : MIMG_gfx10<!cast<int>(op.SI_GFX10), (outs DataRC:$vdst), 451 !if(enableDisasm, "AMDGPU", "")> { 452 let Constraints = "$vdst = $vdata"; 453 let AsmMatchConverter = "cvtMIMGAtomic"; 454 455 let InOperandList = (ins DataRC:$vdata, AddrRC:$vaddr0, SReg_256:$srsrc, 456 DMask:$dmask, Dim:$dim, UNorm:$unorm, DLC:$dlc, 457 GLC:$glc, SLC:$slc, R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe); 458 let AsmString = opcode#" $vdst, $vaddr0, $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$a16$tfe$lwe"; 459} 460 461class MIMG_Atomic_nsa_gfx10<mimg op, string opcode, 462 RegisterClass DataRC, int num_addrs, 463 bit enableDisasm = 0> 464 : MIMG_nsa_gfx10<!cast<int>(op.SI_GFX10), (outs DataRC:$vdst), num_addrs, 465 !if(enableDisasm, "AMDGPU", "")> { 466 let Constraints = "$vdst = $vdata"; 467 let AsmMatchConverter = "cvtMIMGAtomic"; 468 469 let InOperandList = !con((ins DataRC:$vdata), 470 AddrIns, 471 (ins SReg_256:$srsrc, DMask:$dmask, 472 Dim:$dim, UNorm:$unorm, DLC:$dlc, GLC:$glc, 473 SLC:$slc, R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe)); 474 let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$a16$tfe$lwe"; 475} 476 477multiclass MIMG_Atomic_Addr_Helper_m <mimg op, string asm, 478 RegisterClass data_rc, 479 bit enableDasm = 0> { 480 let hasSideEffects = 1, // FIXME: remove this 481 mayLoad = 1, mayStore = 1, hasPostISelHook = 0, DisableWQM = 1, 482 ssamp = 0 in { 483 let VAddrDwords = 1 in { 484 def _V1_si : MIMG_Atomic_si <op, asm, data_rc, VGPR_32, enableDasm>; 485 def _V1_vi : MIMG_Atomic_vi <op, asm, data_rc, VGPR_32, enableDasm>; 486 def _V1_gfx10 : MIMG_Atomic_gfx10 <op, asm, data_rc, VGPR_32, enableDasm>; 487 } 488 let VAddrDwords = 2 in { 489 def _V2_si : MIMG_Atomic_si <op, asm, data_rc, VReg_64, 0>; 490 def _V2_vi : MIMG_Atomic_vi <op, asm, data_rc, VReg_64, 0>; 491 def _V2_gfx10 : MIMG_Atomic_gfx10 <op, asm, data_rc, VReg_64, 0>; 492 def _V2_nsa_gfx10 : MIMG_Atomic_nsa_gfx10 <op, asm, data_rc, 2, 0>; 493 } 494 let VAddrDwords = 3 in { 495 def _V3_si : MIMG_Atomic_si <op, asm, data_rc, VReg_96, 0>; 496 def _V3_vi : MIMG_Atomic_vi <op, asm, data_rc, VReg_96, 0>; 497 def _V3_gfx10 : MIMG_Atomic_gfx10 <op, asm, data_rc, VReg_96, 0>; 498 def _V3_nsa_gfx10 : MIMG_Atomic_nsa_gfx10 <op, asm, data_rc, 3, 0>; 499 } 500 let VAddrDwords = 4 in { 501 def _V4_si : MIMG_Atomic_si <op, asm, data_rc, VReg_128, 0>; 502 def _V4_vi : MIMG_Atomic_vi <op, asm, data_rc, VReg_128, 0>; 503 def _V4_gfx10 : MIMG_Atomic_gfx10 <op, asm, data_rc, VReg_128, 0>; 504 def _V4_nsa_gfx10 : MIMG_Atomic_nsa_gfx10 <op, asm, data_rc, 4, enableDasm>; 505 } 506 } 507} 508 509multiclass MIMG_Atomic <mimg op, string asm, bit isCmpSwap = 0> { // 64-bit atomics 510 def "" : MIMGBaseOpcode { 511 let Atomic = 1; 512 let AtomicX2 = isCmpSwap; 513 } 514 515 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME) in { 516 // _V* variants have different dst size, but the size is encoded implicitly, 517 // using dmask and tfe. Only 32-bit variant is registered with disassembler. 518 // Other variants are reconstructed by disassembler using dmask and tfe. 519 let VDataDwords = !if(isCmpSwap, 2, 1) in 520 defm _V1 : MIMG_Atomic_Addr_Helper_m <op, asm, !if(isCmpSwap, VReg_64, VGPR_32), 1>; 521 let VDataDwords = !if(isCmpSwap, 4, 2) in 522 defm _V2 : MIMG_Atomic_Addr_Helper_m <op, asm, !if(isCmpSwap, VReg_128, VReg_64)>; 523 } 524} 525 526class MIMG_Sampler_Helper <bits<8> op, string asm, RegisterClass dst_rc, 527 RegisterClass src_rc, string dns=""> 528 : MIMG_gfx6789 <op, (outs dst_rc:$vdata), dns> { 529 let InOperandList = !con((ins src_rc:$vaddr, SReg_256:$srsrc, SReg_128:$ssamp, 530 DMask:$dmask, UNorm:$unorm, GLC:$glc, SLC:$slc, 531 R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da), 532 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 533 let AsmString = asm#" $vdata, $vaddr, $srsrc, $ssamp$dmask$unorm$glc$slc$r128$tfe$lwe$da" 534 #!if(BaseOpcode.HasD16, "$d16", ""); 535} 536 537class MIMG_Sampler_gfx10<int op, string opcode, 538 RegisterClass DataRC, RegisterClass AddrRC, 539 string dns=""> 540 : MIMG_gfx10<op, (outs DataRC:$vdata), dns> { 541 let InOperandList = !con((ins AddrRC:$vaddr0, SReg_256:$srsrc, SReg_128:$ssamp, 542 DMask:$dmask, Dim:$dim, UNorm:$unorm, DLC:$dlc, 543 GLC:$glc, SLC:$slc, R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe), 544 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 545 let AsmString = opcode#" $vdata, $vaddr0, $srsrc, $ssamp$dmask$dim$unorm" 546 #"$dlc$glc$slc$r128$a16$tfe$lwe" 547 #!if(BaseOpcode.HasD16, "$d16", ""); 548} 549 550class MIMG_Sampler_nsa_gfx10<int op, string opcode, 551 RegisterClass DataRC, int num_addrs, 552 string dns=""> 553 : MIMG_nsa_gfx10<op, (outs DataRC:$vdata), num_addrs, dns> { 554 let InOperandList = !con(AddrIns, 555 (ins SReg_256:$srsrc, SReg_128:$ssamp, DMask:$dmask, 556 Dim:$dim, UNorm:$unorm, DLC:$dlc, GLC:$glc, 557 SLC:$slc, R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe), 558 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 559 let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc, $ssamp$dmask$dim$unorm" 560 #"$dlc$glc$slc$r128$a16$tfe$lwe" 561 #!if(BaseOpcode.HasD16, "$d16", ""); 562} 563 564class MIMGAddrSize<int dw, bit enable_disasm> { 565 int NumWords = dw; 566 567 RegisterClass RegClass = !if(!le(NumWords, 0), ?, 568 !if(!eq(NumWords, 1), VGPR_32, 569 !if(!eq(NumWords, 2), VReg_64, 570 !if(!eq(NumWords, 3), VReg_96, 571 !if(!eq(NumWords, 4), VReg_128, 572 !if(!le(NumWords, 8), VReg_256, 573 !if(!le(NumWords, 16), VReg_512, ?))))))); 574 575 // Whether the instruction variant with this vaddr size should be enabled for 576 // the auto-generated disassembler. 577 bit Disassemble = enable_disasm; 578} 579 580// Return whether x is in lst. 581class isIntInList<int x, list<int> lst> { 582 bit ret = !foldl(0, lst, lhs, y, !or(lhs, !eq(x, y))); 583} 584 585// Return whether a value inside the range [min, max] (endpoints inclusive) 586// is in the given list. 587class isRangeInList<int min, int max, list<int> lst> { 588 bit ret = !foldl(0, lst, lhs, y, !or(lhs, !and(!le(min, y), !le(y, max)))); 589} 590 591class MIMGAddrSizes_tmp<list<MIMGAddrSize> lst, int min> { 592 list<MIMGAddrSize> List = lst; 593 int Min = min; 594} 595 596class MIMG_Sampler_AddrSizes<AMDGPUSampleVariant sample> { 597 // List of all possible numbers of address words, taking all combinations of 598 // A16 and image dimension into account (note: no MSAA, since this is for 599 // sample/gather ops). 600 list<int> AllNumAddrWords = 601 !foreach(dw, !if(sample.Gradients, 602 !if(!eq(sample.LodOrClamp, ""), 603 [2, 3, 4, 5, 6, 7, 9], 604 [2, 3, 4, 5, 7, 8, 10]), 605 !if(!eq(sample.LodOrClamp, ""), 606 [1, 2, 3], 607 [1, 2, 3, 4])), 608 !add(dw, !size(sample.ExtraAddrArgs))); 609 610 // Generate machine instructions based on possible register classes for the 611 // required numbers of address words. The disassembler defaults to the 612 // smallest register class. 613 list<MIMGAddrSize> MachineInstrs = 614 !foldl(MIMGAddrSizes_tmp<[], 0>, [1, 2, 3, 4, 8, 16], lhs, dw, 615 !if(isRangeInList<lhs.Min, dw, AllNumAddrWords>.ret, 616 MIMGAddrSizes_tmp< 617 !listconcat(lhs.List, [MIMGAddrSize<dw, !empty(lhs.List)>]), 618 !if(!eq(dw, 3), 3, !add(dw, 1))>, // we still need _V4 for codegen w/ 3 dwords 619 lhs)).List; 620 621 // For NSA, generate machine instructions for all possible numbers of words 622 // except 1 (which is already covered by the non-NSA case). 623 // The disassembler defaults to the largest number of arguments among the 624 // variants with the same number of NSA words, and custom code then derives 625 // the exact variant based on the sample variant and the image dimension. 626 list<MIMGAddrSize> NSAInstrs = 627 !foldl([]<MIMGAddrSize>, [[12, 11, 10], [9, 8, 7, 6], [5, 4, 3, 2]], prev, nsa_group, 628 !listconcat(prev, 629 !foldl([]<MIMGAddrSize>, nsa_group, lhs, dw, 630 !if(isIntInList<dw, AllNumAddrWords>.ret, 631 !listconcat(lhs, [MIMGAddrSize<dw, !empty(lhs)>]), 632 lhs)))); 633} 634 635multiclass MIMG_Sampler_Src_Helper <bits<8> op, string asm, 636 AMDGPUSampleVariant sample, RegisterClass dst_rc, 637 bit enableDisasm = 0> { 638 foreach addr = MIMG_Sampler_AddrSizes<sample>.MachineInstrs in { 639 let VAddrDwords = addr.NumWords in { 640 def _V # addr.NumWords 641 : MIMG_Sampler_Helper <op, asm, dst_rc, addr.RegClass, 642 !if(!and(enableDisasm, addr.Disassemble), "AMDGPU", "")>; 643 def _V # addr.NumWords # _gfx10 644 : MIMG_Sampler_gfx10 <op, asm, dst_rc, addr.RegClass, 645 !if(!and(enableDisasm, addr.Disassemble), "AMDGPU", "")>; 646 } 647 } 648 649 foreach addr = MIMG_Sampler_AddrSizes<sample>.NSAInstrs in { 650 let VAddrDwords = addr.NumWords in { 651 def _V # addr.NumWords # _nsa_gfx10 652 : MIMG_Sampler_nsa_gfx10<op, asm, dst_rc, addr.NumWords, 653 !if(!and(enableDisasm, addr.Disassemble), "AMDGPU", "")>; 654 } 655 } 656} 657 658class MIMG_Sampler_BaseOpcode<AMDGPUSampleVariant sample> 659 : MIMGBaseOpcode { 660 let Sampler = 1; 661 let NumExtraArgs = !size(sample.ExtraAddrArgs); 662 let Gradients = sample.Gradients; 663 let LodOrClampOrMip = !ne(sample.LodOrClamp, ""); 664} 665 666multiclass MIMG_Sampler <bits<8> op, AMDGPUSampleVariant sample, bit wqm = 0, 667 bit isG16 = 0, bit isGetLod = 0, 668 string asm = "image_sample"#sample.LowerCaseMod#!if(isG16, "_g16", "")> { 669 def "" : MIMG_Sampler_BaseOpcode<sample> { 670 let HasD16 = !not(isGetLod); 671 let G16 = isG16; 672 } 673 674 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME), WQM = wqm, 675 mayLoad = !not(isGetLod) in { 676 let VDataDwords = 1 in 677 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, sample, VGPR_32, 1>; 678 let VDataDwords = 2 in 679 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_64>; 680 let VDataDwords = 3 in 681 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_96>; 682 let VDataDwords = 4 in 683 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_128>; 684 let VDataDwords = 5 in 685 defm _V5 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_160>; 686 } 687} 688 689multiclass MIMG_Sampler_WQM <bits<8> op, AMDGPUSampleVariant sample> 690 : MIMG_Sampler<op, sample, 1>; 691 692multiclass MIMG_Gather <bits<8> op, AMDGPUSampleVariant sample, bit wqm = 0, 693 string asm = "image_gather4"#sample.LowerCaseMod> { 694 def "" : MIMG_Sampler_BaseOpcode<sample> { 695 let HasD16 = 1; 696 let Gather4 = 1; 697 } 698 699 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME), WQM = wqm, 700 Gather4 = 1, hasPostISelHook = 0 in { 701 let VDataDwords = 2 in 702 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_64>; /* for packed D16 only */ 703 let VDataDwords = 4 in 704 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_128, 1>; 705 let VDataDwords = 5 in 706 defm _V5 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_160>; 707 } 708} 709 710multiclass MIMG_Gather_WQM <bits<8> op, AMDGPUSampleVariant sample> 711 : MIMG_Gather<op, sample, 1>; 712 713class MIMG_IntersectRay_gfx10<int op, string opcode, RegisterClass AddrRC, bit A16> 714 : MIMG_gfx10<op, (outs VReg_128:$vdata), "AMDGPU"> { 715 716 let InOperandList = !con((ins AddrRC:$vaddr0, SReg_128:$srsrc), 717 !if(A16, (ins GFX10A16:$a16), (ins))); 718 let AsmString = opcode#" $vdata, $vaddr0, $srsrc"#!if(A16, "$a16", ""); 719 720 let nsa = 0; 721} 722 723class MIMG_IntersectRay_nsa_gfx10<int op, string opcode, int num_addrs, bit A16> 724 : MIMG_nsa_gfx10<op, (outs VReg_128:$vdata), num_addrs, "AMDGPU"> { 725 let InOperandList = !con(nsah.AddrIns, 726 (ins SReg_128:$srsrc), 727 !if(A16, (ins GFX10A16:$a16), (ins))); 728 let AsmString = opcode#" $vdata, "#nsah.AddrAsm#", $srsrc"#!if(A16, "$a16", ""); 729} 730 731multiclass MIMG_IntersectRay<int op, string opcode, int num_addrs, bit A16> { 732 def "" : MIMGBaseOpcode; 733 let SubtargetPredicate = HasGFX10_BEncoding, 734 AssemblerPredicate = HasGFX10_BEncoding, 735 AsmMatchConverter = !if(A16, "cvtIntersectRay", ""), 736 dmask = 0xf, 737 unorm = 1, 738 d16 = 0, 739 glc = 0, 740 slc = 0, 741 dlc = 0, 742 tfe = 0, 743 lwe = 0, 744 r128 = 1, 745 ssamp = 0, 746 dim = {0, 0, 0}, 747 a16 = A16, 748 d16 = 0, 749 BaseOpcode = !cast<MIMGBaseOpcode>(NAME), 750 VDataDwords = 4 in { 751 // TODO: MIMGAddrSize will choose VReg_512 which is a 16 register tuple, 752 // when we only need 9, 11 or 12 depending on A16 field and ptr size. 753 def "_sa" : MIMG_IntersectRay_gfx10<op, opcode, MIMGAddrSize<num_addrs, 0>.RegClass, A16> { 754 let VAddrDwords = !srl(MIMGAddrSize<num_addrs, 0>.RegClass.Size, 5); 755 } 756 def _nsa : MIMG_IntersectRay_nsa_gfx10<op, opcode, num_addrs, A16> { 757 let VAddrDwords = num_addrs; 758 } 759 } 760} 761 762//===----------------------------------------------------------------------===// 763// MIMG Instructions 764//===----------------------------------------------------------------------===// 765defm IMAGE_LOAD : MIMG_NoSampler <0x00000000, "image_load", 1>; 766defm IMAGE_LOAD_MIP : MIMG_NoSampler <0x00000001, "image_load_mip", 1, 1>; 767defm IMAGE_LOAD_PCK : MIMG_NoSampler <0x00000002, "image_load_pck", 0>; 768defm IMAGE_LOAD_PCK_SGN : MIMG_NoSampler <0x00000003, "image_load_pck_sgn", 0>; 769defm IMAGE_LOAD_MIP_PCK : MIMG_NoSampler <0x00000004, "image_load_mip_pck", 0, 1>; 770defm IMAGE_LOAD_MIP_PCK_SGN : MIMG_NoSampler <0x00000005, "image_load_mip_pck_sgn", 0, 1>; 771defm IMAGE_STORE : MIMG_Store <0x00000008, "image_store", 1>; 772defm IMAGE_STORE_MIP : MIMG_Store <0x00000009, "image_store_mip", 1, 1>; 773defm IMAGE_STORE_PCK : MIMG_Store <0x0000000a, "image_store_pck", 0>; 774defm IMAGE_STORE_MIP_PCK : MIMG_Store <0x0000000b, "image_store_mip_pck", 0, 1>; 775 776defm IMAGE_GET_RESINFO : MIMG_NoSampler <0x0000000e, "image_get_resinfo", 0, 1, 1>; 777 778defm IMAGE_ATOMIC_SWAP : MIMG_Atomic <mimg<0x0f, 0x10>, "image_atomic_swap">; 779defm IMAGE_ATOMIC_CMPSWAP : MIMG_Atomic <mimg<0x10, 0x11>, "image_atomic_cmpswap", 1>; 780defm IMAGE_ATOMIC_ADD : MIMG_Atomic <mimg<0x11, 0x12>, "image_atomic_add">; 781defm IMAGE_ATOMIC_SUB : MIMG_Atomic <mimg<0x12, 0x13>, "image_atomic_sub">; 782//def IMAGE_ATOMIC_RSUB : MIMG_NoPattern_ <"image_atomic_rsub", 0x00000013>; -- not on VI 783defm IMAGE_ATOMIC_SMIN : MIMG_Atomic <mimg<0x14>, "image_atomic_smin">; 784defm IMAGE_ATOMIC_UMIN : MIMG_Atomic <mimg<0x15>, "image_atomic_umin">; 785defm IMAGE_ATOMIC_SMAX : MIMG_Atomic <mimg<0x16>, "image_atomic_smax">; 786defm IMAGE_ATOMIC_UMAX : MIMG_Atomic <mimg<0x17>, "image_atomic_umax">; 787defm IMAGE_ATOMIC_AND : MIMG_Atomic <mimg<0x18>, "image_atomic_and">; 788defm IMAGE_ATOMIC_OR : MIMG_Atomic <mimg<0x19>, "image_atomic_or">; 789defm IMAGE_ATOMIC_XOR : MIMG_Atomic <mimg<0x1a>, "image_atomic_xor">; 790defm IMAGE_ATOMIC_INC : MIMG_Atomic <mimg<0x1b>, "image_atomic_inc">; 791defm IMAGE_ATOMIC_DEC : MIMG_Atomic <mimg<0x1c>, "image_atomic_dec">; 792//let FPAtomic = 1 in { 793//def IMAGE_ATOMIC_FCMPSWAP : MIMG_NoPattern_ <"image_atomic_fcmpswap", 0x0000001d, 1>; -- not on VI 794//def IMAGE_ATOMIC_FMIN : MIMG_NoPattern_ <"image_atomic_fmin", 0x0000001e>; -- not on VI 795//def IMAGE_ATOMIC_FMAX : MIMG_NoPattern_ <"image_atomic_fmax", 0x0000001f>; -- not on VI 796//} // End let FPAtomic = 1 797defm IMAGE_SAMPLE : MIMG_Sampler_WQM <0x00000020, AMDGPUSample>; 798defm IMAGE_SAMPLE_CL : MIMG_Sampler_WQM <0x00000021, AMDGPUSample_cl>; 799defm IMAGE_SAMPLE_D : MIMG_Sampler <0x00000022, AMDGPUSample_d>; 800defm IMAGE_SAMPLE_D_CL : MIMG_Sampler <0x00000023, AMDGPUSample_d_cl>; 801defm IMAGE_SAMPLE_D_G16 : MIMG_Sampler <0x000000a2, AMDGPUSample_d, 0, 1>; 802defm IMAGE_SAMPLE_D_CL_G16 : MIMG_Sampler <0x000000a3, AMDGPUSample_d_cl, 0, 1>; 803defm IMAGE_SAMPLE_L : MIMG_Sampler <0x00000024, AMDGPUSample_l>; 804defm IMAGE_SAMPLE_B : MIMG_Sampler_WQM <0x00000025, AMDGPUSample_b>; 805defm IMAGE_SAMPLE_B_CL : MIMG_Sampler_WQM <0x00000026, AMDGPUSample_b_cl>; 806defm IMAGE_SAMPLE_LZ : MIMG_Sampler <0x00000027, AMDGPUSample_lz>; 807defm IMAGE_SAMPLE_C : MIMG_Sampler_WQM <0x00000028, AMDGPUSample_c>; 808defm IMAGE_SAMPLE_C_CL : MIMG_Sampler_WQM <0x00000029, AMDGPUSample_c_cl>; 809defm IMAGE_SAMPLE_C_D : MIMG_Sampler <0x0000002a, AMDGPUSample_c_d>; 810defm IMAGE_SAMPLE_C_D_CL : MIMG_Sampler <0x0000002b, AMDGPUSample_c_d_cl>; 811defm IMAGE_SAMPLE_C_D_G16 : MIMG_Sampler <0x000000aa, AMDGPUSample_c_d, 0, 1>; 812defm IMAGE_SAMPLE_C_D_CL_G16 : MIMG_Sampler <0x000000ab, AMDGPUSample_c_d_cl, 0, 1>; 813defm IMAGE_SAMPLE_C_L : MIMG_Sampler <0x0000002c, AMDGPUSample_c_l>; 814defm IMAGE_SAMPLE_C_B : MIMG_Sampler_WQM <0x0000002d, AMDGPUSample_c_b>; 815defm IMAGE_SAMPLE_C_B_CL : MIMG_Sampler_WQM <0x0000002e, AMDGPUSample_c_b_cl>; 816defm IMAGE_SAMPLE_C_LZ : MIMG_Sampler <0x0000002f, AMDGPUSample_c_lz>; 817defm IMAGE_SAMPLE_O : MIMG_Sampler_WQM <0x00000030, AMDGPUSample_o>; 818defm IMAGE_SAMPLE_CL_O : MIMG_Sampler_WQM <0x00000031, AMDGPUSample_cl_o>; 819defm IMAGE_SAMPLE_D_O : MIMG_Sampler <0x00000032, AMDGPUSample_d_o>; 820defm IMAGE_SAMPLE_D_CL_O : MIMG_Sampler <0x00000033, AMDGPUSample_d_cl_o>; 821defm IMAGE_SAMPLE_D_O_G16 : MIMG_Sampler <0x000000b2, AMDGPUSample_d_o, 0, 1>; 822defm IMAGE_SAMPLE_D_CL_O_G16 : MIMG_Sampler <0x000000b3, AMDGPUSample_d_cl_o, 0, 1>; 823defm IMAGE_SAMPLE_L_O : MIMG_Sampler <0x00000034, AMDGPUSample_l_o>; 824defm IMAGE_SAMPLE_B_O : MIMG_Sampler_WQM <0x00000035, AMDGPUSample_b_o>; 825defm IMAGE_SAMPLE_B_CL_O : MIMG_Sampler_WQM <0x00000036, AMDGPUSample_b_cl_o>; 826defm IMAGE_SAMPLE_LZ_O : MIMG_Sampler <0x00000037, AMDGPUSample_lz_o>; 827defm IMAGE_SAMPLE_C_O : MIMG_Sampler_WQM <0x00000038, AMDGPUSample_c_o>; 828defm IMAGE_SAMPLE_C_CL_O : MIMG_Sampler_WQM <0x00000039, AMDGPUSample_c_cl_o>; 829defm IMAGE_SAMPLE_C_D_O : MIMG_Sampler <0x0000003a, AMDGPUSample_c_d_o>; 830defm IMAGE_SAMPLE_C_D_CL_O : MIMG_Sampler <0x0000003b, AMDGPUSample_c_d_cl_o>; 831defm IMAGE_SAMPLE_C_D_O_G16 : MIMG_Sampler <0x000000ba, AMDGPUSample_c_d_o, 0, 1>; 832defm IMAGE_SAMPLE_C_D_CL_O_G16 : MIMG_Sampler <0x000000bb, AMDGPUSample_c_d_cl_o, 0, 1>; 833defm IMAGE_SAMPLE_C_L_O : MIMG_Sampler <0x0000003c, AMDGPUSample_c_l_o>; 834defm IMAGE_SAMPLE_C_B_CL_O : MIMG_Sampler_WQM <0x0000003e, AMDGPUSample_c_b_cl_o>; 835defm IMAGE_SAMPLE_C_B_O : MIMG_Sampler_WQM <0x0000003d, AMDGPUSample_c_b_o>; 836defm IMAGE_SAMPLE_C_LZ_O : MIMG_Sampler <0x0000003f, AMDGPUSample_c_lz_o>; 837defm IMAGE_GATHER4 : MIMG_Gather_WQM <0x00000040, AMDGPUSample>; 838defm IMAGE_GATHER4_CL : MIMG_Gather_WQM <0x00000041, AMDGPUSample_cl>; 839defm IMAGE_GATHER4_L : MIMG_Gather <0x00000044, AMDGPUSample_l>; 840defm IMAGE_GATHER4_B : MIMG_Gather_WQM <0x00000045, AMDGPUSample_b>; 841defm IMAGE_GATHER4_B_CL : MIMG_Gather_WQM <0x00000046, AMDGPUSample_b_cl>; 842defm IMAGE_GATHER4_LZ : MIMG_Gather <0x00000047, AMDGPUSample_lz>; 843defm IMAGE_GATHER4_C : MIMG_Gather_WQM <0x00000048, AMDGPUSample_c>; 844defm IMAGE_GATHER4_C_CL : MIMG_Gather_WQM <0x00000049, AMDGPUSample_c_cl>; 845defm IMAGE_GATHER4_C_L : MIMG_Gather <0x0000004c, AMDGPUSample_c_l>; 846defm IMAGE_GATHER4_C_B : MIMG_Gather_WQM <0x0000004d, AMDGPUSample_c_b>; 847defm IMAGE_GATHER4_C_B_CL : MIMG_Gather_WQM <0x0000004e, AMDGPUSample_c_b_cl>; 848defm IMAGE_GATHER4_C_LZ : MIMG_Gather <0x0000004f, AMDGPUSample_c_lz>; 849defm IMAGE_GATHER4_O : MIMG_Gather_WQM <0x00000050, AMDGPUSample_o>; 850defm IMAGE_GATHER4_CL_O : MIMG_Gather_WQM <0x00000051, AMDGPUSample_cl_o>; 851defm IMAGE_GATHER4_L_O : MIMG_Gather <0x00000054, AMDGPUSample_l_o>; 852defm IMAGE_GATHER4_B_O : MIMG_Gather_WQM <0x00000055, AMDGPUSample_b_o>; 853defm IMAGE_GATHER4_B_CL_O : MIMG_Gather <0x00000056, AMDGPUSample_b_cl_o>; 854defm IMAGE_GATHER4_LZ_O : MIMG_Gather <0x00000057, AMDGPUSample_lz_o>; 855defm IMAGE_GATHER4_C_O : MIMG_Gather_WQM <0x00000058, AMDGPUSample_c_o>; 856defm IMAGE_GATHER4_C_CL_O : MIMG_Gather_WQM <0x00000059, AMDGPUSample_c_cl_o>; 857defm IMAGE_GATHER4_C_L_O : MIMG_Gather <0x0000005c, AMDGPUSample_c_l_o>; 858defm IMAGE_GATHER4_C_B_O : MIMG_Gather_WQM <0x0000005d, AMDGPUSample_c_b_o>; 859defm IMAGE_GATHER4_C_B_CL_O : MIMG_Gather_WQM <0x0000005e, AMDGPUSample_c_b_cl_o>; 860defm IMAGE_GATHER4_C_LZ_O : MIMG_Gather <0x0000005f, AMDGPUSample_c_lz_o>; 861 862defm IMAGE_GET_LOD : MIMG_Sampler <0x00000060, AMDGPUSample, 1, 0, 1, "image_get_lod">; 863 864defm IMAGE_SAMPLE_CD : MIMG_Sampler <0x00000068, AMDGPUSample_cd>; 865defm IMAGE_SAMPLE_CD_CL : MIMG_Sampler <0x00000069, AMDGPUSample_cd_cl>; 866defm IMAGE_SAMPLE_C_CD : MIMG_Sampler <0x0000006a, AMDGPUSample_c_cd>; 867defm IMAGE_SAMPLE_C_CD_CL : MIMG_Sampler <0x0000006b, AMDGPUSample_c_cd_cl>; 868defm IMAGE_SAMPLE_CD_O : MIMG_Sampler <0x0000006c, AMDGPUSample_cd_o>; 869defm IMAGE_SAMPLE_CD_CL_O : MIMG_Sampler <0x0000006d, AMDGPUSample_cd_cl_o>; 870defm IMAGE_SAMPLE_C_CD_O : MIMG_Sampler <0x0000006e, AMDGPUSample_c_cd_o>; 871defm IMAGE_SAMPLE_C_CD_CL_O : MIMG_Sampler <0x0000006f, AMDGPUSample_c_cd_cl_o>; 872defm IMAGE_SAMPLE_CD_G16 : MIMG_Sampler <0x000000e8, AMDGPUSample_cd, 0, 1>; 873defm IMAGE_SAMPLE_CD_CL_G16 : MIMG_Sampler <0x000000e9, AMDGPUSample_cd_cl, 0, 1>; 874defm IMAGE_SAMPLE_C_CD_G16 : MIMG_Sampler <0x000000ea, AMDGPUSample_c_cd, 0, 1>; 875defm IMAGE_SAMPLE_C_CD_CL_G16 : MIMG_Sampler <0x000000eb, AMDGPUSample_c_cd_cl, 0, 1>; 876defm IMAGE_SAMPLE_CD_O_G16 : MIMG_Sampler <0x000000ec, AMDGPUSample_cd_o, 0, 1>; 877defm IMAGE_SAMPLE_CD_CL_O_G16 : MIMG_Sampler <0x000000ed, AMDGPUSample_cd_cl_o, 0, 1>; 878defm IMAGE_SAMPLE_C_CD_O_G16 : MIMG_Sampler <0x000000ee, AMDGPUSample_c_cd_o, 0, 1>; 879defm IMAGE_SAMPLE_C_CD_CL_O_G16 : MIMG_Sampler <0x000000ef, AMDGPUSample_c_cd_cl_o, 0, 1>; 880//def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"image_rsrc256", 0x0000007e>; 881//def IMAGE_SAMPLER : MIMG_NoPattern_ <"image_sampler", 0x0000007f>; 882 883let SubtargetPredicate = HasGFX10_BEncoding in 884defm IMAGE_MSAA_LOAD : MIMG_NoSampler <0x00000080, "image_msaa_load", 1>; 885 886defm IMAGE_BVH_INTERSECT_RAY : MIMG_IntersectRay<0xe6, "image_bvh_intersect_ray", 11, 0>; 887defm IMAGE_BVH_INTERSECT_RAY_a16 : MIMG_IntersectRay<0xe6, "image_bvh_intersect_ray", 8, 1>; 888defm IMAGE_BVH64_INTERSECT_RAY : MIMG_IntersectRay<0xe7, "image_bvh64_intersect_ray", 12, 0>; 889defm IMAGE_BVH64_INTERSECT_RAY_a16 : MIMG_IntersectRay<0xe7, "image_bvh64_intersect_ray", 9, 1>; 890 891/********** ========================================= **********/ 892/********** Table of dimension-aware image intrinsics **********/ 893/********** ========================================= **********/ 894 895class ImageDimIntrinsicInfo<AMDGPUImageDimIntrinsic I> { 896 Intrinsic Intr = I; 897 MIMGBaseOpcode BaseOpcode = !cast<MIMGBaseOpcode>(!strconcat("IMAGE_", I.P.OpMod)); 898 AMDGPUDimProps Dim = I.P.Dim; 899 AMDGPUImageDimIntrinsicEval DimEval = AMDGPUImageDimIntrinsicEval<I.P>; 900 901 bits<8> NumGradients = DimEval.NumGradientArgs; 902 bits<8> NumDmask = DimEval.NumDmaskArgs; 903 bits<8> NumData = DimEval.NumDataArgs; 904 bits<8> NumVAddrs = DimEval.NumVAddrArgs; 905 bits<8> NumArgs = !add(DimEval.CachePolicyArgIndex, 1); 906 907 bits<8> DMaskIndex = DimEval.DmaskArgIndex; 908 bits<8> VAddrStart = DimEval.VAddrArgIndex; 909 bits<8> GradientStart = DimEval.GradientArgIndex; 910 bits<8> CoordStart = DimEval.CoordArgIndex; 911 bits<8> LodIndex = DimEval.LodArgIndex; 912 bits<8> MipIndex = DimEval.MipArgIndex; 913 bits<8> VAddrEnd = !add(DimEval.VAddrArgIndex, DimEval.NumVAddrArgs); 914 bits<8> RsrcIndex = DimEval.RsrcArgIndex; 915 bits<8> SampIndex = DimEval.SampArgIndex; 916 bits<8> UnormIndex = DimEval.UnormArgIndex; 917 bits<8> TexFailCtrlIndex = DimEval.TexFailCtrlArgIndex; 918 bits<8> CachePolicyIndex = DimEval.CachePolicyArgIndex; 919 920 bits<8> GradientTyArg = !add(I.P.NumRetAndDataAnyTypes, 921 !foldl(0, I.P.ExtraAddrArgs, cnt, arg, !add(cnt, arg.Type.isAny))); 922 bits<8> CoordTyArg = !add(GradientTyArg, !if(I.P.Gradients, 1, 0)); 923} 924 925def ImageDimIntrinsicTable : GenericTable { 926 let FilterClass = "ImageDimIntrinsicInfo"; 927 let Fields = ["Intr", "BaseOpcode", "Dim", "NumGradients", "NumDmask", "NumData", "NumVAddrs", "NumArgs", 928 "DMaskIndex", "VAddrStart", "GradientStart", "CoordStart", "LodIndex", "MipIndex", "VAddrEnd", 929 "RsrcIndex", "SampIndex", "UnormIndex", "TexFailCtrlIndex", "CachePolicyIndex", 930 "GradientTyArg", "CoordTyArg"]; 931 string TypeOf_BaseOpcode = "MIMGBaseOpcode"; 932 string TypeOf_Dim = "MIMGDim"; 933 934 let PrimaryKey = ["Intr"]; 935 let PrimaryKeyName = "getImageDimIntrinsicInfo"; 936 let PrimaryKeyEarlyOut = 1; 937} 938 939def getImageDimInstrinsicByBaseOpcode : SearchIndex { 940 let Table = ImageDimIntrinsicTable; 941 let Key = ["BaseOpcode", "Dim"]; 942} 943 944foreach intr = !listconcat(AMDGPUImageDimIntrinsics, 945 AMDGPUImageDimAtomicIntrinsics) in { 946 def : ImageDimIntrinsicInfo<intr>; 947} 948 949// L to LZ Optimization Mapping 950def : MIMGLZMapping<IMAGE_SAMPLE_L, IMAGE_SAMPLE_LZ>; 951def : MIMGLZMapping<IMAGE_SAMPLE_C_L, IMAGE_SAMPLE_C_LZ>; 952def : MIMGLZMapping<IMAGE_SAMPLE_L_O, IMAGE_SAMPLE_LZ_O>; 953def : MIMGLZMapping<IMAGE_SAMPLE_C_L_O, IMAGE_SAMPLE_C_LZ_O>; 954def : MIMGLZMapping<IMAGE_GATHER4_L, IMAGE_GATHER4_LZ>; 955def : MIMGLZMapping<IMAGE_GATHER4_C_L, IMAGE_GATHER4_C_LZ>; 956def : MIMGLZMapping<IMAGE_GATHER4_L_O, IMAGE_GATHER4_LZ_O>; 957def : MIMGLZMapping<IMAGE_GATHER4_C_L_O, IMAGE_GATHER4_C_LZ_O>; 958 959// MIP to NONMIP Optimization Mapping 960def : MIMGMIPMapping<IMAGE_LOAD_MIP, IMAGE_LOAD>; 961def : MIMGMIPMapping<IMAGE_STORE_MIP, IMAGE_STORE>; 962 963// G to G16 Optimization Mapping 964def : MIMGG16Mapping<IMAGE_SAMPLE_D, IMAGE_SAMPLE_D_G16>; 965def : MIMGG16Mapping<IMAGE_SAMPLE_D_CL, IMAGE_SAMPLE_D_CL_G16>; 966def : MIMGG16Mapping<IMAGE_SAMPLE_C_D, IMAGE_SAMPLE_C_D_G16>; 967def : MIMGG16Mapping<IMAGE_SAMPLE_C_D_CL, IMAGE_SAMPLE_C_D_CL_G16>; 968def : MIMGG16Mapping<IMAGE_SAMPLE_D_O, IMAGE_SAMPLE_D_O_G16>; 969def : MIMGG16Mapping<IMAGE_SAMPLE_D_CL_O, IMAGE_SAMPLE_D_CL_O_G16>; 970def : MIMGG16Mapping<IMAGE_SAMPLE_C_D_O, IMAGE_SAMPLE_C_D_O_G16>; 971def : MIMGG16Mapping<IMAGE_SAMPLE_C_D_CL_O, IMAGE_SAMPLE_C_D_CL_O_G16>; 972def : MIMGG16Mapping<IMAGE_SAMPLE_CD, IMAGE_SAMPLE_CD_G16>; 973def : MIMGG16Mapping<IMAGE_SAMPLE_CD_CL, IMAGE_SAMPLE_CD_CL_G16>; 974def : MIMGG16Mapping<IMAGE_SAMPLE_C_CD, IMAGE_SAMPLE_C_CD_G16>; 975def : MIMGG16Mapping<IMAGE_SAMPLE_C_CD_CL, IMAGE_SAMPLE_C_CD_CL_G16>; 976def : MIMGG16Mapping<IMAGE_SAMPLE_CD_O, IMAGE_SAMPLE_CD_O_G16>; 977def : MIMGG16Mapping<IMAGE_SAMPLE_CD_CL_O, IMAGE_SAMPLE_CD_CL_O_G16>; 978def : MIMGG16Mapping<IMAGE_SAMPLE_C_CD_O, IMAGE_SAMPLE_C_CD_O_G16>; 979def : MIMGG16Mapping<IMAGE_SAMPLE_C_CD_CL_O, IMAGE_SAMPLE_C_CD_CL_O_G16>; 980