1//===-- SIInstrFormats.td - SI Instruction Encodings ----------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// SI Instruction format definitions.
10//
11//===----------------------------------------------------------------------===//
12
13class InstSI <dag outs, dag ins, string asm = "",
14              list<dag> pattern = []> :
15  AMDGPUInst<outs, ins, asm, pattern>, GCNPredicateControl {
16  // Low bits - basic encoding information.
17  field bit SALU = 0;
18  field bit VALU = 0;
19
20  // SALU instruction formats.
21  field bit SOP1 = 0;
22  field bit SOP2 = 0;
23  field bit SOPC = 0;
24  field bit SOPK = 0;
25  field bit SOPP = 0;
26
27  // VALU instruction formats.
28  field bit VOP1 = 0;
29  field bit VOP2 = 0;
30  field bit VOPC = 0;
31  field bit VOP3 = 0;
32  field bit VOP3P = 0;
33  field bit VINTRP = 0;
34  field bit SDWA = 0;
35  field bit DPP = 0;
36  field bit TRANS = 0;
37
38  // Memory instruction formats.
39  field bit MUBUF = 0;
40  field bit MTBUF = 0;
41  field bit SMRD = 0;
42  field bit MIMG = 0;
43  field bit EXP = 0;
44  field bit FLAT = 0;
45  field bit DS = 0;
46
47  // Pseudo instruction formats.
48  field bit VGPRSpill = 0;
49  field bit SGPRSpill = 0;
50
51  // LDSDIR instruction format.
52  field bit LDSDIR = 0;
53
54  // VINTERP instruction format.
55  field bit VINTERP = 0;
56
57  // High bits - other information.
58  field bit VM_CNT = 0;
59  field bit EXP_CNT = 0;
60  field bit LGKM_CNT = 0;
61
62  // Whether WQM _must_ be enabled for this instruction.
63  field bit WQM = 0;
64
65  // Whether WQM _must_ be disabled for this instruction.
66  field bit DisableWQM = 0;
67
68  field bit Gather4 = 0;
69
70  // Most sopk treat the immediate as a signed 16-bit, however some
71  // use it as unsigned.
72  field bit SOPKZext = 0;
73
74  // This is an s_store_dword* instruction that requires a cache flush
75  // on wave termination. It is necessary to distinguish from mayStore
76  // SMEM instructions like the cache flush ones.
77  field bit ScalarStore = 0;
78
79  // Whether the operands can be ignored when computing the
80  // instruction size.
81  field bit FixedSize = 0;
82
83  // This bit tells the assembler to use the 32-bit encoding in case it
84  // is unable to infer the encoding from the operands.
85  field bit VOPAsmPrefer32Bit = 0;
86
87  // This bit indicates that this is a VOP3 opcode which supports op_sel
88  // modifier.
89  field bit VOP3_OPSEL = 0;
90
91  // Is it possible for this instruction to be atomic?
92  field bit maybeAtomic = 0;
93
94  // This bit indicates that this is a VI instruction which is renamed
95  // in GFX9. Required for correct mapping from pseudo to MC.
96  field bit renamedInGFX9 = 0;
97
98  // This bit indicates that this has a floating point result type, so
99  // the clamp modifier has floating point semantics.
100  field bit FPClamp = 0;
101
102  // This bit indicates that instruction may support integer clamping
103  // which depends on GPU features.
104  field bit IntClamp = 0;
105
106  // This field indicates that the clamp applies to the low component
107  // of a packed output register.
108  field bit ClampLo = 0;
109
110  // This field indicates that the clamp applies to the high component
111  // of a packed output register.
112  field bit ClampHi = 0;
113
114  // This bit indicates that this is a packed VOP3P instruction
115  field bit IsPacked = 0;
116
117  // This bit indicates that this is a D16 buffer instruction.
118  field bit D16Buf = 0;
119
120  // This field indicates that FLAT instruction accesses FLAT_GLBL segment.
121  // Must be 0 for non-FLAT instructions.
122  field bit FlatGlobal = 0;
123
124  // Reads the mode register, usually for FP environment.
125  field bit ReadsModeReg = 0;
126
127  // This bit indicates that this uses the floating point double precision
128  // rounding mode flags
129  field bit FPDPRounding = 0;
130
131  // Instruction is FP atomic.
132  field bit FPAtomic = 0;
133
134  // This bit indicates that this is one of MFMA instructions.
135  field bit IsMAI = 0;
136
137  // This bit indicates that this is one of DOT instructions.
138  field bit IsDOT = 0;
139
140  // This field indicates that FLAT instruction accesses FLAT_SCRATCH segment.
141  // Must be 0 for non-FLAT instructions.
142  field bit FlatScratch = 0;
143
144  // Atomic without a return.
145  field bit IsAtomicNoRet = 0;
146
147  // Atomic with return.
148  field bit IsAtomicRet = 0;
149
150  // This bit indicates that this is one of WMMA instructions.
151  field bit IsWMMA = 0;
152
153  // These need to be kept in sync with the enum in SIInstrFlags.
154  let TSFlags{0} = SALU;
155  let TSFlags{1} = VALU;
156
157  let TSFlags{2} = SOP1;
158  let TSFlags{3} = SOP2;
159  let TSFlags{4} = SOPC;
160  let TSFlags{5} = SOPK;
161  let TSFlags{6} = SOPP;
162
163  let TSFlags{7} = VOP1;
164  let TSFlags{8} = VOP2;
165  let TSFlags{9} = VOPC;
166  let TSFlags{10} = VOP3;
167  let TSFlags{12} = VOP3P;
168
169  let TSFlags{13} = VINTRP;
170  let TSFlags{14} = SDWA;
171  let TSFlags{15} = DPP;
172  let TSFlags{16} = TRANS;
173
174  let TSFlags{17} = MUBUF;
175  let TSFlags{18} = MTBUF;
176  let TSFlags{19} = SMRD;
177  let TSFlags{20} = MIMG;
178  let TSFlags{21} = EXP;
179  let TSFlags{22} = FLAT;
180  let TSFlags{23} = DS;
181
182  let TSFlags{24} = VGPRSpill;
183  let TSFlags{25} = SGPRSpill;
184
185  let TSFlags{26} = LDSDIR;
186  let TSFlags{27} = VINTERP;
187
188  let TSFlags{32} = VM_CNT;
189  let TSFlags{33} = EXP_CNT;
190  let TSFlags{34} = LGKM_CNT;
191
192  let TSFlags{35} = WQM;
193  let TSFlags{36} = DisableWQM;
194  let TSFlags{37} = Gather4;
195
196  let TSFlags{38} = SOPKZext;
197  let TSFlags{39} = ScalarStore;
198  let TSFlags{40} = FixedSize;
199  let TSFlags{41} = VOPAsmPrefer32Bit;
200  let TSFlags{42} = VOP3_OPSEL;
201
202  let TSFlags{43} = maybeAtomic;
203  let TSFlags{44} = renamedInGFX9;
204
205  let TSFlags{45} = FPClamp;
206  let TSFlags{46} = IntClamp;
207  let TSFlags{47} = ClampLo;
208  let TSFlags{48} = ClampHi;
209
210  let TSFlags{49} = IsPacked;
211
212  let TSFlags{50} = D16Buf;
213
214  let TSFlags{51} = FlatGlobal;
215
216  let TSFlags{52} = FPDPRounding;
217
218  let TSFlags{53} = FPAtomic;
219
220  let TSFlags{54} = IsMAI;
221
222  let TSFlags{55} = IsDOT;
223
224  let TSFlags{56} = FlatScratch;
225
226  let TSFlags{57} = IsAtomicNoRet;
227
228  let TSFlags{58} = IsAtomicRet;
229
230  let TSFlags{59} = IsWMMA;
231
232  let SchedRW = [Write32Bit];
233
234  let AsmVariantName = AMDGPUAsmVariants.Default;
235
236  // Avoid changing source registers in a way that violates constant bus read limitations.
237  let hasExtraSrcRegAllocReq = !or(VOP1, VOP2, VOP3, VOPC, SDWA, VALU);
238}
239
240class PseudoInstSI<dag outs, dag ins, list<dag> pattern = [], string asm = "">
241  : InstSI<outs, ins, asm, pattern> {
242  let isPseudo = 1;
243  let isCodeGenOnly = 1;
244}
245
246class SPseudoInstSI<dag outs, dag ins, list<dag> pattern = [], string asm = "">
247  : PseudoInstSI<outs, ins, pattern, asm> {
248  let SALU = 1;
249}
250
251class VPseudoInstSI<dag outs, dag ins, list<dag> pattern = [], string asm = "">
252  : PseudoInstSI<outs, ins, pattern, asm> {
253  let VALU = 1;
254  let Uses = [EXEC];
255}
256
257class CFPseudoInstSI<dag outs, dag ins, list<dag> pattern = [],
258  bit UseExec = 0, bit DefExec = 0> :
259  SPseudoInstSI<outs, ins, pattern> {
260
261  let Uses = !if(UseExec, [EXEC], []);
262  let Defs = !if(DefExec, [EXEC, SCC], [SCC]);
263  let mayLoad = 0;
264  let mayStore = 0;
265  let hasSideEffects = 0;
266}
267
268class Enc32 {
269  field bits<32> Inst;
270  int Size = 4;
271}
272
273class Enc64 {
274  field bits<64> Inst;
275  int Size = 8;
276}
277
278class Enc96 {
279  field bits<96> Inst;
280  int Size = 12;
281}
282
283def CPolBit {
284  int GLC = 0;
285  int SLC = 1;
286  int DLC = 2;
287  int SCC = 4;
288}
289
290class VOPDstOperand <RegisterClass rc> : RegisterOperand <rc, "printVOPDst">;
291
292class VINTRPe <bits<2> op> : Enc32 {
293  bits<8> vdst;
294  bits<8> vsrc;
295  bits<2> attrchan;
296  bits<6> attr;
297
298  let Inst{7-0} = vsrc;
299  let Inst{9-8} = attrchan;
300  let Inst{15-10} = attr;
301  let Inst{17-16} = op;
302  let Inst{25-18} = vdst;
303  let Inst{31-26} = 0x32; // encoding
304}
305
306class MIMGe_gfxpre11 : Enc64 {
307  bits<10> vdata;
308  bits<4> dmask;
309  bits<1> unorm;
310  bits<5> cpol;
311  bits<1> r128;
312  bits<1> tfe;
313  bits<1> lwe;
314  bit d16;
315  bits<7> srsrc;
316  bits<7> ssamp;
317
318  let Inst{11-8} = dmask;
319  let Inst{12} = unorm;
320  let Inst{13} = cpol{CPolBit.GLC};
321  let Inst{15} = r128;
322  let Inst{17} = lwe;
323  let Inst{25} = cpol{CPolBit.SLC};
324  let Inst{31-26} = 0x3c;
325  let Inst{47-40} = vdata{7-0};
326  let Inst{52-48} = srsrc{6-2};
327  let Inst{57-53} = ssamp{6-2};
328  let Inst{63} = d16;
329}
330
331class MIMGe_gfx6789 <bits<8> op> : MIMGe_gfxpre11 {
332  bits<8> vaddr;
333  bits<1> da;
334
335  let Inst{0} = op{7};
336  let Inst{7} = cpol{CPolBit.SCC};
337  let Inst{14} = da;
338  let Inst{16} = tfe;
339  let Inst{24-18} = op{6-0};
340  let Inst{39-32} = vaddr;
341}
342
343class MIMGe_gfx90a <bits<8> op> : MIMGe_gfxpre11 {
344  bits<8> vaddr;
345  bits<1> da;
346
347  let Inst{0} = op{7};
348  let Inst{7} = cpol{CPolBit.SCC};
349  let Inst{14} = da;
350  let Inst{16} = vdata{9}; // ACC bit
351  let Inst{24-18} = op{6-0};
352  let Inst{39-32} = vaddr;
353}
354
355class MIMGe_gfx10 <bits<8> op> : MIMGe_gfxpre11 {
356  bits<8> vaddr0;
357  bits<3> dim;
358  bits<2> nsa;
359  bits<1> a16;
360
361  let Inst{0} = op{7};
362  let Inst{2-1} = nsa;
363  let Inst{5-3} = dim;
364  let Inst{7} = cpol{CPolBit.DLC};
365  let Inst{16} = tfe;
366  let Inst{24-18} = op{6-0};
367  let Inst{39-32} = vaddr0;
368  let Inst{62} = a16;
369}
370
371class MIMGe_gfx11 <bits<8> op> : Enc64 {
372  bits<8> vdata;
373  bits<4> dmask;
374  bits<1> unorm;
375  bits<5> cpol;
376  bits<1> r128;
377  bits<1> tfe;
378  bits<1> lwe;
379  bits<7> srsrc;
380  bits<7> ssamp;
381  bit d16;
382  bits<1> a16;
383  bits<8> vaddr0;
384  bits<3> dim;
385  bits<1> nsa;
386
387  let Inst{0} = nsa;
388  let Inst{4-2} = dim;
389  let Inst{7} = unorm;
390  let Inst{11-8} = dmask;
391  let Inst{12} = cpol{CPolBit.SLC};
392  let Inst{13} = cpol{CPolBit.DLC};
393  let Inst{14} = cpol{CPolBit.GLC};
394  let Inst{15} = r128;
395  let Inst{16} = a16;
396  let Inst{17} = d16;
397  let Inst{25-18} = op;
398  let Inst{31-26} = 0x3c;
399  let Inst{39-32} = vaddr0;
400  let Inst{47-40} = vdata;
401  let Inst{52-48} = srsrc{6-2};
402  let Inst{53} = tfe;
403  let Inst{54} = lwe;
404  let Inst{62-58} = ssamp{6-2};
405}
406
407class EXPe : Enc64 {
408  bits<4> en;
409  bits<6> tgt;
410  bits<1> done;
411  bits<8> src0;
412  bits<8> src1;
413  bits<8> src2;
414  bits<8> src3;
415
416  let Inst{3-0} = en;
417  let Inst{9-4} = tgt;
418  let Inst{11} = done;
419  let Inst{31-26} = 0x3e;
420  let Inst{39-32} = src0;
421  let Inst{47-40} = src1;
422  let Inst{55-48} = src2;
423  let Inst{63-56} = src3;
424}
425
426// Pre-GFX11 encoding has compr and vm bits.
427class EXPe_ComprVM : EXPe {
428  bits<1> compr;
429  bits<1> vm;
430
431  let Inst{10} = compr;
432  let Inst{12} = vm;
433}
434
435// GFX11+ encoding has row bit.
436class EXPe_Row : EXPe {
437  bits<1> row;
438
439  let Inst{13} = row;
440}
441
442let Uses = [EXEC] in {
443
444class VINTRPCommon <dag outs, dag ins, string asm, list<dag> pattern> :
445    InstSI <outs, ins, asm, pattern> {
446  let VINTRP = 1;
447  // VINTRP instructions read parameter values from LDS, but these parameter
448  // values are stored outside of the LDS memory that is allocated to the
449  // shader for general purpose use.
450  //
451  // While it may be possible for ds_read/ds_write instructions to access
452  // the parameter values in LDS, this would essentially be an out-of-bounds
453  // memory access which we consider to be undefined behavior.
454  //
455  // So even though these instructions read memory, this memory is outside the
456  // addressable memory space for the shader, and we consider these instructions
457  // to be readnone.
458  let mayLoad = 0;
459  let mayStore = 0;
460  let hasSideEffects = 0;
461  let VALU = 1;
462}
463
464} // End Uses = [EXEC]
465