10b57cec5SDimitry Andric //===- SIInstrInfo.h - SI Instruction Info Interface ------------*- C++ -*-===//
20b57cec5SDimitry Andric //
30b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
40b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information.
50b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
60b57cec5SDimitry Andric //
70b57cec5SDimitry Andric //===----------------------------------------------------------------------===//
80b57cec5SDimitry Andric //
90b57cec5SDimitry Andric /// \file
100b57cec5SDimitry Andric /// Interface definition for SIInstrInfo.
110b57cec5SDimitry Andric //
120b57cec5SDimitry Andric //===----------------------------------------------------------------------===//
130b57cec5SDimitry Andric
140b57cec5SDimitry Andric #ifndef LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
150b57cec5SDimitry Andric #define LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
160b57cec5SDimitry Andric
17e8d8bef9SDimitry Andric #include "AMDGPUMIRFormatter.h"
1881ad6265SDimitry Andric #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
190b57cec5SDimitry Andric #include "SIRegisterInfo.h"
200b57cec5SDimitry Andric #include "Utils/AMDGPUBaseInfo.h"
210b57cec5SDimitry Andric #include "llvm/ADT/SetVector.h"
22e8d8bef9SDimitry Andric #include "llvm/CodeGen/TargetInstrInfo.h"
23480093f4SDimitry Andric #include "llvm/CodeGen/TargetSchedule.h"
240b57cec5SDimitry Andric
250b57cec5SDimitry Andric #define GET_INSTRINFO_HEADER
260b57cec5SDimitry Andric #include "AMDGPUGenInstrInfo.inc"
270b57cec5SDimitry Andric
280b57cec5SDimitry Andric namespace llvm {
290b57cec5SDimitry Andric
300b57cec5SDimitry Andric class APInt;
31e8d8bef9SDimitry Andric class GCNSubtarget;
32e8d8bef9SDimitry Andric class LiveVariables;
330b57cec5SDimitry Andric class MachineDominatorTree;
340b57cec5SDimitry Andric class MachineRegisterInfo;
350b57cec5SDimitry Andric class RegScavenger;
360b57cec5SDimitry Andric class TargetRegisterClass;
37e8d8bef9SDimitry Andric class ScheduleHazardRecognizer;
380b57cec5SDimitry Andric
3981ad6265SDimitry Andric /// Mark the MMO of a uniform load if there are no potentially clobbering stores
4081ad6265SDimitry Andric /// on any path from the start of an entry function to this load.
4181ad6265SDimitry Andric static const MachineMemOperand::Flags MONoClobber =
4281ad6265SDimitry Andric MachineMemOperand::MOTargetFlag1;
4381ad6265SDimitry Andric
447a6dacacSDimitry Andric /// Mark the MMO of a load as the last use.
457a6dacacSDimitry Andric static const MachineMemOperand::Flags MOLastUse =
467a6dacacSDimitry Andric MachineMemOperand::MOTargetFlag2;
477a6dacacSDimitry Andric
4806c3fb27SDimitry Andric /// Utility to store machine instructions worklist.
4906c3fb27SDimitry Andric struct SIInstrWorklist {
505f757f3fSDimitry Andric SIInstrWorklist() = default;
5106c3fb27SDimitry Andric
5206c3fb27SDimitry Andric void insert(MachineInstr *MI);
5306c3fb27SDimitry Andric
topSIInstrWorklist5406c3fb27SDimitry Andric MachineInstr *top() const {
5506c3fb27SDimitry Andric auto iter = InstrList.begin();
5606c3fb27SDimitry Andric return *iter;
5706c3fb27SDimitry Andric }
5806c3fb27SDimitry Andric
erase_topSIInstrWorklist5906c3fb27SDimitry Andric void erase_top() {
6006c3fb27SDimitry Andric auto iter = InstrList.begin();
6106c3fb27SDimitry Andric InstrList.erase(iter);
6206c3fb27SDimitry Andric }
6306c3fb27SDimitry Andric
emptySIInstrWorklist6406c3fb27SDimitry Andric bool empty() const { return InstrList.empty(); }
6506c3fb27SDimitry Andric
clearSIInstrWorklist6606c3fb27SDimitry Andric void clear() {
6706c3fb27SDimitry Andric InstrList.clear();
6806c3fb27SDimitry Andric DeferredList.clear();
6906c3fb27SDimitry Andric }
7006c3fb27SDimitry Andric
7106c3fb27SDimitry Andric bool isDeferred(MachineInstr *MI);
7206c3fb27SDimitry Andric
getDeferredListSIInstrWorklist7306c3fb27SDimitry Andric SetVector<MachineInstr *> &getDeferredList() { return DeferredList; }
7406c3fb27SDimitry Andric
7506c3fb27SDimitry Andric private:
7606c3fb27SDimitry Andric /// InstrList contains the MachineInstrs.
7706c3fb27SDimitry Andric SetVector<MachineInstr *> InstrList;
7806c3fb27SDimitry Andric /// Deferred instructions are specific MachineInstr
7906c3fb27SDimitry Andric /// that will be added by insert method.
8006c3fb27SDimitry Andric SetVector<MachineInstr *> DeferredList;
8106c3fb27SDimitry Andric };
8206c3fb27SDimitry Andric
830b57cec5SDimitry Andric class SIInstrInfo final : public AMDGPUGenInstrInfo {
840b57cec5SDimitry Andric private:
850b57cec5SDimitry Andric const SIRegisterInfo RI;
860b57cec5SDimitry Andric const GCNSubtarget &ST;
87480093f4SDimitry Andric TargetSchedModel SchedModel;
88e8d8bef9SDimitry Andric mutable std::unique_ptr<AMDGPUMIRFormatter> Formatter;
890b57cec5SDimitry Andric
900b57cec5SDimitry Andric // The inverse predicate should have the negative value.
910b57cec5SDimitry Andric enum BranchPredicate {
920b57cec5SDimitry Andric INVALID_BR = 0,
930b57cec5SDimitry Andric SCC_TRUE = 1,
940b57cec5SDimitry Andric SCC_FALSE = -1,
950b57cec5SDimitry Andric VCCNZ = 2,
960b57cec5SDimitry Andric VCCZ = -2,
970b57cec5SDimitry Andric EXECNZ = -3,
980b57cec5SDimitry Andric EXECZ = 3
990b57cec5SDimitry Andric };
1000b57cec5SDimitry Andric
1010b57cec5SDimitry Andric using SetVectorType = SmallSetVector<MachineInstr *, 32>;
1020b57cec5SDimitry Andric
1030b57cec5SDimitry Andric static unsigned getBranchOpcode(BranchPredicate Cond);
1040b57cec5SDimitry Andric static BranchPredicate getBranchPredicate(unsigned Opcode);
1050b57cec5SDimitry Andric
1060b57cec5SDimitry Andric public:
1070b57cec5SDimitry Andric unsigned buildExtractSubReg(MachineBasicBlock::iterator MI,
1080b57cec5SDimitry Andric MachineRegisterInfo &MRI,
1095f757f3fSDimitry Andric const MachineOperand &SuperReg,
1100b57cec5SDimitry Andric const TargetRegisterClass *SuperRC,
1110b57cec5SDimitry Andric unsigned SubIdx,
1120b57cec5SDimitry Andric const TargetRegisterClass *SubRC) const;
1135f757f3fSDimitry Andric MachineOperand buildExtractSubRegOrImm(
1145f757f3fSDimitry Andric MachineBasicBlock::iterator MI, MachineRegisterInfo &MRI,
1155f757f3fSDimitry Andric const MachineOperand &SuperReg, const TargetRegisterClass *SuperRC,
1165f757f3fSDimitry Andric unsigned SubIdx, const TargetRegisterClass *SubRC) const;
1175f757f3fSDimitry Andric
1180b57cec5SDimitry Andric private:
1190b57cec5SDimitry Andric void swapOperands(MachineInstr &Inst) const;
1200b57cec5SDimitry Andric
121e8d8bef9SDimitry Andric std::pair<bool, MachineBasicBlock *>
12206c3fb27SDimitry Andric moveScalarAddSub(SIInstrWorklist &Worklist, MachineInstr &Inst,
1230b57cec5SDimitry Andric MachineDominatorTree *MDT = nullptr) const;
1240b57cec5SDimitry Andric
12506c3fb27SDimitry Andric void lowerSelect(SIInstrWorklist &Worklist, MachineInstr &Inst,
1265ffd83dbSDimitry Andric MachineDominatorTree *MDT = nullptr) const;
1275ffd83dbSDimitry Andric
12806c3fb27SDimitry Andric void lowerScalarAbs(SIInstrWorklist &Worklist, MachineInstr &Inst) const;
1290b57cec5SDimitry Andric
13006c3fb27SDimitry Andric void lowerScalarXnor(SIInstrWorklist &Worklist, MachineInstr &Inst) const;
1310b57cec5SDimitry Andric
13206c3fb27SDimitry Andric void splitScalarNotBinop(SIInstrWorklist &Worklist, MachineInstr &Inst,
1330b57cec5SDimitry Andric unsigned Opcode) const;
1340b57cec5SDimitry Andric
13506c3fb27SDimitry Andric void splitScalarBinOpN2(SIInstrWorklist &Worklist, MachineInstr &Inst,
1360b57cec5SDimitry Andric unsigned Opcode) const;
1370b57cec5SDimitry Andric
13806c3fb27SDimitry Andric void splitScalar64BitUnaryOp(SIInstrWorklist &Worklist, MachineInstr &Inst,
13906c3fb27SDimitry Andric unsigned Opcode, bool Swap = false) const;
1400b57cec5SDimitry Andric
14106c3fb27SDimitry Andric void splitScalar64BitBinaryOp(SIInstrWorklist &Worklist, MachineInstr &Inst,
1420b57cec5SDimitry Andric unsigned Opcode,
1430b57cec5SDimitry Andric MachineDominatorTree *MDT = nullptr) const;
1440b57cec5SDimitry Andric
1451db9f3b2SDimitry Andric void splitScalarSMulU64(SIInstrWorklist &Worklist, MachineInstr &Inst,
1461db9f3b2SDimitry Andric MachineDominatorTree *MDT) const;
1471db9f3b2SDimitry Andric
1481db9f3b2SDimitry Andric void splitScalarSMulPseudo(SIInstrWorklist &Worklist, MachineInstr &Inst,
1491db9f3b2SDimitry Andric MachineDominatorTree *MDT) const;
1501db9f3b2SDimitry Andric
15106c3fb27SDimitry Andric void splitScalar64BitXnor(SIInstrWorklist &Worklist, MachineInstr &Inst,
1520b57cec5SDimitry Andric MachineDominatorTree *MDT = nullptr) const;
1530b57cec5SDimitry Andric
15406c3fb27SDimitry Andric void splitScalar64BitBCNT(SIInstrWorklist &Worklist,
1550b57cec5SDimitry Andric MachineInstr &Inst) const;
15606c3fb27SDimitry Andric void splitScalar64BitBFE(SIInstrWorklist &Worklist, MachineInstr &Inst) const;
157cb14a3feSDimitry Andric void splitScalar64BitCountOp(SIInstrWorklist &Worklist, MachineInstr &Inst,
158cb14a3feSDimitry Andric unsigned Opcode,
159cb14a3feSDimitry Andric MachineDominatorTree *MDT = nullptr) const;
16006c3fb27SDimitry Andric void movePackToVALU(SIInstrWorklist &Worklist, MachineRegisterInfo &MRI,
1610b57cec5SDimitry Andric MachineInstr &Inst) const;
1620b57cec5SDimitry Andric
1635ffd83dbSDimitry Andric void addUsersToMoveToVALUWorklist(Register Reg, MachineRegisterInfo &MRI,
16406c3fb27SDimitry Andric SIInstrWorklist &Worklist) const;
1650b57cec5SDimitry Andric
1660b57cec5SDimitry Andric void addSCCDefUsersToVALUWorklist(MachineOperand &Op,
1670b57cec5SDimitry Andric MachineInstr &SCCDefInst,
16806c3fb27SDimitry Andric SIInstrWorklist &Worklist,
169349cc55cSDimitry Andric Register NewCond = Register()) const;
170bdd1243dSDimitry Andric void addSCCDefsToVALUWorklist(MachineInstr *SCCUseInst,
17106c3fb27SDimitry Andric SIInstrWorklist &Worklist) const;
1720b57cec5SDimitry Andric
1730b57cec5SDimitry Andric const TargetRegisterClass *
1740b57cec5SDimitry Andric getDestEquivalentVGPRClass(const MachineInstr &Inst) const;
1750b57cec5SDimitry Andric
1760b57cec5SDimitry Andric bool checkInstOffsetsDoNotOverlap(const MachineInstr &MIa,
1770b57cec5SDimitry Andric const MachineInstr &MIb) const;
1780b57cec5SDimitry Andric
1795ffd83dbSDimitry Andric Register findUsedSGPR(const MachineInstr &MI, int OpIndices[3]) const;
1800b57cec5SDimitry Andric
1810b57cec5SDimitry Andric protected:
1825f757f3fSDimitry Andric /// If the specific machine instruction is a instruction that moves/copies
1835f757f3fSDimitry Andric /// value from one register to another register return destination and source
1845f757f3fSDimitry Andric /// registers as machine operands.
1855f757f3fSDimitry Andric std::optional<DestSourcePair>
1865f757f3fSDimitry Andric isCopyInstrImpl(const MachineInstr &MI) const override;
1875f757f3fSDimitry Andric
1880b57cec5SDimitry Andric bool swapSourceModifiers(MachineInstr &MI,
1890b57cec5SDimitry Andric MachineOperand &Src0, unsigned Src0OpName,
1900b57cec5SDimitry Andric MachineOperand &Src1, unsigned Src1OpName) const;
1910b57cec5SDimitry Andric
1920b57cec5SDimitry Andric MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
1930b57cec5SDimitry Andric unsigned OpIdx0,
1940b57cec5SDimitry Andric unsigned OpIdx1) const override;
1950b57cec5SDimitry Andric
1960b57cec5SDimitry Andric public:
1970b57cec5SDimitry Andric enum TargetOperandFlags {
1980b57cec5SDimitry Andric MO_MASK = 0xf,
1990b57cec5SDimitry Andric
2000b57cec5SDimitry Andric MO_NONE = 0,
2010b57cec5SDimitry Andric // MO_GOTPCREL -> symbol@GOTPCREL -> R_AMDGPU_GOTPCREL.
2020b57cec5SDimitry Andric MO_GOTPCREL = 1,
2030b57cec5SDimitry Andric // MO_GOTPCREL32_LO -> symbol@gotpcrel32@lo -> R_AMDGPU_GOTPCREL32_LO.
2040b57cec5SDimitry Andric MO_GOTPCREL32 = 2,
2050b57cec5SDimitry Andric MO_GOTPCREL32_LO = 2,
2060b57cec5SDimitry Andric // MO_GOTPCREL32_HI -> symbol@gotpcrel32@hi -> R_AMDGPU_GOTPCREL32_HI.
2070b57cec5SDimitry Andric MO_GOTPCREL32_HI = 3,
2080b57cec5SDimitry Andric // MO_REL32_LO -> symbol@rel32@lo -> R_AMDGPU_REL32_LO.
2090b57cec5SDimitry Andric MO_REL32 = 4,
2100b57cec5SDimitry Andric MO_REL32_LO = 4,
2110b57cec5SDimitry Andric // MO_REL32_HI -> symbol@rel32@hi -> R_AMDGPU_REL32_HI.
2120b57cec5SDimitry Andric MO_REL32_HI = 5,
2130b57cec5SDimitry Andric
214fe6060f1SDimitry Andric MO_FAR_BRANCH_OFFSET = 6,
2150b57cec5SDimitry Andric
2160b57cec5SDimitry Andric MO_ABS32_LO = 8,
2170b57cec5SDimitry Andric MO_ABS32_HI = 9,
2180b57cec5SDimitry Andric };
2190b57cec5SDimitry Andric
2200b57cec5SDimitry Andric explicit SIInstrInfo(const GCNSubtarget &ST);
2210b57cec5SDimitry Andric
getRegisterInfo()2220b57cec5SDimitry Andric const SIRegisterInfo &getRegisterInfo() const {
2230b57cec5SDimitry Andric return RI;
2240b57cec5SDimitry Andric }
2250b57cec5SDimitry Andric
getSubtarget()226fe6060f1SDimitry Andric const GCNSubtarget &getSubtarget() const {
227fe6060f1SDimitry Andric return ST;
228fe6060f1SDimitry Andric }
229fe6060f1SDimitry Andric
230fcaf7f86SDimitry Andric bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override;
2310b57cec5SDimitry Andric
232fe6060f1SDimitry Andric bool isIgnorableUse(const MachineOperand &MO) const override;
233fe6060f1SDimitry Andric
2345f757f3fSDimitry Andric bool isSafeToSink(MachineInstr &MI, MachineBasicBlock *SuccToSinkTo,
2355f757f3fSDimitry Andric MachineCycleInfo *CI) const override;
2365f757f3fSDimitry Andric
237bdd1243dSDimitry Andric bool areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1, int64_t &Offset0,
238bdd1243dSDimitry Andric int64_t &Offset1) const override;
2390b57cec5SDimitry Andric
2405ffd83dbSDimitry Andric bool getMemOperandsWithOffsetWidth(
2415ffd83dbSDimitry Andric const MachineInstr &LdSt,
2425ffd83dbSDimitry Andric SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset,
2435ffd83dbSDimitry Andric bool &OffsetIsScalable, unsigned &Width,
2440b57cec5SDimitry Andric const TargetRegisterInfo *TRI) const final;
2450b57cec5SDimitry Andric
2465ffd83dbSDimitry Andric bool shouldClusterMemOps(ArrayRef<const MachineOperand *> BaseOps1,
2475f757f3fSDimitry Andric int64_t Offset1, bool OffsetIsScalable1,
2485ffd83dbSDimitry Andric ArrayRef<const MachineOperand *> BaseOps2,
2495f757f3fSDimitry Andric int64_t Offset2, bool OffsetIsScalable2,
2505f757f3fSDimitry Andric unsigned ClusterSize,
2515f757f3fSDimitry Andric unsigned NumBytes) const override;
2520b57cec5SDimitry Andric
2530b57cec5SDimitry Andric bool shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1, int64_t Offset0,
2540b57cec5SDimitry Andric int64_t Offset1, unsigned NumLoads) const override;
2550b57cec5SDimitry Andric
2560b57cec5SDimitry Andric void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
257480093f4SDimitry Andric const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
2580b57cec5SDimitry Andric bool KillSrc) const override;
2590b57cec5SDimitry Andric
2600b57cec5SDimitry Andric void materializeImmediate(MachineBasicBlock &MBB,
261bdd1243dSDimitry Andric MachineBasicBlock::iterator MI, const DebugLoc &DL,
262bdd1243dSDimitry Andric Register DestReg, int64_t Value) const;
2630b57cec5SDimitry Andric
2640b57cec5SDimitry Andric const TargetRegisterClass *getPreferredSelectRegClass(
2650b57cec5SDimitry Andric unsigned Size) const;
2660b57cec5SDimitry Andric
2675ffd83dbSDimitry Andric Register insertNE(MachineBasicBlock *MBB,
2680b57cec5SDimitry Andric MachineBasicBlock::iterator I, const DebugLoc &DL,
2695ffd83dbSDimitry Andric Register SrcReg, int Value) const;
2700b57cec5SDimitry Andric
2715ffd83dbSDimitry Andric Register insertEQ(MachineBasicBlock *MBB,
2720b57cec5SDimitry Andric MachineBasicBlock::iterator I, const DebugLoc &DL,
2735ffd83dbSDimitry Andric Register SrcReg, int Value) const;
2740b57cec5SDimitry Andric
2750b57cec5SDimitry Andric void storeRegToStackSlot(MachineBasicBlock &MBB,
2765ffd83dbSDimitry Andric MachineBasicBlock::iterator MI, Register SrcReg,
2770b57cec5SDimitry Andric bool isKill, int FrameIndex,
2780b57cec5SDimitry Andric const TargetRegisterClass *RC,
279bdd1243dSDimitry Andric const TargetRegisterInfo *TRI,
280bdd1243dSDimitry Andric Register VReg) const override;
2810b57cec5SDimitry Andric
2820b57cec5SDimitry Andric void loadRegFromStackSlot(MachineBasicBlock &MBB,
2835ffd83dbSDimitry Andric MachineBasicBlock::iterator MI, Register DestReg,
2840b57cec5SDimitry Andric int FrameIndex, const TargetRegisterClass *RC,
285bdd1243dSDimitry Andric const TargetRegisterInfo *TRI,
286bdd1243dSDimitry Andric Register VReg) const override;
2870b57cec5SDimitry Andric
2880b57cec5SDimitry Andric bool expandPostRAPseudo(MachineInstr &MI) const override;
2890b57cec5SDimitry Andric
2905f757f3fSDimitry Andric void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
2915f757f3fSDimitry Andric Register DestReg, unsigned SubIdx,
2925f757f3fSDimitry Andric const MachineInstr &Orig,
2935f757f3fSDimitry Andric const TargetRegisterInfo &TRI) const override;
2945f757f3fSDimitry Andric
2958bcb0991SDimitry Andric // Splits a V_MOV_B64_DPP_PSEUDO opcode into a pair of v_mov_b32_dpp
2968bcb0991SDimitry Andric // instructions. Returns a pair of generated instructions.
2978bcb0991SDimitry Andric // Can split either post-RA with physical registers or pre-RA with
2988bcb0991SDimitry Andric // virtual registers. In latter case IR needs to be in SSA form and
2998bcb0991SDimitry Andric // and a REG_SEQUENCE is produced to define original register.
3008bcb0991SDimitry Andric std::pair<MachineInstr*, MachineInstr*>
3018bcb0991SDimitry Andric expandMovDPP64(MachineInstr &MI) const;
3028bcb0991SDimitry Andric
3030b57cec5SDimitry Andric // Returns an opcode that can be used to move a value to a \p DstRC
3040b57cec5SDimitry Andric // register. If there is no hardware instruction that can store to \p
3050b57cec5SDimitry Andric // DstRC, then AMDGPU::COPY is returned.
3060b57cec5SDimitry Andric unsigned getMovOpcode(const TargetRegisterClass *DstRC) const;
3070b57cec5SDimitry Andric
308e8d8bef9SDimitry Andric const MCInstrDesc &getIndirectRegWriteMovRelPseudo(unsigned VecSize,
309e8d8bef9SDimitry Andric unsigned EltSize,
310e8d8bef9SDimitry Andric bool IsSGPR) const;
3115ffd83dbSDimitry Andric
312e8d8bef9SDimitry Andric const MCInstrDesc &getIndirectGPRIDXPseudo(unsigned VecSize,
313e8d8bef9SDimitry Andric bool IsIndirectSrc) const;
3140b57cec5SDimitry Andric LLVM_READONLY
3150b57cec5SDimitry Andric int commuteOpcode(unsigned Opc) const;
3160b57cec5SDimitry Andric
3170b57cec5SDimitry Andric LLVM_READONLY
commuteOpcode(const MachineInstr & MI)3180b57cec5SDimitry Andric inline int commuteOpcode(const MachineInstr &MI) const {
3190b57cec5SDimitry Andric return commuteOpcode(MI.getOpcode());
3200b57cec5SDimitry Andric }
3210b57cec5SDimitry Andric
322bdd1243dSDimitry Andric bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx0,
323bdd1243dSDimitry Andric unsigned &SrcOpIdx1) const override;
3240b57cec5SDimitry Andric
325bdd1243dSDimitry Andric bool findCommutedOpIndices(const MCInstrDesc &Desc, unsigned &SrcOpIdx0,
3260b57cec5SDimitry Andric unsigned &SrcOpIdx1) const;
3270b57cec5SDimitry Andric
3280b57cec5SDimitry Andric bool isBranchOffsetInRange(unsigned BranchOpc,
3290b57cec5SDimitry Andric int64_t BrOffset) const override;
3300b57cec5SDimitry Andric
3310b57cec5SDimitry Andric MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
3320b57cec5SDimitry Andric
333bdd1243dSDimitry Andric /// Return whether the block terminate with divergent branch.
334bdd1243dSDimitry Andric /// Note this only work before lowering the pseudo control flow instructions.
335bdd1243dSDimitry Andric bool hasDivergentBranch(const MachineBasicBlock *MBB) const;
336bdd1243dSDimitry Andric
337349cc55cSDimitry Andric void insertIndirectBranch(MachineBasicBlock &MBB,
3380b57cec5SDimitry Andric MachineBasicBlock &NewDestBB,
339349cc55cSDimitry Andric MachineBasicBlock &RestoreBB, const DebugLoc &DL,
340349cc55cSDimitry Andric int64_t BrOffset, RegScavenger *RS) const override;
3410b57cec5SDimitry Andric
3420b57cec5SDimitry Andric bool analyzeBranchImpl(MachineBasicBlock &MBB,
3430b57cec5SDimitry Andric MachineBasicBlock::iterator I,
3440b57cec5SDimitry Andric MachineBasicBlock *&TBB,
3450b57cec5SDimitry Andric MachineBasicBlock *&FBB,
3460b57cec5SDimitry Andric SmallVectorImpl<MachineOperand> &Cond,
3470b57cec5SDimitry Andric bool AllowModify) const;
3480b57cec5SDimitry Andric
3490b57cec5SDimitry Andric bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
3500b57cec5SDimitry Andric MachineBasicBlock *&FBB,
3510b57cec5SDimitry Andric SmallVectorImpl<MachineOperand> &Cond,
3520b57cec5SDimitry Andric bool AllowModify = false) const override;
3530b57cec5SDimitry Andric
3540b57cec5SDimitry Andric unsigned removeBranch(MachineBasicBlock &MBB,
3550b57cec5SDimitry Andric int *BytesRemoved = nullptr) const override;
3560b57cec5SDimitry Andric
3570b57cec5SDimitry Andric unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
3580b57cec5SDimitry Andric MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
3590b57cec5SDimitry Andric const DebugLoc &DL,
3600b57cec5SDimitry Andric int *BytesAdded = nullptr) const override;
3610b57cec5SDimitry Andric
3620b57cec5SDimitry Andric bool reverseBranchCondition(
3630b57cec5SDimitry Andric SmallVectorImpl<MachineOperand> &Cond) const override;
3640b57cec5SDimitry Andric
3650b57cec5SDimitry Andric bool canInsertSelect(const MachineBasicBlock &MBB,
3665ffd83dbSDimitry Andric ArrayRef<MachineOperand> Cond, Register DstReg,
3675ffd83dbSDimitry Andric Register TrueReg, Register FalseReg, int &CondCycles,
3680b57cec5SDimitry Andric int &TrueCycles, int &FalseCycles) const override;
3690b57cec5SDimitry Andric
3700b57cec5SDimitry Andric void insertSelect(MachineBasicBlock &MBB,
3710b57cec5SDimitry Andric MachineBasicBlock::iterator I, const DebugLoc &DL,
3725ffd83dbSDimitry Andric Register DstReg, ArrayRef<MachineOperand> Cond,
3735ffd83dbSDimitry Andric Register TrueReg, Register FalseReg) const override;
3740b57cec5SDimitry Andric
3750b57cec5SDimitry Andric void insertVectorSelect(MachineBasicBlock &MBB,
3760b57cec5SDimitry Andric MachineBasicBlock::iterator I, const DebugLoc &DL,
3775ffd83dbSDimitry Andric Register DstReg, ArrayRef<MachineOperand> Cond,
3785ffd83dbSDimitry Andric Register TrueReg, Register FalseReg) const;
3790b57cec5SDimitry Andric
380349cc55cSDimitry Andric bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
381349cc55cSDimitry Andric Register &SrcReg2, int64_t &CmpMask,
382349cc55cSDimitry Andric int64_t &CmpValue) const override;
383349cc55cSDimitry Andric
384349cc55cSDimitry Andric bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
385349cc55cSDimitry Andric Register SrcReg2, int64_t CmpMask, int64_t CmpValue,
386349cc55cSDimitry Andric const MachineRegisterInfo *MRI) const override;
387349cc55cSDimitry Andric
3880b57cec5SDimitry Andric bool
3890b57cec5SDimitry Andric areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
3908bcb0991SDimitry Andric const MachineInstr &MIb) const override;
3910b57cec5SDimitry Andric
392349cc55cSDimitry Andric static bool isFoldableCopy(const MachineInstr &MI);
3930b57cec5SDimitry Andric
39481ad6265SDimitry Andric void removeModOperands(MachineInstr &MI) const;
39581ad6265SDimitry Andric
3965ffd83dbSDimitry Andric bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg,
3970b57cec5SDimitry Andric MachineRegisterInfo *MRI) const final;
3980b57cec5SDimitry Andric
getMachineCSELookAheadLimit()3990b57cec5SDimitry Andric unsigned getMachineCSELookAheadLimit() const override { return 500; }
4000b57cec5SDimitry Andric
401349cc55cSDimitry Andric MachineInstr *convertToThreeAddress(MachineInstr &MI, LiveVariables *LV,
402349cc55cSDimitry Andric LiveIntervals *LIS) const override;
4030b57cec5SDimitry Andric
4040b57cec5SDimitry Andric bool isSchedulingBoundary(const MachineInstr &MI,
4050b57cec5SDimitry Andric const MachineBasicBlock *MBB,
4060b57cec5SDimitry Andric const MachineFunction &MF) const override;
4070b57cec5SDimitry Andric
isSALU(const MachineInstr & MI)4080b57cec5SDimitry Andric static bool isSALU(const MachineInstr &MI) {
4090b57cec5SDimitry Andric return MI.getDesc().TSFlags & SIInstrFlags::SALU;
4100b57cec5SDimitry Andric }
4110b57cec5SDimitry Andric
isSALU(uint16_t Opcode)4120b57cec5SDimitry Andric bool isSALU(uint16_t Opcode) const {
4130b57cec5SDimitry Andric return get(Opcode).TSFlags & SIInstrFlags::SALU;
4140b57cec5SDimitry Andric }
4150b57cec5SDimitry Andric
isVALU(const MachineInstr & MI)4160b57cec5SDimitry Andric static bool isVALU(const MachineInstr &MI) {
4170b57cec5SDimitry Andric return MI.getDesc().TSFlags & SIInstrFlags::VALU;
4180b57cec5SDimitry Andric }
4190b57cec5SDimitry Andric
isVALU(uint16_t Opcode)4200b57cec5SDimitry Andric bool isVALU(uint16_t Opcode) const {
4210b57cec5SDimitry Andric return get(Opcode).TSFlags & SIInstrFlags::VALU;
4220b57cec5SDimitry Andric }
4230b57cec5SDimitry Andric
isImage(const MachineInstr & MI)4245f757f3fSDimitry Andric static bool isImage(const MachineInstr &MI) {
4255f757f3fSDimitry Andric return isMIMG(MI) || isVSAMPLE(MI) || isVIMAGE(MI);
4265f757f3fSDimitry Andric }
4275f757f3fSDimitry Andric
isImage(uint16_t Opcode)4285f757f3fSDimitry Andric bool isImage(uint16_t Opcode) const {
4295f757f3fSDimitry Andric return isMIMG(Opcode) || isVSAMPLE(Opcode) || isVIMAGE(Opcode);
4305f757f3fSDimitry Andric }
4315f757f3fSDimitry Andric
isVMEM(const MachineInstr & MI)4320b57cec5SDimitry Andric static bool isVMEM(const MachineInstr &MI) {
4335f757f3fSDimitry Andric return isMUBUF(MI) || isMTBUF(MI) || isImage(MI);
4340b57cec5SDimitry Andric }
4350b57cec5SDimitry Andric
isVMEM(uint16_t Opcode)4360b57cec5SDimitry Andric bool isVMEM(uint16_t Opcode) const {
4375f757f3fSDimitry Andric return isMUBUF(Opcode) || isMTBUF(Opcode) || isImage(Opcode);
4380b57cec5SDimitry Andric }
4390b57cec5SDimitry Andric
isSOP1(const MachineInstr & MI)4400b57cec5SDimitry Andric static bool isSOP1(const MachineInstr &MI) {
4410b57cec5SDimitry Andric return MI.getDesc().TSFlags & SIInstrFlags::SOP1;
4420b57cec5SDimitry Andric }
4430b57cec5SDimitry Andric
isSOP1(uint16_t Opcode)4440b57cec5SDimitry Andric bool isSOP1(uint16_t Opcode) const {
4450b57cec5SDimitry Andric return get(Opcode).TSFlags & SIInstrFlags::SOP1;
4460b57cec5SDimitry Andric }
4470b57cec5SDimitry Andric
isSOP2(const MachineInstr & MI)4480b57cec5SDimitry Andric static bool isSOP2(const MachineInstr &MI) {
4490b57cec5SDimitry Andric return MI.getDesc().TSFlags & SIInstrFlags::SOP2;
4500b57cec5SDimitry Andric }
4510b57cec5SDimitry Andric
isSOP2(uint16_t Opcode)4520b57cec5SDimitry Andric bool isSOP2(uint16_t Opcode) const {
4530b57cec5SDimitry Andric return get(Opcode).TSFlags & SIInstrFlags::SOP2;
4540b57cec5SDimitry Andric }
4550b57cec5SDimitry Andric
isSOPC(const MachineInstr & MI)4560b57cec5SDimitry Andric static bool isSOPC(const MachineInstr &MI) {
4570b57cec5SDimitry Andric return MI.getDesc().TSFlags & SIInstrFlags::SOPC;
4580b57cec5SDimitry Andric }
4590b57cec5SDimitry Andric
isSOPC(uint16_t Opcode)4600b57cec5SDimitry Andric bool isSOPC(uint16_t Opcode) const {
4610b57cec5SDimitry Andric return get(Opcode).TSFlags & SIInstrFlags::SOPC;
4620b57cec5SDimitry Andric }
4630b57cec5SDimitry Andric
isSOPK(const MachineInstr & MI)4640b57cec5SDimitry Andric static bool isSOPK(const MachineInstr &MI) {
4650b57cec5SDimitry Andric return MI.getDesc().TSFlags & SIInstrFlags::SOPK;
4660b57cec5SDimitry Andric }
4670b57cec5SDimitry Andric
isSOPK(uint16_t Opcode)4680b57cec5SDimitry Andric bool isSOPK(uint16_t Opcode) const {
4690b57cec5SDimitry Andric return get(Opcode).TSFlags & SIInstrFlags::SOPK;
4700b57cec5SDimitry Andric }
4710b57cec5SDimitry Andric
isSOPP(const MachineInstr & MI)4720b57cec5SDimitry Andric static bool isSOPP(const MachineInstr &MI) {
4730b57cec5SDimitry Andric return MI.getDesc().TSFlags & SIInstrFlags::SOPP;
4740b57cec5SDimitry Andric }
4750b57cec5SDimitry Andric
isSOPP(uint16_t Opcode)4760b57cec5SDimitry Andric bool isSOPP(uint16_t Opcode) const {
4770b57cec5SDimitry Andric return get(Opcode).TSFlags & SIInstrFlags::SOPP;
4780b57cec5SDimitry Andric }
4790b57cec5SDimitry Andric
isPacked(const MachineInstr & MI)4800b57cec5SDimitry Andric static bool isPacked(const MachineInstr &MI) {
4810b57cec5SDimitry Andric return MI.getDesc().TSFlags & SIInstrFlags::IsPacked;
4820b57cec5SDimitry Andric }
4830b57cec5SDimitry Andric
isPacked(uint16_t Opcode)4840b57cec5SDimitry Andric bool isPacked(uint16_t Opcode) const {
4850b57cec5SDimitry Andric return get(Opcode).TSFlags & SIInstrFlags::IsPacked;
4860b57cec5SDimitry Andric }
4870b57cec5SDimitry Andric
isVOP1(const MachineInstr & MI)4880b57cec5SDimitry Andric static bool isVOP1(const MachineInstr &MI) {
4890b57cec5SDimitry Andric return MI.getDesc().TSFlags & SIInstrFlags::VOP1;
4900b57cec5SDimitry Andric }
4910b57cec5SDimitry Andric
isVOP1(uint16_t Opcode)4920b57cec5SDimitry Andric bool isVOP1(uint16_t Opcode) const {
4930b57cec5SDimitry Andric return get(Opcode).TSFlags & SIInstrFlags::VOP1;
4940b57cec5SDimitry Andric }
4950b57cec5SDimitry Andric
isVOP2(const MachineInstr & MI)4960b57cec5SDimitry Andric static bool isVOP2(const MachineInstr &MI) {
4970b57cec5SDimitry Andric return MI.getDesc().TSFlags & SIInstrFlags::VOP2;
4980b57cec5SDimitry Andric }
4990b57cec5SDimitry Andric
isVOP2(uint16_t Opcode)5000b57cec5SDimitry Andric bool isVOP2(uint16_t Opcode) const {
5010b57cec5SDimitry Andric return get(Opcode).TSFlags & SIInstrFlags::VOP2;
5020b57cec5SDimitry Andric }
5030b57cec5SDimitry Andric
isVOP3(const MachineInstr & MI)5040b57cec5SDimitry Andric static bool isVOP3(const MachineInstr &MI) {
5050b57cec5SDimitry Andric return MI.getDesc().TSFlags & SIInstrFlags::VOP3;
5060b57cec5SDimitry Andric }
5070b57cec5SDimitry Andric
isVOP3(uint16_t Opcode)5080b57cec5SDimitry Andric bool isVOP3(uint16_t Opcode) const {
5090b57cec5SDimitry Andric return get(Opcode).TSFlags & SIInstrFlags::VOP3;
5100b57cec5SDimitry Andric }
5110b57cec5SDimitry Andric
isSDWA(const MachineInstr & MI)5120b57cec5SDimitry Andric static bool isSDWA(const MachineInstr &MI) {
5130b57cec5SDimitry Andric return MI.getDesc().TSFlags & SIInstrFlags::SDWA;
5140b57cec5SDimitry Andric }
5150b57cec5SDimitry Andric
isSDWA(uint16_t Opcode)5160b57cec5SDimitry Andric bool isSDWA(uint16_t Opcode) const {
5170b57cec5SDimitry Andric return get(Opcode).TSFlags & SIInstrFlags::SDWA;
5180b57cec5SDimitry Andric }
5190b57cec5SDimitry Andric
isVOPC(const MachineInstr & MI)5200b57cec5SDimitry Andric static bool isVOPC(const MachineInstr &MI) {
5210b57cec5SDimitry Andric return MI.getDesc().TSFlags & SIInstrFlags::VOPC;
5220b57cec5SDimitry Andric }
5230b57cec5SDimitry Andric
isVOPC(uint16_t Opcode)5240b57cec5SDimitry Andric bool isVOPC(uint16_t Opcode) const {
5250b57cec5SDimitry Andric return get(Opcode).TSFlags & SIInstrFlags::VOPC;
5260b57cec5SDimitry Andric }
5270b57cec5SDimitry Andric
isMUBUF(const MachineInstr & MI)5280b57cec5SDimitry Andric static bool isMUBUF(const MachineInstr &MI) {
5290b57cec5SDimitry Andric return MI.getDesc().TSFlags & SIInstrFlags::MUBUF;
5300b57cec5SDimitry Andric }
5310b57cec5SDimitry Andric
isMUBUF(uint16_t Opcode)5320b57cec5SDimitry Andric bool isMUBUF(uint16_t Opcode) const {
5330b57cec5SDimitry Andric return get(Opcode).TSFlags & SIInstrFlags::MUBUF;
5340b57cec5SDimitry Andric }
5350b57cec5SDimitry Andric
isMTBUF(const MachineInstr & MI)5360b57cec5SDimitry Andric static bool isMTBUF(const MachineInstr &MI) {
5370b57cec5SDimitry Andric return MI.getDesc().TSFlags & SIInstrFlags::MTBUF;
5380b57cec5SDimitry Andric }
5390b57cec5SDimitry Andric
isMTBUF(uint16_t Opcode)5400b57cec5SDimitry Andric bool isMTBUF(uint16_t Opcode) const {
5410b57cec5SDimitry Andric return get(Opcode).TSFlags & SIInstrFlags::MTBUF;
5420b57cec5SDimitry Andric }
5430b57cec5SDimitry Andric
isSMRD(const MachineInstr & MI)5440b57cec5SDimitry Andric static bool isSMRD(const MachineInstr &MI) {
5450b57cec5SDimitry Andric return MI.getDesc().TSFlags & SIInstrFlags::SMRD;
5460b57cec5SDimitry Andric }
5470b57cec5SDimitry Andric
isSMRD(uint16_t Opcode)5480b57cec5SDimitry Andric bool isSMRD(uint16_t Opcode) const {
5490b57cec5SDimitry Andric return get(Opcode).TSFlags & SIInstrFlags::SMRD;
5500b57cec5SDimitry Andric }
5510b57cec5SDimitry Andric
5520b57cec5SDimitry Andric bool isBufferSMRD(const MachineInstr &MI) const;
5530b57cec5SDimitry Andric
isDS(const MachineInstr & MI)5540b57cec5SDimitry Andric static bool isDS(const MachineInstr &MI) {
5550b57cec5SDimitry Andric return MI.getDesc().TSFlags & SIInstrFlags::DS;
5560b57cec5SDimitry Andric }
5570b57cec5SDimitry Andric
isDS(uint16_t Opcode)5580b57cec5SDimitry Andric bool isDS(uint16_t Opcode) const {
5590b57cec5SDimitry Andric return get(Opcode).TSFlags & SIInstrFlags::DS;
5600b57cec5SDimitry Andric }
5610b57cec5SDimitry Andric
isLDSDMA(const MachineInstr & MI)5625f757f3fSDimitry Andric static bool isLDSDMA(const MachineInstr &MI) {
5635f757f3fSDimitry Andric return isVALU(MI) && (isMUBUF(MI) || isFLAT(MI));
5645f757f3fSDimitry Andric }
5655f757f3fSDimitry Andric
isLDSDMA(uint16_t Opcode)5665f757f3fSDimitry Andric bool isLDSDMA(uint16_t Opcode) {
5675f757f3fSDimitry Andric return isVALU(Opcode) && (isMUBUF(Opcode) || isFLAT(Opcode));
5685f757f3fSDimitry Andric }
5695f757f3fSDimitry Andric
isGWS(const MachineInstr & MI)5705f757f3fSDimitry Andric static bool isGWS(const MachineInstr &MI) {
5715f757f3fSDimitry Andric return MI.getDesc().TSFlags & SIInstrFlags::GWS;
5725f757f3fSDimitry Andric }
5735f757f3fSDimitry Andric
isGWS(uint16_t Opcode)5745f757f3fSDimitry Andric bool isGWS(uint16_t Opcode) const {
5755f757f3fSDimitry Andric return get(Opcode).TSFlags & SIInstrFlags::GWS;
5765f757f3fSDimitry Andric }
5775f757f3fSDimitry Andric
5780b57cec5SDimitry Andric bool isAlwaysGDS(uint16_t Opcode) const;
5790b57cec5SDimitry Andric
isMIMG(const MachineInstr & MI)5800b57cec5SDimitry Andric static bool isMIMG(const MachineInstr &MI) {
5810b57cec5SDimitry Andric return MI.getDesc().TSFlags & SIInstrFlags::MIMG;
5820b57cec5SDimitry Andric }
5830b57cec5SDimitry Andric
isMIMG(uint16_t Opcode)5840b57cec5SDimitry Andric bool isMIMG(uint16_t Opcode) const {
5850b57cec5SDimitry Andric return get(Opcode).TSFlags & SIInstrFlags::MIMG;
5860b57cec5SDimitry Andric }
5870b57cec5SDimitry Andric
isVIMAGE(const MachineInstr & MI)5885f757f3fSDimitry Andric static bool isVIMAGE(const MachineInstr &MI) {
5895f757f3fSDimitry Andric return MI.getDesc().TSFlags & SIInstrFlags::VIMAGE;
5905f757f3fSDimitry Andric }
5915f757f3fSDimitry Andric
isVIMAGE(uint16_t Opcode)5925f757f3fSDimitry Andric bool isVIMAGE(uint16_t Opcode) const {
5935f757f3fSDimitry Andric return get(Opcode).TSFlags & SIInstrFlags::VIMAGE;
5945f757f3fSDimitry Andric }
5955f757f3fSDimitry Andric
isVSAMPLE(const MachineInstr & MI)5965f757f3fSDimitry Andric static bool isVSAMPLE(const MachineInstr &MI) {
5975f757f3fSDimitry Andric return MI.getDesc().TSFlags & SIInstrFlags::VSAMPLE;
5985f757f3fSDimitry Andric }
5995f757f3fSDimitry Andric
isVSAMPLE(uint16_t Opcode)6005f757f3fSDimitry Andric bool isVSAMPLE(uint16_t Opcode) const {
6015f757f3fSDimitry Andric return get(Opcode).TSFlags & SIInstrFlags::VSAMPLE;
6025f757f3fSDimitry Andric }
6035f757f3fSDimitry Andric
isGather4(const MachineInstr & MI)6040b57cec5SDimitry Andric static bool isGather4(const MachineInstr &MI) {
6050b57cec5SDimitry Andric return MI.getDesc().TSFlags & SIInstrFlags::Gather4;
6060b57cec5SDimitry Andric }
6070b57cec5SDimitry Andric
isGather4(uint16_t Opcode)6080b57cec5SDimitry Andric bool isGather4(uint16_t Opcode) const {
6090b57cec5SDimitry Andric return get(Opcode).TSFlags & SIInstrFlags::Gather4;
6100b57cec5SDimitry Andric }
6110b57cec5SDimitry Andric
isFLAT(const MachineInstr & MI)6120b57cec5SDimitry Andric static bool isFLAT(const MachineInstr &MI) {
6130b57cec5SDimitry Andric return MI.getDesc().TSFlags & SIInstrFlags::FLAT;
6140b57cec5SDimitry Andric }
6150b57cec5SDimitry Andric
6160b57cec5SDimitry Andric // Is a FLAT encoded instruction which accesses a specific segment,
6170b57cec5SDimitry Andric // i.e. global_* or scratch_*.
isSegmentSpecificFLAT(const MachineInstr & MI)6180b57cec5SDimitry Andric static bool isSegmentSpecificFLAT(const MachineInstr &MI) {
6190b57cec5SDimitry Andric auto Flags = MI.getDesc().TSFlags;
620fe6060f1SDimitry Andric return Flags & (SIInstrFlags::FlatGlobal | SIInstrFlags::FlatScratch);
6210b57cec5SDimitry Andric }
6220b57cec5SDimitry Andric
isSegmentSpecificFLAT(uint16_t Opcode)623e8d8bef9SDimitry Andric bool isSegmentSpecificFLAT(uint16_t Opcode) const {
624e8d8bef9SDimitry Andric auto Flags = get(Opcode).TSFlags;
625fe6060f1SDimitry Andric return Flags & (SIInstrFlags::FlatGlobal | SIInstrFlags::FlatScratch);
626e8d8bef9SDimitry Andric }
627e8d8bef9SDimitry Andric
isFLATGlobal(const MachineInstr & MI)628e8d8bef9SDimitry Andric static bool isFLATGlobal(const MachineInstr &MI) {
629fe6060f1SDimitry Andric return MI.getDesc().TSFlags & SIInstrFlags::FlatGlobal;
630e8d8bef9SDimitry Andric }
631e8d8bef9SDimitry Andric
isFLATGlobal(uint16_t Opcode)632e8d8bef9SDimitry Andric bool isFLATGlobal(uint16_t Opcode) const {
633fe6060f1SDimitry Andric return get(Opcode).TSFlags & SIInstrFlags::FlatGlobal;
634e8d8bef9SDimitry Andric }
635e8d8bef9SDimitry Andric
isFLATScratch(const MachineInstr & MI)6360b57cec5SDimitry Andric static bool isFLATScratch(const MachineInstr &MI) {
637fe6060f1SDimitry Andric return MI.getDesc().TSFlags & SIInstrFlags::FlatScratch;
638e8d8bef9SDimitry Andric }
639e8d8bef9SDimitry Andric
isFLATScratch(uint16_t Opcode)640e8d8bef9SDimitry Andric bool isFLATScratch(uint16_t Opcode) const {
641fe6060f1SDimitry Andric return get(Opcode).TSFlags & SIInstrFlags::FlatScratch;
6420b57cec5SDimitry Andric }
6430b57cec5SDimitry Andric
6440b57cec5SDimitry Andric // Any FLAT encoded instruction, including global_* and scratch_*.
isFLAT(uint16_t Opcode)6450b57cec5SDimitry Andric bool isFLAT(uint16_t Opcode) const {
6460b57cec5SDimitry Andric return get(Opcode).TSFlags & SIInstrFlags::FLAT;
6470b57cec5SDimitry Andric }
6480b57cec5SDimitry Andric
isEXP(const MachineInstr & MI)6490b57cec5SDimitry Andric static bool isEXP(const MachineInstr &MI) {
6500b57cec5SDimitry Andric return MI.getDesc().TSFlags & SIInstrFlags::EXP;
6510b57cec5SDimitry Andric }
6520b57cec5SDimitry Andric
isDualSourceBlendEXP(const MachineInstr & MI)65381ad6265SDimitry Andric static bool isDualSourceBlendEXP(const MachineInstr &MI) {
65481ad6265SDimitry Andric if (!isEXP(MI))
65581ad6265SDimitry Andric return false;
65681ad6265SDimitry Andric unsigned Target = MI.getOperand(0).getImm();
65781ad6265SDimitry Andric return Target == AMDGPU::Exp::ET_DUAL_SRC_BLEND0 ||
65881ad6265SDimitry Andric Target == AMDGPU::Exp::ET_DUAL_SRC_BLEND1;
65981ad6265SDimitry Andric }
66081ad6265SDimitry Andric
isEXP(uint16_t Opcode)6610b57cec5SDimitry Andric bool isEXP(uint16_t Opcode) const {
6620b57cec5SDimitry Andric return get(Opcode).TSFlags & SIInstrFlags::EXP;
6630b57cec5SDimitry Andric }
6640b57cec5SDimitry Andric
isAtomicNoRet(const MachineInstr & MI)665fe6060f1SDimitry Andric static bool isAtomicNoRet(const MachineInstr &MI) {
666fe6060f1SDimitry Andric return MI.getDesc().TSFlags & SIInstrFlags::IsAtomicNoRet;
667fe6060f1SDimitry Andric }
668fe6060f1SDimitry Andric
isAtomicNoRet(uint16_t Opcode)669fe6060f1SDimitry Andric bool isAtomicNoRet(uint16_t Opcode) const {
670fe6060f1SDimitry Andric return get(Opcode).TSFlags & SIInstrFlags::IsAtomicNoRet;
671fe6060f1SDimitry Andric }
672fe6060f1SDimitry Andric
isAtomicRet(const MachineInstr & MI)673fe6060f1SDimitry Andric static bool isAtomicRet(const MachineInstr &MI) {
674fe6060f1SDimitry Andric return MI.getDesc().TSFlags & SIInstrFlags::IsAtomicRet;
675fe6060f1SDimitry Andric }
676fe6060f1SDimitry Andric
isAtomicRet(uint16_t Opcode)677fe6060f1SDimitry Andric bool isAtomicRet(uint16_t Opcode) const {
678fe6060f1SDimitry Andric return get(Opcode).TSFlags & SIInstrFlags::IsAtomicRet;
679fe6060f1SDimitry Andric }
680fe6060f1SDimitry Andric
isAtomic(const MachineInstr & MI)681fe6060f1SDimitry Andric static bool isAtomic(const MachineInstr &MI) {
682fe6060f1SDimitry Andric return MI.getDesc().TSFlags & (SIInstrFlags::IsAtomicRet |
683fe6060f1SDimitry Andric SIInstrFlags::IsAtomicNoRet);
684fe6060f1SDimitry Andric }
685fe6060f1SDimitry Andric
isAtomic(uint16_t Opcode)686fe6060f1SDimitry Andric bool isAtomic(uint16_t Opcode) const {
687fe6060f1SDimitry Andric return get(Opcode).TSFlags & (SIInstrFlags::IsAtomicRet |
688fe6060f1SDimitry Andric SIInstrFlags::IsAtomicNoRet);
689fe6060f1SDimitry Andric }
690fe6060f1SDimitry Andric
mayWriteLDSThroughDMA(const MachineInstr & MI)6915f757f3fSDimitry Andric static bool mayWriteLDSThroughDMA(const MachineInstr &MI) {
6925f757f3fSDimitry Andric return isLDSDMA(MI) && MI.getOpcode() != AMDGPU::BUFFER_STORE_LDS_DWORD;
6935f757f3fSDimitry Andric }
6945f757f3fSDimitry Andric
isWQM(const MachineInstr & MI)6950b57cec5SDimitry Andric static bool isWQM(const MachineInstr &MI) {
6960b57cec5SDimitry Andric return MI.getDesc().TSFlags & SIInstrFlags::WQM;
6970b57cec5SDimitry Andric }
6980b57cec5SDimitry Andric
isWQM(uint16_t Opcode)6990b57cec5SDimitry Andric bool isWQM(uint16_t Opcode) const {
7000b57cec5SDimitry Andric return get(Opcode).TSFlags & SIInstrFlags::WQM;
7010b57cec5SDimitry Andric }
7020b57cec5SDimitry Andric
isDisableWQM(const MachineInstr & MI)7030b57cec5SDimitry Andric static bool isDisableWQM(const MachineInstr &MI) {
7040b57cec5SDimitry Andric return MI.getDesc().TSFlags & SIInstrFlags::DisableWQM;
7050b57cec5SDimitry Andric }
7060b57cec5SDimitry Andric
isDisableWQM(uint16_t Opcode)7070b57cec5SDimitry Andric bool isDisableWQM(uint16_t Opcode) const {
7080b57cec5SDimitry Andric return get(Opcode).TSFlags & SIInstrFlags::DisableWQM;
7090b57cec5SDimitry Andric }
7100b57cec5SDimitry Andric
isVGPRSpill(const MachineInstr & MI)7110b57cec5SDimitry Andric static bool isVGPRSpill(const MachineInstr &MI) {
7120b57cec5SDimitry Andric return MI.getDesc().TSFlags & SIInstrFlags::VGPRSpill;
7130b57cec5SDimitry Andric }
7140b57cec5SDimitry Andric
isVGPRSpill(uint16_t Opcode)7150b57cec5SDimitry Andric bool isVGPRSpill(uint16_t Opcode) const {
7160b57cec5SDimitry Andric return get(Opcode).TSFlags & SIInstrFlags::VGPRSpill;
7170b57cec5SDimitry Andric }
7180b57cec5SDimitry Andric
isSGPRSpill(const MachineInstr & MI)7190b57cec5SDimitry Andric static bool isSGPRSpill(const MachineInstr &MI) {
7200b57cec5SDimitry Andric return MI.getDesc().TSFlags & SIInstrFlags::SGPRSpill;
7210b57cec5SDimitry Andric }
7220b57cec5SDimitry Andric
isSGPRSpill(uint16_t Opcode)7230b57cec5SDimitry Andric bool isSGPRSpill(uint16_t Opcode) const {
7240b57cec5SDimitry Andric return get(Opcode).TSFlags & SIInstrFlags::SGPRSpill;
7250b57cec5SDimitry Andric }
7260b57cec5SDimitry Andric
isSpillOpcode(uint16_t Opcode)7275f757f3fSDimitry Andric bool isSpillOpcode(uint16_t Opcode) const {
7285f757f3fSDimitry Andric return get(Opcode).TSFlags &
7295f757f3fSDimitry Andric (SIInstrFlags::SGPRSpill | SIInstrFlags::VGPRSpill);
7305f757f3fSDimitry Andric }
7315f757f3fSDimitry Andric
isWWMRegSpillOpcode(uint16_t Opcode)73206c3fb27SDimitry Andric static bool isWWMRegSpillOpcode(uint16_t Opcode) {
73306c3fb27SDimitry Andric return Opcode == AMDGPU::SI_SPILL_WWM_V32_SAVE ||
7345f757f3fSDimitry Andric Opcode == AMDGPU::SI_SPILL_WWM_AV32_SAVE ||
7355f757f3fSDimitry Andric Opcode == AMDGPU::SI_SPILL_WWM_V32_RESTORE ||
7365f757f3fSDimitry Andric Opcode == AMDGPU::SI_SPILL_WWM_AV32_RESTORE;
7375f757f3fSDimitry Andric }
7385f757f3fSDimitry Andric
isChainCallOpcode(uint64_t Opcode)7395f757f3fSDimitry Andric static bool isChainCallOpcode(uint64_t Opcode) {
7405f757f3fSDimitry Andric return Opcode == AMDGPU::SI_CS_CHAIN_TC_W32 ||
7415f757f3fSDimitry Andric Opcode == AMDGPU::SI_CS_CHAIN_TC_W64;
74206c3fb27SDimitry Andric }
74306c3fb27SDimitry Andric
isDPP(const MachineInstr & MI)7440b57cec5SDimitry Andric static bool isDPP(const MachineInstr &MI) {
7450b57cec5SDimitry Andric return MI.getDesc().TSFlags & SIInstrFlags::DPP;
7460b57cec5SDimitry Andric }
7470b57cec5SDimitry Andric
isDPP(uint16_t Opcode)7480b57cec5SDimitry Andric bool isDPP(uint16_t Opcode) const {
7490b57cec5SDimitry Andric return get(Opcode).TSFlags & SIInstrFlags::DPP;
7500b57cec5SDimitry Andric }
7510b57cec5SDimitry Andric
isTRANS(const MachineInstr & MI)752e8d8bef9SDimitry Andric static bool isTRANS(const MachineInstr &MI) {
753e8d8bef9SDimitry Andric return MI.getDesc().TSFlags & SIInstrFlags::TRANS;
754e8d8bef9SDimitry Andric }
755e8d8bef9SDimitry Andric
isTRANS(uint16_t Opcode)756e8d8bef9SDimitry Andric bool isTRANS(uint16_t Opcode) const {
757e8d8bef9SDimitry Andric return get(Opcode).TSFlags & SIInstrFlags::TRANS;
758e8d8bef9SDimitry Andric }
759e8d8bef9SDimitry Andric
isVOP3P(const MachineInstr & MI)7600b57cec5SDimitry Andric static bool isVOP3P(const MachineInstr &MI) {
7610b57cec5SDimitry Andric return MI.getDesc().TSFlags & SIInstrFlags::VOP3P;
7620b57cec5SDimitry Andric }
7630b57cec5SDimitry Andric
isVOP3P(uint16_t Opcode)7640b57cec5SDimitry Andric bool isVOP3P(uint16_t Opcode) const {
7650b57cec5SDimitry Andric return get(Opcode).TSFlags & SIInstrFlags::VOP3P;
7660b57cec5SDimitry Andric }
7670b57cec5SDimitry Andric
isVINTRP(const MachineInstr & MI)7680b57cec5SDimitry Andric static bool isVINTRP(const MachineInstr &MI) {
7690b57cec5SDimitry Andric return MI.getDesc().TSFlags & SIInstrFlags::VINTRP;
7700b57cec5SDimitry Andric }
7710b57cec5SDimitry Andric
isVINTRP(uint16_t Opcode)7720b57cec5SDimitry Andric bool isVINTRP(uint16_t Opcode) const {
7730b57cec5SDimitry Andric return get(Opcode).TSFlags & SIInstrFlags::VINTRP;
7740b57cec5SDimitry Andric }
7750b57cec5SDimitry Andric
isMAI(const MachineInstr & MI)7760b57cec5SDimitry Andric static bool isMAI(const MachineInstr &MI) {
7770b57cec5SDimitry Andric return MI.getDesc().TSFlags & SIInstrFlags::IsMAI;
7780b57cec5SDimitry Andric }
7790b57cec5SDimitry Andric
isMAI(uint16_t Opcode)7800b57cec5SDimitry Andric bool isMAI(uint16_t Opcode) const {
7810b57cec5SDimitry Andric return get(Opcode).TSFlags & SIInstrFlags::IsMAI;
7820b57cec5SDimitry Andric }
7830b57cec5SDimitry Andric
isMFMA(const MachineInstr & MI)78481ad6265SDimitry Andric static bool isMFMA(const MachineInstr &MI) {
78581ad6265SDimitry Andric return isMAI(MI) && MI.getOpcode() != AMDGPU::V_ACCVGPR_WRITE_B32_e64 &&
78681ad6265SDimitry Andric MI.getOpcode() != AMDGPU::V_ACCVGPR_READ_B32_e64;
78781ad6265SDimitry Andric }
78881ad6265SDimitry Andric
isDOT(const MachineInstr & MI)7898bcb0991SDimitry Andric static bool isDOT(const MachineInstr &MI) {
7908bcb0991SDimitry Andric return MI.getDesc().TSFlags & SIInstrFlags::IsDOT;
7918bcb0991SDimitry Andric }
7928bcb0991SDimitry Andric
isWMMA(const MachineInstr & MI)79381ad6265SDimitry Andric static bool isWMMA(const MachineInstr &MI) {
79481ad6265SDimitry Andric return MI.getDesc().TSFlags & SIInstrFlags::IsWMMA;
79581ad6265SDimitry Andric }
79681ad6265SDimitry Andric
isWMMA(uint16_t Opcode)79781ad6265SDimitry Andric bool isWMMA(uint16_t Opcode) const {
79881ad6265SDimitry Andric return get(Opcode).TSFlags & SIInstrFlags::IsWMMA;
79981ad6265SDimitry Andric }
80081ad6265SDimitry Andric
isMFMAorWMMA(const MachineInstr & MI)801bdd1243dSDimitry Andric static bool isMFMAorWMMA(const MachineInstr &MI) {
802bdd1243dSDimitry Andric return isMFMA(MI) || isWMMA(MI);
803bdd1243dSDimitry Andric }
804bdd1243dSDimitry Andric
isSWMMAC(const MachineInstr & MI)805b3edf446SDimitry Andric static bool isSWMMAC(const MachineInstr &MI) {
806b3edf446SDimitry Andric return MI.getDesc().TSFlags & SIInstrFlags::IsSWMMAC;
807b3edf446SDimitry Andric }
808b3edf446SDimitry Andric
isSWMMAC(uint16_t Opcode)809b3edf446SDimitry Andric bool isSWMMAC(uint16_t Opcode) const {
810b3edf446SDimitry Andric return get(Opcode).TSFlags & SIInstrFlags::IsSWMMAC;
811b3edf446SDimitry Andric }
812b3edf446SDimitry Andric
isDOT(uint16_t Opcode)8138bcb0991SDimitry Andric bool isDOT(uint16_t Opcode) const {
8148bcb0991SDimitry Andric return get(Opcode).TSFlags & SIInstrFlags::IsDOT;
8158bcb0991SDimitry Andric }
8168bcb0991SDimitry Andric
isLDSDIR(const MachineInstr & MI)81781ad6265SDimitry Andric static bool isLDSDIR(const MachineInstr &MI) {
81881ad6265SDimitry Andric return MI.getDesc().TSFlags & SIInstrFlags::LDSDIR;
81981ad6265SDimitry Andric }
82081ad6265SDimitry Andric
isLDSDIR(uint16_t Opcode)82181ad6265SDimitry Andric bool isLDSDIR(uint16_t Opcode) const {
82281ad6265SDimitry Andric return get(Opcode).TSFlags & SIInstrFlags::LDSDIR;
82381ad6265SDimitry Andric }
82481ad6265SDimitry Andric
isVINTERP(const MachineInstr & MI)82581ad6265SDimitry Andric static bool isVINTERP(const MachineInstr &MI) {
82681ad6265SDimitry Andric return MI.getDesc().TSFlags & SIInstrFlags::VINTERP;
82781ad6265SDimitry Andric }
82881ad6265SDimitry Andric
isVINTERP(uint16_t Opcode)82981ad6265SDimitry Andric bool isVINTERP(uint16_t Opcode) const {
83081ad6265SDimitry Andric return get(Opcode).TSFlags & SIInstrFlags::VINTERP;
83181ad6265SDimitry Andric }
83281ad6265SDimitry Andric
isScalarUnit(const MachineInstr & MI)8330b57cec5SDimitry Andric static bool isScalarUnit(const MachineInstr &MI) {
8340b57cec5SDimitry Andric return MI.getDesc().TSFlags & (SIInstrFlags::SALU | SIInstrFlags::SMRD);
8350b57cec5SDimitry Andric }
8360b57cec5SDimitry Andric
usesVM_CNT(const MachineInstr & MI)8370b57cec5SDimitry Andric static bool usesVM_CNT(const MachineInstr &MI) {
8380b57cec5SDimitry Andric return MI.getDesc().TSFlags & SIInstrFlags::VM_CNT;
8390b57cec5SDimitry Andric }
8400b57cec5SDimitry Andric
usesLGKM_CNT(const MachineInstr & MI)8410b57cec5SDimitry Andric static bool usesLGKM_CNT(const MachineInstr &MI) {
8420b57cec5SDimitry Andric return MI.getDesc().TSFlags & SIInstrFlags::LGKM_CNT;
8430b57cec5SDimitry Andric }
8440b57cec5SDimitry Andric
sopkIsZext(const MachineInstr & MI)8450b57cec5SDimitry Andric static bool sopkIsZext(const MachineInstr &MI) {
8460b57cec5SDimitry Andric return MI.getDesc().TSFlags & SIInstrFlags::SOPK_ZEXT;
8470b57cec5SDimitry Andric }
8480b57cec5SDimitry Andric
sopkIsZext(uint16_t Opcode)8490b57cec5SDimitry Andric bool sopkIsZext(uint16_t Opcode) const {
8500b57cec5SDimitry Andric return get(Opcode).TSFlags & SIInstrFlags::SOPK_ZEXT;
8510b57cec5SDimitry Andric }
8520b57cec5SDimitry Andric
8530b57cec5SDimitry Andric /// \returns true if this is an s_store_dword* instruction. This is more
854bdd1243dSDimitry Andric /// specific than isSMEM && mayStore.
isScalarStore(const MachineInstr & MI)8550b57cec5SDimitry Andric static bool isScalarStore(const MachineInstr &MI) {
8560b57cec5SDimitry Andric return MI.getDesc().TSFlags & SIInstrFlags::SCALAR_STORE;
8570b57cec5SDimitry Andric }
8580b57cec5SDimitry Andric
isScalarStore(uint16_t Opcode)8590b57cec5SDimitry Andric bool isScalarStore(uint16_t Opcode) const {
8600b57cec5SDimitry Andric return get(Opcode).TSFlags & SIInstrFlags::SCALAR_STORE;
8610b57cec5SDimitry Andric }
8620b57cec5SDimitry Andric
isFixedSize(const MachineInstr & MI)8630b57cec5SDimitry Andric static bool isFixedSize(const MachineInstr &MI) {
8640b57cec5SDimitry Andric return MI.getDesc().TSFlags & SIInstrFlags::FIXED_SIZE;
8650b57cec5SDimitry Andric }
8660b57cec5SDimitry Andric
isFixedSize(uint16_t Opcode)8670b57cec5SDimitry Andric bool isFixedSize(uint16_t Opcode) const {
8680b57cec5SDimitry Andric return get(Opcode).TSFlags & SIInstrFlags::FIXED_SIZE;
8690b57cec5SDimitry Andric }
8700b57cec5SDimitry Andric
hasFPClamp(const MachineInstr & MI)8710b57cec5SDimitry Andric static bool hasFPClamp(const MachineInstr &MI) {
8720b57cec5SDimitry Andric return MI.getDesc().TSFlags & SIInstrFlags::FPClamp;
8730b57cec5SDimitry Andric }
8740b57cec5SDimitry Andric
hasFPClamp(uint16_t Opcode)8750b57cec5SDimitry Andric bool hasFPClamp(uint16_t Opcode) const {
8760b57cec5SDimitry Andric return get(Opcode).TSFlags & SIInstrFlags::FPClamp;
8770b57cec5SDimitry Andric }
8780b57cec5SDimitry Andric
hasIntClamp(const MachineInstr & MI)8790b57cec5SDimitry Andric static bool hasIntClamp(const MachineInstr &MI) {
8800b57cec5SDimitry Andric return MI.getDesc().TSFlags & SIInstrFlags::IntClamp;
8810b57cec5SDimitry Andric }
8820b57cec5SDimitry Andric
getClampMask(const MachineInstr & MI)8830b57cec5SDimitry Andric uint64_t getClampMask(const MachineInstr &MI) const {
8840b57cec5SDimitry Andric const uint64_t ClampFlags = SIInstrFlags::FPClamp |
8850b57cec5SDimitry Andric SIInstrFlags::IntClamp |
8860b57cec5SDimitry Andric SIInstrFlags::ClampLo |
8870b57cec5SDimitry Andric SIInstrFlags::ClampHi;
8880b57cec5SDimitry Andric return MI.getDesc().TSFlags & ClampFlags;
8890b57cec5SDimitry Andric }
8900b57cec5SDimitry Andric
usesFPDPRounding(const MachineInstr & MI)8910b57cec5SDimitry Andric static bool usesFPDPRounding(const MachineInstr &MI) {
8920b57cec5SDimitry Andric return MI.getDesc().TSFlags & SIInstrFlags::FPDPRounding;
8930b57cec5SDimitry Andric }
8940b57cec5SDimitry Andric
usesFPDPRounding(uint16_t Opcode)8950b57cec5SDimitry Andric bool usesFPDPRounding(uint16_t Opcode) const {
8960b57cec5SDimitry Andric return get(Opcode).TSFlags & SIInstrFlags::FPDPRounding;
8970b57cec5SDimitry Andric }
8980b57cec5SDimitry Andric
isFPAtomic(const MachineInstr & MI)8990b57cec5SDimitry Andric static bool isFPAtomic(const MachineInstr &MI) {
9000b57cec5SDimitry Andric return MI.getDesc().TSFlags & SIInstrFlags::FPAtomic;
9010b57cec5SDimitry Andric }
9020b57cec5SDimitry Andric
isFPAtomic(uint16_t Opcode)9030b57cec5SDimitry Andric bool isFPAtomic(uint16_t Opcode) const {
9040b57cec5SDimitry Andric return get(Opcode).TSFlags & SIInstrFlags::FPAtomic;
9050b57cec5SDimitry Andric }
9060b57cec5SDimitry Andric
isNeverUniform(const MachineInstr & MI)90706c3fb27SDimitry Andric static bool isNeverUniform(const MachineInstr &MI) {
90806c3fb27SDimitry Andric return MI.getDesc().TSFlags & SIInstrFlags::IsNeverUniform;
90906c3fb27SDimitry Andric }
91006c3fb27SDimitry Andric
911*3a079333SDimitry Andric // Check to see if opcode is for a barrier start. Pre gfx12 this is just the
912*3a079333SDimitry Andric // S_BARRIER, but after support for S_BARRIER_SIGNAL* / S_BARRIER_WAIT we want
913*3a079333SDimitry Andric // to check for the barrier start (S_BARRIER_SIGNAL*)
isBarrierStart(unsigned Opcode)914*3a079333SDimitry Andric bool isBarrierStart(unsigned Opcode) const {
915*3a079333SDimitry Andric return Opcode == AMDGPU::S_BARRIER ||
916*3a079333SDimitry Andric Opcode == AMDGPU::S_BARRIER_SIGNAL_M0 ||
917*3a079333SDimitry Andric Opcode == AMDGPU::S_BARRIER_SIGNAL_ISFIRST_M0 ||
918*3a079333SDimitry Andric Opcode == AMDGPU::S_BARRIER_SIGNAL_IMM ||
919*3a079333SDimitry Andric Opcode == AMDGPU::S_BARRIER_SIGNAL_ISFIRST_IMM;
920*3a079333SDimitry Andric }
921*3a079333SDimitry Andric
doesNotReadTiedSource(const MachineInstr & MI)922bdd1243dSDimitry Andric static bool doesNotReadTiedSource(const MachineInstr &MI) {
923bdd1243dSDimitry Andric return MI.getDesc().TSFlags & SIInstrFlags::TiedSourceNotRead;
924bdd1243dSDimitry Andric }
925bdd1243dSDimitry Andric
doesNotReadTiedSource(uint16_t Opcode)926bdd1243dSDimitry Andric bool doesNotReadTiedSource(uint16_t Opcode) const {
927bdd1243dSDimitry Andric return get(Opcode).TSFlags & SIInstrFlags::TiedSourceNotRead;
928bdd1243dSDimitry Andric }
929bdd1243dSDimitry Andric
getNonSoftWaitcntOpcode(unsigned Opcode)9305f757f3fSDimitry Andric static unsigned getNonSoftWaitcntOpcode(unsigned Opcode) {
9317a6dacacSDimitry Andric switch (Opcode) {
9327a6dacacSDimitry Andric case AMDGPU::S_WAITCNT_soft:
9335f757f3fSDimitry Andric return AMDGPU::S_WAITCNT;
9347a6dacacSDimitry Andric case AMDGPU::S_WAITCNT_VSCNT_soft:
9355f757f3fSDimitry Andric return AMDGPU::S_WAITCNT_VSCNT;
9367a6dacacSDimitry Andric case AMDGPU::S_WAIT_LOADCNT_soft:
9377a6dacacSDimitry Andric return AMDGPU::S_WAIT_LOADCNT;
9387a6dacacSDimitry Andric case AMDGPU::S_WAIT_STORECNT_soft:
9397a6dacacSDimitry Andric return AMDGPU::S_WAIT_STORECNT;
9407a6dacacSDimitry Andric case AMDGPU::S_WAIT_SAMPLECNT_soft:
9417a6dacacSDimitry Andric return AMDGPU::S_WAIT_SAMPLECNT;
9427a6dacacSDimitry Andric case AMDGPU::S_WAIT_BVHCNT_soft:
9437a6dacacSDimitry Andric return AMDGPU::S_WAIT_BVHCNT;
9447a6dacacSDimitry Andric case AMDGPU::S_WAIT_DSCNT_soft:
9457a6dacacSDimitry Andric return AMDGPU::S_WAIT_DSCNT;
9467a6dacacSDimitry Andric default:
9477a6dacacSDimitry Andric return Opcode;
9485f757f3fSDimitry Andric }
9495f757f3fSDimitry Andric }
9505f757f3fSDimitry Andric
isVGPRCopy(const MachineInstr & MI)9510b57cec5SDimitry Andric bool isVGPRCopy(const MachineInstr &MI) const {
9525f757f3fSDimitry Andric assert(isCopyInstr(MI));
953e8d8bef9SDimitry Andric Register Dest = MI.getOperand(0).getReg();
9540b57cec5SDimitry Andric const MachineFunction &MF = *MI.getParent()->getParent();
9550b57cec5SDimitry Andric const MachineRegisterInfo &MRI = MF.getRegInfo();
9560b57cec5SDimitry Andric return !RI.isSGPRReg(MRI, Dest);
9570b57cec5SDimitry Andric }
9580b57cec5SDimitry Andric
hasVGPRUses(const MachineInstr & MI)9590b57cec5SDimitry Andric bool hasVGPRUses(const MachineInstr &MI) const {
9600b57cec5SDimitry Andric const MachineFunction &MF = *MI.getParent()->getParent();
9610b57cec5SDimitry Andric const MachineRegisterInfo &MRI = MF.getRegInfo();
9620b57cec5SDimitry Andric return llvm::any_of(MI.explicit_uses(),
9630b57cec5SDimitry Andric [&MRI, this](const MachineOperand &MO) {
9640b57cec5SDimitry Andric return MO.isReg() && RI.isVGPR(MRI, MO.getReg());});
9650b57cec5SDimitry Andric }
9660b57cec5SDimitry Andric
9675ffd83dbSDimitry Andric /// Return true if the instruction modifies the mode register.q
9685ffd83dbSDimitry Andric static bool modifiesModeRegister(const MachineInstr &MI);
9695ffd83dbSDimitry Andric
9700b57cec5SDimitry Andric /// Whether we must prevent this instruction from executing with EXEC = 0.
9710b57cec5SDimitry Andric bool hasUnwantedEffectsWhenEXECEmpty(const MachineInstr &MI) const;
9720b57cec5SDimitry Andric
9730b57cec5SDimitry Andric /// Returns true if the instruction could potentially depend on the value of
9740b57cec5SDimitry Andric /// exec. If false, exec dependencies may safely be ignored.
9750b57cec5SDimitry Andric bool mayReadEXEC(const MachineRegisterInfo &MRI, const MachineInstr &MI) const;
9760b57cec5SDimitry Andric
9770b57cec5SDimitry Andric bool isInlineConstant(const APInt &Imm) const;
9780b57cec5SDimitry Andric
isInlineConstant(const APFloat & Imm)979480093f4SDimitry Andric bool isInlineConstant(const APFloat &Imm) const {
980480093f4SDimitry Andric return isInlineConstant(Imm.bitcastToAPInt());
981480093f4SDimitry Andric }
982480093f4SDimitry Andric
983bdd1243dSDimitry Andric // Returns true if this non-register operand definitely does not need to be
984bdd1243dSDimitry Andric // encoded as a 32-bit literal. Note that this function handles all kinds of
985bdd1243dSDimitry Andric // operands, not just immediates.
986bdd1243dSDimitry Andric //
987bdd1243dSDimitry Andric // Some operands like FrameIndexes could resolve to an inline immediate value
988bdd1243dSDimitry Andric // that will not require an additional 4-bytes; this function assumes that it
989bdd1243dSDimitry Andric // will.
9900b57cec5SDimitry Andric bool isInlineConstant(const MachineOperand &MO, uint8_t OperandType) const;
9910b57cec5SDimitry Andric
isInlineConstant(const MachineOperand & MO,const MCOperandInfo & OpInfo)9920b57cec5SDimitry Andric bool isInlineConstant(const MachineOperand &MO,
9930b57cec5SDimitry Andric const MCOperandInfo &OpInfo) const {
9940b57cec5SDimitry Andric return isInlineConstant(MO, OpInfo.OperandType);
9950b57cec5SDimitry Andric }
9960b57cec5SDimitry Andric
9970b57cec5SDimitry Andric /// \p returns true if \p UseMO is substituted with \p DefMO in \p MI it would
9980b57cec5SDimitry Andric /// be an inline immediate.
isInlineConstant(const MachineInstr & MI,const MachineOperand & UseMO,const MachineOperand & DefMO)9990b57cec5SDimitry Andric bool isInlineConstant(const MachineInstr &MI,
10000b57cec5SDimitry Andric const MachineOperand &UseMO,
10010b57cec5SDimitry Andric const MachineOperand &DefMO) const {
10020b57cec5SDimitry Andric assert(UseMO.getParent() == &MI);
100306c3fb27SDimitry Andric int OpIdx = UseMO.getOperandNo();
1004bdd1243dSDimitry Andric if (OpIdx >= MI.getDesc().NumOperands)
10050b57cec5SDimitry Andric return false;
10060b57cec5SDimitry Andric
1007bdd1243dSDimitry Andric return isInlineConstant(DefMO, MI.getDesc().operands()[OpIdx]);
10080b57cec5SDimitry Andric }
10090b57cec5SDimitry Andric
10100b57cec5SDimitry Andric /// \p returns true if the operand \p OpIdx in \p MI is a valid inline
10110b57cec5SDimitry Andric /// immediate.
isInlineConstant(const MachineInstr & MI,unsigned OpIdx)10120b57cec5SDimitry Andric bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx) const {
10130b57cec5SDimitry Andric const MachineOperand &MO = MI.getOperand(OpIdx);
1014bdd1243dSDimitry Andric return isInlineConstant(MO, MI.getDesc().operands()[OpIdx].OperandType);
10150b57cec5SDimitry Andric }
10160b57cec5SDimitry Andric
isInlineConstant(const MachineInstr & MI,unsigned OpIdx,const MachineOperand & MO)10170b57cec5SDimitry Andric bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx,
10180b57cec5SDimitry Andric const MachineOperand &MO) const {
1019bdd1243dSDimitry Andric if (OpIdx >= MI.getDesc().NumOperands)
10200b57cec5SDimitry Andric return false;
10210b57cec5SDimitry Andric
10225f757f3fSDimitry Andric if (isCopyInstr(MI)) {
10230b57cec5SDimitry Andric unsigned Size = getOpSize(MI, OpIdx);
10240b57cec5SDimitry Andric assert(Size == 8 || Size == 4);
10250b57cec5SDimitry Andric
10260b57cec5SDimitry Andric uint8_t OpType = (Size == 8) ?
10270b57cec5SDimitry Andric AMDGPU::OPERAND_REG_IMM_INT64 : AMDGPU::OPERAND_REG_IMM_INT32;
10280b57cec5SDimitry Andric return isInlineConstant(MO, OpType);
10290b57cec5SDimitry Andric }
10300b57cec5SDimitry Andric
1031bdd1243dSDimitry Andric return isInlineConstant(MO, MI.getDesc().operands()[OpIdx].OperandType);
10320b57cec5SDimitry Andric }
10330b57cec5SDimitry Andric
isInlineConstant(const MachineOperand & MO)10340b57cec5SDimitry Andric bool isInlineConstant(const MachineOperand &MO) const {
103506c3fb27SDimitry Andric return isInlineConstant(*MO.getParent(), MO.getOperandNo());
10360b57cec5SDimitry Andric }
10370b57cec5SDimitry Andric
10380b57cec5SDimitry Andric bool isImmOperandLegal(const MachineInstr &MI, unsigned OpNo,
10390b57cec5SDimitry Andric const MachineOperand &MO) const;
10400b57cec5SDimitry Andric
10410b57cec5SDimitry Andric /// Return true if this 64-bit VALU instruction has a 32-bit encoding.
10420b57cec5SDimitry Andric /// This function will return false if you pass it a 32-bit instruction.
10430b57cec5SDimitry Andric bool hasVALU32BitEncoding(unsigned Opcode) const;
10440b57cec5SDimitry Andric
10450b57cec5SDimitry Andric /// Returns true if this operand uses the constant bus.
10460b57cec5SDimitry Andric bool usesConstantBus(const MachineRegisterInfo &MRI,
10470b57cec5SDimitry Andric const MachineOperand &MO,
10480b57cec5SDimitry Andric const MCOperandInfo &OpInfo) const;
10490b57cec5SDimitry Andric
10500b57cec5SDimitry Andric /// Return true if this instruction has any modifiers.
10510b57cec5SDimitry Andric /// e.g. src[012]_mod, omod, clamp.
10520b57cec5SDimitry Andric bool hasModifiers(unsigned Opcode) const;
10530b57cec5SDimitry Andric
10540b57cec5SDimitry Andric bool hasModifiersSet(const MachineInstr &MI,
10550b57cec5SDimitry Andric unsigned OpName) const;
10560b57cec5SDimitry Andric bool hasAnyModifiersSet(const MachineInstr &MI) const;
10570b57cec5SDimitry Andric
10580b57cec5SDimitry Andric bool canShrink(const MachineInstr &MI,
10590b57cec5SDimitry Andric const MachineRegisterInfo &MRI) const;
10600b57cec5SDimitry Andric
10610b57cec5SDimitry Andric MachineInstr *buildShrunkInst(MachineInstr &MI,
10620b57cec5SDimitry Andric unsigned NewOpcode) const;
10630b57cec5SDimitry Andric
10640b57cec5SDimitry Andric bool verifyInstruction(const MachineInstr &MI,
10650b57cec5SDimitry Andric StringRef &ErrInfo) const override;
10660b57cec5SDimitry Andric
10670b57cec5SDimitry Andric unsigned getVALUOp(const MachineInstr &MI) const;
10680b57cec5SDimitry Andric
106906c3fb27SDimitry Andric void insertScratchExecCopy(MachineFunction &MF, MachineBasicBlock &MBB,
107006c3fb27SDimitry Andric MachineBasicBlock::iterator MBBI,
10715f757f3fSDimitry Andric const DebugLoc &DL, Register Reg, bool IsSCCLive,
10725f757f3fSDimitry Andric SlotIndexes *Indexes = nullptr) const;
107306c3fb27SDimitry Andric
107406c3fb27SDimitry Andric void restoreExec(MachineFunction &MF, MachineBasicBlock &MBB,
107506c3fb27SDimitry Andric MachineBasicBlock::iterator MBBI, const DebugLoc &DL,
10765f757f3fSDimitry Andric Register Reg, SlotIndexes *Indexes = nullptr) const;
107706c3fb27SDimitry Andric
10780b57cec5SDimitry Andric /// Return the correct register class for \p OpNo. For target-specific
10790b57cec5SDimitry Andric /// instructions, this will return the register class that has been defined
10800b57cec5SDimitry Andric /// in tablegen. For generic instructions, like REG_SEQUENCE it will return
10810b57cec5SDimitry Andric /// the register class of its machine operand.
10820b57cec5SDimitry Andric /// to infer the correct register class base on the other operands.
10830b57cec5SDimitry Andric const TargetRegisterClass *getOpRegClass(const MachineInstr &MI,
10840b57cec5SDimitry Andric unsigned OpNo) const;
10850b57cec5SDimitry Andric
10860b57cec5SDimitry Andric /// Return the size in bytes of the operand OpNo on the given
10870b57cec5SDimitry Andric // instruction opcode.
getOpSize(uint16_t Opcode,unsigned OpNo)10880b57cec5SDimitry Andric unsigned getOpSize(uint16_t Opcode, unsigned OpNo) const {
1089bdd1243dSDimitry Andric const MCOperandInfo &OpInfo = get(Opcode).operands()[OpNo];
10900b57cec5SDimitry Andric
10910b57cec5SDimitry Andric if (OpInfo.RegClass == -1) {
10920b57cec5SDimitry Andric // If this is an immediate operand, this must be a 32-bit literal.
10930b57cec5SDimitry Andric assert(OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE);
10940b57cec5SDimitry Andric return 4;
10950b57cec5SDimitry Andric }
10960b57cec5SDimitry Andric
10970b57cec5SDimitry Andric return RI.getRegSizeInBits(*RI.getRegClass(OpInfo.RegClass)) / 8;
10980b57cec5SDimitry Andric }
10990b57cec5SDimitry Andric
11000b57cec5SDimitry Andric /// This form should usually be preferred since it handles operands
11010b57cec5SDimitry Andric /// with unknown register classes.
getOpSize(const MachineInstr & MI,unsigned OpNo)11020b57cec5SDimitry Andric unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const {
11030b57cec5SDimitry Andric const MachineOperand &MO = MI.getOperand(OpNo);
11040b57cec5SDimitry Andric if (MO.isReg()) {
11050b57cec5SDimitry Andric if (unsigned SubReg = MO.getSubReg()) {
11065ffd83dbSDimitry Andric return RI.getSubRegIdxSize(SubReg) / 8;
11070b57cec5SDimitry Andric }
11080b57cec5SDimitry Andric }
11090b57cec5SDimitry Andric return RI.getRegSizeInBits(*getOpRegClass(MI, OpNo)) / 8;
11100b57cec5SDimitry Andric }
11110b57cec5SDimitry Andric
11120b57cec5SDimitry Andric /// Legalize the \p OpIndex operand of this instruction by inserting
11130b57cec5SDimitry Andric /// a MOV. For example:
11140b57cec5SDimitry Andric /// ADD_I32_e32 VGPR0, 15
11150b57cec5SDimitry Andric /// to
11160b57cec5SDimitry Andric /// MOV VGPR1, 15
11170b57cec5SDimitry Andric /// ADD_I32_e32 VGPR0, VGPR1
11180b57cec5SDimitry Andric ///
11190b57cec5SDimitry Andric /// If the operand being legalized is a register, then a COPY will be used
11200b57cec5SDimitry Andric /// instead of MOV.
11210b57cec5SDimitry Andric void legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const;
11220b57cec5SDimitry Andric
11230b57cec5SDimitry Andric /// Check if \p MO is a legal operand if it was the \p OpIdx Operand
11240b57cec5SDimitry Andric /// for \p MI.
11250b57cec5SDimitry Andric bool isOperandLegal(const MachineInstr &MI, unsigned OpIdx,
11260b57cec5SDimitry Andric const MachineOperand *MO = nullptr) const;
11270b57cec5SDimitry Andric
11280b57cec5SDimitry Andric /// Check if \p MO would be a valid operand for the given operand
11290b57cec5SDimitry Andric /// definition \p OpInfo. Note this does not attempt to validate constant bus
11300b57cec5SDimitry Andric /// restrictions (e.g. literal constant usage).
11310b57cec5SDimitry Andric bool isLegalVSrcOperand(const MachineRegisterInfo &MRI,
11320b57cec5SDimitry Andric const MCOperandInfo &OpInfo,
11330b57cec5SDimitry Andric const MachineOperand &MO) const;
11340b57cec5SDimitry Andric
11350b57cec5SDimitry Andric /// Check if \p MO (a register operand) is a legal register for the
11360b57cec5SDimitry Andric /// given operand description.
11370b57cec5SDimitry Andric bool isLegalRegOperand(const MachineRegisterInfo &MRI,
11380b57cec5SDimitry Andric const MCOperandInfo &OpInfo,
11390b57cec5SDimitry Andric const MachineOperand &MO) const;
11400b57cec5SDimitry Andric
11410b57cec5SDimitry Andric /// Legalize operands in \p MI by either commuting it or inserting a
11420b57cec5SDimitry Andric /// copy of src1.
11430b57cec5SDimitry Andric void legalizeOperandsVOP2(MachineRegisterInfo &MRI, MachineInstr &MI) const;
11440b57cec5SDimitry Andric
11450b57cec5SDimitry Andric /// Fix operands in \p MI to satisfy constant bus requirements.
11460b57cec5SDimitry Andric void legalizeOperandsVOP3(MachineRegisterInfo &MRI, MachineInstr &MI) const;
11470b57cec5SDimitry Andric
11480b57cec5SDimitry Andric /// Copy a value from a VGPR (\p SrcReg) to SGPR. This function can only
11490b57cec5SDimitry Andric /// be used when it is know that the value in SrcReg is same across all
11500b57cec5SDimitry Andric /// threads in the wave.
11510b57cec5SDimitry Andric /// \returns The SGPR register that \p SrcReg was copied to.
11525ffd83dbSDimitry Andric Register readlaneVGPRToSGPR(Register SrcReg, MachineInstr &UseMI,
11530b57cec5SDimitry Andric MachineRegisterInfo &MRI) const;
11540b57cec5SDimitry Andric
11550b57cec5SDimitry Andric void legalizeOperandsSMRD(MachineRegisterInfo &MRI, MachineInstr &MI) const;
1156e8d8bef9SDimitry Andric void legalizeOperandsFLAT(MachineRegisterInfo &MRI, MachineInstr &MI) const;
11570b57cec5SDimitry Andric
11580b57cec5SDimitry Andric void legalizeGenericOperand(MachineBasicBlock &InsertMBB,
11590b57cec5SDimitry Andric MachineBasicBlock::iterator I,
11600b57cec5SDimitry Andric const TargetRegisterClass *DstRC,
11610b57cec5SDimitry Andric MachineOperand &Op, MachineRegisterInfo &MRI,
11620b57cec5SDimitry Andric const DebugLoc &DL) const;
11630b57cec5SDimitry Andric
11640b57cec5SDimitry Andric /// Legalize all operands in this instruction. This function may create new
11650b57cec5SDimitry Andric /// instructions and control-flow around \p MI. If present, \p MDT is
11660b57cec5SDimitry Andric /// updated.
1167e8d8bef9SDimitry Andric /// \returns A new basic block that contains \p MI if new blocks were created.
1168e8d8bef9SDimitry Andric MachineBasicBlock *
1169e8d8bef9SDimitry Andric legalizeOperands(MachineInstr &MI, MachineDominatorTree *MDT = nullptr) const;
11700b57cec5SDimitry Andric
1171fe6060f1SDimitry Andric /// Change SADDR form of a FLAT \p Inst to its VADDR form if saddr operand
1172fe6060f1SDimitry Andric /// was moved to VGPR. \returns true if succeeded.
1173fe6060f1SDimitry Andric bool moveFlatAddrToVGPR(MachineInstr &Inst) const;
1174fe6060f1SDimitry Andric
117506c3fb27SDimitry Andric /// Replace the instructions opcode with the equivalent VALU
117606c3fb27SDimitry Andric /// opcode. This function will also move the users of MachineInstruntions
117706c3fb27SDimitry Andric /// in the \p WorkList to the VALU if necessary. If present, \p MDT is
117806c3fb27SDimitry Andric /// updated.
117906c3fb27SDimitry Andric void moveToVALU(SIInstrWorklist &Worklist, MachineDominatorTree *MDT) const;
118006c3fb27SDimitry Andric
118106c3fb27SDimitry Andric void moveToVALUImpl(SIInstrWorklist &Worklist, MachineDominatorTree *MDT,
118206c3fb27SDimitry Andric MachineInstr &Inst) const;
11830b57cec5SDimitry Andric
11840b57cec5SDimitry Andric void insertNoop(MachineBasicBlock &MBB,
11850b57cec5SDimitry Andric MachineBasicBlock::iterator MI) const override;
11860b57cec5SDimitry Andric
1187e8d8bef9SDimitry Andric void insertNoops(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
1188e8d8bef9SDimitry Andric unsigned Quantity) const override;
1189e8d8bef9SDimitry Andric
11900b57cec5SDimitry Andric void insertReturn(MachineBasicBlock &MBB) const;
11910b57cec5SDimitry Andric /// Return the number of wait states that result from executing this
11920b57cec5SDimitry Andric /// instruction.
11930b57cec5SDimitry Andric static unsigned getNumWaitStates(const MachineInstr &MI);
11940b57cec5SDimitry Andric
11950b57cec5SDimitry Andric /// Returns the operand named \p Op. If \p MI does not have an
11960b57cec5SDimitry Andric /// operand named \c Op, this function returns nullptr.
11970b57cec5SDimitry Andric LLVM_READONLY
11980b57cec5SDimitry Andric MachineOperand *getNamedOperand(MachineInstr &MI, unsigned OperandName) const;
11990b57cec5SDimitry Andric
12000b57cec5SDimitry Andric LLVM_READONLY
getNamedOperand(const MachineInstr & MI,unsigned OpName)12010b57cec5SDimitry Andric const MachineOperand *getNamedOperand(const MachineInstr &MI,
12020b57cec5SDimitry Andric unsigned OpName) const {
12030b57cec5SDimitry Andric return getNamedOperand(const_cast<MachineInstr &>(MI), OpName);
12040b57cec5SDimitry Andric }
12050b57cec5SDimitry Andric
12060b57cec5SDimitry Andric /// Get required immediate operand
getNamedImmOperand(const MachineInstr & MI,unsigned OpName)12070b57cec5SDimitry Andric int64_t getNamedImmOperand(const MachineInstr &MI, unsigned OpName) const {
12080b57cec5SDimitry Andric int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), OpName);
12090b57cec5SDimitry Andric return MI.getOperand(Idx).getImm();
12100b57cec5SDimitry Andric }
12110b57cec5SDimitry Andric
12120b57cec5SDimitry Andric uint64_t getDefaultRsrcDataFormat() const;
12130b57cec5SDimitry Andric uint64_t getScratchRsrcWords23() const;
12140b57cec5SDimitry Andric
12150b57cec5SDimitry Andric bool isLowLatencyInstruction(const MachineInstr &MI) const;
12165ffd83dbSDimitry Andric bool isHighLatencyDef(int Opc) const override;
12170b57cec5SDimitry Andric
12180b57cec5SDimitry Andric /// Return the descriptor of the target-specific machine instruction
12190b57cec5SDimitry Andric /// that corresponds to the specified pseudo or native opcode.
getMCOpcodeFromPseudo(unsigned Opcode)12200b57cec5SDimitry Andric const MCInstrDesc &getMCOpcodeFromPseudo(unsigned Opcode) const {
12210b57cec5SDimitry Andric return get(pseudoToMCOpcode(Opcode));
12220b57cec5SDimitry Andric }
12230b57cec5SDimitry Andric
12240b57cec5SDimitry Andric unsigned isStackAccess(const MachineInstr &MI, int &FrameIndex) const;
12250b57cec5SDimitry Andric unsigned isSGPRStackAccess(const MachineInstr &MI, int &FrameIndex) const;
12260b57cec5SDimitry Andric
12270b57cec5SDimitry Andric unsigned isLoadFromStackSlot(const MachineInstr &MI,
12280b57cec5SDimitry Andric int &FrameIndex) const override;
12290b57cec5SDimitry Andric unsigned isStoreToStackSlot(const MachineInstr &MI,
12300b57cec5SDimitry Andric int &FrameIndex) const override;
12310b57cec5SDimitry Andric
12320b57cec5SDimitry Andric unsigned getInstBundleSize(const MachineInstr &MI) const;
12330b57cec5SDimitry Andric unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
12340b57cec5SDimitry Andric
12350b57cec5SDimitry Andric bool mayAccessFlatAddressSpace(const MachineInstr &MI) const;
12360b57cec5SDimitry Andric
12370b57cec5SDimitry Andric bool isNonUniformBranchInstr(MachineInstr &Instr) const;
12380b57cec5SDimitry Andric
12390b57cec5SDimitry Andric void convertNonUniformIfRegion(MachineBasicBlock *IfEntry,
12400b57cec5SDimitry Andric MachineBasicBlock *IfEnd) const;
12410b57cec5SDimitry Andric
12420b57cec5SDimitry Andric void convertNonUniformLoopRegion(MachineBasicBlock *LoopEntry,
12430b57cec5SDimitry Andric MachineBasicBlock *LoopEnd) const;
12440b57cec5SDimitry Andric
12450b57cec5SDimitry Andric std::pair<unsigned, unsigned>
12460b57cec5SDimitry Andric decomposeMachineOperandsTargetFlags(unsigned TF) const override;
12470b57cec5SDimitry Andric
12480b57cec5SDimitry Andric ArrayRef<std::pair<int, const char *>>
12490b57cec5SDimitry Andric getSerializableTargetIndices() const override;
12500b57cec5SDimitry Andric
12510b57cec5SDimitry Andric ArrayRef<std::pair<unsigned, const char *>>
12520b57cec5SDimitry Andric getSerializableDirectMachineOperandTargetFlags() const override;
12530b57cec5SDimitry Andric
125481ad6265SDimitry Andric ArrayRef<std::pair<MachineMemOperand::Flags, const char *>>
125581ad6265SDimitry Andric getSerializableMachineMemOperandTargetFlags() const override;
125681ad6265SDimitry Andric
12570b57cec5SDimitry Andric ScheduleHazardRecognizer *
12580b57cec5SDimitry Andric CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
12590b57cec5SDimitry Andric const ScheduleDAG *DAG) const override;
12600b57cec5SDimitry Andric
12610b57cec5SDimitry Andric ScheduleHazardRecognizer *
12620b57cec5SDimitry Andric CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const override;
12630b57cec5SDimitry Andric
1264349cc55cSDimitry Andric ScheduleHazardRecognizer *
1265349cc55cSDimitry Andric CreateTargetMIHazardRecognizer(const InstrItineraryData *II,
1266349cc55cSDimitry Andric const ScheduleDAGMI *DAG) const override;
1267349cc55cSDimitry Andric
12685f757f3fSDimitry Andric unsigned getLiveRangeSplitOpcode(Register Reg,
12695f757f3fSDimitry Andric const MachineFunction &MF) const override;
12705f757f3fSDimitry Andric
12715f757f3fSDimitry Andric bool isBasicBlockPrologue(const MachineInstr &MI,
12725f757f3fSDimitry Andric Register Reg = Register()) const override;
12730b57cec5SDimitry Andric
12748bcb0991SDimitry Andric MachineInstr *createPHIDestinationCopy(MachineBasicBlock &MBB,
12758bcb0991SDimitry Andric MachineBasicBlock::iterator InsPt,
12768bcb0991SDimitry Andric const DebugLoc &DL, Register Src,
12778bcb0991SDimitry Andric Register Dst) const override;
12788bcb0991SDimitry Andric
12798bcb0991SDimitry Andric MachineInstr *createPHISourceCopy(MachineBasicBlock &MBB,
12808bcb0991SDimitry Andric MachineBasicBlock::iterator InsPt,
12818bcb0991SDimitry Andric const DebugLoc &DL, Register Src,
1282480093f4SDimitry Andric unsigned SrcSubReg,
12838bcb0991SDimitry Andric Register Dst) const override;
12848bcb0991SDimitry Andric
12858bcb0991SDimitry Andric bool isWave32() const;
12868bcb0991SDimitry Andric
12870b57cec5SDimitry Andric /// Return a partially built integer add instruction without carry.
12880b57cec5SDimitry Andric /// Caller must add source operands.
12890b57cec5SDimitry Andric /// For pre-GFX9 it will generate unused carry destination operand.
12900b57cec5SDimitry Andric /// TODO: After GFX9 it should return a no-carry operation.
12910b57cec5SDimitry Andric MachineInstrBuilder getAddNoCarry(MachineBasicBlock &MBB,
12920b57cec5SDimitry Andric MachineBasicBlock::iterator I,
12930b57cec5SDimitry Andric const DebugLoc &DL,
12945ffd83dbSDimitry Andric Register DestReg) const;
12950b57cec5SDimitry Andric
12968bcb0991SDimitry Andric MachineInstrBuilder getAddNoCarry(MachineBasicBlock &MBB,
12978bcb0991SDimitry Andric MachineBasicBlock::iterator I,
12988bcb0991SDimitry Andric const DebugLoc &DL,
12998bcb0991SDimitry Andric Register DestReg,
13008bcb0991SDimitry Andric RegScavenger &RS) const;
13018bcb0991SDimitry Andric
13020b57cec5SDimitry Andric static bool isKillTerminator(unsigned Opcode);
13030b57cec5SDimitry Andric const MCInstrDesc &getKillTerminatorFromPseudo(unsigned Opcode) const;
13040b57cec5SDimitry Andric
13055f757f3fSDimitry Andric bool isLegalMUBUFImmOffset(unsigned Imm) const;
13060b57cec5SDimitry Andric
13075f757f3fSDimitry Andric static unsigned getMaxMUBUFImmOffset(const GCNSubtarget &ST);
130806c3fb27SDimitry Andric
130906c3fb27SDimitry Andric bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset,
131006c3fb27SDimitry Andric Align Alignment = Align(4)) const;
131106c3fb27SDimitry Andric
13120b57cec5SDimitry Andric /// Returns if \p Offset is legal for the subtarget as the offset to a FLAT
13130b57cec5SDimitry Andric /// encoded instruction. If \p Signed, this is for an instruction that
13140b57cec5SDimitry Andric /// interprets the offset as signed.
13150b57cec5SDimitry Andric bool isLegalFLATOffset(int64_t Offset, unsigned AddrSpace,
1316fe6060f1SDimitry Andric uint64_t FlatVariant) const;
13170b57cec5SDimitry Andric
1318e8d8bef9SDimitry Andric /// Split \p COffsetVal into {immediate offset field, remainder offset}
1319e8d8bef9SDimitry Andric /// values.
1320e8d8bef9SDimitry Andric std::pair<int64_t, int64_t> splitFlatOffset(int64_t COffsetVal,
1321e8d8bef9SDimitry Andric unsigned AddrSpace,
1322fe6060f1SDimitry Andric uint64_t FlatVariant) const;
1323e8d8bef9SDimitry Andric
13245f757f3fSDimitry Andric /// Returns true if negative offsets are allowed for the given \p FlatVariant.
13255f757f3fSDimitry Andric bool allowNegativeFlatOffset(uint64_t FlatVariant) const;
13265f757f3fSDimitry Andric
13270b57cec5SDimitry Andric /// \brief Return a target-specific opcode if Opcode is a pseudo instruction.
13280b57cec5SDimitry Andric /// Return -1 if the target-specific opcode for the pseudo instruction does
13290b57cec5SDimitry Andric /// not exist. If Opcode is not a pseudo instruction, this is identity.
13300b57cec5SDimitry Andric int pseudoToMCOpcode(int Opcode) const;
13310b57cec5SDimitry Andric
1332480093f4SDimitry Andric /// \brief Check if this instruction should only be used by assembler.
1333480093f4SDimitry Andric /// Return true if this opcode should not be used by codegen.
1334480093f4SDimitry Andric bool isAsmOnlyOpcode(int MCOp) const;
1335480093f4SDimitry Andric
13360b57cec5SDimitry Andric const TargetRegisterClass *getRegClass(const MCInstrDesc &TID, unsigned OpNum,
13370b57cec5SDimitry Andric const TargetRegisterInfo *TRI,
13380b57cec5SDimitry Andric const MachineFunction &MF)
1339fe6060f1SDimitry Andric const override;
13400b57cec5SDimitry Andric
13410b57cec5SDimitry Andric void fixImplicitOperands(MachineInstr &MI) const;
1342480093f4SDimitry Andric
1343480093f4SDimitry Andric MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
1344480093f4SDimitry Andric ArrayRef<unsigned> Ops,
1345480093f4SDimitry Andric MachineBasicBlock::iterator InsertPt,
1346480093f4SDimitry Andric int FrameIndex,
1347480093f4SDimitry Andric LiveIntervals *LIS = nullptr,
1348480093f4SDimitry Andric VirtRegMap *VRM = nullptr) const override;
1349480093f4SDimitry Andric
1350480093f4SDimitry Andric unsigned getInstrLatency(const InstrItineraryData *ItinData,
1351480093f4SDimitry Andric const MachineInstr &MI,
1352480093f4SDimitry Andric unsigned *PredCost = nullptr) const override;
1353e8d8bef9SDimitry Andric
1354bdd1243dSDimitry Andric InstructionUniformity
1355bdd1243dSDimitry Andric getInstructionUniformity(const MachineInstr &MI) const override final;
1356bdd1243dSDimitry Andric
1357bdd1243dSDimitry Andric InstructionUniformity
1358bdd1243dSDimitry Andric getGenericInstructionUniformity(const MachineInstr &MI) const;
1359bdd1243dSDimitry Andric
getMIRFormatter()1360e8d8bef9SDimitry Andric const MIRFormatter *getMIRFormatter() const override {
1361e8d8bef9SDimitry Andric if (!Formatter.get())
1362e8d8bef9SDimitry Andric Formatter = std::make_unique<AMDGPUMIRFormatter>();
1363e8d8bef9SDimitry Andric return Formatter.get();
1364e8d8bef9SDimitry Andric }
1365e8d8bef9SDimitry Andric
1366e8d8bef9SDimitry Andric static unsigned getDSShaderTypeValue(const MachineFunction &MF);
1367349cc55cSDimitry Andric
getSchedModel()1368349cc55cSDimitry Andric const TargetSchedModel &getSchedModel() const { return SchedModel; }
136981ad6265SDimitry Andric
137081ad6265SDimitry Andric // Enforce operand's \p OpName even alignment if required by target.
137181ad6265SDimitry Andric // This is used if an operand is a 32 bit register but needs to be aligned
137281ad6265SDimitry Andric // regardless.
137381ad6265SDimitry Andric void enforceOperandRCAlignment(MachineInstr &MI, unsigned OpName) const;
13740b57cec5SDimitry Andric };
13750b57cec5SDimitry Andric
13760b57cec5SDimitry Andric /// \brief Returns true if a reg:subreg pair P has a TRC class
isOfRegClass(const TargetInstrInfo::RegSubRegPair & P,const TargetRegisterClass & TRC,MachineRegisterInfo & MRI)13770b57cec5SDimitry Andric inline bool isOfRegClass(const TargetInstrInfo::RegSubRegPair &P,
13780b57cec5SDimitry Andric const TargetRegisterClass &TRC,
13790b57cec5SDimitry Andric MachineRegisterInfo &MRI) {
13800b57cec5SDimitry Andric auto *RC = MRI.getRegClass(P.Reg);
13810b57cec5SDimitry Andric if (!P.SubReg)
13820b57cec5SDimitry Andric return RC == &TRC;
13830b57cec5SDimitry Andric auto *TRI = MRI.getTargetRegisterInfo();
13840b57cec5SDimitry Andric return RC == TRI->getMatchingSuperRegClass(RC, &TRC, P.SubReg);
13850b57cec5SDimitry Andric }
13860b57cec5SDimitry Andric
13870b57cec5SDimitry Andric /// \brief Create RegSubRegPair from a register MachineOperand
13880b57cec5SDimitry Andric inline
getRegSubRegPair(const MachineOperand & O)13890b57cec5SDimitry Andric TargetInstrInfo::RegSubRegPair getRegSubRegPair(const MachineOperand &O) {
13900b57cec5SDimitry Andric assert(O.isReg());
13910b57cec5SDimitry Andric return TargetInstrInfo::RegSubRegPair(O.getReg(), O.getSubReg());
13920b57cec5SDimitry Andric }
13930b57cec5SDimitry Andric
13940b57cec5SDimitry Andric /// \brief Return the SubReg component from REG_SEQUENCE
13950b57cec5SDimitry Andric TargetInstrInfo::RegSubRegPair getRegSequenceSubReg(MachineInstr &MI,
13960b57cec5SDimitry Andric unsigned SubReg);
13970b57cec5SDimitry Andric
13980b57cec5SDimitry Andric /// \brief Return the defining instruction for a given reg:subreg pair
13990b57cec5SDimitry Andric /// skipping copy like instructions and subreg-manipulation pseudos.
14000b57cec5SDimitry Andric /// Following another subreg of a reg:subreg isn't supported.
14010b57cec5SDimitry Andric MachineInstr *getVRegSubRegDef(const TargetInstrInfo::RegSubRegPair &P,
14020b57cec5SDimitry Andric MachineRegisterInfo &MRI);
14030b57cec5SDimitry Andric
14040b57cec5SDimitry Andric /// \brief Return false if EXEC is not changed between the def of \p VReg at \p
14050b57cec5SDimitry Andric /// DefMI and the use at \p UseMI. Should be run on SSA. Currently does not
14060b57cec5SDimitry Andric /// attempt to track between blocks.
14070b57cec5SDimitry Andric bool execMayBeModifiedBeforeUse(const MachineRegisterInfo &MRI,
14080b57cec5SDimitry Andric Register VReg,
14090b57cec5SDimitry Andric const MachineInstr &DefMI,
14100b57cec5SDimitry Andric const MachineInstr &UseMI);
14110b57cec5SDimitry Andric
14120b57cec5SDimitry Andric /// \brief Return false if EXEC is not changed between the def of \p VReg at \p
14130b57cec5SDimitry Andric /// DefMI and all its uses. Should be run on SSA. Currently does not attempt to
14140b57cec5SDimitry Andric /// track between blocks.
14150b57cec5SDimitry Andric bool execMayBeModifiedBeforeAnyUse(const MachineRegisterInfo &MRI,
14160b57cec5SDimitry Andric Register VReg,
14170b57cec5SDimitry Andric const MachineInstr &DefMI);
14180b57cec5SDimitry Andric
14190b57cec5SDimitry Andric namespace AMDGPU {
14200b57cec5SDimitry Andric
14210b57cec5SDimitry Andric LLVM_READONLY
14220b57cec5SDimitry Andric int getVOPe64(uint16_t Opcode);
14230b57cec5SDimitry Andric
14240b57cec5SDimitry Andric LLVM_READONLY
14250b57cec5SDimitry Andric int getVOPe32(uint16_t Opcode);
14260b57cec5SDimitry Andric
14270b57cec5SDimitry Andric LLVM_READONLY
14280b57cec5SDimitry Andric int getSDWAOp(uint16_t Opcode);
14290b57cec5SDimitry Andric
14300b57cec5SDimitry Andric LLVM_READONLY
14310b57cec5SDimitry Andric int getDPPOp32(uint16_t Opcode);
14320b57cec5SDimitry Andric
14330b57cec5SDimitry Andric LLVM_READONLY
1434753f127fSDimitry Andric int getDPPOp64(uint16_t Opcode);
1435753f127fSDimitry Andric
1436753f127fSDimitry Andric LLVM_READONLY
14370b57cec5SDimitry Andric int getBasicFromSDWAOp(uint16_t Opcode);
14380b57cec5SDimitry Andric
14390b57cec5SDimitry Andric LLVM_READONLY
14400b57cec5SDimitry Andric int getCommuteRev(uint16_t Opcode);
14410b57cec5SDimitry Andric
14420b57cec5SDimitry Andric LLVM_READONLY
14430b57cec5SDimitry Andric int getCommuteOrig(uint16_t Opcode);
14440b57cec5SDimitry Andric
14450b57cec5SDimitry Andric LLVM_READONLY
14460b57cec5SDimitry Andric int getAddr64Inst(uint16_t Opcode);
14470b57cec5SDimitry Andric
14480b57cec5SDimitry Andric /// Check if \p Opcode is an Addr64 opcode.
14490b57cec5SDimitry Andric ///
14500b57cec5SDimitry Andric /// \returns \p Opcode if it is an Addr64 opcode, otherwise -1.
14510b57cec5SDimitry Andric LLVM_READONLY
14520b57cec5SDimitry Andric int getIfAddr64Inst(uint16_t Opcode);
14530b57cec5SDimitry Andric
14540b57cec5SDimitry Andric LLVM_READONLY
14550b57cec5SDimitry Andric int getAtomicNoRetOp(uint16_t Opcode);
14560b57cec5SDimitry Andric
14570b57cec5SDimitry Andric LLVM_READONLY
14580b57cec5SDimitry Andric int getSOPKOp(uint16_t Opcode);
14590b57cec5SDimitry Andric
1460fe6060f1SDimitry Andric /// \returns SADDR form of a FLAT Global instruction given an \p Opcode
1461fe6060f1SDimitry Andric /// of a VADDR form.
14620b57cec5SDimitry Andric LLVM_READONLY
14630b57cec5SDimitry Andric int getGlobalSaddrOp(uint16_t Opcode);
14640b57cec5SDimitry Andric
1465fe6060f1SDimitry Andric /// \returns VADDR form of a FLAT Global instruction given an \p Opcode
1466fe6060f1SDimitry Andric /// of a SADDR form.
1467fe6060f1SDimitry Andric LLVM_READONLY
1468fe6060f1SDimitry Andric int getGlobalVaddrOp(uint16_t Opcode);
1469fe6060f1SDimitry Andric
14700b57cec5SDimitry Andric LLVM_READONLY
14710b57cec5SDimitry Andric int getVCMPXNoSDstOp(uint16_t Opcode);
14720b57cec5SDimitry Andric
1473fe6060f1SDimitry Andric /// \returns ST form with only immediate offset of a FLAT Scratch instruction
1474fe6060f1SDimitry Andric /// given an \p Opcode of an SS (SADDR) form.
1475e8d8bef9SDimitry Andric LLVM_READONLY
1476e8d8bef9SDimitry Andric int getFlatScratchInstSTfromSS(uint16_t Opcode);
1477e8d8bef9SDimitry Andric
147881ad6265SDimitry Andric /// \returns SV (VADDR) form of a FLAT Scratch instruction given an \p Opcode
147981ad6265SDimitry Andric /// of an SVS (SADDR + VADDR) form.
148081ad6265SDimitry Andric LLVM_READONLY
148181ad6265SDimitry Andric int getFlatScratchInstSVfromSVS(uint16_t Opcode);
148281ad6265SDimitry Andric
1483fe6060f1SDimitry Andric /// \returns SS (SADDR) form of a FLAT Scratch instruction given an \p Opcode
1484fe6060f1SDimitry Andric /// of an SV (VADDR) form.
1485e8d8bef9SDimitry Andric LLVM_READONLY
1486e8d8bef9SDimitry Andric int getFlatScratchInstSSfromSV(uint16_t Opcode);
1487e8d8bef9SDimitry Andric
1488fe6060f1SDimitry Andric /// \returns SV (VADDR) form of a FLAT Scratch instruction given an \p Opcode
1489fe6060f1SDimitry Andric /// of an SS (SADDR) form.
1490fe6060f1SDimitry Andric LLVM_READONLY
1491fe6060f1SDimitry Andric int getFlatScratchInstSVfromSS(uint16_t Opcode);
1492fe6060f1SDimitry Andric
149304eeddc0SDimitry Andric /// \returns earlyclobber version of a MAC MFMA is exists.
149404eeddc0SDimitry Andric LLVM_READONLY
149504eeddc0SDimitry Andric int getMFMAEarlyClobberOp(uint16_t Opcode);
149604eeddc0SDimitry Andric
149781ad6265SDimitry Andric /// \returns v_cmpx version of a v_cmp instruction.
149881ad6265SDimitry Andric LLVM_READONLY
149981ad6265SDimitry Andric int getVCMPXOpFromVCMP(uint16_t Opcode);
150081ad6265SDimitry Andric
15010b57cec5SDimitry Andric const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL;
15020b57cec5SDimitry Andric const uint64_t RSRC_ELEMENT_SIZE_SHIFT = (32 + 19);
15030b57cec5SDimitry Andric const uint64_t RSRC_INDEX_STRIDE_SHIFT = (32 + 21);
15040b57cec5SDimitry Andric const uint64_t RSRC_TID_ENABLE = UINT64_C(1) << (32 + 23);
15050b57cec5SDimitry Andric
15060b57cec5SDimitry Andric } // end namespace AMDGPU
15070b57cec5SDimitry Andric
15085f757f3fSDimitry Andric namespace AMDGPU {
15095f757f3fSDimitry Andric enum AsmComments {
15105f757f3fSDimitry Andric // For sgpr to vgpr spill instructions
15115f757f3fSDimitry Andric SGPR_SPILL = MachineInstr::TAsmComments
15125f757f3fSDimitry Andric };
15135f757f3fSDimitry Andric } // namespace AMDGPU
15145f757f3fSDimitry Andric
15150b57cec5SDimitry Andric namespace SI {
15160b57cec5SDimitry Andric namespace KernelInputOffsets {
15170b57cec5SDimitry Andric
15180b57cec5SDimitry Andric /// Offsets in bytes from the start of the input buffer
15190b57cec5SDimitry Andric enum Offsets {
15200b57cec5SDimitry Andric NGROUPS_X = 0,
15210b57cec5SDimitry Andric NGROUPS_Y = 4,
15220b57cec5SDimitry Andric NGROUPS_Z = 8,
15230b57cec5SDimitry Andric GLOBAL_SIZE_X = 12,
15240b57cec5SDimitry Andric GLOBAL_SIZE_Y = 16,
15250b57cec5SDimitry Andric GLOBAL_SIZE_Z = 20,
15260b57cec5SDimitry Andric LOCAL_SIZE_X = 24,
15270b57cec5SDimitry Andric LOCAL_SIZE_Y = 28,
15280b57cec5SDimitry Andric LOCAL_SIZE_Z = 32
15290b57cec5SDimitry Andric };
15300b57cec5SDimitry Andric
15310b57cec5SDimitry Andric } // end namespace KernelInputOffsets
15320b57cec5SDimitry Andric } // end namespace SI
15330b57cec5SDimitry Andric
15340b57cec5SDimitry Andric } // end namespace llvm
15350b57cec5SDimitry Andric
15360b57cec5SDimitry Andric #endif // LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
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