1 //===-- SIOptimizeExecMasking.cpp -----------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "AMDGPU.h"
10 #include "AMDGPUSubtarget.h"
11 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
12 #include "SIInstrInfo.h"
13 #include "llvm/ADT/SmallSet.h"
14 #include "llvm/CodeGen/MachineFunctionPass.h"
15 #include "llvm/CodeGen/MachineInstrBuilder.h"
16 #include "llvm/CodeGen/MachineRegisterInfo.h"
17 #include "llvm/InitializePasses.h"
18 #include "llvm/Support/Debug.h"
19 
20 using namespace llvm;
21 
22 #define DEBUG_TYPE "si-optimize-exec-masking"
23 
24 namespace {
25 
26 class SIOptimizeExecMasking : public MachineFunctionPass {
27 public:
28   static char ID;
29 
30 public:
31   SIOptimizeExecMasking() : MachineFunctionPass(ID) {
32     initializeSIOptimizeExecMaskingPass(*PassRegistry::getPassRegistry());
33   }
34 
35   bool runOnMachineFunction(MachineFunction &MF) override;
36 
37   StringRef getPassName() const override {
38     return "SI optimize exec mask operations";
39   }
40 
41   void getAnalysisUsage(AnalysisUsage &AU) const override {
42     AU.setPreservesCFG();
43     MachineFunctionPass::getAnalysisUsage(AU);
44   }
45 };
46 
47 } // End anonymous namespace.
48 
49 INITIALIZE_PASS_BEGIN(SIOptimizeExecMasking, DEBUG_TYPE,
50                       "SI optimize exec mask operations", false, false)
51 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
52 INITIALIZE_PASS_END(SIOptimizeExecMasking, DEBUG_TYPE,
53                     "SI optimize exec mask operations", false, false)
54 
55 char SIOptimizeExecMasking::ID = 0;
56 
57 char &llvm::SIOptimizeExecMaskingID = SIOptimizeExecMasking::ID;
58 
59 /// If \p MI is a copy from exec, return the register copied to.
60 static Register isCopyFromExec(const MachineInstr &MI, const GCNSubtarget &ST) {
61   switch (MI.getOpcode()) {
62   case AMDGPU::COPY:
63   case AMDGPU::S_MOV_B64:
64   case AMDGPU::S_MOV_B64_term:
65   case AMDGPU::S_MOV_B32:
66   case AMDGPU::S_MOV_B32_term: {
67     const MachineOperand &Src = MI.getOperand(1);
68     if (Src.isReg() &&
69         Src.getReg() == (ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC))
70       return MI.getOperand(0).getReg();
71   }
72   }
73 
74   return AMDGPU::NoRegister;
75 }
76 
77 /// If \p MI is a copy to exec, return the register copied from.
78 static Register isCopyToExec(const MachineInstr &MI, const GCNSubtarget &ST) {
79   switch (MI.getOpcode()) {
80   case AMDGPU::COPY:
81   case AMDGPU::S_MOV_B64:
82   case AMDGPU::S_MOV_B32: {
83     const MachineOperand &Dst = MI.getOperand(0);
84     if (Dst.isReg() &&
85         Dst.getReg() == (ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC) &&
86         MI.getOperand(1).isReg())
87       return MI.getOperand(1).getReg();
88     break;
89   }
90   case AMDGPU::S_MOV_B64_term:
91   case AMDGPU::S_MOV_B32_term:
92     llvm_unreachable("should have been replaced");
93   }
94 
95   return Register();
96 }
97 
98 /// If \p MI is a logical operation on an exec value,
99 /// return the register copied to.
100 static Register isLogicalOpOnExec(const MachineInstr &MI) {
101   switch (MI.getOpcode()) {
102   case AMDGPU::S_AND_B64:
103   case AMDGPU::S_OR_B64:
104   case AMDGPU::S_XOR_B64:
105   case AMDGPU::S_ANDN2_B64:
106   case AMDGPU::S_ORN2_B64:
107   case AMDGPU::S_NAND_B64:
108   case AMDGPU::S_NOR_B64:
109   case AMDGPU::S_XNOR_B64: {
110     const MachineOperand &Src1 = MI.getOperand(1);
111     if (Src1.isReg() && Src1.getReg() == AMDGPU::EXEC)
112       return MI.getOperand(0).getReg();
113     const MachineOperand &Src2 = MI.getOperand(2);
114     if (Src2.isReg() && Src2.getReg() == AMDGPU::EXEC)
115       return MI.getOperand(0).getReg();
116     break;
117   }
118   case AMDGPU::S_AND_B32:
119   case AMDGPU::S_OR_B32:
120   case AMDGPU::S_XOR_B32:
121   case AMDGPU::S_ANDN2_B32:
122   case AMDGPU::S_ORN2_B32:
123   case AMDGPU::S_NAND_B32:
124   case AMDGPU::S_NOR_B32:
125   case AMDGPU::S_XNOR_B32: {
126     const MachineOperand &Src1 = MI.getOperand(1);
127     if (Src1.isReg() && Src1.getReg() == AMDGPU::EXEC_LO)
128       return MI.getOperand(0).getReg();
129     const MachineOperand &Src2 = MI.getOperand(2);
130     if (Src2.isReg() && Src2.getReg() == AMDGPU::EXEC_LO)
131       return MI.getOperand(0).getReg();
132     break;
133   }
134   }
135 
136   return AMDGPU::NoRegister;
137 }
138 
139 static unsigned getSaveExecOp(unsigned Opc) {
140   switch (Opc) {
141   case AMDGPU::S_AND_B64:
142     return AMDGPU::S_AND_SAVEEXEC_B64;
143   case AMDGPU::S_OR_B64:
144     return AMDGPU::S_OR_SAVEEXEC_B64;
145   case AMDGPU::S_XOR_B64:
146     return AMDGPU::S_XOR_SAVEEXEC_B64;
147   case AMDGPU::S_ANDN2_B64:
148     return AMDGPU::S_ANDN2_SAVEEXEC_B64;
149   case AMDGPU::S_ORN2_B64:
150     return AMDGPU::S_ORN2_SAVEEXEC_B64;
151   case AMDGPU::S_NAND_B64:
152     return AMDGPU::S_NAND_SAVEEXEC_B64;
153   case AMDGPU::S_NOR_B64:
154     return AMDGPU::S_NOR_SAVEEXEC_B64;
155   case AMDGPU::S_XNOR_B64:
156     return AMDGPU::S_XNOR_SAVEEXEC_B64;
157   case AMDGPU::S_AND_B32:
158     return AMDGPU::S_AND_SAVEEXEC_B32;
159   case AMDGPU::S_OR_B32:
160     return AMDGPU::S_OR_SAVEEXEC_B32;
161   case AMDGPU::S_XOR_B32:
162     return AMDGPU::S_XOR_SAVEEXEC_B32;
163   case AMDGPU::S_ANDN2_B32:
164     return AMDGPU::S_ANDN2_SAVEEXEC_B32;
165   case AMDGPU::S_ORN2_B32:
166     return AMDGPU::S_ORN2_SAVEEXEC_B32;
167   case AMDGPU::S_NAND_B32:
168     return AMDGPU::S_NAND_SAVEEXEC_B32;
169   case AMDGPU::S_NOR_B32:
170     return AMDGPU::S_NOR_SAVEEXEC_B32;
171   case AMDGPU::S_XNOR_B32:
172     return AMDGPU::S_XNOR_SAVEEXEC_B32;
173   default:
174     return AMDGPU::INSTRUCTION_LIST_END;
175   }
176 }
177 
178 // These are only terminators to get correct spill code placement during
179 // register allocation, so turn them back into normal instructions. Only one of
180 // these is expected per block.
181 static bool removeTerminatorBit(const SIInstrInfo &TII, MachineInstr &MI) {
182   switch (MI.getOpcode()) {
183   case AMDGPU::S_MOV_B64_term:
184   case AMDGPU::S_MOV_B32_term: {
185     MI.setDesc(TII.get(AMDGPU::COPY));
186     return true;
187   }
188   case AMDGPU::S_XOR_B64_term: {
189     // This is only a terminator to get the correct spill code placement during
190     // register allocation.
191     MI.setDesc(TII.get(AMDGPU::S_XOR_B64));
192     return true;
193   }
194   case AMDGPU::S_XOR_B32_term: {
195     // This is only a terminator to get the correct spill code placement during
196     // register allocation.
197     MI.setDesc(TII.get(AMDGPU::S_XOR_B32));
198     return true;
199   }
200   case AMDGPU::S_OR_B32_term: {
201     // This is only a terminator to get the correct spill code placement during
202     // register allocation.
203     MI.setDesc(TII.get(AMDGPU::S_OR_B32));
204     return true;
205   }
206   case AMDGPU::S_ANDN2_B64_term: {
207     // This is only a terminator to get the correct spill code placement during
208     // register allocation.
209     MI.setDesc(TII.get(AMDGPU::S_ANDN2_B64));
210     return true;
211   }
212   case AMDGPU::S_ANDN2_B32_term: {
213     // This is only a terminator to get the correct spill code placement during
214     // register allocation.
215     MI.setDesc(TII.get(AMDGPU::S_ANDN2_B32));
216     return true;
217   }
218   default:
219     return false;
220   }
221 }
222 
223 static MachineBasicBlock::reverse_iterator fixTerminators(
224   const SIInstrInfo &TII,
225   MachineBasicBlock &MBB) {
226   MachineBasicBlock::reverse_iterator I = MBB.rbegin(), E = MBB.rend();
227   for (; I != E; ++I) {
228     if (!I->isTerminator())
229       return I;
230 
231     if (removeTerminatorBit(TII, *I))
232       return I;
233   }
234 
235   return E;
236 }
237 
238 static MachineBasicBlock::reverse_iterator findExecCopy(
239   const SIInstrInfo &TII,
240   const GCNSubtarget &ST,
241   MachineBasicBlock &MBB,
242   MachineBasicBlock::reverse_iterator I,
243   unsigned CopyToExec) {
244   const unsigned InstLimit = 25;
245 
246   auto E = MBB.rend();
247   for (unsigned N = 0; N <= InstLimit && I != E; ++I, ++N) {
248     Register CopyFromExec = isCopyFromExec(*I, ST);
249     if (CopyFromExec.isValid())
250       return I;
251   }
252 
253   return E;
254 }
255 
256 // XXX - Seems LivePhysRegs doesn't work correctly since it will incorrectly
257 // report the register as unavailable because a super-register with a lane mask
258 // is unavailable.
259 static bool isLiveOut(const MachineBasicBlock &MBB, unsigned Reg) {
260   for (MachineBasicBlock *Succ : MBB.successors()) {
261     if (Succ->isLiveIn(Reg))
262       return true;
263   }
264 
265   return false;
266 }
267 
268 bool SIOptimizeExecMasking::runOnMachineFunction(MachineFunction &MF) {
269   if (skipFunction(MF.getFunction()))
270     return false;
271 
272   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
273   const SIRegisterInfo *TRI = ST.getRegisterInfo();
274   const SIInstrInfo *TII = ST.getInstrInfo();
275   MCRegister Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
276 
277   // Optimize sequences emitted for control flow lowering. They are originally
278   // emitted as the separate operations because spill code may need to be
279   // inserted for the saved copy of exec.
280   //
281   //     x = copy exec
282   //     z = s_<op>_b64 x, y
283   //     exec = copy z
284   // =>
285   //     x = s_<op>_saveexec_b64 y
286   //
287 
288   for (MachineBasicBlock &MBB : MF) {
289     MachineBasicBlock::reverse_iterator I = fixTerminators(*TII, MBB);
290     MachineBasicBlock::reverse_iterator E = MBB.rend();
291     if (I == E)
292       continue;
293 
294     Register CopyToExec = isCopyToExec(*I, ST);
295     if (!CopyToExec.isValid())
296       continue;
297 
298     // Scan backwards to find the def.
299     auto CopyToExecInst = &*I;
300     auto CopyFromExecInst = findExecCopy(*TII, ST, MBB, I, CopyToExec);
301     if (CopyFromExecInst == E) {
302       auto PrepareExecInst = std::next(I);
303       if (PrepareExecInst == E)
304         continue;
305       // Fold exec = COPY (S_AND_B64 reg, exec) -> exec = S_AND_B64 reg, exec
306       if (CopyToExecInst->getOperand(1).isKill() &&
307           isLogicalOpOnExec(*PrepareExecInst) == CopyToExec) {
308         LLVM_DEBUG(dbgs() << "Fold exec copy: " << *PrepareExecInst);
309 
310         PrepareExecInst->getOperand(0).setReg(Exec);
311 
312         LLVM_DEBUG(dbgs() << "into: " << *PrepareExecInst << '\n');
313 
314         CopyToExecInst->eraseFromParent();
315       }
316 
317       continue;
318     }
319 
320     if (isLiveOut(MBB, CopyToExec)) {
321       // The copied register is live out and has a second use in another block.
322       LLVM_DEBUG(dbgs() << "Exec copy source register is live out\n");
323       continue;
324     }
325 
326     Register CopyFromExec = CopyFromExecInst->getOperand(0).getReg();
327     MachineInstr *SaveExecInst = nullptr;
328     SmallVector<MachineInstr *, 4> OtherUseInsts;
329 
330     for (MachineBasicBlock::iterator J
331            = std::next(CopyFromExecInst->getIterator()), JE = I->getIterator();
332          J != JE; ++J) {
333       if (SaveExecInst && J->readsRegister(Exec, TRI)) {
334         LLVM_DEBUG(dbgs() << "exec read prevents saveexec: " << *J << '\n');
335         // Make sure this is inserted after any VALU ops that may have been
336         // scheduled in between.
337         SaveExecInst = nullptr;
338         break;
339       }
340 
341       bool ReadsCopyFromExec = J->readsRegister(CopyFromExec, TRI);
342 
343       if (J->modifiesRegister(CopyToExec, TRI)) {
344         if (SaveExecInst) {
345           LLVM_DEBUG(dbgs() << "Multiple instructions modify "
346                             << printReg(CopyToExec, TRI) << '\n');
347           SaveExecInst = nullptr;
348           break;
349         }
350 
351         unsigned SaveExecOp = getSaveExecOp(J->getOpcode());
352         if (SaveExecOp == AMDGPU::INSTRUCTION_LIST_END)
353           break;
354 
355         if (ReadsCopyFromExec) {
356           SaveExecInst = &*J;
357           LLVM_DEBUG(dbgs() << "Found save exec op: " << *SaveExecInst << '\n');
358           continue;
359         } else {
360           LLVM_DEBUG(dbgs()
361                      << "Instruction does not read exec copy: " << *J << '\n');
362           break;
363         }
364       } else if (ReadsCopyFromExec && !SaveExecInst) {
365         // Make sure no other instruction is trying to use this copy, before it
366         // will be rewritten by the saveexec, i.e. hasOneUse. There may have
367         // been another use, such as an inserted spill. For example:
368         //
369         // %sgpr0_sgpr1 = COPY %exec
370         // spill %sgpr0_sgpr1
371         // %sgpr2_sgpr3 = S_AND_B64 %sgpr0_sgpr1
372         //
373         LLVM_DEBUG(dbgs() << "Found second use of save inst candidate: " << *J
374                           << '\n');
375         break;
376       }
377 
378       if (SaveExecInst && J->readsRegister(CopyToExec, TRI)) {
379         assert(SaveExecInst != &*J);
380         OtherUseInsts.push_back(&*J);
381       }
382     }
383 
384     if (!SaveExecInst)
385       continue;
386 
387     LLVM_DEBUG(dbgs() << "Insert save exec op: " << *SaveExecInst << '\n');
388 
389     MachineOperand &Src0 = SaveExecInst->getOperand(1);
390     MachineOperand &Src1 = SaveExecInst->getOperand(2);
391 
392     MachineOperand *OtherOp = nullptr;
393 
394     if (Src0.isReg() && Src0.getReg() == CopyFromExec) {
395       OtherOp = &Src1;
396     } else if (Src1.isReg() && Src1.getReg() == CopyFromExec) {
397       if (!SaveExecInst->isCommutable())
398         break;
399 
400       OtherOp = &Src0;
401     } else
402       llvm_unreachable("unexpected");
403 
404     CopyFromExecInst->eraseFromParent();
405 
406     auto InsPt = SaveExecInst->getIterator();
407     const DebugLoc &DL = SaveExecInst->getDebugLoc();
408 
409     BuildMI(MBB, InsPt, DL, TII->get(getSaveExecOp(SaveExecInst->getOpcode())),
410             CopyFromExec)
411       .addReg(OtherOp->getReg());
412     SaveExecInst->eraseFromParent();
413 
414     CopyToExecInst->eraseFromParent();
415 
416     for (MachineInstr *OtherInst : OtherUseInsts) {
417       OtherInst->substituteRegister(CopyToExec, Exec,
418                                     AMDGPU::NoSubRegister, *TRI);
419     }
420   }
421 
422   return true;
423 
424 }
425