1//===-- SIRegisterInfo.td - SI Register defs ---------------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// Subregister declarations 11//===----------------------------------------------------------------------===// 12 13class Indexes<int N> { 14 list<int> all = [0, 1, 2, 3, 4, 5, 6 , 7, 15 8, 9, 10, 11, 12, 13, 14, 15, 16 16, 17, 18, 19, 20, 21, 22, 23, 17 24, 25, 26, 27, 28, 29, 30, 31]; 18 19 // Returns list of indexes [0..N) 20 list<int> slice = !filter(i, all, !lt(i, N)); 21} 22 23let Namespace = "AMDGPU" in { 24 25def lo16 : SubRegIndex<16, 0>; 26def hi16 : SubRegIndex<16, 16>; 27 28foreach Index = 0...31 in { 29 def sub#Index : SubRegIndex<32, !shl(Index, 5)>; 30} 31 32foreach Index = 1...31 in { 33 def sub#Index#_lo16 : ComposedSubRegIndex<!cast<SubRegIndex>(sub#Index), lo16>; 34 def sub#Index#_hi16 : ComposedSubRegIndex<!cast<SubRegIndex>(sub#Index), hi16>; 35} 36 37foreach Size = {2...6,8,16} in { 38 foreach Index = Indexes<!sub(33, Size)>.slice in { 39 def !interleave(!foreach(cur, Indexes<Size>.slice, "sub"#!add(cur, Index)), 40 "_") : 41 SubRegIndex<!mul(Size, 32), !shl(Index, 5)> { 42 let CoveringSubRegIndices = 43 !foreach(cur, Indexes<Size>.slice, 44 !cast<SubRegIndex>(sub#!add(cur, Index))); 45 } 46 } 47} 48 49} 50 51//===----------------------------------------------------------------------===// 52// Helpers 53//===----------------------------------------------------------------------===// 54 55class getSubRegs<int size> { 56 list<SubRegIndex> ret2 = [sub0, sub1]; 57 list<SubRegIndex> ret3 = [sub0, sub1, sub2]; 58 list<SubRegIndex> ret4 = [sub0, sub1, sub2, sub3]; 59 list<SubRegIndex> ret5 = [sub0, sub1, sub2, sub3, sub4]; 60 list<SubRegIndex> ret6 = [sub0, sub1, sub2, sub3, sub4, sub5]; 61 list<SubRegIndex> ret7 = [sub0, sub1, sub2, sub3, sub4, sub5, sub6]; 62 list<SubRegIndex> ret8 = [sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7]; 63 list<SubRegIndex> ret16 = [sub0, sub1, sub2, sub3, 64 sub4, sub5, sub6, sub7, 65 sub8, sub9, sub10, sub11, 66 sub12, sub13, sub14, sub15]; 67 list<SubRegIndex> ret32 = [sub0, sub1, sub2, sub3, 68 sub4, sub5, sub6, sub7, 69 sub8, sub9, sub10, sub11, 70 sub12, sub13, sub14, sub15, 71 sub16, sub17, sub18, sub19, 72 sub20, sub21, sub22, sub23, 73 sub24, sub25, sub26, sub27, 74 sub28, sub29, sub30, sub31]; 75 76 list<SubRegIndex> ret = !if(!eq(size, 2), ret2, 77 !if(!eq(size, 3), ret3, 78 !if(!eq(size, 4), ret4, 79 !if(!eq(size, 5), ret5, 80 !if(!eq(size, 6), ret6, 81 !if(!eq(size, 7), ret7, 82 !if(!eq(size, 8), ret8, 83 !if(!eq(size, 16), ret16, 84 ret32)))))))); 85} 86 87// Generates list of sequential register tuple names. 88// E.g. RegSeq<3,2,2,"s">.ret -> [ "s[0:1]", "s[2:3]" ] 89class RegSeqNames<int last_reg, int stride, int size, string prefix, 90 int start = 0> { 91 int next = !add(start, stride); 92 int end_reg = !add(start, size, -1); 93 list<string> ret = 94 !if(!le(end_reg, last_reg), 95 !listconcat([prefix # "[" # start # ":" # end_reg # "]"], 96 RegSeqNames<last_reg, stride, size, prefix, next>.ret), 97 []); 98} 99 100// Generates list of dags for register tupless. 101class RegSeqDags<RegisterClass RC, int last_reg, int stride, int size, 102 int start = 0> { 103 dag trunc_rc = (trunc RC, 104 !if(!and(!eq(stride, 1), !eq(start, 0)), 105 !sub(!add(last_reg, 2), size), 106 !add(last_reg, 1))); 107 list<dag> ret = 108 !if(!lt(start, size), 109 !listconcat([(add (decimate (shl trunc_rc, start), stride))], 110 RegSeqDags<RC, last_reg, stride, size, !add(start, 1)>.ret), 111 []); 112} 113 114class SIRegisterTuples<list<SubRegIndex> Indices, RegisterClass RC, 115 int last_reg, int stride, int size, string prefix> : 116 RegisterTuples<Indices, 117 RegSeqDags<RC, last_reg, stride, size>.ret, 118 RegSeqNames<last_reg, stride, size, prefix>.ret>; 119 120//===----------------------------------------------------------------------===// 121// Declarations that describe the SI registers 122//===----------------------------------------------------------------------===// 123class SIReg <string n, bits<16> regIdx = 0> : 124 Register<n> { 125 let Namespace = "AMDGPU"; 126 let HWEncoding = regIdx; 127} 128 129class SIRegWithSubRegs <string n, list<Register> subregs, bits<16> regIdx> : 130 RegisterWithSubRegs<n, subregs> { 131} 132 133multiclass SIRegLoHi16 <string n, bits<16> regIdx, bit ArtificialHigh = 1, 134 bit HWEncodingHigh = 0> { 135 // There is no special encoding for 16 bit subregs, these are not real 136 // registers but rather operands for instructions preserving other 16 bits 137 // of the result or reading just 16 bits of a 32 bit VGPR. 138 // It is encoded as a corresponding 32 bit register. 139 // Non-VGPR register classes use it as we need to have matching subregisters 140 // to move instructions and data between ALUs. 141 def _LO16 : SIReg<n#".l", regIdx> { 142 let HWEncoding{8} = HWEncodingHigh; 143 } 144 def _HI16 : SIReg<!if(ArtificialHigh, "", n#".h"), regIdx> { 145 let isArtificial = ArtificialHigh; 146 let HWEncoding{8} = HWEncodingHigh; 147 } 148 def "" : RegisterWithSubRegs<n, [!cast<Register>(NAME#"_LO16"), 149 !cast<Register>(NAME#"_HI16")]> { 150 let Namespace = "AMDGPU"; 151 let SubRegIndices = [lo16, hi16]; 152 let CoveredBySubRegs = !not(ArtificialHigh); 153 let HWEncoding = regIdx; 154 let HWEncoding{8} = HWEncodingHigh; 155 } 156} 157 158// Special Registers 159defm VCC_LO : SIRegLoHi16<"vcc_lo", 106>; 160defm VCC_HI : SIRegLoHi16<"vcc_hi", 107>; 161 162// Pseudo-registers: Used as placeholders during isel and immediately 163// replaced, never seeing the verifier. 164def PRIVATE_RSRC_REG : SIReg<"private_rsrc", 0>; 165def FP_REG : SIReg<"fp", 0>; 166def SP_REG : SIReg<"sp", 0>; 167 168// Pseudo-register to represent the program-counter DWARF register. 169def PC_REG : SIReg<"pc", 0>, DwarfRegNum<[16, 16]> { 170 // There is no physical register corresponding to a "program counter", but 171 // we need to encode the concept in debug information in order to represent 172 // things like the return value in unwind information. 173 let isArtificial = 1; 174} 175 176// VCC for 64-bit instructions 177def VCC : RegisterWithSubRegs<"vcc", [VCC_LO, VCC_HI]> { 178 let Namespace = "AMDGPU"; 179 let SubRegIndices = [sub0, sub1]; 180 let HWEncoding = 106; 181} 182 183defm EXEC_LO : SIRegLoHi16<"exec_lo", 126>, DwarfRegNum<[1, 1]>; 184defm EXEC_HI : SIRegLoHi16<"exec_hi", 127>; 185 186def EXEC : RegisterWithSubRegs<"exec", [EXEC_LO, EXEC_HI]>, DwarfRegNum<[17, 1]> { 187 let Namespace = "AMDGPU"; 188 let SubRegIndices = [sub0, sub1]; 189 let HWEncoding = 126; 190} 191 192// 32-bit real registers, for MC only. 193// May be used with both 32-bit and 64-bit operands. 194defm SRC_VCCZ : SIRegLoHi16<"src_vccz", 251>; 195defm SRC_EXECZ : SIRegLoHi16<"src_execz", 252>; 196defm SRC_SCC : SIRegLoHi16<"src_scc", 253>; 197 198// 1-bit pseudo register, for codegen only. 199// Should never be emitted. 200def SCC : SIReg<"scc">; 201 202defm M0 : SIRegLoHi16 <"m0", 124>; 203defm SGPR_NULL : SIRegLoHi16 <"null", 125>; 204 205defm SRC_SHARED_BASE : SIRegLoHi16<"src_shared_base", 235>; 206defm SRC_SHARED_LIMIT : SIRegLoHi16<"src_shared_limit", 236>; 207defm SRC_PRIVATE_BASE : SIRegLoHi16<"src_private_base", 237>; 208defm SRC_PRIVATE_LIMIT : SIRegLoHi16<"src_private_limit", 238>; 209defm SRC_POPS_EXITING_WAVE_ID : SIRegLoHi16<"src_pops_exiting_wave_id", 239>; 210 211// Not addressable 212def MODE : SIReg <"mode", 0>; 213 214def LDS_DIRECT : SIReg <"src_lds_direct", 254> { 215 // There is no physical register corresponding to this. This is an 216 // encoding value in a source field, which will ultimately trigger a 217 // read from m0. 218 let isArtificial = 1; 219} 220 221defm XNACK_MASK_LO : SIRegLoHi16<"xnack_mask_lo", 104>; 222defm XNACK_MASK_HI : SIRegLoHi16<"xnack_mask_hi", 105>; 223 224def XNACK_MASK : 225 RegisterWithSubRegs<"xnack_mask", [XNACK_MASK_LO, XNACK_MASK_HI]> { 226 let Namespace = "AMDGPU"; 227 let SubRegIndices = [sub0, sub1]; 228 let HWEncoding = 104; 229} 230 231// Trap handler registers 232defm TBA_LO : SIRegLoHi16<"tba_lo", 108>; 233defm TBA_HI : SIRegLoHi16<"tba_hi", 109>; 234 235def TBA : RegisterWithSubRegs<"tba", [TBA_LO, TBA_HI]> { 236 let Namespace = "AMDGPU"; 237 let SubRegIndices = [sub0, sub1]; 238 let HWEncoding = 108; 239} 240 241defm TMA_LO : SIRegLoHi16<"tma_lo", 110>; 242defm TMA_HI : SIRegLoHi16<"tma_hi", 111>; 243 244def TMA : RegisterWithSubRegs<"tma", [TMA_LO, TMA_HI]> { 245 let Namespace = "AMDGPU"; 246 let SubRegIndices = [sub0, sub1]; 247 let HWEncoding = 110; 248} 249 250foreach Index = 0...15 in { 251 defm TTMP#Index#_vi : SIRegLoHi16<"ttmp"#Index, !add(112, Index)>; 252 defm TTMP#Index#_gfx9plus : SIRegLoHi16<"ttmp"#Index, !add(108, Index)>; 253 defm TTMP#Index : SIRegLoHi16<"ttmp"#Index, 0>; 254} 255 256multiclass FLAT_SCR_LOHI_m <string n, bits<16> ci_e, bits<16> vi_e> { 257 defm _ci : SIRegLoHi16<n, ci_e>; 258 defm _vi : SIRegLoHi16<n, vi_e>; 259 defm "" : SIRegLoHi16<n, 0>; 260} 261 262class FlatReg <Register lo, Register hi, bits<16> encoding> : 263 RegisterWithSubRegs<"flat_scratch", [lo, hi]> { 264 let Namespace = "AMDGPU"; 265 let SubRegIndices = [sub0, sub1]; 266 let HWEncoding = encoding; 267} 268 269defm FLAT_SCR_LO : FLAT_SCR_LOHI_m<"flat_scratch_lo", 104, 102>; // Offset in units of 256-bytes. 270defm FLAT_SCR_HI : FLAT_SCR_LOHI_m<"flat_scratch_hi", 105, 103>; // Size is the per-thread scratch size, in bytes. 271 272def FLAT_SCR_ci : FlatReg<FLAT_SCR_LO_ci, FLAT_SCR_HI_ci, 104>; 273def FLAT_SCR_vi : FlatReg<FLAT_SCR_LO_vi, FLAT_SCR_HI_vi, 102>; 274def FLAT_SCR : FlatReg<FLAT_SCR_LO, FLAT_SCR_HI, 0>; 275 276// SGPR registers 277foreach Index = 0...105 in { 278 defm SGPR#Index : 279 SIRegLoHi16 <"s"#Index, Index>, 280 DwarfRegNum<[!if(!le(Index, 63), !add(Index, 32), !add(Index, 1024)), 281 !if(!le(Index, 63), !add(Index, 32), !add(Index, 1024))]>; 282} 283 284// VGPR registers 285foreach Index = 0...255 in { 286 defm VGPR#Index : 287 SIRegLoHi16 <"v"#Index, Index, 0, 1>, 288 DwarfRegNum<[!add(Index, 2560), !add(Index, 1536)]>; 289} 290 291// AccVGPR registers 292foreach Index = 0...255 in { 293 defm AGPR#Index : 294 SIRegLoHi16 <"a"#Index, Index, 1, 1>, 295 DwarfRegNum<[!add(Index, 3072), !add(Index, 2048)]>; 296} 297 298//===----------------------------------------------------------------------===// 299// Groupings using register classes and tuples 300//===----------------------------------------------------------------------===// 301 302def SCC_CLASS : RegisterClass<"AMDGPU", [i1], 1, (add SCC)> { 303 let CopyCost = -1; 304 let isAllocatable = 0; 305} 306 307def M0_CLASS : RegisterClass<"AMDGPU", [i32], 32, (add M0)> { 308 let CopyCost = 1; 309 let isAllocatable = 0; 310} 311 312def M0_CLASS_LO16 : RegisterClass<"AMDGPU", [i16, f16], 16, (add M0_LO16)> { 313 let CopyCost = 1; 314 let Size = 16; 315 let isAllocatable = 0; 316} 317 318// TODO: Do we need to set DwarfRegAlias on register tuples? 319 320def SGPR_LO16 : RegisterClass<"AMDGPU", [i16, f16], 16, 321 (add (sequence "SGPR%u_LO16", 0, 105))> { 322 let AllocationPriority = 9; 323 let Size = 16; 324 let GeneratePressureSet = 0; 325} 326 327def SGPR_HI16 : RegisterClass<"AMDGPU", [i16, f16], 16, 328 (add (sequence "SGPR%u_HI16", 0, 105))> { 329 let isAllocatable = 0; 330 let Size = 16; 331 let GeneratePressureSet = 0; 332} 333 334// SGPR 32-bit registers 335def SGPR_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, 336 (add (sequence "SGPR%u", 0, 105))> { 337 // Give all SGPR classes higher priority than VGPR classes, because 338 // we want to spill SGPRs to VGPRs. 339 let AllocationPriority = 9; 340 let GeneratePressureSet = 0; 341} 342 343// SGPR 64-bit registers 344def SGPR_64Regs : SIRegisterTuples<getSubRegs<2>.ret, SGPR_32, 105, 2, 2, "s">; 345 346// SGPR 96-bit registers. No operations use these, but for symmetry with 96-bit VGPRs. 347def SGPR_96Regs : SIRegisterTuples<getSubRegs<3>.ret, SGPR_32, 105, 3, 3, "s">; 348 349// SGPR 128-bit registers 350def SGPR_128Regs : SIRegisterTuples<getSubRegs<4>.ret, SGPR_32, 105, 4, 4, "s">; 351 352// SGPR 160-bit registers. No operations use these, but for symmetry with 160-bit VGPRs. 353def SGPR_160Regs : SIRegisterTuples<getSubRegs<5>.ret, SGPR_32, 105, 4, 5, "s">; 354 355// SGPR 192-bit registers. No operations use these, but for symmetry with 192-bit VGPRs. 356def SGPR_192Regs : SIRegisterTuples<getSubRegs<6>.ret, SGPR_32, 105, 4, 6, "s">; 357 358// SGPR 224-bit registers. No operations use these, but for symmetry with 224-bit VGPRs. 359def SGPR_224Regs : SIRegisterTuples<getSubRegs<7>.ret, SGPR_32, 105, 4, 7, "s">; 360 361// SGPR 256-bit registers 362def SGPR_256Regs : SIRegisterTuples<getSubRegs<8>.ret, SGPR_32, 105, 4, 8, "s">; 363 364// SGPR 512-bit registers 365def SGPR_512Regs : SIRegisterTuples<getSubRegs<16>.ret, SGPR_32, 105, 4, 16, "s">; 366 367// SGPR 1024-bit registers 368def SGPR_1024Regs : SIRegisterTuples<getSubRegs<32>.ret, SGPR_32, 105, 4, 32, "s">; 369 370// Trap handler TMP 32-bit registers 371def TTMP_32 : RegisterClass<"AMDGPU", [i32, f32, v2i16, v2f16], 32, 372 (add (sequence "TTMP%u", 0, 15))> { 373 let isAllocatable = 0; 374} 375 376// Trap handler TMP 16-bit registers 377def TTMP_LO16 : RegisterClass<"AMDGPU", [i16, f16], 16, 378 (add (sequence "TTMP%u_LO16", 0, 15))> { 379 let Size = 16; 380 let isAllocatable = 0; 381} 382 383// Trap handler TMP 64-bit registers 384def TTMP_64Regs : SIRegisterTuples<getSubRegs<2>.ret, TTMP_32, 15, 2, 2, "ttmp">; 385 386// Trap handler TMP 96-bit registers 387def TTMP_96Regs : SIRegisterTuples<getSubRegs<3>.ret, TTMP_32, 15, 3, 3, "ttmp">; 388 389// Trap handler TMP 128-bit registers 390def TTMP_128Regs : SIRegisterTuples<getSubRegs<4>.ret, TTMP_32, 15, 4, 4, "ttmp">; 391 392// Trap handler TMP 160-bit registers 393def TTMP_160Regs : SIRegisterTuples<getSubRegs<5>.ret, TTMP_32, 15, 4, 5, "ttmp">; 394 395// Trap handler TMP 192-bit registers 396def TTMP_192Regs : SIRegisterTuples<getSubRegs<6>.ret, TTMP_32, 15, 4, 6, "ttmp">; 397 398// Trap handler TMP 224-bit registers 399def TTMP_224Regs : SIRegisterTuples<getSubRegs<7>.ret, TTMP_32, 15, 4, 7, "ttmp">; 400 401// Trap handler TMP 256-bit registers 402def TTMP_256Regs : SIRegisterTuples<getSubRegs<8>.ret, TTMP_32, 15, 4, 8, "ttmp">; 403 404// Trap handler TMP 512-bit registers 405def TTMP_512Regs : SIRegisterTuples<getSubRegs<16>.ret, TTMP_32, 15, 4, 16, "ttmp">; 406 407class TmpRegTuplesBase<int index, int size, 408 list<Register> subRegs, 409 list<SubRegIndex> indices = getSubRegs<size>.ret, 410 int index1 = !add(index, size, -1), 411 string name = "ttmp["#index#":"#index1#"]"> : 412 RegisterWithSubRegs<name, subRegs> { 413 let HWEncoding = subRegs[0].HWEncoding; 414 let SubRegIndices = indices; 415} 416 417class TmpRegTuples<string tgt, 418 int size, 419 int index0, 420 int index1 = !add(index0, 1), 421 int index2 = !add(index0, !if(!eq(size, 2), 1, 2)), 422 int index3 = !add(index0, !if(!eq(size, 2), 1, 3)), 423 int index4 = !add(index0, !if(!eq(size, 8), 4, 1)), 424 int index5 = !add(index0, !if(!eq(size, 8), 5, 1)), 425 int index6 = !add(index0, !if(!eq(size, 8), 6, 1)), 426 int index7 = !add(index0, !if(!eq(size, 8), 7, 1)), 427 Register r0 = !cast<Register>("TTMP"#index0#tgt), 428 Register r1 = !cast<Register>("TTMP"#index1#tgt), 429 Register r2 = !cast<Register>("TTMP"#index2#tgt), 430 Register r3 = !cast<Register>("TTMP"#index3#tgt), 431 Register r4 = !cast<Register>("TTMP"#index4#tgt), 432 Register r5 = !cast<Register>("TTMP"#index5#tgt), 433 Register r6 = !cast<Register>("TTMP"#index6#tgt), 434 Register r7 = !cast<Register>("TTMP"#index7#tgt)> : 435 TmpRegTuplesBase<index0, size, 436 !if(!eq(size, 2), [r0, r1], 437 !if(!eq(size, 4), [r0, r1, r2, r3], 438 [r0, r1, r2, r3, r4, r5, r6, r7])), 439 getSubRegs<size>.ret>; 440 441foreach Index = {0, 2, 4, 6, 8, 10, 12, 14} in { 442 def TTMP#Index#_TTMP#!add(Index,1)#_vi : TmpRegTuples<"_vi", 2, Index>; 443 def TTMP#Index#_TTMP#!add(Index,1)#_gfx9plus : TmpRegTuples<"_gfx9plus", 2, Index>; 444} 445 446foreach Index = {0, 4, 8, 12} in { 447 def TTMP#Index#_TTMP#!add(Index,1)# 448 _TTMP#!add(Index,2)# 449 _TTMP#!add(Index,3)#_vi : TmpRegTuples<"_vi", 4, Index>; 450 def TTMP#Index#_TTMP#!add(Index,1)# 451 _TTMP#!add(Index,2)# 452 _TTMP#!add(Index,3)#_gfx9plus : TmpRegTuples<"_gfx9plus", 4, Index>; 453} 454 455foreach Index = {0, 4, 8} in { 456 def TTMP#Index#_TTMP#!add(Index,1)# 457 _TTMP#!add(Index,2)# 458 _TTMP#!add(Index,3)# 459 _TTMP#!add(Index,4)# 460 _TTMP#!add(Index,5)# 461 _TTMP#!add(Index,6)# 462 _TTMP#!add(Index,7)#_vi : TmpRegTuples<"_vi", 8, Index>; 463 def TTMP#Index#_TTMP#!add(Index,1)# 464 _TTMP#!add(Index,2)# 465 _TTMP#!add(Index,3)# 466 _TTMP#!add(Index,4)# 467 _TTMP#!add(Index,5)# 468 _TTMP#!add(Index,6)# 469 _TTMP#!add(Index,7)#_gfx9plus : TmpRegTuples<"_gfx9plus", 8, Index>; 470} 471 472def TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15_vi : 473 TmpRegTuplesBase<0, 16, 474 [TTMP0_vi, TTMP1_vi, TTMP2_vi, TTMP3_vi, 475 TTMP4_vi, TTMP5_vi, TTMP6_vi, TTMP7_vi, 476 TTMP8_vi, TTMP9_vi, TTMP10_vi, TTMP11_vi, 477 TTMP12_vi, TTMP13_vi, TTMP14_vi, TTMP15_vi]>; 478 479def TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15_gfx9plus : 480 TmpRegTuplesBase<0, 16, 481 [TTMP0_gfx9plus, TTMP1_gfx9plus, TTMP2_gfx9plus, TTMP3_gfx9plus, 482 TTMP4_gfx9plus, TTMP5_gfx9plus, TTMP6_gfx9plus, TTMP7_gfx9plus, 483 TTMP8_gfx9plus, TTMP9_gfx9plus, TTMP10_gfx9plus, TTMP11_gfx9plus, 484 TTMP12_gfx9plus, TTMP13_gfx9plus, TTMP14_gfx9plus, TTMP15_gfx9plus]>; 485 486class RegisterTypes<list<ValueType> reg_types> { 487 list<ValueType> types = reg_types; 488} 489 490def Reg16Types : RegisterTypes<[i16, f16]>; 491def Reg32Types : RegisterTypes<[i32, f32, v2i16, v2f16, p2, p3, p5, p6]>; 492 493def VGPR_LO16 : RegisterClass<"AMDGPU", Reg16Types.types, 16, 494 (add (sequence "VGPR%u_LO16", 0, 255))> { 495 let AllocationPriority = 1; 496 let Size = 16; 497 let GeneratePressureSet = 0; 498} 499 500def VGPR_HI16 : RegisterClass<"AMDGPU", Reg16Types.types, 16, 501 (add (sequence "VGPR%u_HI16", 0, 255))> { 502 let AllocationPriority = 1; 503 let Size = 16; 504 let GeneratePressureSet = 0; 505} 506 507// VGPR 32-bit registers 508// i16/f16 only on VI+ 509def VGPR_32 : RegisterClass<"AMDGPU", !listconcat(Reg32Types.types, Reg16Types.types), 32, 510 (add (sequence "VGPR%u", 0, 255))> { 511 let AllocationPriority = 1; 512 let Size = 32; 513 let Weight = 1; 514} 515 516// VGPR 64-bit registers 517def VGPR_64 : SIRegisterTuples<getSubRegs<2>.ret, VGPR_32, 255, 1, 2, "v">; 518 519// VGPR 96-bit registers 520def VGPR_96 : SIRegisterTuples<getSubRegs<3>.ret, VGPR_32, 255, 1, 3, "v">; 521 522// VGPR 128-bit registers 523def VGPR_128 : SIRegisterTuples<getSubRegs<4>.ret, VGPR_32, 255, 1, 4, "v">; 524 525// VGPR 160-bit registers 526def VGPR_160 : SIRegisterTuples<getSubRegs<5>.ret, VGPR_32, 255, 1, 5, "v">; 527 528// VGPR 192-bit registers 529def VGPR_192 : SIRegisterTuples<getSubRegs<6>.ret, VGPR_32, 255, 1, 6, "v">; 530 531// VGPR 224-bit registers 532def VGPR_224 : SIRegisterTuples<getSubRegs<7>.ret, VGPR_32, 255, 1, 7, "v">; 533 534// VGPR 256-bit registers 535def VGPR_256 : SIRegisterTuples<getSubRegs<8>.ret, VGPR_32, 255, 1, 8, "v">; 536 537// VGPR 512-bit registers 538def VGPR_512 : SIRegisterTuples<getSubRegs<16>.ret, VGPR_32, 255, 1, 16, "v">; 539 540// VGPR 1024-bit registers 541def VGPR_1024 : SIRegisterTuples<getSubRegs<32>.ret, VGPR_32, 255, 1, 32, "v">; 542 543def AGPR_LO16 : RegisterClass<"AMDGPU", Reg16Types.types, 16, 544 (add (sequence "AGPR%u_LO16", 0, 255))> { 545 let isAllocatable = 0; 546 let Size = 16; 547 let GeneratePressureSet = 0; 548} 549 550// AccVGPR 32-bit registers 551def AGPR_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, 552 (add (sequence "AGPR%u", 0, 255))> { 553 let AllocationPriority = 1; 554 let Size = 32; 555 let Weight = 1; 556} 557 558// AGPR 64-bit registers 559def AGPR_64 : SIRegisterTuples<getSubRegs<2>.ret, AGPR_32, 255, 1, 2, "a">; 560 561// AGPR 96-bit registers 562def AGPR_96 : SIRegisterTuples<getSubRegs<3>.ret, AGPR_32, 255, 1, 3, "a">; 563 564// AGPR 128-bit registers 565def AGPR_128 : SIRegisterTuples<getSubRegs<4>.ret, AGPR_32, 255, 1, 4, "a">; 566 567// AGPR 160-bit registers 568def AGPR_160 : SIRegisterTuples<getSubRegs<5>.ret, AGPR_32, 255, 1, 5, "a">; 569 570// AGPR 192-bit registers 571def AGPR_192 : SIRegisterTuples<getSubRegs<6>.ret, AGPR_32, 255, 1, 6, "a">; 572 573// AGPR 224-bit registers 574def AGPR_224 : SIRegisterTuples<getSubRegs<7>.ret, AGPR_32, 255, 1, 7, "a">; 575 576// AGPR 256-bit registers 577def AGPR_256 : SIRegisterTuples<getSubRegs<8>.ret, AGPR_32, 255, 1, 8, "a">; 578 579// AGPR 512-bit registers 580def AGPR_512 : SIRegisterTuples<getSubRegs<16>.ret, AGPR_32, 255, 1, 16, "a">; 581 582// AGPR 1024-bit registers 583def AGPR_1024 : SIRegisterTuples<getSubRegs<32>.ret, AGPR_32, 255, 1, 32, "a">; 584 585//===----------------------------------------------------------------------===// 586// Register classes used as source and destination 587//===----------------------------------------------------------------------===// 588 589def Pseudo_SReg_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, 590 (add FP_REG, SP_REG)> { 591 let isAllocatable = 0; 592 let CopyCost = -1; 593} 594 595def Pseudo_SReg_128 : RegisterClass<"AMDGPU", [v4i32, v2i64, v2f64], 32, 596 (add PRIVATE_RSRC_REG)> { 597 let isAllocatable = 0; 598 let CopyCost = -1; 599} 600 601def LDS_DIRECT_CLASS : RegisterClass<"AMDGPU", [i32], 32, 602 (add LDS_DIRECT)> { 603 let isAllocatable = 0; 604 let CopyCost = -1; 605} 606 607let GeneratePressureSet = 0 in { 608// Subset of SReg_32 without M0 for SMRD instructions and alike. 609// See comments in SIInstructions.td for more info. 610def SReg_32_XM0_XEXEC : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32, 611 (add SGPR_32, VCC_LO, VCC_HI, FLAT_SCR_LO, FLAT_SCR_HI, XNACK_MASK_LO, XNACK_MASK_HI, 612 SGPR_NULL, TTMP_32, TMA_LO, TMA_HI, TBA_LO, TBA_HI, SRC_SHARED_BASE, SRC_SHARED_LIMIT, 613 SRC_PRIVATE_BASE, SRC_PRIVATE_LIMIT, SRC_POPS_EXITING_WAVE_ID, 614 SRC_VCCZ, SRC_EXECZ, SRC_SCC)> { 615 let AllocationPriority = 10; 616} 617 618def SReg_LO16_XM0_XEXEC : RegisterClass<"AMDGPU", [i16, f16], 16, 619 (add SGPR_LO16, VCC_LO_LO16, VCC_HI_LO16, FLAT_SCR_LO_LO16, FLAT_SCR_HI_LO16, 620 XNACK_MASK_LO_LO16, XNACK_MASK_HI_LO16, SGPR_NULL_LO16, TTMP_LO16, TMA_LO_LO16, 621 TMA_HI_LO16, TBA_LO_LO16, TBA_HI_LO16, SRC_SHARED_BASE_LO16, 622 SRC_SHARED_LIMIT_LO16, SRC_PRIVATE_BASE_LO16, SRC_PRIVATE_LIMIT_LO16, 623 SRC_POPS_EXITING_WAVE_ID_LO16, SRC_VCCZ_LO16, SRC_EXECZ_LO16, SRC_SCC_LO16)> { 624 let Size = 16; 625 let AllocationPriority = 10; 626} 627 628def SReg_32_XEXEC_HI : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32, 629 (add SReg_32_XM0_XEXEC, EXEC_LO, M0_CLASS)> { 630 let AllocationPriority = 10; 631} 632 633def SReg_LO16_XEXEC_HI : RegisterClass<"AMDGPU", [i16, f16], 16, 634 (add SReg_LO16_XM0_XEXEC, EXEC_LO_LO16, M0_CLASS_LO16)> { 635 let Size = 16; 636 let AllocationPriority = 10; 637} 638 639def SReg_32_XM0 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32, 640 (add SReg_32_XM0_XEXEC, EXEC_LO, EXEC_HI)> { 641 let AllocationPriority = 10; 642} 643 644def SReg_LO16_XM0 : RegisterClass<"AMDGPU", [i16, f16], 16, 645 (add SReg_LO16_XM0_XEXEC, EXEC_LO_LO16, EXEC_HI_LO16)> { 646 let Size = 16; 647 let AllocationPriority = 10; 648} 649 650def SReg_LO16 : RegisterClass<"AMDGPU", [i16, f16], 16, 651 (add SGPR_LO16, SReg_LO16_XM0, M0_CLASS_LO16, EXEC_LO_LO16, EXEC_HI_LO16, SReg_LO16_XEXEC_HI)> { 652 let Size = 16; 653 let AllocationPriority = 10; 654} 655} // End GeneratePressureSet = 0 656 657// Register class for all scalar registers (SGPRs + Special Registers) 658def SReg_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32, 659 (add SReg_32_XM0, M0_CLASS, EXEC_LO, EXEC_HI, SReg_32_XEXEC_HI)> { 660 let AllocationPriority = 10; 661} 662 663let GeneratePressureSet = 0 in { 664def SRegOrLds_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, 665 (add SReg_32, LDS_DIRECT_CLASS)> { 666 let isAllocatable = 0; 667} 668 669def SGPR_64 : RegisterClass<"AMDGPU", [v2i32, i64, v2f32, f64, v4i16, v4f16], 32, 670 (add SGPR_64Regs)> { 671 let CopyCost = 1; 672 let AllocationPriority = 11; 673} 674 675// CCR (call clobbered registers) SGPR 64-bit registers 676def CCR_SGPR_64 : RegisterClass<"AMDGPU", SGPR_64.RegTypes, 32, 677 (add (trunc SGPR_64, 16))> { 678 let CopyCost = SGPR_64.CopyCost; 679 let AllocationPriority = SGPR_64.AllocationPriority; 680} 681 682def TTMP_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64, v4i16, v4f16], 32, 683 (add TTMP_64Regs)> { 684 let isAllocatable = 0; 685} 686 687def SReg_64_XEXEC : RegisterClass<"AMDGPU", [v2i32, i64, v2f32, f64, i1, v4i16, v4f16], 32, 688 (add SGPR_64, VCC, FLAT_SCR, XNACK_MASK, TTMP_64, TBA, TMA)> { 689 let CopyCost = 1; 690 let AllocationPriority = 13; 691} 692 693def SReg_64 : RegisterClass<"AMDGPU", [v2i32, i64, v2f32, f64, i1, v4i16, v4f16], 32, 694 (add SReg_64_XEXEC, EXEC)> { 695 let CopyCost = 1; 696 let AllocationPriority = 13; 697} 698 699def SReg_1_XEXEC : RegisterClass<"AMDGPU", [i1], 32, 700 (add SReg_64_XEXEC, SReg_32_XM0_XEXEC)> { 701 let CopyCost = 1; 702 let isAllocatable = 0; 703} 704 705def SReg_1 : RegisterClass<"AMDGPU", [i1], 32, 706 (add SReg_1_XEXEC, EXEC, EXEC_LO)> { 707 let CopyCost = 1; 708 let isAllocatable = 0; 709} 710 711multiclass SRegClass<int numRegs, int priority, 712 list<ValueType> regTypes, 713 SIRegisterTuples regList, 714 SIRegisterTuples ttmpList = regList, 715 int copyCost = !sra(!add(numRegs, 1), 1)> { 716 defvar hasTTMP = !ne(regList, ttmpList); 717 defvar suffix = !cast<string>(!mul(numRegs, 32)); 718 defvar sgprName = !strconcat("SGPR_", suffix); 719 defvar ttmpName = !strconcat("TTMP_", suffix); 720 721 let AllocationPriority = priority, CopyCost = copyCost in { 722 def "" # sgprName : RegisterClass<"AMDGPU", regTypes, 32, (add regList)> { 723 } 724 725 if hasTTMP then { 726 def "" # ttmpName : RegisterClass<"AMDGPU", regTypes, 32, (add ttmpList)> { 727 let isAllocatable = 0; 728 } 729 } 730 731 def SReg_ # suffix : 732 RegisterClass<"AMDGPU", regTypes, 32, 733 !con(!dag(add, [!cast<RegisterClass>(sgprName)], ["sgpr"]), 734 !if(hasTTMP, 735 !dag(add, [!cast<RegisterClass>(ttmpName)], ["ttmp"]), 736 (add)))> { 737 let isAllocatable = 0; 738 } 739 } 740} 741 742defm "" : SRegClass<3, 14, [v3i32, v3f32], SGPR_96Regs, TTMP_96Regs>; 743defm "" : SRegClass<4, 15, [v4i32, v4f32, v2i64], SGPR_128Regs, TTMP_128Regs>; 744defm "" : SRegClass<5, 16, [v5i32, v5f32], SGPR_160Regs, TTMP_160Regs>; 745defm "" : SRegClass<6, 17, [v6i32, v6f32, v3i64, v3f64], SGPR_192Regs, TTMP_192Regs>; 746defm "" : SRegClass<7, 18, [v7i32, v7f32], SGPR_224Regs, TTMP_224Regs>; 747defm "" : SRegClass<8, 19, [v8i32, v8f32, v4i64, v4f64], SGPR_256Regs, TTMP_256Regs>; 748defm "" : SRegClass<16, 20, [v16i32, v16f32, v8i64, v8f64], SGPR_512Regs, TTMP_512Regs>; 749defm "" : SRegClass<32, 21, [v32i32, v32f32, v16i64, v16f64], SGPR_1024Regs>; 750 751def VRegOrLds_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, 752 (add VGPR_32, LDS_DIRECT_CLASS)> { 753 let isAllocatable = 0; 754} 755 756// Register class for all vector registers (VGPRs + Interpolation Registers) 757class VRegClassBase<int numRegs, list<ValueType> regTypes, dag regList> : 758 RegisterClass<"AMDGPU", regTypes, 32, regList> { 759 let Size = !mul(numRegs, 32); 760 761 // Requires n v_mov_b32 to copy 762 let CopyCost = numRegs; 763 let AllocationPriority = numRegs; 764 let Weight = numRegs; 765} 766 767// Define a register tuple class, along with one requiring an even 768// aligned base register. 769multiclass VRegClass<int numRegs, list<ValueType> regTypes, dag regList> { 770 // Define the regular class. 771 def "" : VRegClassBase<numRegs, regTypes, regList>; 772 773 // Define 2-aligned variant 774 def _Align2 : VRegClassBase<numRegs, regTypes, (decimate regList, 2)>; 775} 776 777defm VReg_64 : VRegClass<2, [i64, f64, v2i32, v2f32, v4f16, v4i16, p0, p1, p4], 778 (add VGPR_64)>; 779defm VReg_96 : VRegClass<3, [v3i32, v3f32], (add VGPR_96)>; 780defm VReg_128 : VRegClass<4, [v4i32, v4f32, v2i64, v2f64], (add VGPR_128)>; 781defm VReg_160 : VRegClass<5, [v5i32, v5f32], (add VGPR_160)>; 782 783defm VReg_192 : VRegClass<6, [v6i32, v6f32, v3i64, v3f64], (add VGPR_192)>; 784defm VReg_224 : VRegClass<7, [v7i32, v7f32], (add VGPR_224)>; 785defm VReg_256 : VRegClass<8, [v8i32, v8f32, v4i64, v4f64], (add VGPR_256)>; 786defm VReg_512 : VRegClass<16, [v16i32, v16f32, v8i64, v8f64], (add VGPR_512)>; 787defm VReg_1024 : VRegClass<32, [v32i32, v32f32, v16i64, v16f64], (add VGPR_1024)>; 788 789multiclass ARegClass<int numRegs, list<ValueType> regTypes, dag regList> { 790 let CopyCost = !add(numRegs, numRegs, 1) in { 791 // Define the regular class. 792 def "" : VRegClassBase<numRegs, regTypes, regList>; 793 794 // Define 2-aligned variant 795 def _Align2 : VRegClassBase<numRegs, regTypes, (decimate regList, 2)>; 796 } 797} 798 799defm AReg_64 : ARegClass<2, [i64, f64, v2i32, v2f32, v4f16, v4i16], 800 (add AGPR_64)>; 801defm AReg_96 : ARegClass<3, [v3i32, v3f32], (add AGPR_96)>; 802defm AReg_128 : ARegClass<4, [v4i32, v4f32, v2i64, v2f64], (add AGPR_128)>; 803defm AReg_160 : ARegClass<5, [v5i32, v5f32], (add AGPR_160)>; 804defm AReg_192 : ARegClass<6, [v6i32, v6f32, v3i64, v3f64], (add AGPR_192)>; 805defm AReg_224 : ARegClass<7, [v7i32, v7f32], (add AGPR_224)>; 806defm AReg_256 : ARegClass<8, [v8i32, v8f32, v4i64, v4f64], (add AGPR_256)>; 807defm AReg_512 : ARegClass<16, [v16i32, v16f32, v8i64, v8f64], (add AGPR_512)>; 808defm AReg_1024 : ARegClass<32, [v32i32, v32f32, v16i64, v16f64], (add AGPR_1024)>; 809 810} // End GeneratePressureSet = 0 811 812// This is not a real register. This is just to have a register to add 813// to VReg_1 that does not alias any real register that would 814// introduce inferred register classess. 815def ARTIFICIAL_VGPR : SIReg <"invalid vgpr", 0> { 816 let isArtificial = 1; 817} 818 819let GeneratePressureSet = 0 in { 820// FIXME: Should specify an empty set for this. No register should 821// ever be allocated using VReg_1. This is a hack for SelectionDAG 822// that should always be lowered by SILowerI1Copies. TableGen crashes 823// on an empty register set, but also sorts register classes based on 824// the number of registerss in them. Add only one register so this is 825// sorted to the end and not preferred over VGPR_32. 826def VReg_1 : RegisterClass<"AMDGPU", [i1], 32, (add ARTIFICIAL_VGPR)> { 827 let Size = 1; 828} 829 830def VS_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, 831 (add VGPR_32, SReg_32, LDS_DIRECT_CLASS)> { 832 let isAllocatable = 0; 833} 834 835def VS_64 : RegisterClass<"AMDGPU", [i64, f64, v2f32], 32, (add VReg_64, SReg_64)> { 836 let isAllocatable = 0; 837} 838 839def AV_32 : RegisterClass<"AMDGPU", VGPR_32.RegTypes, 32, 840 (add AGPR_32, VGPR_32)> { 841 let isAllocatable = 0; 842} 843 844def AV_64 : RegisterClass<"AMDGPU", VReg_64.RegTypes, 32, 845 (add AReg_64, VReg_64)> { 846 let isAllocatable = 0; 847} 848} // End GeneratePressureSet = 0 849 850def AV_96 : RegisterClass<"AMDGPU", VReg_96.RegTypes, 32, 851 (add AReg_96, VReg_96)> { 852 let isAllocatable = 0; 853} 854 855def AV_128 : RegisterClass<"AMDGPU", VReg_128.RegTypes, 32, 856 (add AReg_128, VReg_128)> { 857 let isAllocatable = 0; 858} 859 860def AV_160 : RegisterClass<"AMDGPU", VReg_160.RegTypes, 32, 861 (add AReg_160, VReg_160)> { 862 let isAllocatable = 0; 863} 864 865//===----------------------------------------------------------------------===// 866// Register operands 867//===----------------------------------------------------------------------===// 868 869class RegImmMatcher<string name> : AsmOperandClass { 870 let Name = name; 871 let RenderMethod = "addRegOrImmOperands"; 872} 873 874multiclass SIRegOperand32 <string rc, string MatchName, string opType, 875 string rc_suffix = "_32"> { 876 let OperandNamespace = "AMDGPU" in { 877 def _b16 : RegisterOperand<!cast<RegisterClass>(rc#rc_suffix)> { 878 let OperandType = opType#"_INT16"; 879 let ParserMatchClass = RegImmMatcher<MatchName#"B16">; 880 let DecoderMethod = "decodeOperand_VSrc16"; 881 } 882 883 def _f16 : RegisterOperand<!cast<RegisterClass>(rc#rc_suffix)> { 884 let OperandType = opType#"_FP16"; 885 let ParserMatchClass = RegImmMatcher<MatchName#"F16">; 886 let DecoderMethod = "decodeOperand_" # rc # "_16"; 887 } 888 889 def _b32 : RegisterOperand<!cast<RegisterClass>(rc#rc_suffix)> { 890 let OperandType = opType#"_INT32"; 891 let ParserMatchClass = RegImmMatcher<MatchName#"B32">; 892 let DecoderMethod = "decodeOperand_" # rc # rc_suffix; 893 } 894 895 def _f32 : RegisterOperand<!cast<RegisterClass>(rc#rc_suffix)> { 896 let OperandType = opType#"_FP32"; 897 let ParserMatchClass = RegImmMatcher<MatchName#"F32">; 898 let DecoderMethod = "decodeOperand_" # rc # rc_suffix; 899 } 900 901 def _v2b16 : RegisterOperand<!cast<RegisterClass>(rc#rc_suffix)> { 902 let OperandType = opType#"_V2INT16"; 903 let ParserMatchClass = RegImmMatcher<MatchName#"V2B16">; 904 let DecoderMethod = "decodeOperand_VSrcV216"; 905 } 906 907 def _v2f16 : RegisterOperand<!cast<RegisterClass>(rc#rc_suffix)> { 908 let OperandType = opType#"_V2FP16"; 909 let ParserMatchClass = RegImmMatcher<MatchName#"V2F16">; 910 let DecoderMethod = "decodeOperand_VSrcV216"; 911 } 912 } 913} 914 915multiclass SIRegOperand64 <string rc, string MatchName, string opType, 916 string rc_suffix = "_64", bit Vectors = 1> { 917 let OperandNamespace = "AMDGPU" in { 918 def _b64 : RegisterOperand<!cast<RegisterClass>(rc#rc_suffix)> { 919 let OperandType = opType#"_INT64"; 920 let ParserMatchClass = RegImmMatcher<MatchName#"B64">; 921 } 922 923 def _f64 : RegisterOperand<!cast<RegisterClass>(rc#rc_suffix)> { 924 let OperandType = opType#"_FP64"; 925 let ParserMatchClass = RegImmMatcher<MatchName#"F64">; 926 } 927 928 if Vectors then 929 def _v2f32 : RegisterOperand<!cast<RegisterClass>(rc#rc_suffix)> { 930 let OperandType = opType#"_V2FP32"; 931 let ParserMatchClass = RegImmMatcher<MatchName#"V2FP32">; 932 let DecoderMethod = "decodeOperand_VSrcV232"; 933 } 934 if Vectors then 935 def _v2b32 : RegisterOperand<!cast<RegisterClass>(rc#rc_suffix)> { 936 let OperandType = opType#"_V2INT32"; 937 let ParserMatchClass = RegImmMatcher<MatchName#"V2INT32">; 938 let DecoderMethod = "decodeOperand_VSrcV232"; 939 } 940 } 941} 942 943multiclass SIRegOperand <string rc, string MatchName, string opType> : 944 SIRegOperand32<rc, MatchName, opType>, 945 SIRegOperand64<rc, MatchName, opType>; 946 947// FIXME: 64-bit sources can sometimes use 32-bit constants. 948multiclass RegImmOperand <string rc, string MatchName> 949 : SIRegOperand<rc, MatchName, "OPERAND_REG_IMM">; 950 951multiclass RegInlineOperand <string rc, string MatchName> 952 : SIRegOperand<rc, MatchName, "OPERAND_REG_INLINE_C">; 953 954multiclass RegInlineOperand32 <string rc, string MatchName, 955 string rc_suffix = "_32"> 956 : SIRegOperand32<rc, MatchName, "OPERAND_REG_INLINE_C", rc_suffix>; 957 958multiclass RegInlineOperand64 <string rc, string MatchName, 959 string rc_suffix = "_64"> 960 : SIRegOperand64<rc, MatchName, "OPERAND_REG_INLINE_C", rc_suffix>; 961 962multiclass RegInlineOperandAC <string rc, string MatchName, 963 string rc_suffix = "_32"> 964 : SIRegOperand32<rc, MatchName, "OPERAND_REG_INLINE_AC", rc_suffix>; 965 966multiclass RegInlineOperandAC64 <string rc, string MatchName, 967 string rc_suffix = "_64"> 968 : SIRegOperand64<rc, MatchName, "OPERAND_REG_INLINE_AC", rc_suffix, 0>; 969 970//===----------------------------------------------------------------------===// 971// SSrc_* Operands with an SGPR or a 32-bit immediate 972//===----------------------------------------------------------------------===// 973 974defm SSrc : RegImmOperand<"SReg", "SSrc">; 975 976def SSrcOrLds_b32 : RegisterOperand<SRegOrLds_32> { 977 let OperandNamespace = "AMDGPU"; 978 let OperandType = "OPERAND_REG_IMM_INT32"; 979 let ParserMatchClass = RegImmMatcher<"SSrcOrLdsB32">; 980} 981 982//===----------------------------------------------------------------------===// 983// SCSrc_* Operands with an SGPR or a inline constant 984//===----------------------------------------------------------------------===// 985 986defm SCSrc : RegInlineOperand<"SReg", "SCSrc"> ; 987 988//===----------------------------------------------------------------------===// 989// VSrc_* Operands with an SGPR, VGPR or a 32-bit immediate 990//===----------------------------------------------------------------------===// 991 992defm VSrc : RegImmOperand<"VS", "VSrc">; 993 994def VSrc_128 : RegisterOperand<VReg_128> { 995 let DecoderMethod = "DecodeVS_128RegisterClass"; 996} 997 998//===----------------------------------------------------------------------===// 999// VRegSrc_* Operands with a VGPR 1000//===----------------------------------------------------------------------===// 1001 1002// This is for operands with the enum(9), VSrc encoding restriction, 1003// but only allows VGPRs. 1004def VRegSrc_32 : RegisterOperand<VGPR_32> { 1005 //let ParserMatchClass = RegImmMatcher<"VRegSrc32">; 1006 let DecoderMethod = "DecodeVS_32RegisterClass"; 1007} 1008 1009//===----------------------------------------------------------------------===// 1010// ASrc_* Operands with an AccVGPR 1011//===----------------------------------------------------------------------===// 1012 1013def ARegSrc_32 : RegisterOperand<AGPR_32> { 1014 let DecoderMethod = "DecodeAGPR_32RegisterClass"; 1015 let EncoderMethod = "getAVOperandEncoding"; 1016} 1017 1018//===----------------------------------------------------------------------===// 1019// VCSrc_* Operands with an SGPR, VGPR or an inline constant 1020//===----------------------------------------------------------------------===// 1021 1022defm VCSrc : RegInlineOperand<"VS", "VCSrc">; 1023 1024//===----------------------------------------------------------------------===// 1025// VISrc_* Operands with a VGPR or an inline constant 1026//===----------------------------------------------------------------------===// 1027 1028defm VISrc : RegInlineOperand32<"VGPR", "VISrc">; 1029let DecoderMethod = "decodeOperand_VReg_64" in 1030defm VISrc_64 : RegInlineOperand64<"VReg", "VISrc_64", "_64">; 1031defm VISrc_128 : RegInlineOperandAC<"VReg", "VISrc_128", "_128">; 1032let DecoderMethod = "decodeOperand_VReg_256" in 1033defm VISrc_256 : RegInlineOperand64<"VReg", "VISrc_256", "_256">; 1034defm VISrc_512 : RegInlineOperandAC<"VReg", "VISrc_512", "_512">; 1035defm VISrc_1024 : RegInlineOperandAC<"VReg", "VISrc_1024", "_1024">; 1036 1037//===----------------------------------------------------------------------===// 1038// AVSrc_* Operands with an AGPR or VGPR 1039//===----------------------------------------------------------------------===// 1040 1041def AVSrc_32 : RegisterOperand<AV_32> { 1042 let DecoderMethod = "DecodeAV_32RegisterClass"; 1043 let EncoderMethod = "getAVOperandEncoding"; 1044} 1045 1046def AVSrc_64 : RegisterOperand<AV_64> { 1047 let DecoderMethod = "DecodeAV_64RegisterClass"; 1048 let EncoderMethod = "getAVOperandEncoding"; 1049} 1050 1051def AVLdSt_32 : RegisterOperand<AV_32> { 1052 let DecoderMethod = "DecodeAVLdSt_32RegisterClass"; 1053 let EncoderMethod = "getAVOperandEncoding"; 1054} 1055 1056def AVLdSt_64 : RegisterOperand<AV_64> { 1057 let DecoderMethod = "DecodeAVLdSt_64RegisterClass"; 1058 let EncoderMethod = "getAVOperandEncoding"; 1059} 1060 1061def AVLdSt_96 : RegisterOperand<AV_96> { 1062 let DecoderMethod = "DecodeAVLdSt_96RegisterClass"; 1063 let EncoderMethod = "getAVOperandEncoding"; 1064} 1065 1066def AVLdSt_128 : RegisterOperand<AV_128> { 1067 let DecoderMethod = "DecodeAVLdSt_128RegisterClass"; 1068 let EncoderMethod = "getAVOperandEncoding"; 1069} 1070 1071def AVLdSt_160 : RegisterOperand<AV_160> { 1072 let DecoderMethod = "DecodeAVLdSt_160RegisterClass"; 1073 let EncoderMethod = "getAVOperandEncoding"; 1074} 1075 1076//===----------------------------------------------------------------------===// 1077// ACSrc_* Operands with an AGPR or an inline constant 1078//===----------------------------------------------------------------------===// 1079 1080defm AISrc : RegInlineOperandAC<"AGPR", "AISrc">; 1081defm AISrc_128 : RegInlineOperandAC<"AReg", "AISrc_128", "_128">; 1082defm AISrc_512 : RegInlineOperandAC<"AReg", "AISrc_512", "_512">; 1083defm AISrc_1024 : RegInlineOperandAC<"AReg", "AISrc_1024", "_1024">; 1084 1085let DecoderMethod = "decodeOperand_AReg_64" in 1086defm AISrc_64 : RegInlineOperandAC64<"AReg", "AISrc_64", "_64">; 1087let DecoderMethod = "decodeOperand_AReg_256" in 1088defm AISrc_256 : RegInlineOperandAC64<"AReg", "AISrc_256", "_256">; 1089