1//===-- SIRegisterInfo.td - SI Register defs ---------------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// Subregister declarations 11//===----------------------------------------------------------------------===// 12 13let Namespace = "AMDGPU" in { 14 15def lo16 : SubRegIndex<16, 0>; 16def hi16 : SubRegIndex<16, 16>; 17 18foreach Index = 0...31 in { 19 def sub#Index : SubRegIndex<32, !shl(Index, 5)>; 20} 21 22foreach Index = 1...31 in { 23 def sub#Index#_lo16 : ComposedSubRegIndex<!cast<SubRegIndex>(sub#Index), lo16>; 24 def sub#Index#_hi16 : ComposedSubRegIndex<!cast<SubRegIndex>(sub#Index), hi16>; 25} 26 27foreach Size = {2...6,8,16} in { 28 foreach Index = !range(!sub(33, Size)) in { 29 def !interleave(!foreach(cur, !range(Size), "sub"#!add(cur, Index)), "_") : 30 SubRegIndex<!mul(Size, 32), !shl(Index, 5)> { 31 let CoveringSubRegIndices = 32 !foreach(cur, !range(Size), !cast<SubRegIndex>(sub#!add(cur, Index))); 33 } 34 } 35} 36 37} 38 39//===----------------------------------------------------------------------===// 40// Helpers 41//===----------------------------------------------------------------------===// 42 43class getSubRegs<int size> { 44 list<SubRegIndex> ret2 = [sub0, sub1]; 45 list<SubRegIndex> ret3 = [sub0, sub1, sub2]; 46 list<SubRegIndex> ret4 = [sub0, sub1, sub2, sub3]; 47 list<SubRegIndex> ret5 = [sub0, sub1, sub2, sub3, sub4]; 48 list<SubRegIndex> ret6 = [sub0, sub1, sub2, sub3, sub4, sub5]; 49 list<SubRegIndex> ret7 = [sub0, sub1, sub2, sub3, sub4, sub5, sub6]; 50 list<SubRegIndex> ret8 = [sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7]; 51 list<SubRegIndex> ret9 = [sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7, sub8]; 52 list<SubRegIndex> ret10 = [sub0, sub1, sub2, sub3, 53 sub4, sub5, sub6, sub7, 54 sub8, sub9]; 55 list<SubRegIndex> ret11 = [sub0, sub1, sub2, sub3, 56 sub4, sub5, sub6, sub7, 57 sub8, sub9, sub10]; 58 list<SubRegIndex> ret12 = [sub0, sub1, sub2, sub3, 59 sub4, sub5, sub6, sub7, 60 sub8, sub9, sub10, sub11]; 61 list<SubRegIndex> ret16 = [sub0, sub1, sub2, sub3, 62 sub4, sub5, sub6, sub7, 63 sub8, sub9, sub10, sub11, 64 sub12, sub13, sub14, sub15]; 65 list<SubRegIndex> ret32 = [sub0, sub1, sub2, sub3, 66 sub4, sub5, sub6, sub7, 67 sub8, sub9, sub10, sub11, 68 sub12, sub13, sub14, sub15, 69 sub16, sub17, sub18, sub19, 70 sub20, sub21, sub22, sub23, 71 sub24, sub25, sub26, sub27, 72 sub28, sub29, sub30, sub31]; 73 74 list<SubRegIndex> ret = !if(!eq(size, 2), ret2, 75 !if(!eq(size, 3), ret3, 76 !if(!eq(size, 4), ret4, 77 !if(!eq(size, 5), ret5, 78 !if(!eq(size, 6), ret6, 79 !if(!eq(size, 7), ret7, 80 !if(!eq(size, 8), ret8, 81 !if(!eq(size, 9), ret9, 82 !if(!eq(size, 10), ret10, 83 !if(!eq(size, 11), ret11, 84 !if(!eq(size, 12), ret12, 85 !if(!eq(size, 16), ret16, 86 ret32)))))))))))); 87} 88 89// Generates list of sequential register tuple names. 90// E.g. RegSeq<3,2,2,"s">.ret -> [ "s[0:1]", "s[2:3]" ] 91class RegSeqNames<int last_reg, int stride, int size, string prefix, 92 int start = 0> { 93 int next = !add(start, stride); 94 int end_reg = !add(start, size, -1); 95 list<string> ret = 96 !if(!le(end_reg, last_reg), 97 !listconcat([prefix # "[" # start # ":" # end_reg # "]"], 98 RegSeqNames<last_reg, stride, size, prefix, next>.ret), 99 []); 100} 101 102// Generates list of dags for register tuples. 103class RegSeqDags<RegisterClass RC, int last_reg, int stride, int size, 104 int start = 0> { 105 dag trunc_rc = (trunc RC, 106 !if(!and(!eq(stride, 1), !eq(start, 0)), 107 !sub(!add(last_reg, 2), size), 108 !add(last_reg, 1))); 109 list<dag> ret = 110 !if(!lt(start, size), 111 !listconcat([(add (decimate (shl trunc_rc, start), stride))], 112 RegSeqDags<RC, last_reg, stride, size, !add(start, 1)>.ret), 113 []); 114} 115 116class SIRegisterTuples<list<SubRegIndex> Indices, RegisterClass RC, 117 int last_reg, int stride, int size, string prefix> : 118 RegisterTuples<Indices, 119 RegSeqDags<RC, last_reg, stride, size>.ret, 120 RegSeqNames<last_reg, stride, size, prefix>.ret>; 121 122//===----------------------------------------------------------------------===// 123// Declarations that describe the SI registers 124//===----------------------------------------------------------------------===// 125class SIReg <string n, bits<16> regIdx = 0> : 126 Register<n> { 127 let Namespace = "AMDGPU"; 128 let HWEncoding = regIdx; 129} 130 131// For register classes that use TSFlags. 132class SIRegisterClass <string n, list<ValueType> rTypes, int Align, dag rList> 133 : RegisterClass <n, rTypes, Align, rList> { 134 // For vector register classes. 135 field bit HasVGPR = 0; 136 field bit HasAGPR = 0; 137 138 // For scalar register classes. 139 field bit HasSGPR = 0; 140 141 // Alignment of the first register in tuple (in 32-bit units). 142 field int RegTupleAlignUnits = 1; 143 144 // These need to be kept in sync with the enum SIRCFlags. 145 let TSFlags{1-0} = RegTupleAlignUnits; 146 let TSFlags{2} = HasVGPR; 147 let TSFlags{3} = HasAGPR; 148 let TSFlags{4} = HasSGPR; 149} 150 151multiclass SIRegLoHi16 <string n, bits<16> regIdx, bit ArtificialHigh = 1, 152 bit HWEncodingHigh = 0> { 153 // There is no special encoding for 16 bit subregs, these are not real 154 // registers but rather operands for instructions preserving other 16 bits 155 // of the result or reading just 16 bits of a 32 bit VGPR. 156 // It is encoded as a corresponding 32 bit register. 157 // Non-VGPR register classes use it as we need to have matching subregisters 158 // to move instructions and data between ALUs. 159 def _LO16 : SIReg<n#".l", regIdx> { 160 let HWEncoding{8} = HWEncodingHigh; 161 } 162 def _HI16 : SIReg<!if(ArtificialHigh, "", n#".h"), regIdx> { 163 let isArtificial = ArtificialHigh; 164 let HWEncoding{8} = HWEncodingHigh; 165 } 166 def "" : RegisterWithSubRegs<n, [!cast<Register>(NAME#"_LO16"), 167 !cast<Register>(NAME#"_HI16")]> { 168 let Namespace = "AMDGPU"; 169 let SubRegIndices = [lo16, hi16]; 170 let CoveredBySubRegs = !not(ArtificialHigh); 171 let HWEncoding = regIdx; 172 let HWEncoding{8} = HWEncodingHigh; 173 } 174} 175 176// Special Registers 177defm VCC_LO : SIRegLoHi16<"vcc_lo", 106>; 178defm VCC_HI : SIRegLoHi16<"vcc_hi", 107>; 179 180// Pseudo-registers: Used as placeholders during isel and immediately 181// replaced, never seeing the verifier. 182def PRIVATE_RSRC_REG : SIReg<"private_rsrc", 0>; 183def FP_REG : SIReg<"fp", 0>; 184def SP_REG : SIReg<"sp", 0>; 185 186// Pseudo-register to represent the program-counter DWARF register. 187def PC_REG : SIReg<"pc", 0>, DwarfRegNum<[16, 16]> { 188 // There is no physical register corresponding to a "program counter", but 189 // we need to encode the concept in debug information in order to represent 190 // things like the return value in unwind information. 191 let isArtificial = 1; 192} 193 194// VCC for 64-bit instructions 195def VCC : RegisterWithSubRegs<"vcc", [VCC_LO, VCC_HI]> { 196 let Namespace = "AMDGPU"; 197 let SubRegIndices = [sub0, sub1]; 198 let HWEncoding = VCC_LO.HWEncoding; 199} 200 201defm EXEC_LO : SIRegLoHi16<"exec_lo", 126>, DwarfRegNum<[1, 1]>; 202defm EXEC_HI : SIRegLoHi16<"exec_hi", 127>; 203 204def EXEC : RegisterWithSubRegs<"exec", [EXEC_LO, EXEC_HI]>, DwarfRegNum<[17, 1]> { 205 let Namespace = "AMDGPU"; 206 let SubRegIndices = [sub0, sub1]; 207 let HWEncoding = EXEC_LO.HWEncoding; 208} 209 210// 32-bit real registers, for MC only. 211// May be used with both 32-bit and 64-bit operands. 212defm SRC_VCCZ : SIRegLoHi16<"src_vccz", 251>; 213defm SRC_EXECZ : SIRegLoHi16<"src_execz", 252>; 214defm SRC_SCC : SIRegLoHi16<"src_scc", 253>; 215 216// 1-bit pseudo register, for codegen only. 217// Should never be emitted. 218def SCC : SIReg<"scc">; 219 220// Encoding changes between subtarget generations. 221// See also Utils/AMDGPUBaseInfo.cpp MAP_REG2REG. 222defm M0_gfxpre11 : SIRegLoHi16 <"m0", 124>; 223defm M0_gfx11plus : SIRegLoHi16 <"m0", 125>; 224defm M0 : SIRegLoHi16 <"m0", 0>; 225 226defm SGPR_NULL_gfxpre11 : SIRegLoHi16 <"null", 125>; 227defm SGPR_NULL_gfx11plus : SIRegLoHi16 <"null", 124>; 228let isConstant = true in { 229defm SGPR_NULL : SIRegLoHi16 <"null", 0>; 230defm SGPR_NULL_HI : SIRegLoHi16 <"", 0>; 231} // isConstant = true 232 233def SGPR_NULL64 : 234 RegisterWithSubRegs<"null", [SGPR_NULL, SGPR_NULL_HI]> { 235 let Namespace = "AMDGPU"; 236 let SubRegIndices = [sub0, sub1]; 237 let HWEncoding = SGPR_NULL.HWEncoding; 238 let isConstant = true; 239} 240 241// Aperture registers are 64 bit registers with a LO/HI 32 bit. 242// HI 32 bit cannot be used, and LO 32 is used by instructions 243// with 32 bit sources. 244// 245// Note that the low 32 bits are essentially useless as they 246// don't contain the lower 32 bits of the address - they are in 247// the high 32 bits. The lower 32 bits are always zero (for base) or 248// -1 (for limit). Since we cannot access the high 32 bits, when we 249// need them, we need to do a 64 bit load and extract the bits manually. 250multiclass ApertureRegister<string name, bits<16> regIdx> { 251 let isConstant = true in { 252 // FIXME: We shouldn't need to define subregisters for these (nor add them to any 16 bit 253 // register classes), but if we don't it seems to confuse the TableGen 254 // backend and we end up with a lot of weird register pressure sets and classes. 255 defm _LO : SIRegLoHi16 <name, regIdx>; 256 defm _HI : SIRegLoHi16 <"", regIdx>; 257 258 def "" : RegisterWithSubRegs<name, [!cast<Register>(NAME#_LO), !cast<Register>(NAME#_HI)]> { 259 let Namespace = "AMDGPU"; 260 let SubRegIndices = [sub0, sub1]; 261 let HWEncoding = !cast<Register>(NAME#_LO).HWEncoding; 262 } 263 } // isConstant = true 264} 265 266defm SRC_SHARED_BASE : ApertureRegister<"src_shared_base", 235>; 267defm SRC_SHARED_LIMIT : ApertureRegister<"src_shared_limit", 236>; 268defm SRC_PRIVATE_BASE : ApertureRegister<"src_private_base", 237>; 269defm SRC_PRIVATE_LIMIT : ApertureRegister<"src_private_limit", 238>; 270 271defm SRC_POPS_EXITING_WAVE_ID : SIRegLoHi16<"src_pops_exiting_wave_id", 239>; 272 273// Not addressable 274def MODE : SIReg <"mode", 0>; 275 276def LDS_DIRECT : SIReg <"src_lds_direct", 254> { 277 // There is no physical register corresponding to this. This is an 278 // encoding value in a source field, which will ultimately trigger a 279 // read from m0. 280 let isArtificial = 1; 281} 282 283defm XNACK_MASK_LO : SIRegLoHi16<"xnack_mask_lo", 104>; 284defm XNACK_MASK_HI : SIRegLoHi16<"xnack_mask_hi", 105>; 285 286def XNACK_MASK : 287 RegisterWithSubRegs<"xnack_mask", [XNACK_MASK_LO, XNACK_MASK_HI]> { 288 let Namespace = "AMDGPU"; 289 let SubRegIndices = [sub0, sub1]; 290 let HWEncoding = XNACK_MASK_LO.HWEncoding; 291} 292 293// Trap handler registers 294defm TBA_LO : SIRegLoHi16<"tba_lo", 108>; 295defm TBA_HI : SIRegLoHi16<"tba_hi", 109>; 296 297def TBA : RegisterWithSubRegs<"tba", [TBA_LO, TBA_HI]> { 298 let Namespace = "AMDGPU"; 299 let SubRegIndices = [sub0, sub1]; 300 let HWEncoding = TBA_LO.HWEncoding; 301} 302 303defm TMA_LO : SIRegLoHi16<"tma_lo", 110>; 304defm TMA_HI : SIRegLoHi16<"tma_hi", 111>; 305 306def TMA : RegisterWithSubRegs<"tma", [TMA_LO, TMA_HI]> { 307 let Namespace = "AMDGPU"; 308 let SubRegIndices = [sub0, sub1]; 309 let HWEncoding = TMA_LO.HWEncoding; 310} 311 312foreach Index = 0...15 in { 313 defm TTMP#Index#_vi : SIRegLoHi16<"ttmp"#Index, !add(112, Index)>; 314 defm TTMP#Index#_gfx9plus : SIRegLoHi16<"ttmp"#Index, !add(108, Index)>; 315 defm TTMP#Index : SIRegLoHi16<"ttmp"#Index, 0>; 316} 317 318multiclass FLAT_SCR_LOHI_m <string n, bits<16> ci_e, bits<16> vi_e> { 319 defm _ci : SIRegLoHi16<n, ci_e>; 320 defm _vi : SIRegLoHi16<n, vi_e>; 321 defm "" : SIRegLoHi16<n, 0>; 322} 323 324class FlatReg <Register lo, Register hi, bits<16> encoding> : 325 RegisterWithSubRegs<"flat_scratch", [lo, hi]> { 326 let Namespace = "AMDGPU"; 327 let SubRegIndices = [sub0, sub1]; 328 let HWEncoding = encoding; 329} 330 331defm FLAT_SCR_LO : FLAT_SCR_LOHI_m<"flat_scratch_lo", 104, 102>; // Offset in units of 256-bytes. 332defm FLAT_SCR_HI : FLAT_SCR_LOHI_m<"flat_scratch_hi", 105, 103>; // Size is the per-thread scratch size, in bytes. 333 334def FLAT_SCR_ci : FlatReg<FLAT_SCR_LO_ci, FLAT_SCR_HI_ci, 104>; 335def FLAT_SCR_vi : FlatReg<FLAT_SCR_LO_vi, FLAT_SCR_HI_vi, 102>; 336def FLAT_SCR : FlatReg<FLAT_SCR_LO, FLAT_SCR_HI, 0>; 337 338// SGPR registers 339foreach Index = 0...105 in { 340 defm SGPR#Index : 341 SIRegLoHi16 <"s"#Index, Index>, 342 DwarfRegNum<[!if(!le(Index, 63), !add(Index, 32), !add(Index, 1024)), 343 !if(!le(Index, 63), !add(Index, 32), !add(Index, 1024))]>; 344} 345 346// VGPR registers 347foreach Index = 0...255 in { 348 defm VGPR#Index : 349 SIRegLoHi16 <"v"#Index, Index, 0, 1>, 350 DwarfRegNum<[!add(Index, 2560), !add(Index, 1536)]>; 351} 352 353// AccVGPR registers 354foreach Index = 0...255 in { 355 defm AGPR#Index : 356 SIRegLoHi16 <"a"#Index, Index, 1, 1>, 357 DwarfRegNum<[!add(Index, 3072), !add(Index, 2048)]>; 358} 359 360//===----------------------------------------------------------------------===// 361// Groupings using register classes and tuples 362//===----------------------------------------------------------------------===// 363 364def SCC_CLASS : SIRegisterClass<"AMDGPU", [i1], 1, (add SCC)> { 365 let CopyCost = -1; 366 let isAllocatable = 0; 367 let HasSGPR = 1; 368 let BaseClassOrder = 10000; 369} 370 371def M0_CLASS : SIRegisterClass<"AMDGPU", [i32], 32, (add M0)> { 372 let CopyCost = 1; 373 let isAllocatable = 0; 374 let HasSGPR = 1; 375} 376 377def M0_CLASS_LO16 : SIRegisterClass<"AMDGPU", [i16, f16], 16, (add M0_LO16)> { 378 let CopyCost = 1; 379 let Size = 16; 380 let isAllocatable = 0; 381 let HasSGPR = 1; 382} 383 384// TODO: Do we need to set DwarfRegAlias on register tuples? 385 386def SGPR_LO16 : SIRegisterClass<"AMDGPU", [i16, f16], 16, 387 (add (sequence "SGPR%u_LO16", 0, 105))> { 388 let AllocationPriority = 0; 389 let Size = 16; 390 let GeneratePressureSet = 0; 391 let HasSGPR = 1; 392} 393 394def SGPR_HI16 : SIRegisterClass<"AMDGPU", [i16, f16], 16, 395 (add (sequence "SGPR%u_HI16", 0, 105))> { 396 let isAllocatable = 0; 397 let Size = 16; 398 let GeneratePressureSet = 0; 399 let HasSGPR = 1; 400} 401 402// SGPR 32-bit registers 403def SGPR_32 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, 404 (add (sequence "SGPR%u", 0, 105))> { 405 // Give all SGPR classes higher priority than VGPR classes, because 406 // we want to spill SGPRs to VGPRs. 407 let AllocationPriority = 0; 408 let GeneratePressureSet = 0; 409 let HasSGPR = 1; 410} 411 412// SGPR 64-bit registers 413def SGPR_64Regs : SIRegisterTuples<getSubRegs<2>.ret, SGPR_32, 105, 2, 2, "s">; 414 415// SGPR 96-bit registers. No operations use these, but for symmetry with 96-bit VGPRs. 416def SGPR_96Regs : SIRegisterTuples<getSubRegs<3>.ret, SGPR_32, 105, 4, 3, "s">; 417 418// SGPR 128-bit registers 419def SGPR_128Regs : SIRegisterTuples<getSubRegs<4>.ret, SGPR_32, 105, 4, 4, "s">; 420 421// SGPR 160-bit registers. No operations use these, but for symmetry with 160-bit VGPRs. 422def SGPR_160Regs : SIRegisterTuples<getSubRegs<5>.ret, SGPR_32, 105, 4, 5, "s">; 423 424// SGPR 192-bit registers. No operations use these, but for symmetry with 192-bit VGPRs. 425def SGPR_192Regs : SIRegisterTuples<getSubRegs<6>.ret, SGPR_32, 105, 4, 6, "s">; 426 427// SGPR 224-bit registers. No operations use these, but for symmetry with 224-bit VGPRs. 428def SGPR_224Regs : SIRegisterTuples<getSubRegs<7>.ret, SGPR_32, 105, 4, 7, "s">; 429 430// SGPR 256-bit registers 431def SGPR_256Regs : SIRegisterTuples<getSubRegs<8>.ret, SGPR_32, 105, 4, 8, "s">; 432 433// SGPR 288-bit registers. No operations use these, but for symmetry with 288-bit VGPRs. 434def SGPR_288Regs : SIRegisterTuples<getSubRegs<9>.ret, SGPR_32, 105, 4, 9, "s">; 435 436// SGPR 320-bit registers. No operations use these, but for symmetry with 320-bit VGPRs. 437def SGPR_320Regs : SIRegisterTuples<getSubRegs<10>.ret, SGPR_32, 105, 4, 10, "s">; 438 439// SGPR 352-bit registers. No operations use these, but for symmetry with 352-bit VGPRs. 440def SGPR_352Regs : SIRegisterTuples<getSubRegs<11>.ret, SGPR_32, 105, 4, 11, "s">; 441 442// SGPR 384-bit registers. No operations use these, but for symmetry with 384-bit VGPRs. 443def SGPR_384Regs : SIRegisterTuples<getSubRegs<12>.ret, SGPR_32, 105, 4, 12, "s">; 444 445// SGPR 512-bit registers 446def SGPR_512Regs : SIRegisterTuples<getSubRegs<16>.ret, SGPR_32, 105, 4, 16, "s">; 447 448// SGPR 1024-bit registers 449def SGPR_1024Regs : SIRegisterTuples<getSubRegs<32>.ret, SGPR_32, 105, 4, 32, "s">; 450 451// Trap handler TMP 32-bit registers 452def TTMP_32 : SIRegisterClass<"AMDGPU", [i32, f32, v2i16, v2f16], 32, 453 (add (sequence "TTMP%u", 0, 15))> { 454 let isAllocatable = 0; 455 let HasSGPR = 1; 456} 457 458// Trap handler TMP 16-bit registers 459def TTMP_LO16 : SIRegisterClass<"AMDGPU", [i16, f16], 16, 460 (add (sequence "TTMP%u_LO16", 0, 15))> { 461 let Size = 16; 462 let isAllocatable = 0; 463 let HasSGPR = 1; 464} 465 466// Trap handler TMP 64-bit registers 467def TTMP_64Regs : SIRegisterTuples<getSubRegs<2>.ret, TTMP_32, 15, 2, 2, "ttmp">; 468 469// Trap handler TMP 96-bit registers 470def TTMP_96Regs : SIRegisterTuples<getSubRegs<3>.ret, TTMP_32, 15, 3, 3, "ttmp">; 471 472// Trap handler TMP 128-bit registers 473def TTMP_128Regs : SIRegisterTuples<getSubRegs<4>.ret, TTMP_32, 15, 4, 4, "ttmp">; 474 475// Trap handler TMP 160-bit registers 476def TTMP_160Regs : SIRegisterTuples<getSubRegs<5>.ret, TTMP_32, 15, 4, 5, "ttmp">; 477 478// Trap handler TMP 192-bit registers 479def TTMP_192Regs : SIRegisterTuples<getSubRegs<6>.ret, TTMP_32, 15, 4, 6, "ttmp">; 480 481// Trap handler TMP 224-bit registers 482def TTMP_224Regs : SIRegisterTuples<getSubRegs<7>.ret, TTMP_32, 15, 4, 7, "ttmp">; 483 484// Trap handler TMP 256-bit registers 485def TTMP_256Regs : SIRegisterTuples<getSubRegs<8>.ret, TTMP_32, 15, 4, 8, "ttmp">; 486 487// Trap handler TMP 288-bit registers 488def TTMP_288Regs : SIRegisterTuples<getSubRegs<9>.ret, TTMP_32, 15, 4, 9, "ttmp">; 489 490// Trap handler TMP 320-bit registers 491def TTMP_320Regs : SIRegisterTuples<getSubRegs<10>.ret, TTMP_32, 15, 4, 10, "ttmp">; 492 493// Trap handler TMP 352-bit registers 494def TTMP_352Regs : SIRegisterTuples<getSubRegs<11>.ret, TTMP_32, 15, 4, 11, "ttmp">; 495 496// Trap handler TMP 384-bit registers 497def TTMP_384Regs : SIRegisterTuples<getSubRegs<12>.ret, TTMP_32, 15, 4, 12, "ttmp">; 498 499// Trap handler TMP 512-bit registers 500def TTMP_512Regs : SIRegisterTuples<getSubRegs<16>.ret, TTMP_32, 15, 4, 16, "ttmp">; 501 502class TmpRegTuplesBase<int index, int size, 503 list<Register> subRegs, 504 list<SubRegIndex> indices = getSubRegs<size>.ret, 505 int index1 = !add(index, size, -1), 506 string name = "ttmp["#index#":"#index1#"]"> : 507 RegisterWithSubRegs<name, subRegs> { 508 let HWEncoding = subRegs[0].HWEncoding; 509 let SubRegIndices = indices; 510} 511 512class TmpRegTuples<string tgt, 513 int size, 514 int index0, 515 int index1 = !add(index0, 1), 516 int index2 = !add(index0, !if(!eq(size, 2), 1, 2)), 517 int index3 = !add(index0, !if(!eq(size, 2), 1, 3)), 518 int index4 = !add(index0, !if(!eq(size, 8), 4, 1)), 519 int index5 = !add(index0, !if(!eq(size, 8), 5, 1)), 520 int index6 = !add(index0, !if(!eq(size, 8), 6, 1)), 521 int index7 = !add(index0, !if(!eq(size, 8), 7, 1)), 522 Register r0 = !cast<Register>("TTMP"#index0#tgt), 523 Register r1 = !cast<Register>("TTMP"#index1#tgt), 524 Register r2 = !cast<Register>("TTMP"#index2#tgt), 525 Register r3 = !cast<Register>("TTMP"#index3#tgt), 526 Register r4 = !cast<Register>("TTMP"#index4#tgt), 527 Register r5 = !cast<Register>("TTMP"#index5#tgt), 528 Register r6 = !cast<Register>("TTMP"#index6#tgt), 529 Register r7 = !cast<Register>("TTMP"#index7#tgt)> : 530 TmpRegTuplesBase<index0, size, 531 !if(!eq(size, 2), [r0, r1], 532 !if(!eq(size, 4), [r0, r1, r2, r3], 533 [r0, r1, r2, r3, r4, r5, r6, r7])), 534 getSubRegs<size>.ret>; 535 536foreach Index = {0, 2, 4, 6, 8, 10, 12, 14} in { 537 def TTMP#Index#_TTMP#!add(Index,1)#_vi : TmpRegTuples<"_vi", 2, Index>; 538 def TTMP#Index#_TTMP#!add(Index,1)#_gfx9plus : TmpRegTuples<"_gfx9plus", 2, Index>; 539} 540 541foreach Index = {0, 4, 8, 12} in { 542 def TTMP#Index#_TTMP#!add(Index,1)# 543 _TTMP#!add(Index,2)# 544 _TTMP#!add(Index,3)#_vi : TmpRegTuples<"_vi", 4, Index>; 545 def TTMP#Index#_TTMP#!add(Index,1)# 546 _TTMP#!add(Index,2)# 547 _TTMP#!add(Index,3)#_gfx9plus : TmpRegTuples<"_gfx9plus", 4, Index>; 548} 549 550foreach Index = {0, 4, 8} in { 551 def TTMP#Index#_TTMP#!add(Index,1)# 552 _TTMP#!add(Index,2)# 553 _TTMP#!add(Index,3)# 554 _TTMP#!add(Index,4)# 555 _TTMP#!add(Index,5)# 556 _TTMP#!add(Index,6)# 557 _TTMP#!add(Index,7)#_vi : TmpRegTuples<"_vi", 8, Index>; 558 def TTMP#Index#_TTMP#!add(Index,1)# 559 _TTMP#!add(Index,2)# 560 _TTMP#!add(Index,3)# 561 _TTMP#!add(Index,4)# 562 _TTMP#!add(Index,5)# 563 _TTMP#!add(Index,6)# 564 _TTMP#!add(Index,7)#_gfx9plus : TmpRegTuples<"_gfx9plus", 8, Index>; 565} 566 567def TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15_vi : 568 TmpRegTuplesBase<0, 16, 569 [TTMP0_vi, TTMP1_vi, TTMP2_vi, TTMP3_vi, 570 TTMP4_vi, TTMP5_vi, TTMP6_vi, TTMP7_vi, 571 TTMP8_vi, TTMP9_vi, TTMP10_vi, TTMP11_vi, 572 TTMP12_vi, TTMP13_vi, TTMP14_vi, TTMP15_vi]>; 573 574def TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15_gfx9plus : 575 TmpRegTuplesBase<0, 16, 576 [TTMP0_gfx9plus, TTMP1_gfx9plus, TTMP2_gfx9plus, TTMP3_gfx9plus, 577 TTMP4_gfx9plus, TTMP5_gfx9plus, TTMP6_gfx9plus, TTMP7_gfx9plus, 578 TTMP8_gfx9plus, TTMP9_gfx9plus, TTMP10_gfx9plus, TTMP11_gfx9plus, 579 TTMP12_gfx9plus, TTMP13_gfx9plus, TTMP14_gfx9plus, TTMP15_gfx9plus]>; 580 581class RegisterTypes<list<ValueType> reg_types> { 582 list<ValueType> types = reg_types; 583} 584 585def Reg16Types : RegisterTypes<[i16, f16]>; 586def Reg32Types : RegisterTypes<[i32, f32, v2i16, v2f16, p2, p3, p5, p6]>; 587 588let HasVGPR = 1 in { 589def VGPR_LO16 : SIRegisterClass<"AMDGPU", Reg16Types.types, 16, 590 (add (sequence "VGPR%u_LO16", 0, 255))> { 591 let AllocationPriority = 0; 592 let Size = 16; 593 let GeneratePressureSet = 0; 594 let BaseClassOrder = 16; 595} 596 597def VGPR_HI16 : SIRegisterClass<"AMDGPU", Reg16Types.types, 16, 598 (add (sequence "VGPR%u_HI16", 0, 255))> { 599 let AllocationPriority = 0; 600 let Size = 16; 601 let GeneratePressureSet = 0; 602 let BaseClassOrder = 17; 603} 604 605// VGPR 32-bit registers 606// i16/f16 only on VI+ 607def VGPR_32 : SIRegisterClass<"AMDGPU", !listconcat(Reg32Types.types, Reg16Types.types), 32, 608 (add (sequence "VGPR%u", 0, 255))> { 609 let AllocationPriority = 0; 610 let Size = 32; 611 let Weight = 1; 612 let BaseClassOrder = 32; 613} 614 615// Identical to VGPR_32 except it only contains the low 128 (Lo128) registers. 616def VGPR_32_Lo128 : SIRegisterClass<"AMDGPU", !listconcat(Reg32Types.types, Reg16Types.types), 32, 617 (add (sequence "VGPR%u", 0, 127))> { 618 let AllocationPriority = 0; 619 let GeneratePressureSet = 0; 620 let Size = 32; 621 let Weight = 1; 622} 623} // End HasVGPR = 1 624 625// VGPR 64-bit registers 626def VGPR_64 : SIRegisterTuples<getSubRegs<2>.ret, VGPR_32, 255, 1, 2, "v">; 627 628// VGPR 96-bit registers 629def VGPR_96 : SIRegisterTuples<getSubRegs<3>.ret, VGPR_32, 255, 1, 3, "v">; 630 631// VGPR 128-bit registers 632def VGPR_128 : SIRegisterTuples<getSubRegs<4>.ret, VGPR_32, 255, 1, 4, "v">; 633 634// VGPR 160-bit registers 635def VGPR_160 : SIRegisterTuples<getSubRegs<5>.ret, VGPR_32, 255, 1, 5, "v">; 636 637// VGPR 192-bit registers 638def VGPR_192 : SIRegisterTuples<getSubRegs<6>.ret, VGPR_32, 255, 1, 6, "v">; 639 640// VGPR 224-bit registers 641def VGPR_224 : SIRegisterTuples<getSubRegs<7>.ret, VGPR_32, 255, 1, 7, "v">; 642 643// VGPR 256-bit registers 644def VGPR_256 : SIRegisterTuples<getSubRegs<8>.ret, VGPR_32, 255, 1, 8, "v">; 645 646// VGPR 288-bit registers 647def VGPR_288 : SIRegisterTuples<getSubRegs<9>.ret, VGPR_32, 255, 1, 9, "v">; 648 649// VGPR 320-bit registers 650def VGPR_320 : SIRegisterTuples<getSubRegs<10>.ret, VGPR_32, 255, 1, 10, "v">; 651 652// VGPR 352-bit registers 653def VGPR_352 : SIRegisterTuples<getSubRegs<11>.ret, VGPR_32, 255, 1, 11, "v">; 654 655// VGPR 384-bit registers 656def VGPR_384 : SIRegisterTuples<getSubRegs<12>.ret, VGPR_32, 255, 1, 12, "v">; 657 658// VGPR 512-bit registers 659def VGPR_512 : SIRegisterTuples<getSubRegs<16>.ret, VGPR_32, 255, 1, 16, "v">; 660 661// VGPR 1024-bit registers 662def VGPR_1024 : SIRegisterTuples<getSubRegs<32>.ret, VGPR_32, 255, 1, 32, "v">; 663 664let HasAGPR = 1 in { 665def AGPR_LO16 : SIRegisterClass<"AMDGPU", Reg16Types.types, 16, 666 (add (sequence "AGPR%u_LO16", 0, 255))> { 667 let isAllocatable = 0; 668 let Size = 16; 669 let GeneratePressureSet = 0; 670 let BaseClassOrder = 16; 671} 672 673// AccVGPR 32-bit registers 674def AGPR_32 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, 675 (add (sequence "AGPR%u", 0, 255))> { 676 let AllocationPriority = 0; 677 let Size = 32; 678 let Weight = 1; 679 let BaseClassOrder = 32; 680} 681} // End HasAGPR = 1 682 683// AGPR 64-bit registers 684def AGPR_64 : SIRegisterTuples<getSubRegs<2>.ret, AGPR_32, 255, 1, 2, "a">; 685 686// AGPR 96-bit registers 687def AGPR_96 : SIRegisterTuples<getSubRegs<3>.ret, AGPR_32, 255, 1, 3, "a">; 688 689// AGPR 128-bit registers 690def AGPR_128 : SIRegisterTuples<getSubRegs<4>.ret, AGPR_32, 255, 1, 4, "a">; 691 692// AGPR 160-bit registers 693def AGPR_160 : SIRegisterTuples<getSubRegs<5>.ret, AGPR_32, 255, 1, 5, "a">; 694 695// AGPR 192-bit registers 696def AGPR_192 : SIRegisterTuples<getSubRegs<6>.ret, AGPR_32, 255, 1, 6, "a">; 697 698// AGPR 224-bit registers 699def AGPR_224 : SIRegisterTuples<getSubRegs<7>.ret, AGPR_32, 255, 1, 7, "a">; 700 701// AGPR 256-bit registers 702def AGPR_256 : SIRegisterTuples<getSubRegs<8>.ret, AGPR_32, 255, 1, 8, "a">; 703 704// AGPR 288-bit registers 705def AGPR_288 : SIRegisterTuples<getSubRegs<9>.ret, AGPR_32, 255, 1, 9, "a">; 706 707// AGPR 320-bit registers 708def AGPR_320 : SIRegisterTuples<getSubRegs<10>.ret, AGPR_32, 255, 1, 10, "a">; 709 710// AGPR 352-bit registers 711def AGPR_352 : SIRegisterTuples<getSubRegs<11>.ret, AGPR_32, 255, 1, 11, "a">; 712 713// AGPR 384-bit registers 714def AGPR_384 : SIRegisterTuples<getSubRegs<12>.ret, AGPR_32, 255, 1, 12, "a">; 715 716// AGPR 512-bit registers 717def AGPR_512 : SIRegisterTuples<getSubRegs<16>.ret, AGPR_32, 255, 1, 16, "a">; 718 719// AGPR 1024-bit registers 720def AGPR_1024 : SIRegisterTuples<getSubRegs<32>.ret, AGPR_32, 255, 1, 32, "a">; 721 722//===----------------------------------------------------------------------===// 723// Register classes used as source and destination 724//===----------------------------------------------------------------------===// 725 726def Pseudo_SReg_32 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, 727 (add FP_REG, SP_REG)> { 728 let isAllocatable = 0; 729 let CopyCost = -1; 730 let HasSGPR = 1; 731 let BaseClassOrder = 10000; 732} 733 734def Pseudo_SReg_128 : SIRegisterClass<"AMDGPU", [v4i32, v2i64, v2f64, v8i16, v8f16], 32, 735 (add PRIVATE_RSRC_REG)> { 736 let isAllocatable = 0; 737 let CopyCost = -1; 738 let HasSGPR = 1; 739 let BaseClassOrder = 10000; 740} 741 742def LDS_DIRECT_CLASS : RegisterClass<"AMDGPU", [i32], 32, 743 (add LDS_DIRECT)> { 744 let isAllocatable = 0; 745 let CopyCost = -1; 746} 747 748let GeneratePressureSet = 0, HasSGPR = 1 in { 749// Subset of SReg_32 without M0 for SMRD instructions and alike. 750// See comments in SIInstructions.td for more info. 751def SReg_32_XM0_XEXEC : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32, 752 (add SGPR_32, VCC_LO, VCC_HI, FLAT_SCR_LO, FLAT_SCR_HI, XNACK_MASK_LO, XNACK_MASK_HI, 753 SGPR_NULL, SGPR_NULL_HI, TTMP_32, TMA_LO, TMA_HI, TBA_LO, TBA_HI, SRC_SHARED_BASE_LO, 754 SRC_SHARED_LIMIT_LO, SRC_PRIVATE_BASE_LO, SRC_PRIVATE_LIMIT_LO, SRC_SHARED_BASE_HI, 755 SRC_SHARED_LIMIT_HI, SRC_PRIVATE_BASE_HI, SRC_PRIVATE_LIMIT_HI, SRC_POPS_EXITING_WAVE_ID, 756 SRC_VCCZ, SRC_EXECZ, SRC_SCC)> { 757 let AllocationPriority = 0; 758} 759 760def SReg_LO16 : SIRegisterClass<"AMDGPU", [i16, f16], 16, 761 (add SGPR_LO16, VCC_LO_LO16, VCC_HI_LO16, FLAT_SCR_LO_LO16, FLAT_SCR_HI_LO16, 762 XNACK_MASK_LO_LO16, XNACK_MASK_HI_LO16, SGPR_NULL_LO16, SGPR_NULL_HI_LO16, TTMP_LO16, 763 TMA_LO_LO16, TMA_HI_LO16, TBA_LO_LO16, TBA_HI_LO16, SRC_SHARED_BASE_LO_LO16, 764 SRC_SHARED_LIMIT_LO_LO16, SRC_PRIVATE_BASE_LO_LO16, SRC_PRIVATE_LIMIT_LO_LO16, 765 SRC_SHARED_BASE_HI_LO16, SRC_SHARED_LIMIT_HI_LO16, SRC_PRIVATE_BASE_HI_LO16, 766 SRC_PRIVATE_LIMIT_HI_LO16, SRC_POPS_EXITING_WAVE_ID_LO16, SRC_VCCZ_LO16, 767 SRC_EXECZ_LO16, SRC_SCC_LO16, EXEC_LO_LO16, EXEC_HI_LO16, M0_CLASS_LO16)> { 768 let Size = 16; 769 let isAllocatable = 0; 770 let BaseClassOrder = 16; 771} 772 773def SReg_32_XEXEC : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32, 774 (add SReg_32_XM0_XEXEC, M0_CLASS)> { 775 let AllocationPriority = 0; 776} 777 778def SReg_32_XEXEC_HI : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32, 779 (add SReg_32_XEXEC, EXEC_LO)> { 780 let AllocationPriority = 0; 781} 782 783def SReg_32_XM0 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32, 784 (add SReg_32_XM0_XEXEC, EXEC_LO, EXEC_HI)> { 785 let AllocationPriority = 0; 786} 787 788} // End GeneratePressureSet = 0 789 790// Register class for all scalar registers (SGPRs + Special Registers) 791def SReg_32 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32, 792 (add SReg_32_XM0, M0_CLASS)> { 793 let AllocationPriority = 0; 794 let HasSGPR = 1; 795 let BaseClassOrder = 32; 796} 797 798let GeneratePressureSet = 0 in { 799def SRegOrLds_32 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, 800 (add SReg_32, LDS_DIRECT_CLASS)> { 801 let isAllocatable = 0; 802 let HasSGPR = 1; 803} 804 805def SGPR_64 : SIRegisterClass<"AMDGPU", [v2i32, i64, v2f32, f64, v4i16, v4f16], 32, 806 (add SGPR_64Regs)> { 807 let CopyCost = 1; 808 let AllocationPriority = 1; 809 let HasSGPR = 1; 810} 811 812// CCR (call clobbered registers) SGPR 64-bit registers 813def CCR_SGPR_64 : SIRegisterClass<"AMDGPU", SGPR_64.RegTypes, 32, (add (trunc SGPR_64, 15))> { 814 let CopyCost = SGPR_64.CopyCost; 815 let AllocationPriority = SGPR_64.AllocationPriority; 816 let HasSGPR = 1; 817} 818 819// Call clobbered 64-bit SGPRs for AMDGPU_Gfx CC 820def Gfx_CCR_SGPR_64 : SIRegisterClass<"AMDGPU", SGPR_64.RegTypes, 32, 821 (add (trunc (shl SGPR_64, 18), 14))> { // s[36:37]-s[s62:63] 822 let CopyCost = SGPR_64.CopyCost; 823 let AllocationPriority = SGPR_64.AllocationPriority; 824 let HasSGPR = 1; 825} 826 827def TTMP_64 : SIRegisterClass<"AMDGPU", [v2i32, i64, f64, v4i16, v4f16], 32, 828 (add TTMP_64Regs)> { 829 let isAllocatable = 0; 830 let HasSGPR = 1; 831} 832 833def SReg_64_XEXEC : SIRegisterClass<"AMDGPU", [v2i32, i64, v2f32, f64, i1, v4i16, v4f16], 32, 834 (add SGPR_64, VCC, FLAT_SCR, XNACK_MASK, SGPR_NULL64, SRC_SHARED_BASE, 835 SRC_SHARED_LIMIT, SRC_PRIVATE_BASE, SRC_PRIVATE_LIMIT, TTMP_64, TBA, TMA)> { 836 let CopyCost = 1; 837 let AllocationPriority = 1; 838 let HasSGPR = 1; 839} 840 841def SReg_64 : SIRegisterClass<"AMDGPU", [v2i32, i64, v2f32, f64, i1, v4i16, v4f16], 32, 842 (add SReg_64_XEXEC, EXEC)> { 843 let CopyCost = 1; 844 let AllocationPriority = 1; 845 let HasSGPR = 1; 846 let BaseClassOrder = 64; 847} 848 849def SReg_1_XEXEC : SIRegisterClass<"AMDGPU", [i1], 32, 850 (add SReg_64_XEXEC, SReg_32_XEXEC)> { 851 let CopyCost = 1; 852 let isAllocatable = 0; 853 let HasSGPR = 1; 854} 855 856def SReg_1 : SIRegisterClass<"AMDGPU", [i1], 32, 857 (add SReg_1_XEXEC, EXEC, EXEC_LO, EXEC_HI)> { 858 let CopyCost = 1; 859 let isAllocatable = 0; 860 let HasSGPR = 1; 861} 862 863multiclass SRegClass<int numRegs, 864 list<ValueType> regTypes, 865 SIRegisterTuples regList, 866 SIRegisterTuples ttmpList = regList, 867 int copyCost = !sra(!add(numRegs, 1), 1)> { 868 defvar hasTTMP = !ne(regList, ttmpList); 869 defvar suffix = !cast<string>(!mul(numRegs, 32)); 870 defvar sgprName = !strconcat("SGPR_", suffix); 871 defvar ttmpName = !strconcat("TTMP_", suffix); 872 873 let AllocationPriority = !sub(numRegs, 1), CopyCost = copyCost, HasSGPR = 1 in { 874 def "" # sgprName : SIRegisterClass<"AMDGPU", regTypes, 32, (add regList)> { 875 } 876 877 if hasTTMP then { 878 def "" # ttmpName : SIRegisterClass<"AMDGPU", regTypes, 32, (add ttmpList)> { 879 let isAllocatable = 0; 880 } 881 } 882 883 def SReg_ # suffix : 884 SIRegisterClass<"AMDGPU", regTypes, 32, 885 !con(!dag(add, [!cast<RegisterClass>(sgprName)], ["sgpr"]), 886 !if(hasTTMP, 887 !dag(add, [!cast<RegisterClass>(ttmpName)], ["ttmp"]), 888 (add)))> { 889 let isAllocatable = 0; 890 let BaseClassOrder = !mul(numRegs, 32); 891 } 892 } 893} 894 895defm "" : SRegClass<3, [v3i32, v3f32], SGPR_96Regs, TTMP_96Regs>; 896defm "" : SRegClass<4, [v4i32, v4f32, v2i64, v2f64, v8i16, v8f16], SGPR_128Regs, TTMP_128Regs>; 897defm "" : SRegClass<5, [v5i32, v5f32], SGPR_160Regs, TTMP_160Regs>; 898defm "" : SRegClass<6, [v6i32, v6f32, v3i64, v3f64], SGPR_192Regs, TTMP_192Regs>; 899defm "" : SRegClass<7, [v7i32, v7f32], SGPR_224Regs, TTMP_224Regs>; 900defm "" : SRegClass<8, [v8i32, v8f32, v4i64, v4f64, v16i16, v16f16], SGPR_256Regs, TTMP_256Regs>; 901defm "" : SRegClass<9, [v9i32, v9f32], SGPR_288Regs, TTMP_288Regs>; 902defm "" : SRegClass<10, [v10i32, v10f32], SGPR_320Regs, TTMP_320Regs>; 903defm "" : SRegClass<11, [v11i32, v11f32], SGPR_352Regs, TTMP_352Regs>; 904defm "" : SRegClass<12, [v12i32, v12f32], SGPR_384Regs, TTMP_384Regs>; 905 906let GlobalPriority = true in { 907defm "" : SRegClass<16, [v16i32, v16f32, v8i64, v8f64], SGPR_512Regs, TTMP_512Regs>; 908defm "" : SRegClass<32, [v32i32, v32f32, v16i64, v16f64], SGPR_1024Regs>; 909} 910 911def VRegOrLds_32 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, 912 (add VGPR_32, LDS_DIRECT_CLASS)> { 913 let isAllocatable = 0; 914 let HasVGPR = 1; 915} 916 917// Register class for all vector registers (VGPRs + Interpolation Registers) 918class VRegClassBase<int numRegs, list<ValueType> regTypes, dag regList> : 919 SIRegisterClass<"AMDGPU", regTypes, 32, regList> { 920 let Size = !mul(numRegs, 32); 921 922 // Requires n v_mov_b32 to copy 923 let CopyCost = numRegs; 924 let AllocationPriority = !sub(numRegs, 1); 925 let Weight = numRegs; 926} 927 928// Define a register tuple class, along with one requiring an even 929// aligned base register. 930multiclass VRegClass<int numRegs, list<ValueType> regTypes, dag regList> { 931 let HasVGPR = 1 in { 932 // Define the regular class. 933 def "" : VRegClassBase<numRegs, regTypes, regList> { 934 let BaseClassOrder = !mul(numRegs, 32); 935 } 936 937 // Define 2-aligned variant 938 def _Align2 : VRegClassBase<numRegs, regTypes, (decimate regList, 2)> { 939 // Give aligned class higher priority in base class resolution 940 let BaseClassOrder = !sub(!mul(numRegs, 32), 1); 941 let RegTupleAlignUnits = 2; 942 } 943 } 944} 945 946defm VReg_64 : VRegClass<2, [i64, f64, v2i32, v2f32, v4f16, v4i16, p0, p1, p4], 947 (add VGPR_64)>; 948defm VReg_96 : VRegClass<3, [v3i32, v3f32], (add VGPR_96)>; 949defm VReg_128 : VRegClass<4, [v4i32, v4f32, v2i64, v2f64, v8i16, v8f16], (add VGPR_128)>; 950defm VReg_160 : VRegClass<5, [v5i32, v5f32], (add VGPR_160)>; 951 952defm VReg_192 : VRegClass<6, [v6i32, v6f32, v3i64, v3f64], (add VGPR_192)>; 953defm VReg_224 : VRegClass<7, [v7i32, v7f32], (add VGPR_224)>; 954defm VReg_256 : VRegClass<8, [v8i32, v8f32, v4i64, v4f64, v16i16, v16f16], (add VGPR_256)>; 955defm VReg_288 : VRegClass<9, [v9i32, v9f32], (add VGPR_288)>; 956defm VReg_320 : VRegClass<10, [v10i32, v10f32], (add VGPR_320)>; 957defm VReg_352 : VRegClass<11, [v11i32, v11f32], (add VGPR_352)>; 958defm VReg_384 : VRegClass<12, [v12i32, v12f32], (add VGPR_384)>; 959 960let GlobalPriority = true in { 961defm VReg_512 : VRegClass<16, [v16i32, v16f32, v8i64, v8f64], (add VGPR_512)>; 962defm VReg_1024 : VRegClass<32, [v32i32, v32f32, v16i64, v16f64], (add VGPR_1024)>; 963} 964 965multiclass ARegClass<int numRegs, list<ValueType> regTypes, dag regList> { 966 let CopyCost = !add(numRegs, numRegs, 1), HasAGPR = 1 in { 967 // Define the regular class. 968 def "" : VRegClassBase<numRegs, regTypes, regList> { 969 let BaseClassOrder = !mul(numRegs, 32); 970 } 971 972 // Define 2-aligned variant 973 def _Align2 : VRegClassBase<numRegs, regTypes, (decimate regList, 2)> { 974 // Give aligned class higher priority in base class resolution 975 let BaseClassOrder = !sub(!mul(numRegs, 32), 1); 976 let RegTupleAlignUnits = 2; 977 } 978 } 979} 980 981defm AReg_64 : ARegClass<2, [i64, f64, v2i32, v2f32, v4f16, v4i16], 982 (add AGPR_64)>; 983defm AReg_96 : ARegClass<3, [v3i32, v3f32], (add AGPR_96)>; 984defm AReg_128 : ARegClass<4, [v4i32, v4f32, v2i64, v2f64, v8i16, v8f16], (add AGPR_128)>; 985defm AReg_160 : ARegClass<5, [v5i32, v5f32], (add AGPR_160)>; 986defm AReg_192 : ARegClass<6, [v6i32, v6f32, v3i64, v3f64], (add AGPR_192)>; 987defm AReg_224 : ARegClass<7, [v7i32, v7f32], (add AGPR_224)>; 988defm AReg_256 : ARegClass<8, [v8i32, v8f32, v4i64, v4f64], (add AGPR_256)>; 989defm AReg_288 : ARegClass<9, [v9i32, v9f32], (add AGPR_288)>; 990defm AReg_320 : ARegClass<10, [v10i32, v10f32], (add AGPR_320)>; 991defm AReg_352 : ARegClass<11, [v11i32, v11f32], (add AGPR_352)>; 992defm AReg_384 : ARegClass<12, [v12i32, v12f32], (add AGPR_384)>; 993 994let GlobalPriority = true in { 995defm AReg_512 : ARegClass<16, [v16i32, v16f32, v8i64, v8f64], (add AGPR_512)>; 996defm AReg_1024 : ARegClass<32, [v32i32, v32f32, v16i64, v16f64], (add AGPR_1024)>; 997} 998 999} // End GeneratePressureSet = 0 1000 1001let GeneratePressureSet = 0 in { 1002// No register should ever be allocated using VReg_1. This is a hack for 1003// SelectionDAG that should always be lowered by SILowerI1Copies. TableGen 1004// sorts register classes based on the number of registers in them so this is 1005// sorted to the end and not preferred over VGPR_32. 1006def VReg_1 : SIRegisterClass<"AMDGPU", [i1], 32, (add)> { 1007 let Size = 1; 1008 let HasVGPR = 1; 1009} 1010 1011def VS_32 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, 1012 (add VGPR_32, SReg_32, LDS_DIRECT_CLASS)> { 1013 let isAllocatable = 0; 1014 let HasVGPR = 1; 1015 let HasSGPR = 1; 1016} 1017 1018def VS_32_Lo128 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, 1019 (add VGPR_32_Lo128, SReg_32, LDS_DIRECT_CLASS)> { 1020 let isAllocatable = 0; 1021 let HasVGPR = 1; 1022 let HasSGPR = 1; 1023} 1024 1025def VS_64 : SIRegisterClass<"AMDGPU", [i64, f64, v2f32], 32, (add VReg_64, SReg_64)> { 1026 let isAllocatable = 0; 1027 let HasVGPR = 1; 1028 let HasSGPR = 1; 1029} 1030 1031def AV_32 : SIRegisterClass<"AMDGPU", VGPR_32.RegTypes, 32, (add VGPR_32, AGPR_32)> { 1032 let HasVGPR = 1; 1033 let HasAGPR = 1; 1034} 1035} // End GeneratePressureSet = 0 1036 1037// Define a register tuple class, along with one requiring an even 1038// aligned base register. 1039multiclass AVRegClass<int numRegs, list<ValueType> regTypes, 1040 dag vregList, dag aregList> { 1041 let HasVGPR = 1, HasAGPR = 1 in { 1042 // Define the regular class. 1043 def "" : VRegClassBase<numRegs, regTypes, (add vregList, aregList)>; 1044 1045 // Define 2-aligned variant 1046 def _Align2 : VRegClassBase<numRegs, regTypes, 1047 (add (decimate vregList, 2), 1048 (decimate aregList, 2))> { 1049 let RegTupleAlignUnits = 2; 1050 } 1051 } 1052} 1053 1054defm AV_64 : AVRegClass<2, VReg_64.RegTypes, (add VGPR_64), (add AGPR_64)>; 1055defm AV_96 : AVRegClass<3, VReg_96.RegTypes, (add VGPR_96), (add AGPR_96)>; 1056defm AV_128 : AVRegClass<4, VReg_128.RegTypes, (add VGPR_128), (add AGPR_128)>; 1057defm AV_160 : AVRegClass<5, VReg_160.RegTypes, (add VGPR_160), (add AGPR_160)>; 1058defm AV_192 : AVRegClass<6, VReg_192.RegTypes, (add VGPR_192), (add AGPR_192)>; 1059defm AV_224 : AVRegClass<7, VReg_224.RegTypes, (add VGPR_224), (add AGPR_224)>; 1060defm AV_256 : AVRegClass<8, VReg_256.RegTypes, (add VGPR_256), (add AGPR_256)>; 1061defm AV_288 : AVRegClass<9, VReg_288.RegTypes, (add VGPR_288), (add AGPR_288)>; 1062defm AV_320 : AVRegClass<10, VReg_320.RegTypes, (add VGPR_320), (add AGPR_320)>; 1063defm AV_352 : AVRegClass<11, VReg_352.RegTypes, (add VGPR_352), (add AGPR_352)>; 1064defm AV_384 : AVRegClass<12, VReg_384.RegTypes, (add VGPR_384), (add AGPR_384)>; 1065 1066let GlobalPriority = true in { 1067defm AV_512 : AVRegClass<16, VReg_512.RegTypes, (add VGPR_512), (add AGPR_512)>; 1068defm AV_1024 : AVRegClass<32, VReg_1024.RegTypes, (add VGPR_1024), (add AGPR_1024)>; 1069} 1070 1071//===----------------------------------------------------------------------===// 1072// Register operands 1073//===----------------------------------------------------------------------===// 1074 1075class RegImmMatcher<string name> : AsmOperandClass { 1076 let Name = name; 1077 let RenderMethod = "addRegOrImmOperands"; 1078} 1079 1080class RegOrImmOperand <string RegisterClassName, string OperandTypeName, 1081 string ParserMatchClassName, string decoderImmSize> 1082 : RegisterOperand<!cast<RegisterClass>(RegisterClassName)> { 1083 let OperandNamespace = "AMDGPU"; 1084 let OperandType = OperandTypeName; 1085 let ParserMatchClass = RegImmMatcher<ParserMatchClassName>; 1086 let DecoderMethod = "decodeOperand_" # RegisterClassName # decoderImmSize; 1087 } 1088 1089class RegOrB16 <string RegisterClass, string OperandTypePrefix> 1090 : RegOrImmOperand <RegisterClass, OperandTypePrefix # "_INT16", 1091 !subst("_b16", "B16", NAME), "_Imm16">; 1092 1093class RegOrF16 <string RegisterClass, string OperandTypePrefix> 1094 : RegOrImmOperand <RegisterClass, OperandTypePrefix # "_FP16", 1095 !subst("_f16", "F16", NAME), "_Imm16">; 1096 1097class RegOrB32 <string RegisterClass, string OperandTypePrefix> 1098 : RegOrImmOperand <RegisterClass, OperandTypePrefix # "_INT32", 1099 !subst("_b32", "B32", NAME), "_Imm32">; 1100 1101class RegOrF32 <string RegisterClass, string OperandTypePrefix> 1102 : RegOrImmOperand <RegisterClass, OperandTypePrefix # "_FP32", 1103 !subst("_f32", "F32", NAME), "_Imm32">; 1104 1105class RegOrV2B16 <string RegisterClass, string OperandTypePrefix> 1106 : RegOrImmOperand <RegisterClass, OperandTypePrefix # "_V2INT16", 1107 !subst("_v2b16", "V2B16", NAME), "_Imm16">; 1108 1109class RegOrV2F16 <string RegisterClass, string OperandTypePrefix> 1110 : RegOrImmOperand <RegisterClass, OperandTypePrefix # "_V2FP16", 1111 !subst("_v2f16", "V2F16", NAME), "_Imm16">; 1112 1113class RegOrF64 <string RegisterClass, string OperandTypePrefix> 1114 : RegOrImmOperand <RegisterClass, OperandTypePrefix # "_FP64", 1115 !subst("_f64", "F64", NAME), "_Imm64">; 1116 1117class RegOrB64 <string RegisterClass, string OperandTypePrefix> 1118 : RegOrImmOperand <RegisterClass, OperandTypePrefix # "_INT64", 1119 !subst("_b64", "B64", NAME), "_Imm64">; 1120 1121class RegOrV2F32 <string RegisterClass, string OperandTypePrefix> 1122 : RegOrImmOperand <RegisterClass, OperandTypePrefix # "_V2FP32", 1123 !subst("_v2f32", "V2FP32", NAME), "_Imm32">; 1124 1125class RegOrV2B32 <string RegisterClass, string OperandTypePrefix> 1126 : RegOrImmOperand <RegisterClass, OperandTypePrefix # "_V2INT32", 1127 !subst("_v2b32", "V2INT32", NAME), "_Imm32">; 1128 1129// For VOP1,2,C True16 instructions. _Lo128 use first 128 32-bit VGPRs only. 1130class RegOrB16_Lo128 <string RegisterClass, string OperandTypePrefix> 1131 : RegOrImmOperand <RegisterClass, OperandTypePrefix # "_INT16", 1132 !subst("_b16_Lo128", "B16_Lo128", NAME), "_Imm16">; 1133 1134class RegOrF16_Lo128 <string RegisterClass, string OperandTypePrefix> 1135 : RegOrImmOperand <RegisterClass, OperandTypePrefix # "_FP16", 1136 !subst("_f16_Lo128", "F16_Lo128", NAME), "_Imm16">; 1137 1138// Deferred operands 1139class RegOrF16_Deferred <string RegisterClass, string OperandTypePrefix> 1140 : RegOrImmOperand <RegisterClass, OperandTypePrefix # "_FP16_DEFERRED", 1141 !subst("_f16_Deferred", "F16", NAME), "_Deferred_Imm16">; 1142 1143class RegOrF32_Deferred <string RegisterClass, string OperandTypePrefix> 1144 : RegOrImmOperand <RegisterClass, OperandTypePrefix # "_FP32_DEFERRED", 1145 !subst("_f32_Deferred", "F32", NAME), "_Deferred_Imm32">; 1146 1147class RegOrF16_Lo128_Deferred <string RegisterClass, 1148 string OperandTypePrefix> 1149 : RegOrImmOperand <RegisterClass, OperandTypePrefix # "_FP16_DEFERRED", 1150 !subst("_f16_Lo128_Deferred", "F16_Lo128", NAME), 1151 "_Deferred_Imm16">; 1152//===----------------------------------------------------------------------===// 1153// SSrc_* Operands with an SGPR or a 32-bit immediate 1154//===----------------------------------------------------------------------===// 1155 1156def SSrc_b32 : RegOrB32 <"SReg_32", "OPERAND_REG_IMM">; 1157def SSrc_f32 : RegOrF32 <"SReg_32", "OPERAND_REG_IMM">; 1158def SSrc_b64 : RegOrB64 <"SReg_64", "OPERAND_REG_IMM">; 1159 1160def SSrcOrLds_b32 : RegOrB32 <"SRegOrLds_32", "OPERAND_REG_IMM">; 1161 1162//===----------------------------------------------------------------------===// 1163// SCSrc_* Operands with an SGPR or a inline constant 1164//===----------------------------------------------------------------------===// 1165 1166def SCSrc_b32 : RegOrB32 <"SReg_32", "OPERAND_REG_INLINE_C">; 1167def SCSrc_b64 : RegOrB64 <"SReg_64", "OPERAND_REG_INLINE_C">; 1168 1169//===----------------------------------------------------------------------===// 1170// VSrc_* Operands with an SGPR, VGPR or a 32-bit immediate 1171//===----------------------------------------------------------------------===// 1172 1173def VSrc_b16 : RegOrB16 <"VS_32", "OPERAND_REG_IMM">; 1174def VSrc_f16 : RegOrF16 <"VS_32", "OPERAND_REG_IMM">; 1175def VSrc_b32 : RegOrB32 <"VS_32", "OPERAND_REG_IMM">; 1176def VSrc_f32 : RegOrF32 <"VS_32", "OPERAND_REG_IMM">; 1177def VSrc_v2b16 : RegOrV2B16 <"VS_32", "OPERAND_REG_IMM">; 1178def VSrc_v2f16 : RegOrV2F16 <"VS_32", "OPERAND_REG_IMM">; 1179def VSrc_b64 : RegOrB64 <"VS_64", "OPERAND_REG_IMM">; 1180def VSrc_f64 : RegOrF64 <"VS_64", "OPERAND_REG_IMM">; 1181def VSrc_v2b32 : RegOrV2B32 <"VS_64", "OPERAND_REG_IMM">; 1182def VSrc_v2f32 : RegOrV2F32 <"VS_64", "OPERAND_REG_IMM">; 1183 1184def VSrcT_b16_Lo128 : RegOrB16_Lo128 <"VS_32_Lo128", "OPERAND_REG_IMM">; 1185def VSrcT_f16_Lo128 : RegOrF16_Lo128 <"VS_32_Lo128", "OPERAND_REG_IMM">; 1186 1187//===----------------------------------------------------------------------===// 1188// VSrc_*_Deferred Operands with an SGPR, VGPR or a 32-bit immediate for use 1189// with FMAMK/FMAAK 1190//===----------------------------------------------------------------------===// 1191 1192def VSrc_f16_Deferred : RegOrF16_Deferred<"VS_32", "OPERAND_REG_IMM">; 1193def VSrc_f32_Deferred : RegOrF32_Deferred<"VS_32", "OPERAND_REG_IMM">; 1194 1195def VSrcT_f16_Lo128_Deferred : RegOrF16_Lo128_Deferred<"VS_32_Lo128", 1196 "OPERAND_REG_IMM">; 1197 1198//===----------------------------------------------------------------------===// 1199// VRegSrc_* Operands with a VGPR 1200//===----------------------------------------------------------------------===// 1201 1202// This is for operands with the enum(9), VSrc encoding restriction, 1203// but only allows VGPRs. 1204def VRegSrc_32 : RegisterOperand<VGPR_32> { 1205 let DecoderMethod = "decodeOperand_VGPR_32"; 1206} 1207 1208def VRegSrc_64 : RegisterOperand<VReg_64> { 1209 let DecoderMethod = "decodeOperand_VReg_64"; 1210} 1211 1212def VRegSrc_128 : RegisterOperand<VReg_128> { 1213 let DecoderMethod = "decodeOperand_VReg_128"; 1214} 1215 1216def VRegSrc_256 : RegisterOperand<VReg_256> { 1217 let DecoderMethod = "decodeOperand_VReg_256"; 1218} 1219 1220def VRegOrLdsSrc_32 : RegisterOperand<VRegOrLds_32> { 1221 let DecoderMethod = "decodeOperand_VRegOrLds_32"; 1222} 1223 1224//===----------------------------------------------------------------------===// 1225// VGPRSrc_* 1226//===----------------------------------------------------------------------===// 1227 1228// An 8-bit RegisterOperand wrapper for a VGPR 1229def VGPRSrc_32 : RegisterOperand<VGPR_32> { 1230 let DecoderMethod = "DecodeVGPR_32RegisterClass"; 1231} 1232def VGPRSrc_32_Lo128 : RegisterOperand<VGPR_32_Lo128> { 1233 let DecoderMethod = "DecodeVGPR_32RegisterClass"; 1234} 1235 1236//===----------------------------------------------------------------------===// 1237// ASrc_* Operands with an AccVGPR 1238//===----------------------------------------------------------------------===// 1239 1240def ARegSrc_32 : RegisterOperand<AGPR_32> { 1241 let DecoderMethod = "decodeOperand_AGPR_32"; 1242 let EncoderMethod = "getAVOperandEncoding"; 1243} 1244 1245//===----------------------------------------------------------------------===// 1246// VCSrc_* Operands with an SGPR, VGPR or an inline constant 1247//===----------------------------------------------------------------------===// 1248 1249def VCSrc_b16 : RegOrB16 <"VS_32", "OPERAND_REG_INLINE_C">; 1250def VCSrc_f16 : RegOrF16 <"VS_32", "OPERAND_REG_INLINE_C">; 1251def VCSrc_b32 : RegOrB32 <"VS_32", "OPERAND_REG_INLINE_C">; 1252def VCSrc_f32 : RegOrF32 <"VS_32", "OPERAND_REG_INLINE_C">; 1253def VCSrc_v2b16 : RegOrV2B16 <"VS_32", "OPERAND_REG_INLINE_C">; 1254def VCSrc_v2f16 : RegOrV2F16 <"VS_32", "OPERAND_REG_INLINE_C">; 1255 1256//===----------------------------------------------------------------------===// 1257// VISrc_* Operands with a VGPR or an inline constant 1258//===----------------------------------------------------------------------===// 1259 1260def VISrc_64_f64 : RegOrF64 <"VReg_64", "OPERAND_REG_INLINE_C">; 1261def VISrc_128_b32 : RegOrB32 <"VReg_128", "OPERAND_REG_INLINE_C">; 1262def VISrc_128_f32 : RegOrF32 <"VReg_128", "OPERAND_REG_INLINE_C">; 1263def VISrc_256_f64 : RegOrF64 <"VReg_256", "OPERAND_REG_INLINE_C">; 1264def VISrc_512_b32 : RegOrB32 <"VReg_512", "OPERAND_REG_INLINE_C">; 1265def VISrc_512_f32 : RegOrF32 <"VReg_512", "OPERAND_REG_INLINE_C">; 1266def VISrc_1024_b32 : RegOrB32 <"VReg_1024", "OPERAND_REG_INLINE_C">; 1267def VISrc_1024_f32 : RegOrF32 <"VReg_1024", "OPERAND_REG_INLINE_C">; 1268 1269//===----------------------------------------------------------------------===// 1270// AVSrc_*, AVDst_*, AVLdSt_* Operands with an AGPR or VGPR 1271//===----------------------------------------------------------------------===// 1272 1273def AVSrc_32 : RegisterOperand<AV_32> { 1274 let DecoderMethod = "decodeOperand_AV_32"; 1275 let EncoderMethod = "getAVOperandEncoding"; 1276} 1277 1278def AVSrc_64 : RegisterOperand<AV_64> { 1279 let DecoderMethod = "decodeOperand_AV_64"; 1280 let EncoderMethod = "getAVOperandEncoding"; 1281} 1282 1283def AVSrc_128 : RegisterOperand<AV_128> { 1284 let DecoderMethod = "decodeOperand_AV_128"; 1285 let EncoderMethod = "getAVOperandEncoding"; 1286} 1287 1288def AVDst_128 : RegisterOperand<AV_128> { 1289 let DecoderMethod = "DecodeAVDst_128RegisterClass"; 1290 let EncoderMethod = "getAVOperandEncoding"; 1291} 1292 1293def AVDst_512 : RegisterOperand<AV_512> { 1294 let DecoderMethod = "DecodeAVDst_512RegisterClass"; 1295 let EncoderMethod = "getAVOperandEncoding"; 1296} 1297 1298def AVLdSt_32 : RegisterOperand<AV_32> { 1299 let DecoderMethod = "DecodeAVLdSt_32RegisterClass"; 1300 let EncoderMethod = "getAVOperandEncoding"; 1301} 1302 1303def AVLdSt_64 : RegisterOperand<AV_64> { 1304 let DecoderMethod = "DecodeAVLdSt_64RegisterClass"; 1305 let EncoderMethod = "getAVOperandEncoding"; 1306} 1307 1308def AVLdSt_96 : RegisterOperand<AV_96> { 1309 let DecoderMethod = "DecodeAVLdSt_96RegisterClass"; 1310 let EncoderMethod = "getAVOperandEncoding"; 1311} 1312 1313def AVLdSt_128 : RegisterOperand<AV_128> { 1314 let DecoderMethod = "DecodeAVLdSt_128RegisterClass"; 1315 let EncoderMethod = "getAVOperandEncoding"; 1316} 1317 1318def AVLdSt_160 : RegisterOperand<AV_160> { 1319 let DecoderMethod = "DecodeAVLdSt_160RegisterClass"; 1320 let EncoderMethod = "getAVOperandEncoding"; 1321} 1322 1323//===----------------------------------------------------------------------===// 1324// ACSrc_* Operands with an AGPR or an inline constant 1325//===----------------------------------------------------------------------===// 1326 1327def AISrc_64_f64 : RegOrF64 <"AReg_64", "OPERAND_REG_INLINE_AC">; 1328def AISrc_128_f32 : RegOrF32 <"AReg_128", "OPERAND_REG_INLINE_AC">; 1329def AISrc_128_b32 : RegOrB32 <"AReg_128", "OPERAND_REG_INLINE_AC">; 1330def AISrc_256_f64 : RegOrF64 <"AReg_256", "OPERAND_REG_INLINE_AC">; 1331def AISrc_512_f32 : RegOrF32 <"AReg_512", "OPERAND_REG_INLINE_AC">; 1332def AISrc_512_b32 : RegOrB32 <"AReg_512", "OPERAND_REG_INLINE_AC">; 1333def AISrc_1024_f32 : RegOrF32 <"AReg_1024", "OPERAND_REG_INLINE_AC">; 1334def AISrc_1024_b32 : RegOrB32 <"AReg_1024", "OPERAND_REG_INLINE_AC">; 1335