1//===-- SIRegisterInfo.td - SI Register defs ---------------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// Subregister declarations 11//===----------------------------------------------------------------------===// 12 13class Indexes<int N> { 14 list<int> all = [0, 1, 2, 3, 4, 5, 6 , 7, 15 8, 9, 10, 11, 12, 13, 14, 15, 16 16, 17, 18, 19, 20, 21, 22, 23, 17 24, 25, 26, 27, 28, 29, 30, 31]; 18 19 // Returns list of indexes [0..N) 20 list<int> slice = 21 !foldl([]<int>, all, acc, cur, 22 !listconcat(acc, !if(!lt(cur, N), [cur], []))); 23} 24 25let Namespace = "AMDGPU" in { 26 27def lo16 : SubRegIndex<16, 0>; 28def hi16 : SubRegIndex<16, 16>; 29 30foreach Index = 0-31 in { 31 def sub#Index : SubRegIndex<32, !shl(Index, 5)>; 32} 33 34foreach Index = 1-31 in { 35 def sub#Index#_lo16 : ComposedSubRegIndex<!cast<SubRegIndex>(sub#Index), lo16>; 36 def sub#Index#_hi16 : ComposedSubRegIndex<!cast<SubRegIndex>(sub#Index), hi16>; 37} 38 39foreach Size = {2-6,8,16} in { 40 foreach Index = Indexes<!add(33, !mul(Size, -1))>.slice in { 41 def !foldl("", Indexes<Size>.slice, acc, cur, 42 !strconcat(acc#!if(!eq(acc,""),"","_"), "sub"#!add(cur, Index))) : 43 SubRegIndex<!mul(Size, 32), !shl(Index, 5)> { 44 let CoveringSubRegIndices = 45 !foldl([]<SubRegIndex>, Indexes<Size>.slice, acc, cur, 46 !listconcat(acc, [!cast<SubRegIndex>(sub#!add(cur, Index))])); 47 } 48 } 49} 50 51} 52 53//===----------------------------------------------------------------------===// 54// Helpers 55//===----------------------------------------------------------------------===// 56 57class getSubRegs<int size> { 58 list<SubRegIndex> ret2 = [sub0, sub1]; 59 list<SubRegIndex> ret3 = [sub0, sub1, sub2]; 60 list<SubRegIndex> ret4 = [sub0, sub1, sub2, sub3]; 61 list<SubRegIndex> ret5 = [sub0, sub1, sub2, sub3, sub4]; 62 list<SubRegIndex> ret6 = [sub0, sub1, sub2, sub3, sub4, sub5]; 63 list<SubRegIndex> ret8 = [sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7]; 64 list<SubRegIndex> ret16 = [sub0, sub1, sub2, sub3, 65 sub4, sub5, sub6, sub7, 66 sub8, sub9, sub10, sub11, 67 sub12, sub13, sub14, sub15]; 68 list<SubRegIndex> ret32 = [sub0, sub1, sub2, sub3, 69 sub4, sub5, sub6, sub7, 70 sub8, sub9, sub10, sub11, 71 sub12, sub13, sub14, sub15, 72 sub16, sub17, sub18, sub19, 73 sub20, sub21, sub22, sub23, 74 sub24, sub25, sub26, sub27, 75 sub28, sub29, sub30, sub31]; 76 77 list<SubRegIndex> ret = !if(!eq(size, 2), ret2, 78 !if(!eq(size, 3), ret3, 79 !if(!eq(size, 4), ret4, 80 !if(!eq(size, 5), ret5, 81 !if(!eq(size, 6), ret6, 82 !if(!eq(size, 8), ret8, 83 !if(!eq(size, 16), ret16, 84 ret32))))))); 85} 86 87// Generates list of sequential register tuple names. 88// E.g. RegSeq<3,2,2,"s">.ret -> [ "s[0:1]", "s[2:3]" ] 89class RegSeqNames<int last_reg, int stride, int size, string prefix, 90 int start = 0> { 91 int next = !add(start, stride); 92 int end_reg = !add(!add(start, size), -1); 93 list<string> ret = 94 !if(!le(end_reg, last_reg), 95 !listconcat([prefix # "[" # start # ":" # end_reg # "]"], 96 RegSeqNames<last_reg, stride, size, prefix, next>.ret), 97 []); 98} 99 100// Generates list of dags for register tupless. 101class RegSeqDags<RegisterClass RC, int last_reg, int stride, int size, 102 int start = 0> { 103 dag trunc_rc = (trunc RC, 104 !if(!and(!eq(stride, 1), !eq(start, 0)), 105 !add(!add(last_reg, 2), !mul(size, -1)), 106 !add(last_reg, 1))); 107 list<dag> ret = 108 !if(!lt(start, size), 109 !listconcat([(add (decimate (shl trunc_rc, start), stride))], 110 RegSeqDags<RC, last_reg, stride, size, !add(start, 1)>.ret), 111 []); 112} 113 114class SIRegisterTuples<list<SubRegIndex> Indices, RegisterClass RC, 115 int last_reg, int stride, int size, string prefix> : 116 RegisterTuples<Indices, 117 RegSeqDags<RC, last_reg, stride, size>.ret, 118 RegSeqNames<last_reg, stride, size, prefix>.ret>; 119 120//===----------------------------------------------------------------------===// 121// Declarations that describe the SI registers 122//===----------------------------------------------------------------------===// 123class SIReg <string n, bits<16> regIdx = 0> : 124 Register<n> { 125 let Namespace = "AMDGPU"; 126 let HWEncoding = regIdx; 127} 128 129class SIRegWithSubRegs <string n, list<Register> subregs, bits<16> regIdx> : 130 RegisterWithSubRegs<n, subregs> { 131} 132 133multiclass SIRegLoHi16 <string n, bits<16> regIdx, bit ArtificialHigh = 1, 134 bit HWEncodingHigh = 0> { 135 // There is no special encoding for 16 bit subregs, these are not real 136 // registers but rather operands for instructions preserving other 16 bits 137 // of the result or reading just 16 bits of a 32 bit VGPR. 138 // It is encoded as a corresponding 32 bit register. 139 // Non-VGPR register classes use it as we need to have matching subregisters 140 // to move instructions and data between ALUs. 141 def _LO16 : SIReg<n#".l", regIdx> { 142 let HWEncoding{8} = HWEncodingHigh; 143 } 144 def _HI16 : SIReg<!if(ArtificialHigh, "", n#".h"), regIdx> { 145 let isArtificial = ArtificialHigh; 146 let HWEncoding{8} = HWEncodingHigh; 147 } 148 def "" : RegisterWithSubRegs<n, [!cast<Register>(NAME#"_LO16"), 149 !cast<Register>(NAME#"_HI16")]> { 150 let Namespace = "AMDGPU"; 151 let SubRegIndices = [lo16, hi16]; 152 let CoveredBySubRegs = !if(ArtificialHigh,0,1); 153 let HWEncoding = regIdx; 154 let HWEncoding{8} = HWEncodingHigh; 155 } 156} 157 158// Special Registers 159defm VCC_LO : SIRegLoHi16<"vcc_lo", 106>; 160defm VCC_HI : SIRegLoHi16<"vcc_hi", 107>; 161 162// Pseudo-registers: Used as placeholders during isel and immediately 163// replaced, never seeing the verifier. 164def PRIVATE_RSRC_REG : SIReg<"private_rsrc", 0>; 165def FP_REG : SIReg<"fp", 0>; 166def SP_REG : SIReg<"sp", 0>; 167 168// Pseudo-register to represent the program-counter DWARF register. 169def PC_REG : SIReg<"pc", 0>, DwarfRegNum<[16, 16]> { 170 // There is no physical register corresponding to a "program counter", but 171 // we need to encode the concept in debug information in order to represent 172 // things like the return value in unwind information. 173 let isArtificial = 1; 174} 175 176// VCC for 64-bit instructions 177def VCC : RegisterWithSubRegs<"vcc", [VCC_LO, VCC_HI]> { 178 let Namespace = "AMDGPU"; 179 let SubRegIndices = [sub0, sub1]; 180 let HWEncoding = 106; 181} 182 183defm EXEC_LO : SIRegLoHi16<"exec_lo", 126>, DwarfRegNum<[1, 1]>; 184defm EXEC_HI : SIRegLoHi16<"exec_hi", 127>; 185 186def EXEC : RegisterWithSubRegs<"exec", [EXEC_LO, EXEC_HI]>, DwarfRegNum<[17, 1]> { 187 let Namespace = "AMDGPU"; 188 let SubRegIndices = [sub0, sub1]; 189 let HWEncoding = 126; 190} 191 192// 32-bit real registers, for MC only. 193// May be used with both 32-bit and 64-bit operands. 194defm SRC_VCCZ : SIRegLoHi16<"src_vccz", 251>; 195defm SRC_EXECZ : SIRegLoHi16<"src_execz", 252>; 196defm SRC_SCC : SIRegLoHi16<"src_scc", 253>; 197 198// 1-bit pseudo register, for codegen only. 199// Should never be emitted. 200def SCC : SIReg<"scc">; 201 202defm M0 : SIRegLoHi16 <"m0", 124>; 203defm SGPR_NULL : SIRegLoHi16 <"null", 125>; 204 205defm SRC_SHARED_BASE : SIRegLoHi16<"src_shared_base", 235>; 206defm SRC_SHARED_LIMIT : SIRegLoHi16<"src_shared_limit", 236>; 207defm SRC_PRIVATE_BASE : SIRegLoHi16<"src_private_base", 237>; 208defm SRC_PRIVATE_LIMIT : SIRegLoHi16<"src_private_limit", 238>; 209defm SRC_POPS_EXITING_WAVE_ID : SIRegLoHi16<"src_pops_exiting_wave_id", 239>; 210 211// Not addressable 212def MODE : SIReg <"mode", 0>; 213 214def LDS_DIRECT : SIReg <"src_lds_direct", 254> { 215 // There is no physical register corresponding to this. This is an 216 // encoding value in a source field, which will ultimately trigger a 217 // read from m0. 218 let isArtificial = 1; 219} 220 221defm XNACK_MASK_LO : SIRegLoHi16<"xnack_mask_lo", 104>; 222defm XNACK_MASK_HI : SIRegLoHi16<"xnack_mask_hi", 105>; 223 224def XNACK_MASK : 225 RegisterWithSubRegs<"xnack_mask", [XNACK_MASK_LO, XNACK_MASK_HI]> { 226 let Namespace = "AMDGPU"; 227 let SubRegIndices = [sub0, sub1]; 228 let HWEncoding = 104; 229} 230 231// Trap handler registers 232defm TBA_LO : SIRegLoHi16<"tba_lo", 108>; 233defm TBA_HI : SIRegLoHi16<"tba_hi", 109>; 234 235def TBA : RegisterWithSubRegs<"tba", [TBA_LO, TBA_HI]> { 236 let Namespace = "AMDGPU"; 237 let SubRegIndices = [sub0, sub1]; 238 let HWEncoding = 108; 239} 240 241defm TMA_LO : SIRegLoHi16<"tma_lo", 110>; 242defm TMA_HI : SIRegLoHi16<"tma_hi", 111>; 243 244def TMA : RegisterWithSubRegs<"tma", [TMA_LO, TMA_HI]> { 245 let Namespace = "AMDGPU"; 246 let SubRegIndices = [sub0, sub1]; 247 let HWEncoding = 110; 248} 249 250foreach Index = 0-15 in { 251 defm TTMP#Index#_vi : SIRegLoHi16<"ttmp"#Index, !add(112, Index)>; 252 defm TTMP#Index#_gfx9_gfx10 : SIRegLoHi16<"ttmp"#Index, !add(108, Index)>; 253 defm TTMP#Index : SIRegLoHi16<"ttmp"#Index, 0>; 254} 255 256multiclass FLAT_SCR_LOHI_m <string n, bits<16> ci_e, bits<16> vi_e> { 257 defm _ci : SIRegLoHi16<n, ci_e>; 258 defm _vi : SIRegLoHi16<n, vi_e>; 259 defm "" : SIRegLoHi16<n, 0>; 260} 261 262class FlatReg <Register lo, Register hi, bits<16> encoding> : 263 RegisterWithSubRegs<"flat_scratch", [lo, hi]> { 264 let Namespace = "AMDGPU"; 265 let SubRegIndices = [sub0, sub1]; 266 let HWEncoding = encoding; 267} 268 269defm FLAT_SCR_LO : FLAT_SCR_LOHI_m<"flat_scratch_lo", 104, 102>; // Offset in units of 256-bytes. 270defm FLAT_SCR_HI : FLAT_SCR_LOHI_m<"flat_scratch_hi", 105, 103>; // Size is the per-thread scratch size, in bytes. 271 272def FLAT_SCR_ci : FlatReg<FLAT_SCR_LO_ci, FLAT_SCR_HI_ci, 104>; 273def FLAT_SCR_vi : FlatReg<FLAT_SCR_LO_vi, FLAT_SCR_HI_vi, 102>; 274def FLAT_SCR : FlatReg<FLAT_SCR_LO, FLAT_SCR_HI, 0>; 275 276// SGPR registers 277foreach Index = 0-105 in { 278 defm SGPR#Index : 279 SIRegLoHi16 <"s"#Index, Index>, 280 DwarfRegNum<[!if(!le(Index, 63), !add(Index, 32), !add(Index, 1024)), 281 !if(!le(Index, 63), !add(Index, 32), !add(Index, 1024))]>; 282} 283 284// VGPR registers 285foreach Index = 0-255 in { 286 defm VGPR#Index : 287 SIRegLoHi16 <"v"#Index, Index, 0, 1>, 288 DwarfRegNum<[!add(Index, 2560), !add(Index, 1536)]>; 289} 290 291// AccVGPR registers 292foreach Index = 0-255 in { 293 defm AGPR#Index : 294 SIRegLoHi16 <"a"#Index, Index, 1, 1>, 295 DwarfRegNum<[!add(Index, 3072), !add(Index, 2048)]>; 296} 297 298//===----------------------------------------------------------------------===// 299// Groupings using register classes and tuples 300//===----------------------------------------------------------------------===// 301 302def SCC_CLASS : RegisterClass<"AMDGPU", [i1], 1, (add SCC)> { 303 let CopyCost = -1; 304 let isAllocatable = 0; 305} 306 307def M0_CLASS : RegisterClass<"AMDGPU", [i32], 32, (add M0)> { 308 let CopyCost = 1; 309 let isAllocatable = 0; 310} 311 312def M0_CLASS_LO16 : RegisterClass<"AMDGPU", [i16, f16], 16, (add M0_LO16)> { 313 let CopyCost = 1; 314 let Size = 16; 315 let isAllocatable = 0; 316} 317 318// TODO: Do we need to set DwarfRegAlias on register tuples? 319 320def SGPR_LO16 : RegisterClass<"AMDGPU", [i16, f16], 16, 321 (add (sequence "SGPR%u_LO16", 0, 105))> { 322 let AllocationPriority = 9; 323 let Size = 16; 324 let GeneratePressureSet = 0; 325} 326 327def SGPR_HI16 : RegisterClass<"AMDGPU", [i16, f16], 16, 328 (add (sequence "SGPR%u_HI16", 0, 105))> { 329 let isAllocatable = 0; 330 let Size = 16; 331 let GeneratePressureSet = 0; 332} 333 334// SGPR 32-bit registers 335def SGPR_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, 336 (add (sequence "SGPR%u", 0, 105))> { 337 // Give all SGPR classes higher priority than VGPR classes, because 338 // we want to spill SGPRs to VGPRs. 339 let AllocationPriority = 9; 340 let GeneratePressureSet = 0; 341} 342 343// SGPR 64-bit registers 344def SGPR_64Regs : SIRegisterTuples<getSubRegs<2>.ret, SGPR_32, 105, 2, 2, "s">; 345 346// SGPR 96-bit registers. No operations use these, but for symmetry with 96-bit VGPRs. 347def SGPR_96Regs : SIRegisterTuples<getSubRegs<3>.ret, SGPR_32, 105, 3, 3, "s">; 348 349// SGPR 128-bit registers 350def SGPR_128Regs : SIRegisterTuples<getSubRegs<4>.ret, SGPR_32, 105, 4, 4, "s">; 351 352// SGPR 160-bit registers. No operations use these, but for symmetry with 160-bit VGPRs. 353def SGPR_160Regs : SIRegisterTuples<getSubRegs<5>.ret, SGPR_32, 105, 4, 5, "s">; 354 355// SGPR 192-bit registers 356def SGPR_192Regs : SIRegisterTuples<getSubRegs<6>.ret, SGPR_32, 105, 4, 6, "s">; 357 358// SGPR 256-bit registers 359def SGPR_256Regs : SIRegisterTuples<getSubRegs<8>.ret, SGPR_32, 105, 4, 8, "s">; 360 361// SGPR 512-bit registers 362def SGPR_512Regs : SIRegisterTuples<getSubRegs<16>.ret, SGPR_32, 105, 4, 16, "s">; 363 364// SGPR 1024-bit registers 365def SGPR_1024Regs : SIRegisterTuples<getSubRegs<32>.ret, SGPR_32, 105, 4, 32, "s">; 366 367// Trap handler TMP 32-bit registers 368def TTMP_32 : RegisterClass<"AMDGPU", [i32, f32, v2i16, v2f16], 32, 369 (add (sequence "TTMP%u", 0, 15))> { 370 let isAllocatable = 0; 371} 372 373def TTMP_LO16 : RegisterClass<"AMDGPU", [i16, f16], 16, 374 (add (sequence "TTMP%u_LO16", 0, 15))> { 375 let Size = 16; 376 let isAllocatable = 0; 377} 378 379// Trap handler TMP 64-bit registers 380def TTMP_64Regs : SIRegisterTuples<getSubRegs<2>.ret, TTMP_32, 15, 2, 2, "ttmp">; 381 382// Trap handler TMP 128-bit registers 383def TTMP_128Regs : SIRegisterTuples<getSubRegs<4>.ret, TTMP_32, 15, 4, 4, "ttmp">; 384 385def TTMP_256Regs : SIRegisterTuples<getSubRegs<8>.ret, TTMP_32, 15, 4, 8, "ttmp">; 386 387def TTMP_512Regs : SIRegisterTuples<getSubRegs<16>.ret, TTMP_32, 15, 4, 16, "ttmp">; 388 389class TmpRegTuplesBase<int index, int size, 390 list<Register> subRegs, 391 list<SubRegIndex> indices = getSubRegs<size>.ret, 392 int index1 = !add(index, !add(size, -1)), 393 string name = "ttmp["#index#":"#index1#"]"> : 394 RegisterWithSubRegs<name, subRegs> { 395 let HWEncoding = subRegs[0].HWEncoding; 396 let SubRegIndices = indices; 397} 398 399class TmpRegTuples<string tgt, 400 int size, 401 int index0, 402 int index1 = !add(index0, 1), 403 int index2 = !add(index0, !if(!eq(size, 2), 1, 2)), 404 int index3 = !add(index0, !if(!eq(size, 2), 1, 3)), 405 int index4 = !add(index0, !if(!eq(size, 8), 4, 1)), 406 int index5 = !add(index0, !if(!eq(size, 8), 5, 1)), 407 int index6 = !add(index0, !if(!eq(size, 8), 6, 1)), 408 int index7 = !add(index0, !if(!eq(size, 8), 7, 1)), 409 Register r0 = !cast<Register>("TTMP"#index0#tgt), 410 Register r1 = !cast<Register>("TTMP"#index1#tgt), 411 Register r2 = !cast<Register>("TTMP"#index2#tgt), 412 Register r3 = !cast<Register>("TTMP"#index3#tgt), 413 Register r4 = !cast<Register>("TTMP"#index4#tgt), 414 Register r5 = !cast<Register>("TTMP"#index5#tgt), 415 Register r6 = !cast<Register>("TTMP"#index6#tgt), 416 Register r7 = !cast<Register>("TTMP"#index7#tgt)> : 417 TmpRegTuplesBase<index0, size, 418 !if(!eq(size, 2), [r0, r1], 419 !if(!eq(size, 4), [r0, r1, r2, r3], 420 [r0, r1, r2, r3, r4, r5, r6, r7])), 421 getSubRegs<size>.ret>; 422 423foreach Index = {0, 2, 4, 6, 8, 10, 12, 14} in { 424 def TTMP#Index#_TTMP#!add(Index,1)#_vi : TmpRegTuples<"_vi", 2, Index>; 425 def TTMP#Index#_TTMP#!add(Index,1)#_gfx9_gfx10 : TmpRegTuples<"_gfx9_gfx10", 2, Index>; 426} 427 428foreach Index = {0, 4, 8, 12} in { 429 def TTMP#Index#_TTMP#!add(Index,1)# 430 _TTMP#!add(Index,2)# 431 _TTMP#!add(Index,3)#_vi : TmpRegTuples<"_vi", 4, Index>; 432 def TTMP#Index#_TTMP#!add(Index,1)# 433 _TTMP#!add(Index,2)# 434 _TTMP#!add(Index,3)#_gfx9_gfx10 : TmpRegTuples<"_gfx9_gfx10", 4, Index>; 435} 436 437foreach Index = {0, 4, 8} in { 438 def TTMP#Index#_TTMP#!add(Index,1)# 439 _TTMP#!add(Index,2)# 440 _TTMP#!add(Index,3)# 441 _TTMP#!add(Index,4)# 442 _TTMP#!add(Index,5)# 443 _TTMP#!add(Index,6)# 444 _TTMP#!add(Index,7)#_vi : TmpRegTuples<"_vi", 8, Index>; 445 def TTMP#Index#_TTMP#!add(Index,1)# 446 _TTMP#!add(Index,2)# 447 _TTMP#!add(Index,3)# 448 _TTMP#!add(Index,4)# 449 _TTMP#!add(Index,5)# 450 _TTMP#!add(Index,6)# 451 _TTMP#!add(Index,7)#_gfx9_gfx10 : TmpRegTuples<"_gfx9_gfx10", 8, Index>; 452} 453 454def TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15_vi : 455 TmpRegTuplesBase<0, 16, 456 [TTMP0_vi, TTMP1_vi, TTMP2_vi, TTMP3_vi, 457 TTMP4_vi, TTMP5_vi, TTMP6_vi, TTMP7_vi, 458 TTMP8_vi, TTMP9_vi, TTMP10_vi, TTMP11_vi, 459 TTMP12_vi, TTMP13_vi, TTMP14_vi, TTMP15_vi]>; 460 461def TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15_gfx9_gfx10 : 462 TmpRegTuplesBase<0, 16, 463 [TTMP0_gfx9_gfx10, TTMP1_gfx9_gfx10, TTMP2_gfx9_gfx10, TTMP3_gfx9_gfx10, 464 TTMP4_gfx9_gfx10, TTMP5_gfx9_gfx10, TTMP6_gfx9_gfx10, TTMP7_gfx9_gfx10, 465 TTMP8_gfx9_gfx10, TTMP9_gfx9_gfx10, TTMP10_gfx9_gfx10, TTMP11_gfx9_gfx10, 466 TTMP12_gfx9_gfx10, TTMP13_gfx9_gfx10, TTMP14_gfx9_gfx10, TTMP15_gfx9_gfx10]>; 467 468class RegisterTypes<list<ValueType> reg_types> { 469 list<ValueType> types = reg_types; 470} 471 472def Reg16Types : RegisterTypes<[i16, f16]>; 473def Reg32Types : RegisterTypes<[i32, f32, v2i16, v2f16, p2, p3, p5, p6]>; 474 475def VGPR_LO16 : RegisterClass<"AMDGPU", Reg16Types.types, 16, 476 (add (sequence "VGPR%u_LO16", 0, 255))> { 477 let AllocationPriority = 1; 478 let Size = 16; 479 let GeneratePressureSet = 0; 480} 481 482def VGPR_HI16 : RegisterClass<"AMDGPU", Reg16Types.types, 16, 483 (add (sequence "VGPR%u_HI16", 0, 255))> { 484 let AllocationPriority = 1; 485 let Size = 16; 486 let GeneratePressureSet = 0; 487} 488 489// VGPR 32-bit registers 490// i16/f16 only on VI+ 491def VGPR_32 : RegisterClass<"AMDGPU", !listconcat(Reg32Types.types, Reg16Types.types), 32, 492 (add (sequence "VGPR%u", 0, 255))> { 493 let AllocationPriority = 1; 494 let Size = 32; 495 let Weight = 1; 496} 497 498// VGPR 64-bit registers 499def VGPR_64 : SIRegisterTuples<getSubRegs<2>.ret, VGPR_32, 255, 1, 2, "v">; 500 501// VGPR 96-bit registers 502def VGPR_96 : SIRegisterTuples<getSubRegs<3>.ret, VGPR_32, 255, 1, 3, "v">; 503 504// VGPR 128-bit registers 505def VGPR_128 : SIRegisterTuples<getSubRegs<4>.ret, VGPR_32, 255, 1, 4, "v">; 506 507// VGPR 160-bit registers 508def VGPR_160 : SIRegisterTuples<getSubRegs<5>.ret, VGPR_32, 255, 1, 5, "v">; 509 510// VGPR 192-bit registers 511def VGPR_192 : SIRegisterTuples<getSubRegs<6>.ret, VGPR_32, 255, 1, 6, "v">; 512 513// VGPR 256-bit registers 514def VGPR_256 : SIRegisterTuples<getSubRegs<8>.ret, VGPR_32, 255, 1, 8, "v">; 515 516// VGPR 512-bit registers 517def VGPR_512 : SIRegisterTuples<getSubRegs<16>.ret, VGPR_32, 255, 1, 16, "v">; 518 519// VGPR 1024-bit registers 520def VGPR_1024 : SIRegisterTuples<getSubRegs<32>.ret, VGPR_32, 255, 1, 32, "v">; 521 522def AGPR_LO16 : RegisterClass<"AMDGPU", Reg16Types.types, 16, 523 (add (sequence "AGPR%u_LO16", 0, 255))> { 524 let isAllocatable = 0; 525 let Size = 16; 526 let GeneratePressureSet = 0; 527} 528 529// AccVGPR 32-bit registers 530def AGPR_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, 531 (add (sequence "AGPR%u", 0, 255))> { 532 let AllocationPriority = 1; 533 let Size = 32; 534 let Weight = 1; 535} 536 537// AGPR 64-bit registers 538def AGPR_64 : SIRegisterTuples<getSubRegs<2>.ret, AGPR_32, 255, 1, 2, "a">; 539 540// AGPR 96-bit registers 541def AGPR_96 : SIRegisterTuples<getSubRegs<3>.ret, AGPR_32, 255, 1, 3, "a">; 542 543// AGPR 128-bit registers 544def AGPR_128 : SIRegisterTuples<getSubRegs<4>.ret, AGPR_32, 255, 1, 4, "a">; 545 546// AGPR 160-bit registers 547def AGPR_160 : SIRegisterTuples<getSubRegs<5>.ret, AGPR_32, 255, 1, 5, "a">; 548 549// AGPR 192-bit registers 550def AGPR_192 : SIRegisterTuples<getSubRegs<6>.ret, AGPR_32, 255, 1, 6, "a">; 551 552// AGPR 256-bit registers 553def AGPR_256 : SIRegisterTuples<getSubRegs<8>.ret, AGPR_32, 255, 1, 8, "a">; 554 555// AGPR 512-bit registers 556def AGPR_512 : SIRegisterTuples<getSubRegs<16>.ret, AGPR_32, 255, 1, 16, "a">; 557 558// AGPR 1024-bit registers 559def AGPR_1024 : SIRegisterTuples<getSubRegs<32>.ret, AGPR_32, 255, 1, 32, "a">; 560 561//===----------------------------------------------------------------------===// 562// Register classes used as source and destination 563//===----------------------------------------------------------------------===// 564 565def Pseudo_SReg_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, 566 (add FP_REG, SP_REG)> { 567 let isAllocatable = 0; 568 let CopyCost = -1; 569} 570 571def Pseudo_SReg_128 : RegisterClass<"AMDGPU", [v4i32, v2i64, v2f64], 32, 572 (add PRIVATE_RSRC_REG)> { 573 let isAllocatable = 0; 574 let CopyCost = -1; 575} 576 577def LDS_DIRECT_CLASS : RegisterClass<"AMDGPU", [i32], 32, 578 (add LDS_DIRECT)> { 579 let isAllocatable = 0; 580 let CopyCost = -1; 581} 582 583let GeneratePressureSet = 0 in { 584// Subset of SReg_32 without M0 for SMRD instructions and alike. 585// See comments in SIInstructions.td for more info. 586def SReg_32_XM0_XEXEC : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32, 587 (add SGPR_32, VCC_LO, VCC_HI, FLAT_SCR_LO, FLAT_SCR_HI, XNACK_MASK_LO, XNACK_MASK_HI, 588 SGPR_NULL, TTMP_32, TMA_LO, TMA_HI, TBA_LO, TBA_HI, SRC_SHARED_BASE, SRC_SHARED_LIMIT, 589 SRC_PRIVATE_BASE, SRC_PRIVATE_LIMIT, SRC_POPS_EXITING_WAVE_ID, 590 SRC_VCCZ, SRC_EXECZ, SRC_SCC)> { 591 let AllocationPriority = 10; 592} 593 594def SReg_LO16_XM0_XEXEC : RegisterClass<"AMDGPU", [i16, f16], 16, 595 (add SGPR_LO16, VCC_LO_LO16, VCC_HI_LO16, FLAT_SCR_LO_LO16, FLAT_SCR_HI_LO16, 596 XNACK_MASK_LO_LO16, XNACK_MASK_HI_LO16, SGPR_NULL_LO16, TTMP_LO16, TMA_LO_LO16, 597 TMA_HI_LO16, TBA_LO_LO16, TBA_HI_LO16, SRC_SHARED_BASE_LO16, 598 SRC_SHARED_LIMIT_LO16, SRC_PRIVATE_BASE_LO16, SRC_PRIVATE_LIMIT_LO16, 599 SRC_POPS_EXITING_WAVE_ID_LO16, SRC_VCCZ_LO16, SRC_EXECZ_LO16, SRC_SCC_LO16)> { 600 let Size = 16; 601 let AllocationPriority = 10; 602} 603 604def SReg_32_XEXEC_HI : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32, 605 (add SReg_32_XM0_XEXEC, EXEC_LO, M0_CLASS)> { 606 let AllocationPriority = 10; 607} 608 609def SReg_LO16_XEXEC_HI : RegisterClass<"AMDGPU", [i16, f16], 16, 610 (add SReg_LO16_XM0_XEXEC, EXEC_LO_LO16, M0_CLASS_LO16)> { 611 let Size = 16; 612 let AllocationPriority = 10; 613} 614 615def SReg_32_XM0 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32, 616 (add SReg_32_XM0_XEXEC, EXEC_LO, EXEC_HI)> { 617 let AllocationPriority = 10; 618} 619 620def SReg_LO16_XM0 : RegisterClass<"AMDGPU", [i16, f16], 16, 621 (add SReg_LO16_XM0_XEXEC, EXEC_LO_LO16, EXEC_HI_LO16)> { 622 let Size = 16; 623 let AllocationPriority = 10; 624} 625 626def SReg_LO16 : RegisterClass<"AMDGPU", [i16, f16], 16, 627 (add SGPR_LO16, SReg_LO16_XM0, M0_CLASS_LO16, EXEC_LO_LO16, EXEC_HI_LO16, SReg_LO16_XEXEC_HI)> { 628 let Size = 16; 629 let AllocationPriority = 10; 630} 631} // End GeneratePressureSet = 0 632 633// Register class for all scalar registers (SGPRs + Special Registers) 634def SReg_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32, 635 (add SReg_32_XM0, M0_CLASS, EXEC_LO, EXEC_HI, SReg_32_XEXEC_HI)> { 636 let AllocationPriority = 10; 637} 638 639let GeneratePressureSet = 0 in { 640def SRegOrLds_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, 641 (add SReg_32, LDS_DIRECT_CLASS)> { 642 let isAllocatable = 0; 643} 644 645def SGPR_64 : RegisterClass<"AMDGPU", [v2i32, i64, v2f32, f64, v4i16, v4f16], 32, 646 (add SGPR_64Regs)> { 647 let CopyCost = 1; 648 let AllocationPriority = 11; 649} 650 651// CCR (call clobbered registers) SGPR 64-bit registers 652def CCR_SGPR_64 : RegisterClass<"AMDGPU", SGPR_64.RegTypes, 32, 653 (add (trunc SGPR_64, 16))> { 654 let CopyCost = SGPR_64.CopyCost; 655 let AllocationPriority = SGPR_64.AllocationPriority; 656} 657 658def TTMP_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64, v4i16, v4f16], 32, 659 (add TTMP_64Regs)> { 660 let isAllocatable = 0; 661} 662 663def SReg_64_XEXEC : RegisterClass<"AMDGPU", [v2i32, i64, v2f32, f64, i1, v4i16, v4f16], 32, 664 (add SGPR_64, VCC, FLAT_SCR, XNACK_MASK, TTMP_64, TBA, TMA)> { 665 let CopyCost = 1; 666 let AllocationPriority = 13; 667} 668 669def SReg_64 : RegisterClass<"AMDGPU", [v2i32, i64, v2f32, f64, i1, v4i16, v4f16], 32, 670 (add SReg_64_XEXEC, EXEC)> { 671 let CopyCost = 1; 672 let AllocationPriority = 13; 673} 674 675def SReg_1_XEXEC : RegisterClass<"AMDGPU", [i1], 32, 676 (add SReg_64_XEXEC, SReg_32_XM0_XEXEC)> { 677 let CopyCost = 1; 678 let isAllocatable = 0; 679} 680 681def SReg_1 : RegisterClass<"AMDGPU", [i1], 32, 682 (add SReg_1_XEXEC, EXEC, EXEC_LO)> { 683 let CopyCost = 1; 684 let isAllocatable = 0; 685} 686 687// Requires 2 s_mov_b64 to copy 688let CopyCost = 2 in { 689 690// There are no 3-component scalar instructions, but this is needed 691// for symmetry with VGPRs. 692def SGPR_96 : RegisterClass<"AMDGPU", [v3i32, v3f32], 32, 693 (add SGPR_96Regs)> { 694 let AllocationPriority = 14; 695} 696 697def SReg_96 : RegisterClass<"AMDGPU", [v3i32, v3f32], 32, 698 (add SGPR_96)> { 699 let AllocationPriority = 14; 700} 701 702def SGPR_128 : RegisterClass<"AMDGPU", [v4i32, v4f32, v2i64], 32, 703 (add SGPR_128Regs)> { 704 let AllocationPriority = 15; 705} 706 707def TTMP_128 : RegisterClass<"AMDGPU", [v4i32, v4f32, v2i64], 32, 708 (add TTMP_128Regs)> { 709 let isAllocatable = 0; 710} 711 712def SReg_128 : RegisterClass<"AMDGPU", [v4i32, v4f32, v2i64, v2f64], 32, 713 (add SGPR_128, TTMP_128)> { 714 let isAllocatable = 0; 715} 716 717} // End CopyCost = 2 718 719// There are no 5-component scalar instructions, but this is needed 720// for symmetry with VGPRs. 721def SGPR_160 : RegisterClass<"AMDGPU", [v5i32, v5f32], 32, 722 (add SGPR_160Regs)> { 723 let AllocationPriority = 16; 724} 725 726def SReg_160 : RegisterClass<"AMDGPU", [v5i32, v5f32], 32, 727 (add SGPR_160)> { 728 // FIXME: Should be isAllocatable = 0, but that causes all TableGen-generated 729 // subclasses of SGPR_160 to be marked unallocatable too. 730} 731 732def SGPR_192 : RegisterClass<"AMDGPU", [untyped], 32, (add SGPR_192Regs)> { 733 let Size = 192; 734 let AllocationPriority = 17; 735} 736 737def SReg_192 : RegisterClass<"AMDGPU", [untyped], 32, (add SGPR_192)> { 738 let Size = 192; 739 let isAllocatable = 0; 740} 741 742def SGPR_256 : RegisterClass<"AMDGPU", [v8i32, v8f32, v4i64, v4f64], 32, (add SGPR_256Regs)> { 743 let AllocationPriority = 18; 744} 745 746def TTMP_256 : RegisterClass<"AMDGPU", [v8i32, v8f32, v4i64, v4f64], 32, (add TTMP_256Regs)> { 747 let isAllocatable = 0; 748} 749 750def SReg_256 : RegisterClass<"AMDGPU", [v8i32, v8f32, v4i64, v4f64], 32, 751 (add SGPR_256, TTMP_256)> { 752 // Requires 4 s_mov_b64 to copy 753 let CopyCost = 4; 754 let isAllocatable = 0; 755} 756 757def SGPR_512 : RegisterClass<"AMDGPU", [v16i32, v16f32, v8i64, v8f64], 32, 758 (add SGPR_512Regs)> { 759 let AllocationPriority = 19; 760} 761 762def TTMP_512 : RegisterClass<"AMDGPU", [v16i32, v16f32, v8i64, v8f64], 32, 763 (add TTMP_512Regs)> { 764 let isAllocatable = 0; 765} 766 767def SReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32, v8i64, v8f64], 32, 768 (add SGPR_512, TTMP_512)> { 769 // Requires 8 s_mov_b64 to copy 770 let CopyCost = 8; 771 let isAllocatable = 0; 772} 773 774def VRegOrLds_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, 775 (add VGPR_32, LDS_DIRECT_CLASS)> { 776 let isAllocatable = 0; 777} 778 779def SGPR_1024 : RegisterClass<"AMDGPU", [v32i32, v32f32, v16i64, v16f64], 32, 780 (add SGPR_1024Regs)> { 781 let AllocationPriority = 20; 782} 783 784def SReg_1024 : RegisterClass<"AMDGPU", [v32i32, v32f32, v16i64, v16f64], 32, 785 (add SGPR_1024)> { 786 let CopyCost = 16; 787 let isAllocatable = 0; 788} 789 790// Register class for all vector registers (VGPRs + Interpolation Registers) 791class VRegClass<int numRegs, list<ValueType> regTypes, dag regList> : 792 RegisterClass<"AMDGPU", regTypes, 32, regList> { 793 let Size = !mul(numRegs, 32); 794 795 // Requires n v_mov_b32 to copy 796 let CopyCost = numRegs; 797 let AllocationPriority = numRegs; 798 let Weight = numRegs; 799} 800 801def VReg_64 : VRegClass<2, [i64, f64, v2i32, v2f32, v4f16, v4i16, p0, p1, p4], 802 (add VGPR_64)>; 803def VReg_96 : VRegClass<3, [v3i32, v3f32], (add VGPR_96)>; 804def VReg_128 : VRegClass<4, [v4i32, v4f32, v2i64, v2f64, i128], (add VGPR_128)>; 805def VReg_160 : VRegClass<5, [v5i32, v5f32], (add VGPR_160)>; 806def VReg_192 : VRegClass<6, [untyped], (add VGPR_192)>; 807def VReg_256 : VRegClass<8, [v8i32, v8f32, v4i64, v4f64], (add VGPR_256)>; 808def VReg_512 : VRegClass<16, [v16i32, v16f32, v8i64, v8f64], (add VGPR_512)>; 809def VReg_1024 : VRegClass<32, [v32i32, v32f32, v16i64, v16f64], (add VGPR_1024)>; 810 811class ARegClass<int numRegs, list<ValueType> regTypes, dag regList> : 812 VRegClass<numRegs, regTypes, regList> { 813 // Requires n v_accvgpr_write and n v_accvgpr_read to copy + burn 1 vgpr 814 let CopyCost = !add(numRegs, numRegs, 1); 815} 816 817def AReg_64 : ARegClass<2, [i64, f64, v2i32, v2f32, v4f16, v4i16], 818 (add AGPR_64)>; 819def AReg_96 : ARegClass<3, [v3i32, v3f32], (add AGPR_96)>; 820def AReg_128 : ARegClass<4, [v4i32, v4f32, v2i64, v2f64], (add AGPR_128)>; 821def AReg_160 : ARegClass<5, [v5i32, v5f32], (add AGPR_160)>; 822def AReg_192 : ARegClass<6, [untyped], (add AGPR_192)>; 823def AReg_256 : ARegClass<8, [v8i32, v8f32, v4i64, v4f64], (add AGPR_256)>; 824def AReg_512 : ARegClass<16, [v16i32, v16f32, v8i64, v8f64], (add AGPR_512)>; 825def AReg_1024 : ARegClass<32, [v32i32, v32f32, v16i64, v16f64], (add AGPR_1024)>; 826 827} // End GeneratePressureSet = 0 828 829// This is not a real register. This is just to have a register to add 830// to VReg_1 that does not alias any real register that would 831// introduce inferred register classess. 832def ARTIFICIAL_VGPR : SIReg <"invalid vgpr", 0> { 833 let isArtificial = 1; 834} 835 836let GeneratePressureSet = 0 in { 837// FIXME: Should specify an empty set for this. No register should 838// ever be allocated using VReg_1. This is a hack for SelectionDAG 839// that should always be lowered by SILowerI1Copies. TableGen crashes 840// on an empty register set, but also sorts register classes based on 841// the number of registerss in them. Add only one register so this is 842// sorted to the end and not preferred over VGPR_32. 843def VReg_1 : RegisterClass<"AMDGPU", [i1], 32, (add ARTIFICIAL_VGPR)> { 844 let Size = 1; 845} 846 847def VS_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, 848 (add VGPR_32, SReg_32, LDS_DIRECT_CLASS)> { 849 let isAllocatable = 0; 850} 851 852def VS_64 : RegisterClass<"AMDGPU", [i64, f64], 32, (add VReg_64, SReg_64)> { 853 let isAllocatable = 0; 854} 855 856def AV_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, 857 (add AGPR_32, VGPR_32)> { 858 let isAllocatable = 0; 859} 860 861def AV_64 : RegisterClass<"AMDGPU", [i64, f64, v4f16], 32, 862 (add AReg_64, VReg_64)> { 863 let isAllocatable = 0; 864} 865} // End GeneratePressureSet = 0 866 867//===----------------------------------------------------------------------===// 868// Register operands 869//===----------------------------------------------------------------------===// 870 871class RegImmMatcher<string name> : AsmOperandClass { 872 let Name = name; 873 let RenderMethod = "addRegOrImmOperands"; 874} 875 876multiclass SIRegOperand32 <string rc, string MatchName, string opType, 877 string rc_suffix = "_32"> { 878 let OperandNamespace = "AMDGPU" in { 879 def _b16 : RegisterOperand<!cast<RegisterClass>(rc#rc_suffix)> { 880 let OperandType = opType#"_INT16"; 881 let ParserMatchClass = RegImmMatcher<MatchName#"B16">; 882 let DecoderMethod = "decodeOperand_VSrc16"; 883 } 884 885 def _f16 : RegisterOperand<!cast<RegisterClass>(rc#rc_suffix)> { 886 let OperandType = opType#"_FP16"; 887 let ParserMatchClass = RegImmMatcher<MatchName#"F16">; 888 let DecoderMethod = "decodeOperand_" # rc # "_16"; 889 } 890 891 def _b32 : RegisterOperand<!cast<RegisterClass>(rc#rc_suffix)> { 892 let OperandType = opType#"_INT32"; 893 let ParserMatchClass = RegImmMatcher<MatchName#"B32">; 894 let DecoderMethod = "decodeOperand_" # rc # rc_suffix; 895 } 896 897 def _f32 : RegisterOperand<!cast<RegisterClass>(rc#rc_suffix)> { 898 let OperandType = opType#"_FP32"; 899 let ParserMatchClass = RegImmMatcher<MatchName#"F32">; 900 let DecoderMethod = "decodeOperand_" # rc # rc_suffix; 901 } 902 903 def _v2b16 : RegisterOperand<!cast<RegisterClass>(rc#rc_suffix)> { 904 let OperandType = opType#"_V2INT16"; 905 let ParserMatchClass = RegImmMatcher<MatchName#"V2B16">; 906 let DecoderMethod = "decodeOperand_VSrcV216"; 907 } 908 909 def _v2f16 : RegisterOperand<!cast<RegisterClass>(rc#rc_suffix)> { 910 let OperandType = opType#"_V2FP16"; 911 let ParserMatchClass = RegImmMatcher<MatchName#"V2F16">; 912 let DecoderMethod = "decodeOperand_VSrcV216"; 913 } 914 } 915} 916 917multiclass SIRegOperand <string rc, string MatchName, string opType> : 918 SIRegOperand32<rc, MatchName, opType> { 919 let OperandNamespace = "AMDGPU" in { 920 def _b64 : RegisterOperand<!cast<RegisterClass>(rc#"_64")> { 921 let OperandType = opType#"_INT64"; 922 let ParserMatchClass = RegImmMatcher<MatchName#"B64">; 923 } 924 925 def _f64 : RegisterOperand<!cast<RegisterClass>(rc#"_64")> { 926 let OperandType = opType#"_FP64"; 927 let ParserMatchClass = RegImmMatcher<MatchName#"F64">; 928 } 929 } 930} 931 932// FIXME: 64-bit sources can sometimes use 32-bit constants. 933multiclass RegImmOperand <string rc, string MatchName> 934 : SIRegOperand<rc, MatchName, "OPERAND_REG_IMM">; 935 936multiclass RegInlineOperand <string rc, string MatchName> 937 : SIRegOperand<rc, MatchName, "OPERAND_REG_INLINE_C">; 938 939multiclass RegInlineOperand32 <string rc, string MatchName, 940 string rc_suffix = "_32"> 941 : SIRegOperand32<rc, MatchName, "OPERAND_REG_INLINE_C", rc_suffix>; 942 943multiclass RegInlineOperandAC <string rc, string MatchName, 944 string rc_suffix = "_32"> 945 : SIRegOperand32<rc, MatchName, "OPERAND_REG_INLINE_AC", rc_suffix>; 946 947//===----------------------------------------------------------------------===// 948// SSrc_* Operands with an SGPR or a 32-bit immediate 949//===----------------------------------------------------------------------===// 950 951defm SSrc : RegImmOperand<"SReg", "SSrc">; 952 953def SSrcOrLds_b32 : RegisterOperand<SRegOrLds_32> { 954 let OperandNamespace = "AMDGPU"; 955 let OperandType = "OPERAND_REG_IMM_INT32"; 956 let ParserMatchClass = RegImmMatcher<"SSrcOrLdsB32">; 957} 958 959//===----------------------------------------------------------------------===// 960// SCSrc_* Operands with an SGPR or a inline constant 961//===----------------------------------------------------------------------===// 962 963defm SCSrc : RegInlineOperand<"SReg", "SCSrc"> ; 964 965//===----------------------------------------------------------------------===// 966// VSrc_* Operands with an SGPR, VGPR or a 32-bit immediate 967//===----------------------------------------------------------------------===// 968 969defm VSrc : RegImmOperand<"VS", "VSrc">; 970 971def VSrc_128 : RegisterOperand<VReg_128> { 972 let DecoderMethod = "DecodeVS_128RegisterClass"; 973} 974 975//===----------------------------------------------------------------------===// 976// VSrc_* Operands with an VGPR 977//===----------------------------------------------------------------------===// 978 979// This is for operands with the enum(9), VSrc encoding restriction, 980// but only allows VGPRs. 981def VRegSrc_32 : RegisterOperand<VGPR_32> { 982 //let ParserMatchClass = RegImmMatcher<"VRegSrc32">; 983 let DecoderMethod = "DecodeVS_32RegisterClass"; 984} 985 986//===----------------------------------------------------------------------===// 987// ASrc_* Operands with an AccVGPR 988//===----------------------------------------------------------------------===// 989 990def ARegSrc_32 : RegisterOperand<AGPR_32> { 991 let DecoderMethod = "DecodeAGPR_32RegisterClass"; 992 let EncoderMethod = "getAVOperandEncoding"; 993} 994 995//===----------------------------------------------------------------------===// 996// VCSrc_* Operands with an SGPR, VGPR or an inline constant 997//===----------------------------------------------------------------------===// 998 999defm VCSrc : RegInlineOperand<"VS", "VCSrc">; 1000 1001//===----------------------------------------------------------------------===// 1002// VISrc_* Operands with a VGPR or an inline constant 1003//===----------------------------------------------------------------------===// 1004 1005defm VISrc : RegInlineOperand32<"VGPR", "VISrc">; 1006 1007//===----------------------------------------------------------------------===// 1008// AVSrc_* Operands with an AGPR or VGPR 1009//===----------------------------------------------------------------------===// 1010 1011def AVSrc_32 : RegisterOperand<AV_32> { 1012 let DecoderMethod = "DecodeAV_32RegisterClass"; 1013 let EncoderMethod = "getAVOperandEncoding"; 1014} 1015 1016def AVSrc_64 : RegisterOperand<AV_64> { 1017 let DecoderMethod = "DecodeAV_64RegisterClass"; 1018 let EncoderMethod = "getAVOperandEncoding"; 1019} 1020 1021//===----------------------------------------------------------------------===// 1022// ACSrc_* Operands with an AGPR or an inline constant 1023//===----------------------------------------------------------------------===// 1024 1025defm AISrc : RegInlineOperandAC<"AGPR", "AISrc">; 1026defm AISrc_128 : RegInlineOperandAC<"AReg", "AISrc_128", "_128">; 1027defm AISrc_512 : RegInlineOperandAC<"AReg", "AISrc_512", "_512">; 1028defm AISrc_1024 : RegInlineOperandAC<"AReg", "AISrc_1024", "_1024">; 1029