1//===-- SIRegisterInfo.td - SI Register defs ---------------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// Subregister declarations 11//===----------------------------------------------------------------------===// 12 13class Indexes<int N> { 14 list<int> all = [0, 1, 2, 3, 4, 5, 6 , 7, 15 8, 9, 10, 11, 12, 13, 14, 15, 16 16, 17, 18, 19, 20, 21, 22, 23, 17 24, 25, 26, 27, 28, 29, 30, 31]; 18 19 // Returns list of indexes [0..N) 20 list<int> slice = !filter(i, all, !lt(i, N)); 21} 22 23let Namespace = "AMDGPU" in { 24 25def lo16 : SubRegIndex<16, 0>; 26def hi16 : SubRegIndex<16, 16>; 27 28foreach Index = 0...31 in { 29 def sub#Index : SubRegIndex<32, !shl(Index, 5)>; 30} 31 32foreach Index = 1...31 in { 33 def sub#Index#_lo16 : ComposedSubRegIndex<!cast<SubRegIndex>(sub#Index), lo16>; 34 def sub#Index#_hi16 : ComposedSubRegIndex<!cast<SubRegIndex>(sub#Index), hi16>; 35} 36 37foreach Size = {2...6,8,16} in { 38 foreach Index = Indexes<!sub(33, Size)>.slice in { 39 def !interleave(!foreach(cur, Indexes<Size>.slice, "sub"#!add(cur, Index)), 40 "_") : 41 SubRegIndex<!mul(Size, 32), !shl(Index, 5)> { 42 let CoveringSubRegIndices = 43 !foreach(cur, Indexes<Size>.slice, 44 !cast<SubRegIndex>(sub#!add(cur, Index))); 45 } 46 } 47} 48 49} 50 51//===----------------------------------------------------------------------===// 52// Helpers 53//===----------------------------------------------------------------------===// 54 55class getSubRegs<int size> { 56 list<SubRegIndex> ret2 = [sub0, sub1]; 57 list<SubRegIndex> ret3 = [sub0, sub1, sub2]; 58 list<SubRegIndex> ret4 = [sub0, sub1, sub2, sub3]; 59 list<SubRegIndex> ret5 = [sub0, sub1, sub2, sub3, sub4]; 60 list<SubRegIndex> ret6 = [sub0, sub1, sub2, sub3, sub4, sub5]; 61 list<SubRegIndex> ret7 = [sub0, sub1, sub2, sub3, sub4, sub5, sub6]; 62 list<SubRegIndex> ret8 = [sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7]; 63 list<SubRegIndex> ret16 = [sub0, sub1, sub2, sub3, 64 sub4, sub5, sub6, sub7, 65 sub8, sub9, sub10, sub11, 66 sub12, sub13, sub14, sub15]; 67 list<SubRegIndex> ret32 = [sub0, sub1, sub2, sub3, 68 sub4, sub5, sub6, sub7, 69 sub8, sub9, sub10, sub11, 70 sub12, sub13, sub14, sub15, 71 sub16, sub17, sub18, sub19, 72 sub20, sub21, sub22, sub23, 73 sub24, sub25, sub26, sub27, 74 sub28, sub29, sub30, sub31]; 75 76 list<SubRegIndex> ret = !if(!eq(size, 2), ret2, 77 !if(!eq(size, 3), ret3, 78 !if(!eq(size, 4), ret4, 79 !if(!eq(size, 5), ret5, 80 !if(!eq(size, 6), ret6, 81 !if(!eq(size, 7), ret7, 82 !if(!eq(size, 8), ret8, 83 !if(!eq(size, 16), ret16, 84 ret32)))))))); 85} 86 87// Generates list of sequential register tuple names. 88// E.g. RegSeq<3,2,2,"s">.ret -> [ "s[0:1]", "s[2:3]" ] 89class RegSeqNames<int last_reg, int stride, int size, string prefix, 90 int start = 0> { 91 int next = !add(start, stride); 92 int end_reg = !add(start, size, -1); 93 list<string> ret = 94 !if(!le(end_reg, last_reg), 95 !listconcat([prefix # "[" # start # ":" # end_reg # "]"], 96 RegSeqNames<last_reg, stride, size, prefix, next>.ret), 97 []); 98} 99 100// Generates list of dags for register tuples. 101class RegSeqDags<RegisterClass RC, int last_reg, int stride, int size, 102 int start = 0> { 103 dag trunc_rc = (trunc RC, 104 !if(!and(!eq(stride, 1), !eq(start, 0)), 105 !sub(!add(last_reg, 2), size), 106 !add(last_reg, 1))); 107 list<dag> ret = 108 !if(!lt(start, size), 109 !listconcat([(add (decimate (shl trunc_rc, start), stride))], 110 RegSeqDags<RC, last_reg, stride, size, !add(start, 1)>.ret), 111 []); 112} 113 114class SIRegisterTuples<list<SubRegIndex> Indices, RegisterClass RC, 115 int last_reg, int stride, int size, string prefix> : 116 RegisterTuples<Indices, 117 RegSeqDags<RC, last_reg, stride, size>.ret, 118 RegSeqNames<last_reg, stride, size, prefix>.ret>; 119 120//===----------------------------------------------------------------------===// 121// Declarations that describe the SI registers 122//===----------------------------------------------------------------------===// 123class SIReg <string n, bits<16> regIdx = 0> : 124 Register<n> { 125 let Namespace = "AMDGPU"; 126 let HWEncoding = regIdx; 127} 128 129// For register classes that use TSFlags. 130class SIRegisterClass <string n, list<ValueType> rTypes, int Align, dag rList> 131 : RegisterClass <n, rTypes, Align, rList> { 132 // For vector register classes. 133 field bit HasVGPR = 0; 134 field bit HasAGPR = 0; 135 136 // For scalar register classes. 137 field bit HasSGPR = 0; 138 139 // These need to be kept in sync with the enum SIRCFlags. 140 let TSFlags{0} = HasVGPR; 141 let TSFlags{1} = HasAGPR; 142 let TSFlags{2} = HasSGPR; 143} 144 145multiclass SIRegLoHi16 <string n, bits<16> regIdx, bit ArtificialHigh = 1, 146 bit HWEncodingHigh = 0> { 147 // There is no special encoding for 16 bit subregs, these are not real 148 // registers but rather operands for instructions preserving other 16 bits 149 // of the result or reading just 16 bits of a 32 bit VGPR. 150 // It is encoded as a corresponding 32 bit register. 151 // Non-VGPR register classes use it as we need to have matching subregisters 152 // to move instructions and data between ALUs. 153 def _LO16 : SIReg<n#".l", regIdx> { 154 let HWEncoding{8} = HWEncodingHigh; 155 } 156 def _HI16 : SIReg<!if(ArtificialHigh, "", n#".h"), regIdx> { 157 let isArtificial = ArtificialHigh; 158 let HWEncoding{8} = HWEncodingHigh; 159 } 160 def "" : RegisterWithSubRegs<n, [!cast<Register>(NAME#"_LO16"), 161 !cast<Register>(NAME#"_HI16")]> { 162 let Namespace = "AMDGPU"; 163 let SubRegIndices = [lo16, hi16]; 164 let CoveredBySubRegs = !not(ArtificialHigh); 165 let HWEncoding = regIdx; 166 let HWEncoding{8} = HWEncodingHigh; 167 } 168} 169 170// Special Registers 171defm VCC_LO : SIRegLoHi16<"vcc_lo", 106>; 172defm VCC_HI : SIRegLoHi16<"vcc_hi", 107>; 173 174// Pseudo-registers: Used as placeholders during isel and immediately 175// replaced, never seeing the verifier. 176def PRIVATE_RSRC_REG : SIReg<"private_rsrc", 0>; 177def FP_REG : SIReg<"fp", 0>; 178def SP_REG : SIReg<"sp", 0>; 179 180// Pseudo-register to represent the program-counter DWARF register. 181def PC_REG : SIReg<"pc", 0>, DwarfRegNum<[16, 16]> { 182 // There is no physical register corresponding to a "program counter", but 183 // we need to encode the concept in debug information in order to represent 184 // things like the return value in unwind information. 185 let isArtificial = 1; 186} 187 188// VCC for 64-bit instructions 189def VCC : RegisterWithSubRegs<"vcc", [VCC_LO, VCC_HI]> { 190 let Namespace = "AMDGPU"; 191 let SubRegIndices = [sub0, sub1]; 192 let HWEncoding = VCC_LO.HWEncoding; 193} 194 195defm EXEC_LO : SIRegLoHi16<"exec_lo", 126>, DwarfRegNum<[1, 1]>; 196defm EXEC_HI : SIRegLoHi16<"exec_hi", 127>; 197 198def EXEC : RegisterWithSubRegs<"exec", [EXEC_LO, EXEC_HI]>, DwarfRegNum<[17, 1]> { 199 let Namespace = "AMDGPU"; 200 let SubRegIndices = [sub0, sub1]; 201 let HWEncoding = EXEC_LO.HWEncoding; 202} 203 204// 32-bit real registers, for MC only. 205// May be used with both 32-bit and 64-bit operands. 206defm SRC_VCCZ : SIRegLoHi16<"src_vccz", 251>; 207defm SRC_EXECZ : SIRegLoHi16<"src_execz", 252>; 208defm SRC_SCC : SIRegLoHi16<"src_scc", 253>; 209 210// 1-bit pseudo register, for codegen only. 211// Should never be emitted. 212def SCC : SIReg<"scc">; 213 214// Encoding changes between subtarget generations. 215// See also Utils/AMDGPUBaseInfo.cpp MAP_REG2REG. 216defm M0_gfxpre11 : SIRegLoHi16 <"m0", 124>; 217defm M0_gfx11plus : SIRegLoHi16 <"m0", 125>; 218defm M0 : SIRegLoHi16 <"m0", 0>; 219 220defm SGPR_NULL_gfxpre11 : SIRegLoHi16 <"null", 125>; 221defm SGPR_NULL_gfx11plus : SIRegLoHi16 <"null", 124>; 222defm SGPR_NULL : SIRegLoHi16 <"null", 0>; 223defm SGPR_NULL_HI : SIRegLoHi16 <"", 0>; 224 225def SGPR_NULL64 : 226 RegisterWithSubRegs<"null", [SGPR_NULL, SGPR_NULL_HI]> { 227 let Namespace = "AMDGPU"; 228 let SubRegIndices = [sub0, sub1]; 229 let HWEncoding = SGPR_NULL.HWEncoding; 230} 231 232defm SRC_SHARED_BASE : SIRegLoHi16<"src_shared_base", 235>; 233defm SRC_SHARED_LIMIT : SIRegLoHi16<"src_shared_limit", 236>; 234defm SRC_PRIVATE_BASE : SIRegLoHi16<"src_private_base", 237>; 235defm SRC_PRIVATE_LIMIT : SIRegLoHi16<"src_private_limit", 238>; 236defm SRC_POPS_EXITING_WAVE_ID : SIRegLoHi16<"src_pops_exiting_wave_id", 239>; 237 238// Not addressable 239def MODE : SIReg <"mode", 0>; 240 241def LDS_DIRECT : SIReg <"src_lds_direct", 254> { 242 // There is no physical register corresponding to this. This is an 243 // encoding value in a source field, which will ultimately trigger a 244 // read from m0. 245 let isArtificial = 1; 246} 247 248defm XNACK_MASK_LO : SIRegLoHi16<"xnack_mask_lo", 104>; 249defm XNACK_MASK_HI : SIRegLoHi16<"xnack_mask_hi", 105>; 250 251def XNACK_MASK : 252 RegisterWithSubRegs<"xnack_mask", [XNACK_MASK_LO, XNACK_MASK_HI]> { 253 let Namespace = "AMDGPU"; 254 let SubRegIndices = [sub0, sub1]; 255 let HWEncoding = XNACK_MASK_LO.HWEncoding; 256} 257 258// Trap handler registers 259defm TBA_LO : SIRegLoHi16<"tba_lo", 108>; 260defm TBA_HI : SIRegLoHi16<"tba_hi", 109>; 261 262def TBA : RegisterWithSubRegs<"tba", [TBA_LO, TBA_HI]> { 263 let Namespace = "AMDGPU"; 264 let SubRegIndices = [sub0, sub1]; 265 let HWEncoding = TBA_LO.HWEncoding; 266} 267 268defm TMA_LO : SIRegLoHi16<"tma_lo", 110>; 269defm TMA_HI : SIRegLoHi16<"tma_hi", 111>; 270 271def TMA : RegisterWithSubRegs<"tma", [TMA_LO, TMA_HI]> { 272 let Namespace = "AMDGPU"; 273 let SubRegIndices = [sub0, sub1]; 274 let HWEncoding = TMA_LO.HWEncoding; 275} 276 277foreach Index = 0...15 in { 278 defm TTMP#Index#_vi : SIRegLoHi16<"ttmp"#Index, !add(112, Index)>; 279 defm TTMP#Index#_gfx9plus : SIRegLoHi16<"ttmp"#Index, !add(108, Index)>; 280 defm TTMP#Index : SIRegLoHi16<"ttmp"#Index, 0>; 281} 282 283multiclass FLAT_SCR_LOHI_m <string n, bits<16> ci_e, bits<16> vi_e> { 284 defm _ci : SIRegLoHi16<n, ci_e>; 285 defm _vi : SIRegLoHi16<n, vi_e>; 286 defm "" : SIRegLoHi16<n, 0>; 287} 288 289class FlatReg <Register lo, Register hi, bits<16> encoding> : 290 RegisterWithSubRegs<"flat_scratch", [lo, hi]> { 291 let Namespace = "AMDGPU"; 292 let SubRegIndices = [sub0, sub1]; 293 let HWEncoding = encoding; 294} 295 296defm FLAT_SCR_LO : FLAT_SCR_LOHI_m<"flat_scratch_lo", 104, 102>; // Offset in units of 256-bytes. 297defm FLAT_SCR_HI : FLAT_SCR_LOHI_m<"flat_scratch_hi", 105, 103>; // Size is the per-thread scratch size, in bytes. 298 299def FLAT_SCR_ci : FlatReg<FLAT_SCR_LO_ci, FLAT_SCR_HI_ci, 104>; 300def FLAT_SCR_vi : FlatReg<FLAT_SCR_LO_vi, FLAT_SCR_HI_vi, 102>; 301def FLAT_SCR : FlatReg<FLAT_SCR_LO, FLAT_SCR_HI, 0>; 302 303// SGPR registers 304foreach Index = 0...105 in { 305 defm SGPR#Index : 306 SIRegLoHi16 <"s"#Index, Index>, 307 DwarfRegNum<[!if(!le(Index, 63), !add(Index, 32), !add(Index, 1024)), 308 !if(!le(Index, 63), !add(Index, 32), !add(Index, 1024))]>; 309} 310 311// VGPR registers 312foreach Index = 0...255 in { 313 defm VGPR#Index : 314 SIRegLoHi16 <"v"#Index, Index, 0, 1>, 315 DwarfRegNum<[!add(Index, 2560), !add(Index, 1536)]>; 316} 317 318// AccVGPR registers 319foreach Index = 0...255 in { 320 defm AGPR#Index : 321 SIRegLoHi16 <"a"#Index, Index, 1, 1>, 322 DwarfRegNum<[!add(Index, 3072), !add(Index, 2048)]>; 323} 324 325//===----------------------------------------------------------------------===// 326// Groupings using register classes and tuples 327//===----------------------------------------------------------------------===// 328 329def SCC_CLASS : SIRegisterClass<"AMDGPU", [i1], 1, (add SCC)> { 330 let CopyCost = -1; 331 let isAllocatable = 0; 332 let HasSGPR = 1; 333} 334 335def M0_CLASS : SIRegisterClass<"AMDGPU", [i32], 32, (add M0)> { 336 let CopyCost = 1; 337 let isAllocatable = 0; 338 let HasSGPR = 1; 339} 340 341def M0_CLASS_LO16 : SIRegisterClass<"AMDGPU", [i16, f16], 16, (add M0_LO16)> { 342 let CopyCost = 1; 343 let Size = 16; 344 let isAllocatable = 0; 345 let HasSGPR = 1; 346} 347 348// TODO: Do we need to set DwarfRegAlias on register tuples? 349 350def SGPR_LO16 : SIRegisterClass<"AMDGPU", [i16, f16], 16, 351 (add (sequence "SGPR%u_LO16", 0, 105))> { 352 let AllocationPriority = 0; 353 let Size = 16; 354 let GeneratePressureSet = 0; 355 let HasSGPR = 1; 356} 357 358def SGPR_HI16 : SIRegisterClass<"AMDGPU", [i16, f16], 16, 359 (add (sequence "SGPR%u_HI16", 0, 105))> { 360 let isAllocatable = 0; 361 let Size = 16; 362 let GeneratePressureSet = 0; 363 let HasSGPR = 1; 364} 365 366// SGPR 32-bit registers 367def SGPR_32 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, 368 (add (sequence "SGPR%u", 0, 105))> { 369 // Give all SGPR classes higher priority than VGPR classes, because 370 // we want to spill SGPRs to VGPRs. 371 let AllocationPriority = 0; 372 let GeneratePressureSet = 0; 373 let HasSGPR = 1; 374} 375 376// SGPR 64-bit registers 377def SGPR_64Regs : SIRegisterTuples<getSubRegs<2>.ret, SGPR_32, 105, 2, 2, "s">; 378 379// SGPR 96-bit registers. No operations use these, but for symmetry with 96-bit VGPRs. 380def SGPR_96Regs : SIRegisterTuples<getSubRegs<3>.ret, SGPR_32, 105, 3, 3, "s">; 381 382// SGPR 128-bit registers 383def SGPR_128Regs : SIRegisterTuples<getSubRegs<4>.ret, SGPR_32, 105, 4, 4, "s">; 384 385// SGPR 160-bit registers. No operations use these, but for symmetry with 160-bit VGPRs. 386def SGPR_160Regs : SIRegisterTuples<getSubRegs<5>.ret, SGPR_32, 105, 4, 5, "s">; 387 388// SGPR 192-bit registers. No operations use these, but for symmetry with 192-bit VGPRs. 389def SGPR_192Regs : SIRegisterTuples<getSubRegs<6>.ret, SGPR_32, 105, 4, 6, "s">; 390 391// SGPR 224-bit registers. No operations use these, but for symmetry with 224-bit VGPRs. 392def SGPR_224Regs : SIRegisterTuples<getSubRegs<7>.ret, SGPR_32, 105, 4, 7, "s">; 393 394// SGPR 256-bit registers 395def SGPR_256Regs : SIRegisterTuples<getSubRegs<8>.ret, SGPR_32, 105, 4, 8, "s">; 396 397// SGPR 512-bit registers 398def SGPR_512Regs : SIRegisterTuples<getSubRegs<16>.ret, SGPR_32, 105, 4, 16, "s">; 399 400// SGPR 1024-bit registers 401def SGPR_1024Regs : SIRegisterTuples<getSubRegs<32>.ret, SGPR_32, 105, 4, 32, "s">; 402 403// Trap handler TMP 32-bit registers 404def TTMP_32 : SIRegisterClass<"AMDGPU", [i32, f32, v2i16, v2f16], 32, 405 (add (sequence "TTMP%u", 0, 15))> { 406 let isAllocatable = 0; 407 let HasSGPR = 1; 408} 409 410// Trap handler TMP 16-bit registers 411def TTMP_LO16 : SIRegisterClass<"AMDGPU", [i16, f16], 16, 412 (add (sequence "TTMP%u_LO16", 0, 15))> { 413 let Size = 16; 414 let isAllocatable = 0; 415 let HasSGPR = 1; 416} 417 418// Trap handler TMP 64-bit registers 419def TTMP_64Regs : SIRegisterTuples<getSubRegs<2>.ret, TTMP_32, 15, 2, 2, "ttmp">; 420 421// Trap handler TMP 96-bit registers 422def TTMP_96Regs : SIRegisterTuples<getSubRegs<3>.ret, TTMP_32, 15, 3, 3, "ttmp">; 423 424// Trap handler TMP 128-bit registers 425def TTMP_128Regs : SIRegisterTuples<getSubRegs<4>.ret, TTMP_32, 15, 4, 4, "ttmp">; 426 427// Trap handler TMP 160-bit registers 428def TTMP_160Regs : SIRegisterTuples<getSubRegs<5>.ret, TTMP_32, 15, 4, 5, "ttmp">; 429 430// Trap handler TMP 192-bit registers 431def TTMP_192Regs : SIRegisterTuples<getSubRegs<6>.ret, TTMP_32, 15, 4, 6, "ttmp">; 432 433// Trap handler TMP 224-bit registers 434def TTMP_224Regs : SIRegisterTuples<getSubRegs<7>.ret, TTMP_32, 15, 4, 7, "ttmp">; 435 436// Trap handler TMP 256-bit registers 437def TTMP_256Regs : SIRegisterTuples<getSubRegs<8>.ret, TTMP_32, 15, 4, 8, "ttmp">; 438 439// Trap handler TMP 512-bit registers 440def TTMP_512Regs : SIRegisterTuples<getSubRegs<16>.ret, TTMP_32, 15, 4, 16, "ttmp">; 441 442class TmpRegTuplesBase<int index, int size, 443 list<Register> subRegs, 444 list<SubRegIndex> indices = getSubRegs<size>.ret, 445 int index1 = !add(index, size, -1), 446 string name = "ttmp["#index#":"#index1#"]"> : 447 RegisterWithSubRegs<name, subRegs> { 448 let HWEncoding = subRegs[0].HWEncoding; 449 let SubRegIndices = indices; 450} 451 452class TmpRegTuples<string tgt, 453 int size, 454 int index0, 455 int index1 = !add(index0, 1), 456 int index2 = !add(index0, !if(!eq(size, 2), 1, 2)), 457 int index3 = !add(index0, !if(!eq(size, 2), 1, 3)), 458 int index4 = !add(index0, !if(!eq(size, 8), 4, 1)), 459 int index5 = !add(index0, !if(!eq(size, 8), 5, 1)), 460 int index6 = !add(index0, !if(!eq(size, 8), 6, 1)), 461 int index7 = !add(index0, !if(!eq(size, 8), 7, 1)), 462 Register r0 = !cast<Register>("TTMP"#index0#tgt), 463 Register r1 = !cast<Register>("TTMP"#index1#tgt), 464 Register r2 = !cast<Register>("TTMP"#index2#tgt), 465 Register r3 = !cast<Register>("TTMP"#index3#tgt), 466 Register r4 = !cast<Register>("TTMP"#index4#tgt), 467 Register r5 = !cast<Register>("TTMP"#index5#tgt), 468 Register r6 = !cast<Register>("TTMP"#index6#tgt), 469 Register r7 = !cast<Register>("TTMP"#index7#tgt)> : 470 TmpRegTuplesBase<index0, size, 471 !if(!eq(size, 2), [r0, r1], 472 !if(!eq(size, 4), [r0, r1, r2, r3], 473 [r0, r1, r2, r3, r4, r5, r6, r7])), 474 getSubRegs<size>.ret>; 475 476foreach Index = {0, 2, 4, 6, 8, 10, 12, 14} in { 477 def TTMP#Index#_TTMP#!add(Index,1)#_vi : TmpRegTuples<"_vi", 2, Index>; 478 def TTMP#Index#_TTMP#!add(Index,1)#_gfx9plus : TmpRegTuples<"_gfx9plus", 2, Index>; 479} 480 481foreach Index = {0, 4, 8, 12} in { 482 def TTMP#Index#_TTMP#!add(Index,1)# 483 _TTMP#!add(Index,2)# 484 _TTMP#!add(Index,3)#_vi : TmpRegTuples<"_vi", 4, Index>; 485 def TTMP#Index#_TTMP#!add(Index,1)# 486 _TTMP#!add(Index,2)# 487 _TTMP#!add(Index,3)#_gfx9plus : TmpRegTuples<"_gfx9plus", 4, Index>; 488} 489 490foreach Index = {0, 4, 8} in { 491 def TTMP#Index#_TTMP#!add(Index,1)# 492 _TTMP#!add(Index,2)# 493 _TTMP#!add(Index,3)# 494 _TTMP#!add(Index,4)# 495 _TTMP#!add(Index,5)# 496 _TTMP#!add(Index,6)# 497 _TTMP#!add(Index,7)#_vi : TmpRegTuples<"_vi", 8, Index>; 498 def TTMP#Index#_TTMP#!add(Index,1)# 499 _TTMP#!add(Index,2)# 500 _TTMP#!add(Index,3)# 501 _TTMP#!add(Index,4)# 502 _TTMP#!add(Index,5)# 503 _TTMP#!add(Index,6)# 504 _TTMP#!add(Index,7)#_gfx9plus : TmpRegTuples<"_gfx9plus", 8, Index>; 505} 506 507def TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15_vi : 508 TmpRegTuplesBase<0, 16, 509 [TTMP0_vi, TTMP1_vi, TTMP2_vi, TTMP3_vi, 510 TTMP4_vi, TTMP5_vi, TTMP6_vi, TTMP7_vi, 511 TTMP8_vi, TTMP9_vi, TTMP10_vi, TTMP11_vi, 512 TTMP12_vi, TTMP13_vi, TTMP14_vi, TTMP15_vi]>; 513 514def TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15_gfx9plus : 515 TmpRegTuplesBase<0, 16, 516 [TTMP0_gfx9plus, TTMP1_gfx9plus, TTMP2_gfx9plus, TTMP3_gfx9plus, 517 TTMP4_gfx9plus, TTMP5_gfx9plus, TTMP6_gfx9plus, TTMP7_gfx9plus, 518 TTMP8_gfx9plus, TTMP9_gfx9plus, TTMP10_gfx9plus, TTMP11_gfx9plus, 519 TTMP12_gfx9plus, TTMP13_gfx9plus, TTMP14_gfx9plus, TTMP15_gfx9plus]>; 520 521class RegisterTypes<list<ValueType> reg_types> { 522 list<ValueType> types = reg_types; 523} 524 525def Reg16Types : RegisterTypes<[i16, f16]>; 526def Reg32Types : RegisterTypes<[i32, f32, v2i16, v2f16, p2, p3, p5, p6]>; 527 528let HasVGPR = 1 in { 529def VGPR_LO16 : SIRegisterClass<"AMDGPU", Reg16Types.types, 16, 530 (add (sequence "VGPR%u_LO16", 0, 255))> { 531 let AllocationPriority = 0; 532 let Size = 16; 533 let GeneratePressureSet = 0; 534} 535 536def VGPR_HI16 : SIRegisterClass<"AMDGPU", Reg16Types.types, 16, 537 (add (sequence "VGPR%u_HI16", 0, 255))> { 538 let AllocationPriority = 0; 539 let Size = 16; 540 let GeneratePressureSet = 0; 541} 542 543// VGPR 32-bit registers 544// i16/f16 only on VI+ 545def VGPR_32 : SIRegisterClass<"AMDGPU", !listconcat(Reg32Types.types, Reg16Types.types), 32, 546 (add (sequence "VGPR%u", 0, 255))> { 547 let AllocationPriority = 0; 548 let Size = 32; 549 let Weight = 1; 550} 551} // End HasVGPR = 1 552 553// VGPR 64-bit registers 554def VGPR_64 : SIRegisterTuples<getSubRegs<2>.ret, VGPR_32, 255, 1, 2, "v">; 555 556// VGPR 96-bit registers 557def VGPR_96 : SIRegisterTuples<getSubRegs<3>.ret, VGPR_32, 255, 1, 3, "v">; 558 559// VGPR 128-bit registers 560def VGPR_128 : SIRegisterTuples<getSubRegs<4>.ret, VGPR_32, 255, 1, 4, "v">; 561 562// VGPR 160-bit registers 563def VGPR_160 : SIRegisterTuples<getSubRegs<5>.ret, VGPR_32, 255, 1, 5, "v">; 564 565// VGPR 192-bit registers 566def VGPR_192 : SIRegisterTuples<getSubRegs<6>.ret, VGPR_32, 255, 1, 6, "v">; 567 568// VGPR 224-bit registers 569def VGPR_224 : SIRegisterTuples<getSubRegs<7>.ret, VGPR_32, 255, 1, 7, "v">; 570 571// VGPR 256-bit registers 572def VGPR_256 : SIRegisterTuples<getSubRegs<8>.ret, VGPR_32, 255, 1, 8, "v">; 573 574// VGPR 512-bit registers 575def VGPR_512 : SIRegisterTuples<getSubRegs<16>.ret, VGPR_32, 255, 1, 16, "v">; 576 577// VGPR 1024-bit registers 578def VGPR_1024 : SIRegisterTuples<getSubRegs<32>.ret, VGPR_32, 255, 1, 32, "v">; 579 580let HasAGPR = 1 in { 581def AGPR_LO16 : SIRegisterClass<"AMDGPU", Reg16Types.types, 16, 582 (add (sequence "AGPR%u_LO16", 0, 255))> { 583 let isAllocatable = 0; 584 let Size = 16; 585 let GeneratePressureSet = 0; 586} 587 588// AccVGPR 32-bit registers 589def AGPR_32 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, 590 (add (sequence "AGPR%u", 0, 255))> { 591 let AllocationPriority = 0; 592 let Size = 32; 593 let Weight = 1; 594} 595} // End HasAGPR = 1 596 597// AGPR 64-bit registers 598def AGPR_64 : SIRegisterTuples<getSubRegs<2>.ret, AGPR_32, 255, 1, 2, "a">; 599 600// AGPR 96-bit registers 601def AGPR_96 : SIRegisterTuples<getSubRegs<3>.ret, AGPR_32, 255, 1, 3, "a">; 602 603// AGPR 128-bit registers 604def AGPR_128 : SIRegisterTuples<getSubRegs<4>.ret, AGPR_32, 255, 1, 4, "a">; 605 606// AGPR 160-bit registers 607def AGPR_160 : SIRegisterTuples<getSubRegs<5>.ret, AGPR_32, 255, 1, 5, "a">; 608 609// AGPR 192-bit registers 610def AGPR_192 : SIRegisterTuples<getSubRegs<6>.ret, AGPR_32, 255, 1, 6, "a">; 611 612// AGPR 224-bit registers 613def AGPR_224 : SIRegisterTuples<getSubRegs<7>.ret, AGPR_32, 255, 1, 7, "a">; 614 615// AGPR 256-bit registers 616def AGPR_256 : SIRegisterTuples<getSubRegs<8>.ret, AGPR_32, 255, 1, 8, "a">; 617 618// AGPR 512-bit registers 619def AGPR_512 : SIRegisterTuples<getSubRegs<16>.ret, AGPR_32, 255, 1, 16, "a">; 620 621// AGPR 1024-bit registers 622def AGPR_1024 : SIRegisterTuples<getSubRegs<32>.ret, AGPR_32, 255, 1, 32, "a">; 623 624//===----------------------------------------------------------------------===// 625// Register classes used as source and destination 626//===----------------------------------------------------------------------===// 627 628def Pseudo_SReg_32 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, 629 (add FP_REG, SP_REG)> { 630 let isAllocatable = 0; 631 let CopyCost = -1; 632 let HasSGPR = 1; 633} 634 635def Pseudo_SReg_128 : SIRegisterClass<"AMDGPU", [v4i32, v2i64, v2f64, v8i16, v8f16], 32, 636 (add PRIVATE_RSRC_REG)> { 637 let isAllocatable = 0; 638 let CopyCost = -1; 639 let HasSGPR = 1; 640} 641 642def LDS_DIRECT_CLASS : RegisterClass<"AMDGPU", [i32], 32, 643 (add LDS_DIRECT)> { 644 let isAllocatable = 0; 645 let CopyCost = -1; 646} 647 648let GeneratePressureSet = 0, HasSGPR = 1 in { 649// Subset of SReg_32 without M0 for SMRD instructions and alike. 650// See comments in SIInstructions.td for more info. 651def SReg_32_XM0_XEXEC : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32, 652 (add SGPR_32, VCC_LO, VCC_HI, FLAT_SCR_LO, FLAT_SCR_HI, XNACK_MASK_LO, XNACK_MASK_HI, 653 SGPR_NULL, SGPR_NULL_HI, TTMP_32, TMA_LO, TMA_HI, TBA_LO, TBA_HI, SRC_SHARED_BASE, 654 SRC_SHARED_LIMIT, SRC_PRIVATE_BASE, SRC_PRIVATE_LIMIT, SRC_POPS_EXITING_WAVE_ID, 655 SRC_VCCZ, SRC_EXECZ, SRC_SCC)> { 656 let AllocationPriority = 0; 657} 658 659def SReg_LO16_XM0_XEXEC : SIRegisterClass<"AMDGPU", [i16, f16], 16, 660 (add SGPR_LO16, VCC_LO_LO16, VCC_HI_LO16, FLAT_SCR_LO_LO16, FLAT_SCR_HI_LO16, 661 XNACK_MASK_LO_LO16, XNACK_MASK_HI_LO16, SGPR_NULL_LO16, SGPR_NULL_HI_LO16, TTMP_LO16, 662 TMA_LO_LO16, TMA_HI_LO16, TBA_LO_LO16, TBA_HI_LO16, SRC_SHARED_BASE_LO16, 663 SRC_SHARED_LIMIT_LO16, SRC_PRIVATE_BASE_LO16, SRC_PRIVATE_LIMIT_LO16, 664 SRC_POPS_EXITING_WAVE_ID_LO16, SRC_VCCZ_LO16, SRC_EXECZ_LO16, SRC_SCC_LO16)> { 665 let Size = 16; 666 let AllocationPriority = 0; 667} 668 669def SReg_32_XEXEC_HI : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32, 670 (add SReg_32_XM0_XEXEC, EXEC_LO, M0_CLASS)> { 671 let AllocationPriority = 0; 672} 673 674def SReg_LO16_XEXEC_HI : SIRegisterClass<"AMDGPU", [i16, f16], 16, 675 (add SReg_LO16_XM0_XEXEC, EXEC_LO_LO16, M0_CLASS_LO16)> { 676 let Size = 16; 677 let AllocationPriority = 0; 678} 679 680def SReg_32_XM0 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32, 681 (add SReg_32_XM0_XEXEC, EXEC_LO, EXEC_HI)> { 682 let AllocationPriority = 0; 683} 684 685def SReg_LO16_XM0 : SIRegisterClass<"AMDGPU", [i16, f16], 16, 686 (add SReg_LO16_XM0_XEXEC, EXEC_LO_LO16, EXEC_HI_LO16)> { 687 let Size = 16; 688 let AllocationPriority = 0; 689} 690 691def SReg_LO16 : SIRegisterClass<"AMDGPU", [i16, f16], 16, 692 (add SGPR_LO16, SReg_LO16_XM0, M0_CLASS_LO16, EXEC_LO_LO16, EXEC_HI_LO16, SReg_LO16_XEXEC_HI)> { 693 let Size = 16; 694 let AllocationPriority = 0; 695} 696} // End GeneratePressureSet = 0 697 698// Register class for all scalar registers (SGPRs + Special Registers) 699def SReg_32 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32, 700 (add SReg_32_XM0, M0_CLASS, EXEC_LO, EXEC_HI, SReg_32_XEXEC_HI)> { 701 let AllocationPriority = 0; 702 let HasSGPR = 1; 703} 704 705let GeneratePressureSet = 0 in { 706def SRegOrLds_32 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, 707 (add SReg_32, LDS_DIRECT_CLASS)> { 708 let isAllocatable = 0; 709 let HasSGPR = 1; 710} 711 712def SGPR_64 : SIRegisterClass<"AMDGPU", [v2i32, i64, v2f32, f64, v4i16, v4f16], 32, 713 (add SGPR_64Regs)> { 714 let CopyCost = 1; 715 let AllocationPriority = 1; 716 let HasSGPR = 1; 717} 718 719def TTMP_64 : SIRegisterClass<"AMDGPU", [v2i32, i64, f64, v4i16, v4f16], 32, 720 (add TTMP_64Regs)> { 721 let isAllocatable = 0; 722 let HasSGPR = 1; 723} 724 725def SReg_64_XEXEC : SIRegisterClass<"AMDGPU", [v2i32, i64, v2f32, f64, i1, v4i16, v4f16], 32, 726 (add SGPR_64, VCC, FLAT_SCR, XNACK_MASK, SGPR_NULL64, TTMP_64, TBA, TMA)> { 727 let CopyCost = 1; 728 let AllocationPriority = 1; 729 let HasSGPR = 1; 730} 731 732def SReg_64 : SIRegisterClass<"AMDGPU", [v2i32, i64, v2f32, f64, i1, v4i16, v4f16], 32, 733 (add SReg_64_XEXEC, EXEC)> { 734 let CopyCost = 1; 735 let AllocationPriority = 1; 736 let HasSGPR = 1; 737} 738 739def SReg_1_XEXEC : SIRegisterClass<"AMDGPU", [i1], 32, 740 (add SReg_64_XEXEC, SReg_32_XM0_XEXEC)> { 741 let CopyCost = 1; 742 let isAllocatable = 0; 743 let HasSGPR = 1; 744} 745 746def SReg_1 : SIRegisterClass<"AMDGPU", [i1], 32, 747 (add SReg_1_XEXEC, EXEC, EXEC_LO)> { 748 let CopyCost = 1; 749 let isAllocatable = 0; 750 let HasSGPR = 1; 751} 752 753multiclass SRegClass<int numRegs, 754 list<ValueType> regTypes, 755 SIRegisterTuples regList, 756 SIRegisterTuples ttmpList = regList, 757 int copyCost = !sra(!add(numRegs, 1), 1)> { 758 defvar hasTTMP = !ne(regList, ttmpList); 759 defvar suffix = !cast<string>(!mul(numRegs, 32)); 760 defvar sgprName = !strconcat("SGPR_", suffix); 761 defvar ttmpName = !strconcat("TTMP_", suffix); 762 763 let AllocationPriority = !sub(numRegs, 1), CopyCost = copyCost, HasSGPR = 1 in { 764 def "" # sgprName : SIRegisterClass<"AMDGPU", regTypes, 32, (add regList)> { 765 } 766 767 if hasTTMP then { 768 def "" # ttmpName : SIRegisterClass<"AMDGPU", regTypes, 32, (add ttmpList)> { 769 let isAllocatable = 0; 770 } 771 } 772 773 def SReg_ # suffix : 774 SIRegisterClass<"AMDGPU", regTypes, 32, 775 !con(!dag(add, [!cast<RegisterClass>(sgprName)], ["sgpr"]), 776 !if(hasTTMP, 777 !dag(add, [!cast<RegisterClass>(ttmpName)], ["ttmp"]), 778 (add)))> { 779 let isAllocatable = 0; 780 } 781 } 782} 783 784defm "" : SRegClass<3, [v3i32, v3f32], SGPR_96Regs, TTMP_96Regs>; 785defm "" : SRegClass<4, [v4i32, v4f32, v2i64, v2f64, v8i16, v8f16], SGPR_128Regs, TTMP_128Regs>; 786defm "" : SRegClass<5, [v5i32, v5f32], SGPR_160Regs, TTMP_160Regs>; 787defm "" : SRegClass<6, [v6i32, v6f32, v3i64, v3f64], SGPR_192Regs, TTMP_192Regs>; 788defm "" : SRegClass<7, [v7i32, v7f32], SGPR_224Regs, TTMP_224Regs>; 789defm "" : SRegClass<8, [v8i32, v8f32, v4i64, v4f64, v16i16, v16f16], SGPR_256Regs, TTMP_256Regs>; 790defm "" : SRegClass<16, [v16i32, v16f32, v8i64, v8f64], SGPR_512Regs, TTMP_512Regs>; 791defm "" : SRegClass<32, [v32i32, v32f32, v16i64, v16f64], SGPR_1024Regs>; 792 793def VRegOrLds_32 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, 794 (add VGPR_32, LDS_DIRECT_CLASS)> { 795 let isAllocatable = 0; 796 let HasVGPR = 1; 797} 798 799// Register class for all vector registers (VGPRs + Interpolation Registers) 800class VRegClassBase<int numRegs, list<ValueType> regTypes, dag regList> : 801 SIRegisterClass<"AMDGPU", regTypes, 32, regList> { 802 let Size = !mul(numRegs, 32); 803 804 // Requires n v_mov_b32 to copy 805 let CopyCost = numRegs; 806 let AllocationPriority = !sub(numRegs, 1); 807 let Weight = numRegs; 808} 809 810// Define a register tuple class, along with one requiring an even 811// aligned base register. 812multiclass VRegClass<int numRegs, list<ValueType> regTypes, dag regList> { 813 let HasVGPR = 1 in { 814 // Define the regular class. 815 def "" : VRegClassBase<numRegs, regTypes, regList>; 816 817 // Define 2-aligned variant 818 def _Align2 : VRegClassBase<numRegs, regTypes, (decimate regList, 2)>; 819 } 820} 821 822defm VReg_64 : VRegClass<2, [i64, f64, v2i32, v2f32, v4f16, v4i16, p0, p1, p4], 823 (add VGPR_64)>; 824defm VReg_96 : VRegClass<3, [v3i32, v3f32], (add VGPR_96)>; 825defm VReg_128 : VRegClass<4, [v4i32, v4f32, v2i64, v2f64, v8i16, v8f16], (add VGPR_128)>; 826defm VReg_160 : VRegClass<5, [v5i32, v5f32], (add VGPR_160)>; 827 828defm VReg_192 : VRegClass<6, [v6i32, v6f32, v3i64, v3f64], (add VGPR_192)>; 829defm VReg_224 : VRegClass<7, [v7i32, v7f32], (add VGPR_224)>; 830defm VReg_256 : VRegClass<8, [v8i32, v8f32, v4i64, v4f64, v16i16, v16f16], (add VGPR_256)>; 831defm VReg_512 : VRegClass<16, [v16i32, v16f32, v8i64, v8f64], (add VGPR_512)>; 832defm VReg_1024 : VRegClass<32, [v32i32, v32f32, v16i64, v16f64], (add VGPR_1024)>; 833 834multiclass ARegClass<int numRegs, list<ValueType> regTypes, dag regList> { 835 let CopyCost = !add(numRegs, numRegs, 1), HasAGPR = 1 in { 836 // Define the regular class. 837 def "" : VRegClassBase<numRegs, regTypes, regList>; 838 839 // Define 2-aligned variant 840 def _Align2 : VRegClassBase<numRegs, regTypes, (decimate regList, 2)>; 841 } 842} 843 844defm AReg_64 : ARegClass<2, [i64, f64, v2i32, v2f32, v4f16, v4i16], 845 (add AGPR_64)>; 846defm AReg_96 : ARegClass<3, [v3i32, v3f32], (add AGPR_96)>; 847defm AReg_128 : ARegClass<4, [v4i32, v4f32, v2i64, v2f64, v8i16, v8f16], (add AGPR_128)>; 848defm AReg_160 : ARegClass<5, [v5i32, v5f32], (add AGPR_160)>; 849defm AReg_192 : ARegClass<6, [v6i32, v6f32, v3i64, v3f64], (add AGPR_192)>; 850defm AReg_224 : ARegClass<7, [v7i32, v7f32], (add AGPR_224)>; 851defm AReg_256 : ARegClass<8, [v8i32, v8f32, v4i64, v4f64], (add AGPR_256)>; 852defm AReg_512 : ARegClass<16, [v16i32, v16f32, v8i64, v8f64], (add AGPR_512)>; 853defm AReg_1024 : ARegClass<32, [v32i32, v32f32, v16i64, v16f64], (add AGPR_1024)>; 854 855} // End GeneratePressureSet = 0 856 857let GeneratePressureSet = 0 in { 858// No register should ever be allocated using VReg_1. This is a hack for 859// SelectionDAG that should always be lowered by SILowerI1Copies. TableGen 860// sorts register classes based on the number of registers in them so this is 861// sorted to the end and not preferred over VGPR_32. 862def VReg_1 : SIRegisterClass<"AMDGPU", [i1], 32, (add)> { 863 let Size = 1; 864 let HasVGPR = 1; 865} 866 867def VS_32 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, 868 (add VGPR_32, SReg_32, LDS_DIRECT_CLASS)> { 869 let isAllocatable = 0; 870 let HasVGPR = 1; 871 let HasSGPR = 1; 872} 873 874def VS_64 : SIRegisterClass<"AMDGPU", [i64, f64, v2f32], 32, (add VReg_64, SReg_64)> { 875 let isAllocatable = 0; 876 let HasVGPR = 1; 877 let HasSGPR = 1; 878} 879 880def AV_32 : SIRegisterClass<"AMDGPU", VGPR_32.RegTypes, 32, (add VGPR_32, AGPR_32)> { 881 let HasVGPR = 1; 882 let HasAGPR = 1; 883} 884} // End GeneratePressureSet = 0 885 886// Define a register tuple class, along with one requiring an even 887// aligned base register. 888multiclass AVRegClass<int numRegs, list<ValueType> regTypes, 889 dag vregList, dag aregList> { 890 let HasVGPR = 1, HasAGPR = 1 in { 891 // Define the regular class. 892 def "" : VRegClassBase<numRegs, regTypes, (add vregList, aregList)>; 893 894 // Define 2-aligned variant 895 def _Align2 : VRegClassBase<numRegs, regTypes, 896 (add (decimate vregList, 2), 897 (decimate aregList, 2))>; 898 } 899} 900 901defm AV_64 : AVRegClass<2, VReg_64.RegTypes, (add VGPR_64), (add AGPR_64)>; 902defm AV_96 : AVRegClass<3, VReg_96.RegTypes, (add VGPR_96), (add AGPR_96)>; 903defm AV_128 : AVRegClass<4, VReg_128.RegTypes, (add VGPR_128), (add AGPR_128)>; 904defm AV_160 : AVRegClass<5, VReg_160.RegTypes, (add VGPR_160), (add AGPR_160)>; 905defm AV_192 : AVRegClass<6, VReg_192.RegTypes, (add VGPR_192), (add AGPR_192)>; 906defm AV_224 : AVRegClass<7, VReg_224.RegTypes, (add VGPR_224), (add AGPR_224)>; 907defm AV_256 : AVRegClass<8, VReg_256.RegTypes, (add VGPR_256), (add AGPR_256)>; 908defm AV_512 : AVRegClass<16, VReg_512.RegTypes, (add VGPR_512), (add AGPR_512)>; 909defm AV_1024 : AVRegClass<32, VReg_1024.RegTypes, (add VGPR_1024), (add AGPR_1024)>; 910 911//===----------------------------------------------------------------------===// 912// Register operands 913//===----------------------------------------------------------------------===// 914 915class RegImmMatcher<string name> : AsmOperandClass { 916 let Name = name; 917 let RenderMethod = "addRegOrImmOperands"; 918} 919 920multiclass SIRegOperand32 <string rc, string MatchName, string opType, 921 string rc_suffix = "_32"> { 922 let OperandNamespace = "AMDGPU" in { 923 def _b16 : RegisterOperand<!cast<RegisterClass>(rc#rc_suffix)> { 924 let OperandType = opType#"_INT16"; 925 let ParserMatchClass = RegImmMatcher<MatchName#"B16">; 926 let DecoderMethod = "decodeOperand_VSrc16"; 927 } 928 929 def _f16 : RegisterOperand<!cast<RegisterClass>(rc#rc_suffix)> { 930 let OperandType = opType#"_FP16"; 931 let ParserMatchClass = RegImmMatcher<MatchName#"F16">; 932 let DecoderMethod = "decodeOperand_" # rc # "_16"; 933 } 934 935 def _b32 : RegisterOperand<!cast<RegisterClass>(rc#rc_suffix)> { 936 let OperandType = opType#"_INT32"; 937 let ParserMatchClass = RegImmMatcher<MatchName#"B32">; 938 let DecoderMethod = "decodeOperand_" # rc # rc_suffix; 939 } 940 941 def _f32 : RegisterOperand<!cast<RegisterClass>(rc#rc_suffix)> { 942 let OperandType = opType#"_FP32"; 943 let ParserMatchClass = RegImmMatcher<MatchName#"F32">; 944 let DecoderMethod = "decodeOperand_" # rc # rc_suffix; 945 } 946 947 def _v2b16 : RegisterOperand<!cast<RegisterClass>(rc#rc_suffix)> { 948 let OperandType = opType#"_V2INT16"; 949 let ParserMatchClass = RegImmMatcher<MatchName#"V2B16">; 950 let DecoderMethod = "decodeOperand_VSrcV216"; 951 } 952 953 def _v2f16 : RegisterOperand<!cast<RegisterClass>(rc#rc_suffix)> { 954 let OperandType = opType#"_V2FP16"; 955 let ParserMatchClass = RegImmMatcher<MatchName#"V2F16">; 956 let DecoderMethod = "decodeOperand_VSrcV216"; 957 } 958 } 959} 960 961multiclass SIRegOperand64 <string rc, string MatchName, string opType, 962 string rc_suffix = "_64", bit Vectors = 1> { 963 let OperandNamespace = "AMDGPU" in { 964 def _b64 : RegisterOperand<!cast<RegisterClass>(rc#rc_suffix)> { 965 let OperandType = opType#"_INT64"; 966 let ParserMatchClass = RegImmMatcher<MatchName#"B64">; 967 } 968 969 def _f64 : RegisterOperand<!cast<RegisterClass>(rc#rc_suffix)> { 970 let OperandType = opType#"_FP64"; 971 let ParserMatchClass = RegImmMatcher<MatchName#"F64">; 972 } 973 974 if Vectors then 975 def _v2f32 : RegisterOperand<!cast<RegisterClass>(rc#rc_suffix)> { 976 let OperandType = opType#"_V2FP32"; 977 let ParserMatchClass = RegImmMatcher<MatchName#"V2FP32">; 978 let DecoderMethod = "decodeOperand_VSrcV232"; 979 } 980 if Vectors then 981 def _v2b32 : RegisterOperand<!cast<RegisterClass>(rc#rc_suffix)> { 982 let OperandType = opType#"_V2INT32"; 983 let ParserMatchClass = RegImmMatcher<MatchName#"V2INT32">; 984 let DecoderMethod = "decodeOperand_VSrcV232"; 985 } 986 } 987} 988 989multiclass SIRegOperand <string rc, string MatchName, string opType> : 990 SIRegOperand32<rc, MatchName, opType>, 991 SIRegOperand64<rc, MatchName, opType>; 992 993// FIXME: 64-bit sources can sometimes use 32-bit constants. 994multiclass RegImmOperand <string rc, string MatchName> 995 : SIRegOperand<rc, MatchName, "OPERAND_REG_IMM">; 996 997multiclass RegInlineOperand <string rc, string MatchName> 998 : SIRegOperand<rc, MatchName, "OPERAND_REG_INLINE_C">; 999 1000multiclass RegInlineOperand32 <string rc, string MatchName, 1001 string rc_suffix = "_32"> 1002 : SIRegOperand32<rc, MatchName, "OPERAND_REG_INLINE_C", rc_suffix>; 1003 1004multiclass RegInlineOperand64 <string rc, string MatchName, 1005 string rc_suffix = "_64"> 1006 : SIRegOperand64<rc, MatchName, "OPERAND_REG_INLINE_C", rc_suffix>; 1007 1008multiclass RegInlineOperandAC <string rc, string MatchName, 1009 string rc_suffix = "_32"> 1010 : SIRegOperand32<rc, MatchName, "OPERAND_REG_INLINE_AC", rc_suffix>; 1011 1012multiclass RegInlineOperandAC64 <string rc, string MatchName, 1013 string rc_suffix = "_64"> 1014 : SIRegOperand64<rc, MatchName, "OPERAND_REG_INLINE_AC", rc_suffix, 0>; 1015 1016//===----------------------------------------------------------------------===// 1017// SSrc_* Operands with an SGPR or a 32-bit immediate 1018//===----------------------------------------------------------------------===// 1019 1020defm SSrc : RegImmOperand<"SReg", "SSrc">; 1021 1022def SSrcOrLds_b32 : RegisterOperand<SRegOrLds_32> { 1023 let OperandNamespace = "AMDGPU"; 1024 let OperandType = "OPERAND_REG_IMM_INT32"; 1025 let ParserMatchClass = RegImmMatcher<"SSrcOrLdsB32">; 1026} 1027 1028//===----------------------------------------------------------------------===// 1029// SCSrc_* Operands with an SGPR or a inline constant 1030//===----------------------------------------------------------------------===// 1031 1032defm SCSrc : RegInlineOperand<"SReg", "SCSrc"> ; 1033 1034//===----------------------------------------------------------------------===// 1035// VSrc_* Operands with an SGPR, VGPR or a 32-bit immediate 1036//===----------------------------------------------------------------------===// 1037 1038defm VSrc : RegImmOperand<"VS", "VSrc">; 1039 1040def VSrc_128 : RegisterOperand<VReg_128> { 1041 let DecoderMethod = "DecodeVS_128RegisterClass"; 1042} 1043 1044//===----------------------------------------------------------------------===// 1045// VSrc_*_Deferred Operands with an SGPR, VGPR or a 32-bit immediate for use 1046// with FMAMK/FMAAK 1047//===----------------------------------------------------------------------===// 1048 1049multiclass SIRegOperand32_Deferred <string rc, string MatchName, string opType, 1050 string rc_suffix = "_32"> { 1051 let OperandNamespace = "AMDGPU" in { 1052 def _f16_Deferred : RegisterOperand<!cast<RegisterClass>(rc#rc_suffix)> { 1053 let OperandType = opType#"_FP16_DEFERRED"; 1054 let ParserMatchClass = RegImmMatcher<MatchName#"F16">; 1055 let DecoderMethod = "decodeOperand_" # rc # "_16_Deferred"; 1056 } 1057 1058 def _f32_Deferred : RegisterOperand<!cast<RegisterClass>(rc#rc_suffix)> { 1059 let OperandType = opType#"_FP32_DEFERRED"; 1060 let ParserMatchClass = RegImmMatcher<MatchName#"F32">; 1061 let DecoderMethod = "decodeOperand_" # rc # "_32_Deferred"; 1062 } 1063 } 1064} 1065 1066defm VSrc : SIRegOperand32_Deferred<"VS", "VSrc", "OPERAND_REG_IMM">; 1067 1068//===----------------------------------------------------------------------===// 1069// VRegSrc_* Operands with a VGPR 1070//===----------------------------------------------------------------------===// 1071 1072// This is for operands with the enum(9), VSrc encoding restriction, 1073// but only allows VGPRs. 1074def VRegSrc_32 : RegisterOperand<VGPR_32> { 1075 //let ParserMatchClass = RegImmMatcher<"VRegSrc32">; 1076 let DecoderMethod = "DecodeVS_32RegisterClass"; 1077} 1078 1079def VRegSrc_64 : RegisterOperand<VReg_64> { 1080 let DecoderMethod = "decodeOperand_VReg_64"; 1081} 1082 1083def VRegSrc_128 : RegisterOperand<VReg_128> { 1084 let DecoderMethod = "decodeOperand_VReg_128"; 1085} 1086 1087def VRegSrc_256 : RegisterOperand<VReg_256> { 1088 let DecoderMethod = "decodeOperand_VReg_256"; 1089} 1090 1091//===----------------------------------------------------------------------===// 1092// VGPRSrc_* 1093//===----------------------------------------------------------------------===// 1094 1095// An 8-bit RegisterOperand wrapper for a VGPR 1096def VGPRSrc_32 : RegisterOperand<VGPR_32> { 1097 let DecoderMethod = "DecodeVGPR_32RegisterClass"; 1098} 1099 1100//===----------------------------------------------------------------------===// 1101// ASrc_* Operands with an AccVGPR 1102//===----------------------------------------------------------------------===// 1103 1104def ARegSrc_32 : RegisterOperand<AGPR_32> { 1105 let DecoderMethod = "DecodeAGPR_32RegisterClass"; 1106 let EncoderMethod = "getAVOperandEncoding"; 1107} 1108 1109//===----------------------------------------------------------------------===// 1110// VCSrc_* Operands with an SGPR, VGPR or an inline constant 1111//===----------------------------------------------------------------------===// 1112 1113defm VCSrc : RegInlineOperand<"VS", "VCSrc">; 1114 1115//===----------------------------------------------------------------------===// 1116// VISrc_* Operands with a VGPR or an inline constant 1117//===----------------------------------------------------------------------===// 1118 1119defm VISrc : RegInlineOperand32<"VGPR", "VISrc">; 1120let DecoderMethod = "decodeOperand_VReg_64" in 1121defm VISrc_64 : RegInlineOperand64<"VReg", "VISrc_64", "_64">; 1122defm VISrc_128 : RegInlineOperandAC<"VReg", "VISrc_128", "_128">; 1123let DecoderMethod = "decodeOperand_VReg_256" in 1124defm VISrc_256 : RegInlineOperand64<"VReg", "VISrc_256", "_256">; 1125defm VISrc_512 : RegInlineOperandAC<"VReg", "VISrc_512", "_512">; 1126defm VISrc_1024 : RegInlineOperandAC<"VReg", "VISrc_1024", "_1024">; 1127 1128//===----------------------------------------------------------------------===// 1129// AVSrc_*, AVDst_*, AVLdSt_* Operands with an AGPR or VGPR 1130//===----------------------------------------------------------------------===// 1131 1132def AVSrc_32 : RegisterOperand<AV_32> { 1133 let DecoderMethod = "DecodeAV_32RegisterClass"; 1134 let EncoderMethod = "getAVOperandEncoding"; 1135} 1136 1137def AVSrc_64 : RegisterOperand<AV_64> { 1138 let DecoderMethod = "DecodeAV_64RegisterClass"; 1139 let EncoderMethod = "getAVOperandEncoding"; 1140} 1141 1142def AVSrc_128 : RegisterOperand<AV_128> { 1143 let DecoderMethod = "DecodeAV_128RegisterClass"; 1144 let EncoderMethod = "getAVOperandEncoding"; 1145} 1146 1147def AVDst_128 : RegisterOperand<AV_128> { 1148 let DecoderMethod = "DecodeAVDst_128RegisterClass"; 1149 let EncoderMethod = "getAVOperandEncoding"; 1150} 1151 1152def AVDst_512 : RegisterOperand<AV_512> { 1153 let DecoderMethod = "DecodeAVDst_512RegisterClass"; 1154 let EncoderMethod = "getAVOperandEncoding"; 1155} 1156 1157def AVLdSt_32 : RegisterOperand<AV_32> { 1158 let DecoderMethod = "DecodeAVLdSt_32RegisterClass"; 1159 let EncoderMethod = "getAVOperandEncoding"; 1160} 1161 1162def AVLdSt_64 : RegisterOperand<AV_64> { 1163 let DecoderMethod = "DecodeAVLdSt_64RegisterClass"; 1164 let EncoderMethod = "getAVOperandEncoding"; 1165} 1166 1167def AVLdSt_96 : RegisterOperand<AV_96> { 1168 let DecoderMethod = "DecodeAVLdSt_96RegisterClass"; 1169 let EncoderMethod = "getAVOperandEncoding"; 1170} 1171 1172def AVLdSt_128 : RegisterOperand<AV_128> { 1173 let DecoderMethod = "DecodeAVLdSt_128RegisterClass"; 1174 let EncoderMethod = "getAVOperandEncoding"; 1175} 1176 1177def AVLdSt_160 : RegisterOperand<AV_160> { 1178 let DecoderMethod = "DecodeAVLdSt_160RegisterClass"; 1179 let EncoderMethod = "getAVOperandEncoding"; 1180} 1181 1182//===----------------------------------------------------------------------===// 1183// ACSrc_* Operands with an AGPR or an inline constant 1184//===----------------------------------------------------------------------===// 1185 1186defm AISrc : RegInlineOperandAC<"AGPR", "AISrc">; 1187defm AISrc_128 : RegInlineOperandAC<"AReg", "AISrc_128", "_128">; 1188defm AISrc_512 : RegInlineOperandAC<"AReg", "AISrc_512", "_512">; 1189defm AISrc_1024 : RegInlineOperandAC<"AReg", "AISrc_1024", "_1024">; 1190 1191let DecoderMethod = "decodeOperand_AReg_64" in 1192defm AISrc_64 : RegInlineOperandAC64<"AReg", "AISrc_64", "_64">; 1193let DecoderMethod = "decodeOperand_AReg_256" in 1194defm AISrc_256 : RegInlineOperandAC64<"AReg", "AISrc_256", "_256">; 1195