1//===-- VINTERPInstructions.td - VINTERP Instruction Definitions ----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9//===----------------------------------------------------------------------===//
10// VINTERP encoding
11//===----------------------------------------------------------------------===//
12
13class VINTERPe_gfx11 <bits<7> op, VOPProfile P> : Enc64 {
14  bits<8> vdst;
15  bits<4> src0_modifiers;
16  bits<9> src0;
17  bits<3> src1_modifiers;
18  bits<9> src1;
19  bits<3> src2_modifiers;
20  bits<9> src2;
21  bits<1> clamp;
22  bits<3> waitexp;
23
24  let Inst{31-26} = 0x33; // VOP3P encoding
25  let Inst{25-24} = 0x1; // VINTERP sub-encoding
26
27  let Inst{7-0}   = vdst;
28  let Inst{10-8}  = waitexp;
29  let Inst{11}    = !if(P.HasOpSel, src0_modifiers{2}, 0); // op_sel(0)
30  let Inst{12}    = !if(P.HasOpSel, src1_modifiers{2}, 0); // op_sel(1)
31  let Inst{13}    = !if(P.HasOpSel, src2_modifiers{2}, 0); // op_sel(2)
32  let Inst{14}    = !if(P.HasOpSel, src0_modifiers{3}, 0); // op_sel(3)
33  let Inst{15}    = clamp;
34  let Inst{22-16} = op;
35  let Inst{40-32} = src0;
36  let Inst{49-41} = src1;
37  let Inst{58-50} = src2;
38  let Inst{61}    = src0_modifiers{0}; // neg(0)
39  let Inst{62}    = src1_modifiers{0}; // neg(1)
40  let Inst{63}    = src2_modifiers{0}; // neg(2)
41}
42
43//===----------------------------------------------------------------------===//
44// VOP3 VINTERP
45//===----------------------------------------------------------------------===//
46
47class VINTERP_Pseudo <string OpName, VOPProfile P, list<dag> pattern = []> :
48  VOP3_Pseudo<OpName, P, pattern, 0, 0> {
49  let AsmMatchConverter = "cvtVINTERP";
50  let mayRaiseFPException = 0;
51
52  let VOP3_OPSEL = 1;
53  let VINTERP = 1;
54}
55
56class VINTERP_Real <VOP_Pseudo ps, int EncodingFamily> :
57  VOP3_Real <ps, EncodingFamily> {
58  let VINTERP = 1;
59}
60
61def VOP3_VINTERP_F32 : VOPProfile<[f32, f32, f32, f32]> {
62  let HasOpSel = 0;
63  let HasModifiers = 1;
64
65  let Src0Mod = FPVRegInputMods;
66  let Src1Mod = FPVRegInputMods;
67  let Src2Mod = FPVRegInputMods;
68
69  let Outs64 = (outs VGPR_32:$vdst);
70  let Ins64 = (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
71                   Src1Mod:$src1_modifiers, VRegSrc_32:$src1,
72                   Src2Mod:$src2_modifiers, VRegSrc_32:$src2,
73                   clampmod:$clamp,
74                   wait_exp:$waitexp);
75
76  let Asm64 = " $vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$clamp$waitexp";
77}
78
79class VOP3_VINTERP_F16 <list<ValueType> ArgVT> : VOPProfile<ArgVT> {
80  let HasOpSel = 1;
81  let HasModifiers = 1;
82
83  let Src0Mod = FPVRegInputMods;
84  let Src1Mod = FPVRegInputMods;
85  let Src2Mod = FPVRegInputMods;
86
87  let Outs64 = (outs VGPR_32:$vdst);
88  let Ins64 = (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
89                   Src1Mod:$src1_modifiers, VRegSrc_32:$src1,
90                   Src2Mod:$src2_modifiers, VRegSrc_32:$src2,
91                   clampmod:$clamp, op_sel0:$op_sel,
92                   wait_exp:$waitexp);
93
94  let Asm64 = " $vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$clamp$op_sel$waitexp";
95}
96
97//===----------------------------------------------------------------------===//
98// VINTERP Pseudo Instructions
99//===----------------------------------------------------------------------===//
100
101let SubtargetPredicate = isGFX11Plus in {
102
103let Uses = [M0, EXEC, MODE] in {
104def V_INTERP_P10_F32_inreg : VINTERP_Pseudo <"v_interp_p10_f32", VOP3_VINTERP_F32>;
105def V_INTERP_P2_F32_inreg : VINTERP_Pseudo <"v_interp_p2_f32", VOP3_VINTERP_F32>;
106def V_INTERP_P10_F16_F32_inreg :
107  VINTERP_Pseudo <"v_interp_p10_f16_f32", VOP3_VINTERP_F16<[f32, f32, f32, f32]>>;
108def V_INTERP_P2_F16_F32_inreg :
109  VINTERP_Pseudo <"v_interp_p2_f16_f32", VOP3_VINTERP_F16<[f16, f32, f32, f32]>>;
110} // Uses = [M0, EXEC, MODE]
111
112let Uses = [M0, EXEC] in {
113def V_INTERP_P10_RTZ_F16_F32_inreg :
114  VINTERP_Pseudo <"v_interp_p10_rtz_f16_f32", VOP3_VINTERP_F16<[f32, f32, f32, f32]>>;
115def V_INTERP_P2_RTZ_F16_F32_inreg :
116  VINTERP_Pseudo <"v_interp_p2_rtz_f16_f32", VOP3_VINTERP_F16<[f16, f32, f32, f32]>>;
117} // Uses = [M0, EXEC]
118
119} // SubtargetPredicate = isGFX11Plus
120
121class VInterpF32Pat <SDPatternOperator op, Instruction inst> : GCNPat <
122   (f32 (op
123      (VINTERPMods f32:$src0, i32:$src0_modifiers),
124      (VINTERPMods f32:$src1, i32:$src1_modifiers),
125      (VINTERPMods f32:$src2, i32:$src2_modifiers))),
126    (inst $src0_modifiers, $src0,
127          $src1_modifiers, $src1,
128          $src2_modifiers, $src2,
129          0, /* clamp */
130          7) /* wait_exp */
131>;
132
133def VINTERP_OPSEL {
134  int LOW = 0;
135  int HIGH = 0xa;
136}
137
138class VInterpF16Pat <SDPatternOperator op, Instruction inst,
139                     ValueType dst_type, bit high,
140                     list<ComplexPattern> pat> : GCNPat <
141   (dst_type (op
142      (pat[0] f32:$src0, i32:$src0_modifiers),
143      (pat[1] f32:$src1, i32:$src1_modifiers),
144      (pat[2] f32:$src2, i32:$src2_modifiers),
145      !if(high, (i1 -1), (i1 0)))),
146    (inst $src0_modifiers, $src0,
147          $src1_modifiers, $src1,
148          $src2_modifiers, $src2,
149          0, /* clamp */
150          /* op_sel = 0 */
151          7) /* wait_exp */
152>;
153
154multiclass VInterpF16Pat <SDPatternOperator op, Instruction inst,
155                          ValueType dst_type, list<ComplexPattern> high_pat> {
156  def : VInterpF16Pat<op, inst, dst_type, 0,
157                      [VINTERPMods, VINTERPMods, VINTERPMods]>;
158  def : VInterpF16Pat<op, inst, dst_type, 1, high_pat>;
159}
160
161def : VInterpF32Pat<int_amdgcn_interp_inreg_p10, V_INTERP_P10_F32_inreg>;
162def : VInterpF32Pat<int_amdgcn_interp_inreg_p2, V_INTERP_P2_F32_inreg>;
163defm : VInterpF16Pat<int_amdgcn_interp_inreg_p10_f16,
164                     V_INTERP_P10_F16_F32_inreg, f32,
165                     [VINTERPModsHi, VINTERPMods, VINTERPModsHi]>;
166defm : VInterpF16Pat<int_amdgcn_interp_inreg_p2_f16,
167                     V_INTERP_P2_F16_F32_inreg, f16,
168                     [VINTERPModsHi, VINTERPMods, VINTERPMods]>;
169
170//===----------------------------------------------------------------------===//
171// VINTERP Real Instructions
172//===----------------------------------------------------------------------===//
173
174let AssemblerPredicate = isGFX11Plus, DecoderNamespace = "GFX11" in {
175  multiclass VINTERP_Real_gfx11 <bits<7> op> {
176    def _gfx11 :
177      VINTERP_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.GFX11>,
178      VINTERPe_gfx11<op, !cast<VOP3_Pseudo>(NAME).Pfl>;
179  }
180}
181
182defm V_INTERP_P10_F32_inreg  : VINTERP_Real_gfx11<0x000>;
183defm V_INTERP_P2_F32_inreg  : VINTERP_Real_gfx11<0x001>;
184defm V_INTERP_P10_F16_F32_inreg  : VINTERP_Real_gfx11<0x002>;
185defm V_INTERP_P2_F16_F32_inreg  : VINTERP_Real_gfx11<0x003>;
186defm V_INTERP_P10_RTZ_F16_F32_inreg  : VINTERP_Real_gfx11<0x004>;
187defm V_INTERP_P2_RTZ_F16_F32_inreg  : VINTERP_Real_gfx11<0x005>;
188