15ffd83dbSDimitry Andric//===-- VOP2Instructions.td - Vector Instruction Definitions --------------===// 20b57cec5SDimitry Andric// 30b57cec5SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric// 70b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric 90b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 100b57cec5SDimitry Andric// VOP2 Classes 110b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 120b57cec5SDimitry Andric 130b57cec5SDimitry Andricclass VOP2e <bits<6> op, VOPProfile P> : Enc32 { 140b57cec5SDimitry Andric bits<8> vdst; 150b57cec5SDimitry Andric bits<9> src0; 160b57cec5SDimitry Andric bits<8> src1; 170b57cec5SDimitry Andric 180b57cec5SDimitry Andric let Inst{8-0} = !if(P.HasSrc0, src0, 0); 190b57cec5SDimitry Andric let Inst{16-9} = !if(P.HasSrc1, src1, 0); 200b57cec5SDimitry Andric let Inst{24-17} = !if(P.EmitDst, vdst, 0); 210b57cec5SDimitry Andric let Inst{30-25} = op; 220b57cec5SDimitry Andric let Inst{31} = 0x0; //encoding 230b57cec5SDimitry Andric} 240b57cec5SDimitry Andric 250b57cec5SDimitry Andricclass VOP2_MADKe <bits<6> op, VOPProfile P> : Enc64 { 260b57cec5SDimitry Andric bits<8> vdst; 270b57cec5SDimitry Andric bits<9> src0; 280b57cec5SDimitry Andric bits<8> src1; 290b57cec5SDimitry Andric bits<32> imm; 300b57cec5SDimitry Andric 310b57cec5SDimitry Andric let Inst{8-0} = !if(P.HasSrc0, src0, 0); 320b57cec5SDimitry Andric let Inst{16-9} = !if(P.HasSrc1, src1, 0); 330b57cec5SDimitry Andric let Inst{24-17} = !if(P.EmitDst, vdst, 0); 340b57cec5SDimitry Andric let Inst{30-25} = op; 350b57cec5SDimitry Andric let Inst{31} = 0x0; // encoding 360b57cec5SDimitry Andric let Inst{63-32} = imm; 370b57cec5SDimitry Andric} 380b57cec5SDimitry Andric 390b57cec5SDimitry Andricclass VOP2_SDWAe <bits<6> op, VOPProfile P> : VOP_SDWAe <P> { 400b57cec5SDimitry Andric bits<8> vdst; 410b57cec5SDimitry Andric bits<8> src1; 420b57cec5SDimitry Andric 430b57cec5SDimitry Andric let Inst{8-0} = 0xf9; // sdwa 440b57cec5SDimitry Andric let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, 0); 450b57cec5SDimitry Andric let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0); 460b57cec5SDimitry Andric let Inst{30-25} = op; 470b57cec5SDimitry Andric let Inst{31} = 0x0; // encoding 480b57cec5SDimitry Andric} 490b57cec5SDimitry Andric 500b57cec5SDimitry Andricclass VOP2_SDWA9Ae <bits<6> op, VOPProfile P> : VOP_SDWA9Ae <P> { 510b57cec5SDimitry Andric bits<8> vdst; 520b57cec5SDimitry Andric bits<9> src1; 530b57cec5SDimitry Andric 540b57cec5SDimitry Andric let Inst{8-0} = 0xf9; // sdwa 550b57cec5SDimitry Andric let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, 0); 560b57cec5SDimitry Andric let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0); 570b57cec5SDimitry Andric let Inst{30-25} = op; 580b57cec5SDimitry Andric let Inst{31} = 0x0; // encoding 590b57cec5SDimitry Andric let Inst{63} = !if(P.HasSrc1, src1{8}, 0); // src1_sgpr 600b57cec5SDimitry Andric} 610b57cec5SDimitry Andric 620b57cec5SDimitry Andricclass VOP2_Pseudo <string opName, VOPProfile P, list<dag> pattern=[], string suffix = "_e32"> : 630b57cec5SDimitry Andric VOP_Pseudo <opName, suffix, P, P.Outs32, P.Ins32, "", pattern> { 640b57cec5SDimitry Andric 650b57cec5SDimitry Andric let AsmOperands = P.Asm32; 660b57cec5SDimitry Andric 670b57cec5SDimitry Andric let Size = 4; 680b57cec5SDimitry Andric let mayLoad = 0; 690b57cec5SDimitry Andric let mayStore = 0; 700b57cec5SDimitry Andric let hasSideEffects = 0; 710b57cec5SDimitry Andric 727a6dacacSDimitry Andric let ReadsModeReg = !or(P.DstVT.isFP, P.Src0VT.isFP); 735ffd83dbSDimitry Andric 745ffd83dbSDimitry Andric let mayRaiseFPException = ReadsModeReg; 755ffd83dbSDimitry Andric 760b57cec5SDimitry Andric let VOP2 = 1; 770b57cec5SDimitry Andric let VALU = 1; 785ffd83dbSDimitry Andric let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]); 790b57cec5SDimitry Andric 800b57cec5SDimitry Andric let AsmVariantName = AMDGPUAsmVariants.Default; 810b57cec5SDimitry Andric} 820b57cec5SDimitry Andric 8381ad6265SDimitry Andricclass VOP2_Real <VOP2_Pseudo ps, int EncodingFamily, string real_name = ps.Mnemonic> : 84fe6060f1SDimitry Andric VOP_Real <ps>, 8581ad6265SDimitry Andric InstSI <ps.OutOperandList, ps.InOperandList, real_name # ps.AsmOperands, []>, 860b57cec5SDimitry Andric SIMCInstr <ps.PseudoInstr, EncodingFamily> { 870b57cec5SDimitry Andric 88fe6060f1SDimitry Andric let VALU = 1; 89fe6060f1SDimitry Andric let VOP2 = 1; 900b57cec5SDimitry Andric let isPseudo = 0; 910b57cec5SDimitry Andric let isCodeGenOnly = 0; 920b57cec5SDimitry Andric 930b57cec5SDimitry Andric let Constraints = ps.Constraints; 940b57cec5SDimitry Andric let DisableEncoding = ps.DisableEncoding; 950b57cec5SDimitry Andric 960b57cec5SDimitry Andric // copy relevant pseudo op flags 970b57cec5SDimitry Andric let SubtargetPredicate = ps.SubtargetPredicate; 98e8d8bef9SDimitry Andric let OtherPredicates = ps.OtherPredicates; 990b57cec5SDimitry Andric let AsmMatchConverter = ps.AsmMatchConverter; 1000b57cec5SDimitry Andric let AsmVariantName = ps.AsmVariantName; 1010b57cec5SDimitry Andric let Constraints = ps.Constraints; 1020b57cec5SDimitry Andric let DisableEncoding = ps.DisableEncoding; 1030b57cec5SDimitry Andric let TSFlags = ps.TSFlags; 1040b57cec5SDimitry Andric let UseNamedOperandTable = ps.UseNamedOperandTable; 1050b57cec5SDimitry Andric let Uses = ps.Uses; 1060b57cec5SDimitry Andric let Defs = ps.Defs; 107fe6060f1SDimitry Andric let SchedRW = ps.SchedRW; 108fe6060f1SDimitry Andric let mayLoad = ps.mayLoad; 109fe6060f1SDimitry Andric let mayStore = ps.mayStore; 1100b57cec5SDimitry Andric} 1110b57cec5SDimitry Andric 1125f757f3fSDimitry Andricclass VOP2_Real_Gen <VOP2_Pseudo ps, GFXGen Gen, string real_name = ps.Mnemonic> : 1135f757f3fSDimitry Andric VOP2_Real <ps, Gen.Subtarget, real_name> { 114297eecfbSDimitry Andric let AssemblerPredicate = Gen.AssemblerPredicate; 115297eecfbSDimitry Andric let OtherPredicates = !if(ps.Pfl.IsRealTrue16, [UseRealTrue16Insts], []); 1165f757f3fSDimitry Andric let DecoderNamespace = Gen.DecoderNamespace# 1175f757f3fSDimitry Andric !if(ps.Pfl.IsRealTrue16, "", "_FAKE16"); 1185f757f3fSDimitry Andric} 1195f757f3fSDimitry Andric 1200b57cec5SDimitry Andricclass VOP2_SDWA_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> : 1210b57cec5SDimitry Andric VOP_SDWA_Pseudo <OpName, P, pattern> { 1220b57cec5SDimitry Andric let AsmMatchConverter = "cvtSdwaVOP2"; 1230b57cec5SDimitry Andric} 1240b57cec5SDimitry Andric 1250b57cec5SDimitry Andricclass VOP2_DPP_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> : 1260b57cec5SDimitry Andric VOP_DPP_Pseudo <OpName, P, pattern> { 1270b57cec5SDimitry Andric} 1280b57cec5SDimitry Andric 1290b57cec5SDimitry Andric 1300b57cec5SDimitry Andricclass getVOP2Pat64 <SDPatternOperator node, VOPProfile P> : LetDummies { 1310b57cec5SDimitry Andric list<dag> ret = !if(P.HasModifiers, 1320b57cec5SDimitry Andric [(set P.DstVT:$vdst, 1330b57cec5SDimitry Andric (node (P.Src0VT 1340b57cec5SDimitry Andric !if(P.HasOMod, 1350b57cec5SDimitry Andric (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod), 1360b57cec5SDimitry Andric (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))), 1370b57cec5SDimitry Andric (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))], 1380b57cec5SDimitry Andric [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]); 1390b57cec5SDimitry Andric} 1400b57cec5SDimitry Andric 1410b57cec5SDimitry Andricmulticlass VOP2Inst_e32<string opName, 1420b57cec5SDimitry Andric VOPProfile P, 1430b57cec5SDimitry Andric SDPatternOperator node = null_frag, 1440b57cec5SDimitry Andric string revOp = opName, 1450b57cec5SDimitry Andric bit GFX9Renamed = 0> { 1460b57cec5SDimitry Andric let renamedInGFX9 = GFX9Renamed in { 1470b57cec5SDimitry Andric def _e32 : VOP2_Pseudo <opName, P, VOPPatOrNull<node,P>.ret>, 1480b57cec5SDimitry Andric Commutable_REV<revOp#"_e32", !eq(revOp, opName)>; 1490b57cec5SDimitry Andric } // End renamedInGFX9 = GFX9Renamed 1500b57cec5SDimitry Andric} 15181ad6265SDimitry Andricmulticlass 15281ad6265SDimitry Andric VOP2Inst_e32_VOPD<string opName, VOPProfile P, bits<5> VOPDOp, 15381ad6265SDimitry Andric string VOPDName, SDPatternOperator node = null_frag, 15481ad6265SDimitry Andric string revOp = opName, bit GFX9Renamed = 0> { 15581ad6265SDimitry Andric defm NAME : VOP2Inst_e32<opName, P, node, revOp, GFX9Renamed>, 15681ad6265SDimitry Andric VOPD_Component<VOPDOp, VOPDName>; 15781ad6265SDimitry Andric} 1580b57cec5SDimitry Andricmulticlass VOP2Inst_e64<string opName, 1590b57cec5SDimitry Andric VOPProfile P, 1600b57cec5SDimitry Andric SDPatternOperator node = null_frag, 1610b57cec5SDimitry Andric string revOp = opName, 1620b57cec5SDimitry Andric bit GFX9Renamed = 0> { 1630b57cec5SDimitry Andric let renamedInGFX9 = GFX9Renamed in { 16481ad6265SDimitry Andric def _e64 : VOP3InstBase <opName, P, node, 1>, 1650b57cec5SDimitry Andric Commutable_REV<revOp#"_e64", !eq(revOp, opName)>; 16681ad6265SDimitry Andric 16781ad6265SDimitry Andric let SubtargetPredicate = isGFX11Plus in { 16806c3fb27SDimitry Andric if P.HasExtVOP3DPP then 16981ad6265SDimitry Andric def _e64_dpp : VOP3_DPP_Pseudo <opName, P>; 17081ad6265SDimitry Andric } // End SubtargetPredicate = isGFX11Plus 1710b57cec5SDimitry Andric } // End renamedInGFX9 = GFX9Renamed 1720b57cec5SDimitry Andric} 1730b57cec5SDimitry Andric 1740b57cec5SDimitry Andricmulticlass VOP2Inst_sdwa<string opName, 1750b57cec5SDimitry Andric VOPProfile P, 1760b57cec5SDimitry Andric bit GFX9Renamed = 0> { 1770b57cec5SDimitry Andric let renamedInGFX9 = GFX9Renamed in { 17806c3fb27SDimitry Andric if P.HasExtSDWA then 1790b57cec5SDimitry Andric def _sdwa : VOP2_SDWA_Pseudo <opName, P>; 1800b57cec5SDimitry Andric } // End renamedInGFX9 = GFX9Renamed 1810b57cec5SDimitry Andric} 1820b57cec5SDimitry Andric 1830b57cec5SDimitry Andricmulticlass VOP2Inst<string opName, 1840b57cec5SDimitry Andric VOPProfile P, 1850b57cec5SDimitry Andric SDPatternOperator node = null_frag, 1860b57cec5SDimitry Andric string revOp = opName, 1870b57cec5SDimitry Andric bit GFX9Renamed = 0> : 1880b57cec5SDimitry Andric VOP2Inst_e32<opName, P, node, revOp, GFX9Renamed>, 1890b57cec5SDimitry Andric VOP2Inst_e64<opName, P, node, revOp, GFX9Renamed>, 190349cc55cSDimitry Andric VOP2Inst_sdwa<opName, P, GFX9Renamed> { 1910b57cec5SDimitry Andric let renamedInGFX9 = GFX9Renamed in { 19206c3fb27SDimitry Andric if P.HasExtDPP then 1930b57cec5SDimitry Andric def _dpp : VOP2_DPP_Pseudo <opName, P>; 1940b57cec5SDimitry Andric } 1950b57cec5SDimitry Andric} 1960b57cec5SDimitry Andric 197bdd1243dSDimitry Andricmulticlass VOP2Inst_t16<string opName, 198bdd1243dSDimitry Andric VOPProfile P, 199bdd1243dSDimitry Andric SDPatternOperator node = null_frag, 200bdd1243dSDimitry Andric string revOp = opName, 201bdd1243dSDimitry Andric bit GFX9Renamed = 0> { 202bdd1243dSDimitry Andric let SubtargetPredicate = NotHasTrue16BitInsts, OtherPredicates = [Has16BitInsts] in { 203bdd1243dSDimitry Andric defm NAME : VOP2Inst<opName, P, node, revOp, GFX9Renamed>; 204bdd1243dSDimitry Andric } 2055f757f3fSDimitry Andric let SubtargetPredicate = UseRealTrue16Insts in { 206bdd1243dSDimitry Andric defm _t16 : VOP2Inst<opName#"_t16", VOPProfile_True16<P>, node, revOp#"_t16", GFX9Renamed>; 207bdd1243dSDimitry Andric } 2085f757f3fSDimitry Andric let SubtargetPredicate = UseFakeTrue16Insts in { 2095f757f3fSDimitry Andric defm _fake16 : VOP2Inst<opName#"_fake16", VOPProfile_Fake16<P>, node, revOp#"_fake16", GFX9Renamed>; 2105f757f3fSDimitry Andric } 211bdd1243dSDimitry Andric} 212bdd1243dSDimitry Andric 213bdd1243dSDimitry Andric// Creating a _t16_e32 pseudo when there is no corresponding real instruction on 214bdd1243dSDimitry Andric// any subtarget is a problem. It makes getMCOpcodeGen return -1, which we 215bdd1243dSDimitry Andric// assume means the instruction is already a real. The fix is to not create that 216bdd1243dSDimitry Andric// _t16_e32 pseudo 217bdd1243dSDimitry Andricmulticlass VOP2Inst_e64_t16<string opName, 218bdd1243dSDimitry Andric VOPProfile P, 219bdd1243dSDimitry Andric SDPatternOperator node = null_frag, 220bdd1243dSDimitry Andric string revOp = opName, 221bdd1243dSDimitry Andric bit GFX9Renamed = 0> { 222bdd1243dSDimitry Andric let SubtargetPredicate = NotHasTrue16BitInsts, OtherPredicates = [Has16BitInsts] in { 223bdd1243dSDimitry Andric defm NAME : VOP2Inst<opName, P, node, revOp, GFX9Renamed>; 224bdd1243dSDimitry Andric } 225bdd1243dSDimitry Andric let SubtargetPredicate = HasTrue16BitInsts in { 2265f757f3fSDimitry Andric defm _t16 : VOP2Inst_e64<opName#"_t16", VOPProfile_Fake16<P>, node, revOp#"_t16", GFX9Renamed>; 227bdd1243dSDimitry Andric } 228bdd1243dSDimitry Andric} 229bdd1243dSDimitry Andric 23081ad6265SDimitry Andricmulticlass VOP2Inst_VOPD<string opName, 23181ad6265SDimitry Andric VOPProfile P, 23281ad6265SDimitry Andric bits<5> VOPDOp, 23381ad6265SDimitry Andric string VOPDName, 23481ad6265SDimitry Andric SDPatternOperator node = null_frag, 23581ad6265SDimitry Andric string revOp = opName, 23681ad6265SDimitry Andric bit GFX9Renamed = 0> : 23781ad6265SDimitry Andric VOP2Inst_e32_VOPD<opName, P, VOPDOp, VOPDName, node, revOp, GFX9Renamed>, 23881ad6265SDimitry Andric VOP2Inst_e64<opName, P, node, revOp, GFX9Renamed>, 23981ad6265SDimitry Andric VOP2Inst_sdwa<opName, P, GFX9Renamed> { 24081ad6265SDimitry Andric let renamedInGFX9 = GFX9Renamed in { 24106c3fb27SDimitry Andric if P.HasExtDPP then 24281ad6265SDimitry Andric def _dpp : VOP2_DPP_Pseudo <opName, P>; 24381ad6265SDimitry Andric } 24481ad6265SDimitry Andric} 24581ad6265SDimitry Andric 2460b57cec5SDimitry Andricmulticlass VOP2bInst <string opName, 2470b57cec5SDimitry Andric VOPProfile P, 2480b57cec5SDimitry Andric SDPatternOperator node = null_frag, 2490b57cec5SDimitry Andric string revOp = opName, 2500b57cec5SDimitry Andric bit GFX9Renamed = 0, 2510b57cec5SDimitry Andric bit useSGPRInput = !eq(P.NumSrcArgs, 3)> { 2520b57cec5SDimitry Andric let renamedInGFX9 = GFX9Renamed in { 2530b57cec5SDimitry Andric let SchedRW = [Write32Bit, WriteSALU] in { 2540b57cec5SDimitry Andric let Uses = !if(useSGPRInput, [VCC, EXEC], [EXEC]), Defs = [VCC] in { 2550b57cec5SDimitry Andric def _e32 : VOP2_Pseudo <opName, P, VOPPatOrNull<node,P>.ret>, 2560b57cec5SDimitry Andric Commutable_REV<revOp#"_e32", !eq(revOp, opName)> { 257349cc55cSDimitry Andric let usesCustomInserter = true; 2580b57cec5SDimitry Andric } 2590b57cec5SDimitry Andric 26006c3fb27SDimitry Andric if P.HasExtSDWA then 2610b57cec5SDimitry Andric def _sdwa : VOP2_SDWA_Pseudo <opName, P> { 2620b57cec5SDimitry Andric let AsmMatchConverter = "cvtSdwaVOP2b"; 2630b57cec5SDimitry Andric } 26406c3fb27SDimitry Andric if P.HasExtDPP then 2650b57cec5SDimitry Andric def _dpp : VOP2_DPP_Pseudo <opName, P>; 26681ad6265SDimitry Andric } // End Uses = !if(useSGPRInput, [VCC, EXEC], [EXEC]), Defs = [VCC] 2670b57cec5SDimitry Andric 26881ad6265SDimitry Andric def _e64 : VOP3InstBase <opName, P, node, 1>, 2690b57cec5SDimitry Andric Commutable_REV<revOp#"_e64", !eq(revOp, opName)>; 27081ad6265SDimitry Andric 27181ad6265SDimitry Andric let SubtargetPredicate = isGFX11Plus in { 27206c3fb27SDimitry Andric if P.HasExtVOP3DPP then 27381ad6265SDimitry Andric def _e64_dpp : VOP3_DPP_Pseudo <opName, P>; 27481ad6265SDimitry Andric } // End SubtargetPredicate = isGFX11Plus 2750b57cec5SDimitry Andric } 2760b57cec5SDimitry Andric } 2770b57cec5SDimitry Andric} 2780b57cec5SDimitry Andric 2790b57cec5SDimitry Andricclass VOP2bInstAlias <VOP2_Pseudo ps, Instruction inst, 2800b57cec5SDimitry Andric string OpName, string opnd> : 2810b57cec5SDimitry Andric InstAlias <OpName#" "#!subst("vcc", opnd, ps.Pfl.Asm32), 2820b57cec5SDimitry Andric (inst ps.Pfl.DstRC:$vdst, ps.Pfl.Src0RC32:$src0, 283bdd1243dSDimitry Andric ps.Pfl.Src1RC32:$src1), 284bdd1243dSDimitry Andric 1, inst.AsmVariantName>, 2850b57cec5SDimitry Andric PredicateControl { 2860b57cec5SDimitry Andric} 2870b57cec5SDimitry Andric 2880b57cec5SDimitry Andricmulticlass VOP2bInstAliases<VOP2_Pseudo ps, VOP2_Real inst, string OpName> { 2890b57cec5SDimitry Andric let WaveSizePredicate = isWave32 in { 2900b57cec5SDimitry Andric def : VOP2bInstAlias<ps, inst, OpName, "vcc_lo">; 2910b57cec5SDimitry Andric } 2920b57cec5SDimitry Andric let WaveSizePredicate = isWave64 in { 2930b57cec5SDimitry Andric def : VOP2bInstAlias<ps, inst, OpName, "vcc">; 2940b57cec5SDimitry Andric } 2950b57cec5SDimitry Andric} 2960b57cec5SDimitry Andric 29781ad6265SDimitry Andricmulticlass 29881ad6265SDimitry Andric VOP2eInst_Base<string opName, VOPProfile P, bits<5> VOPDOp, string VOPDName, 29981ad6265SDimitry Andric SDPatternOperator node, string revOp, bit useSGPRInput> { 3000b57cec5SDimitry Andric 3010b57cec5SDimitry Andric let SchedRW = [Write32Bit] in { 3020b57cec5SDimitry Andric let Uses = !if(useSGPRInput, [VCC, EXEC], [EXEC]) in { 30381ad6265SDimitry Andric if !eq(VOPDOp, -1) then 3040b57cec5SDimitry Andric def _e32 : VOP2_Pseudo <opName, P>, 3050b57cec5SDimitry Andric Commutable_REV<revOp#"_e32", !eq(revOp, opName)>; 30681ad6265SDimitry Andric else 30781ad6265SDimitry Andric def _e32 : VOP2_Pseudo <opName, P>, 30881ad6265SDimitry Andric Commutable_REV<revOp#"_e32", !eq(revOp, opName)>, 30981ad6265SDimitry Andric VOPD_Component<VOPDOp, VOPDName>; 3100b57cec5SDimitry Andric 31106c3fb27SDimitry Andric if P.HasExtSDWA then 3120b57cec5SDimitry Andric def _sdwa : VOP2_SDWA_Pseudo <opName, P> { 3138bcb0991SDimitry Andric let AsmMatchConverter = "cvtSdwaVOP2e"; 3140b57cec5SDimitry Andric } 3150b57cec5SDimitry Andric 31606c3fb27SDimitry Andric if P.HasExtDPP then 3170b57cec5SDimitry Andric def _dpp : VOP2_DPP_Pseudo <opName, P>; 3180b57cec5SDimitry Andric } 3190b57cec5SDimitry Andric 32081ad6265SDimitry Andric def _e64 : VOP3InstBase <opName, P, node, 1>, 321fe6060f1SDimitry Andric Commutable_REV<revOp#"_e64", !eq(revOp, opName)> { 322fe6060f1SDimitry Andric let isReMaterializable = 1; 323fe6060f1SDimitry Andric } 32481ad6265SDimitry Andric 32581ad6265SDimitry Andric let SubtargetPredicate = isGFX11Plus in { 32606c3fb27SDimitry Andric if P.HasExtVOP3DPP then 32781ad6265SDimitry Andric def _e64_dpp : VOP3_DPP_Pseudo <opName, P>; 32881ad6265SDimitry Andric } // End SubtargetPredicate = isGFX11Plus 3290b57cec5SDimitry Andric } 3300b57cec5SDimitry Andric} 3310b57cec5SDimitry Andric 33281ad6265SDimitry Andricmulticlass 33381ad6265SDimitry Andric VOP2eInst<string opName, VOPProfile P, SDPatternOperator node = null_frag, 33481ad6265SDimitry Andric string revOp = opName, bit useSGPRInput = !eq(P.NumSrcArgs, 3)> 33581ad6265SDimitry Andric : VOP2eInst_Base<opName, P, -1, "", node, revOp, useSGPRInput>; 33681ad6265SDimitry Andric 33781ad6265SDimitry Andricmulticlass 33881ad6265SDimitry Andric VOP2eInst_VOPD<string opName, VOPProfile P, bits<5> VOPDOp, string VOPDName, 33981ad6265SDimitry Andric SDPatternOperator node = null_frag, string revOp = opName, 34081ad6265SDimitry Andric bit useSGPRInput = !eq(P.NumSrcArgs, 3)> 34181ad6265SDimitry Andric : VOP2eInst_Base<opName, P, VOPDOp, VOPDName, node, revOp, useSGPRInput>; 34281ad6265SDimitry Andric 343e8d8bef9SDimitry Andricclass VOP2eInstAlias <VOP2_Pseudo ps, Instruction inst, string opnd = ""> : 3440b57cec5SDimitry Andric InstAlias <ps.OpName#" "#ps.Pfl.Asm32#", "#opnd, 3450b57cec5SDimitry Andric (inst ps.Pfl.DstRC:$vdst, ps.Pfl.Src0RC32:$src0, 346bdd1243dSDimitry Andric ps.Pfl.Src1RC32:$src1), 347bdd1243dSDimitry Andric 1, inst.AsmVariantName>, 348bdd1243dSDimitry Andric PredicateControl; 349e8d8bef9SDimitry Andric 350e8d8bef9SDimitry Andricclass VOP2e64InstAlias <VOP3_Pseudo ps, Instruction inst> : 351e8d8bef9SDimitry Andric InstAlias <ps.OpName#" "#ps.Pfl.Asm64, 352e8d8bef9SDimitry Andric (inst ps.Pfl.DstRC:$vdst, VOPDstS64orS32:$sdst, 353bdd1243dSDimitry Andric ps.Pfl.Src0RC32:$src0, ps.Pfl.Src1RC32:$src1, clampmod:$clamp), 354bdd1243dSDimitry Andric 1, inst.AsmVariantName>, 355e8d8bef9SDimitry Andric PredicateControl; 3560b57cec5SDimitry Andric 3570b57cec5SDimitry Andricmulticlass VOP2eInstAliases<VOP2_Pseudo ps, VOP2_Real inst> { 3580b57cec5SDimitry Andric let WaveSizePredicate = isWave32 in { 3590b57cec5SDimitry Andric def : VOP2eInstAlias<ps, inst, "vcc_lo">; 3600b57cec5SDimitry Andric } 3610b57cec5SDimitry Andric let WaveSizePredicate = isWave64 in { 3620b57cec5SDimitry Andric def : VOP2eInstAlias<ps, inst, "vcc">; 3630b57cec5SDimitry Andric } 3640b57cec5SDimitry Andric} 3650b57cec5SDimitry Andric 36681ad6265SDimitry Andricclass VOP_MADK_Base<ValueType vt> : VOPProfile <[vt, vt, vt, vt]> { 36781ad6265SDimitry Andric string AsmVOPDXDeferred = ?; 36881ad6265SDimitry Andric} 36981ad6265SDimitry Andric 37081ad6265SDimitry Andricclass VOP_MADAK <ValueType vt> : VOP_MADK_Base<vt> { 37106c3fb27SDimitry Andric field Operand ImmOpType = !if(!eq(vt.Size, 32), KImmFP32, KImmFP16); 3728bcb0991SDimitry Andric field dag Ins32 = !if(!eq(vt.Size, 32), 373349cc55cSDimitry Andric (ins VSrc_f32_Deferred:$src0, VGPR_32:$src1, ImmOpType:$imm), 374349cc55cSDimitry Andric (ins VSrc_f16_Deferred:$src0, VGPR_32:$src1, ImmOpType:$imm)); 37581ad6265SDimitry Andric field dag InsVOPDX = (ins VSrc_f32_Deferred:$src0X, VGPR_32:$vsrc1X, ImmOpType:$imm); 37681ad6265SDimitry Andric // Note that both src0X and imm are deferred 37781ad6265SDimitry Andric let InsVOPDXDeferred = (ins VSrc_f32_Deferred:$src0X, VGPR_32:$vsrc1X, ImmOpType:$immDeferred); 37881ad6265SDimitry Andric field dag InsVOPDY = (ins VSrc_f32_Deferred:$src0Y, VGPR_32:$vsrc1Y, ImmOpType:$imm); 37981ad6265SDimitry Andric 380349cc55cSDimitry Andric field string Asm32 = "$vdst, $src0, $src1, $imm"; 38181ad6265SDimitry Andric field string AsmVOPDX = "$vdstX, $src0X, $vsrc1X, $imm"; 38281ad6265SDimitry Andric let AsmVOPDXDeferred = "$vdstX, $src0X, $vsrc1X, $immDeferred"; 38381ad6265SDimitry Andric field string AsmVOPDY = "$vdstY, $src0Y, $vsrc1Y, $imm"; 3840b57cec5SDimitry Andric field bit HasExt = 0; 385fe6060f1SDimitry Andric let IsSingle = 1; 3860b57cec5SDimitry Andric} 3870b57cec5SDimitry Andric 3880b57cec5SDimitry Andricdef VOP_MADAK_F16 : VOP_MADAK <f16>; 389bdd1243dSDimitry Andricdef VOP_MADAK_F16_t16 : VOP_MADAK <f16> { 390bdd1243dSDimitry Andric let IsTrue16 = 1; 391bdd1243dSDimitry Andric let DstRC = VOPDstOperand<VGPR_32_Lo128>; 3925f757f3fSDimitry Andric let Ins32 = (ins VSrcFake16_f16_Lo128_Deferred:$src0, VGPR_32_Lo128:$src1, ImmOpType:$imm); 393bdd1243dSDimitry Andric} 3940b57cec5SDimitry Andricdef VOP_MADAK_F32 : VOP_MADAK <f32>; 3950b57cec5SDimitry Andric 39681ad6265SDimitry Andricclass VOP_MADMK <ValueType vt> : VOP_MADK_Base<vt> { 39706c3fb27SDimitry Andric field Operand ImmOpType = !if(!eq(vt.Size, 32), KImmFP32, KImmFP16); 398bdd1243dSDimitry Andric field dag Ins32 = !if(!eq(vt.Size, 32), 399bdd1243dSDimitry Andric (ins VSrc_f32_Deferred:$src0, ImmOpType:$imm, VGPR_32:$src1), 400bdd1243dSDimitry Andric (ins VSrc_f16_Deferred:$src0, ImmOpType:$imm, VGPR_32:$src1)); 40181ad6265SDimitry Andric field dag InsVOPDX = (ins VSrc_f32_Deferred:$src0X, ImmOpType:$imm, VGPR_32:$vsrc1X); 40281ad6265SDimitry Andric let InsVOPDXDeferred = (ins VSrc_f32_Deferred:$src0X, ImmOpType:$immDeferred, VGPR_32:$vsrc1X); 40381ad6265SDimitry Andric field dag InsVOPDY = (ins VSrc_f32_Deferred:$src0Y, ImmOpType:$imm, VGPR_32:$vsrc1Y); 40481ad6265SDimitry Andric 405349cc55cSDimitry Andric field string Asm32 = "$vdst, $src0, $imm, $src1"; 40681ad6265SDimitry Andric field string AsmVOPDX = "$vdstX, $src0X, $imm, $vsrc1X"; 40781ad6265SDimitry Andric let AsmVOPDXDeferred = "$vdstX, $src0X, $immDeferred, $vsrc1X"; 40881ad6265SDimitry Andric field string AsmVOPDY = "$vdstY, $src0Y, $imm, $vsrc1Y"; 4090b57cec5SDimitry Andric field bit HasExt = 0; 410fe6060f1SDimitry Andric let IsSingle = 1; 4110b57cec5SDimitry Andric} 4120b57cec5SDimitry Andric 4130b57cec5SDimitry Andricdef VOP_MADMK_F16 : VOP_MADMK <f16>; 414bdd1243dSDimitry Andricdef VOP_MADMK_F16_t16 : VOP_MADMK <f16> { 415bdd1243dSDimitry Andric let IsTrue16 = 1; 416bdd1243dSDimitry Andric let DstRC = VOPDstOperand<VGPR_32_Lo128>; 4175f757f3fSDimitry Andric let Ins32 = (ins VSrcFake16_f16_Lo128_Deferred:$src0, ImmOpType:$imm, VGPR_32_Lo128:$src1); 418bdd1243dSDimitry Andric} 4190b57cec5SDimitry Andricdef VOP_MADMK_F32 : VOP_MADMK <f32>; 4200b57cec5SDimitry Andric 4210b57cec5SDimitry Andric// FIXME: Remove src2_modifiers. It isn't used, so is wasting memory 4220b57cec5SDimitry Andric// and processing time but it makes it easier to convert to mad. 4230b57cec5SDimitry Andricclass VOP_MAC <ValueType vt0, ValueType vt1=vt0> : VOPProfile <[vt0, vt1, vt1, vt0]> { 424fe6060f1SDimitry Andric let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, getVregSrcForVT<Src2VT>.ret:$src2); 4257a6dacacSDimitry Andric let Ins64 = getIns64<Src0RC64, Src1RC64, getVregSrcForVT<Src2VT>.ret, 3, 4260b57cec5SDimitry Andric 0, HasModifiers, HasModifiers, HasOMod, 4270b57cec5SDimitry Andric Src0Mod, Src1Mod, Src2Mod>.ret; 4280b57cec5SDimitry Andric let InsDPP = (ins Src0ModDPP:$src0_modifiers, Src0DPP:$src0, 4290b57cec5SDimitry Andric Src1ModDPP:$src1_modifiers, Src1DPP:$src1, 430fe6060f1SDimitry Andric getVregSrcForVT<Src2VT>.ret:$src2, // stub argument 4310b57cec5SDimitry Andric dpp_ctrl:$dpp_ctrl, row_mask:$row_mask, 4320b57cec5SDimitry Andric bank_mask:$bank_mask, bound_ctrl:$bound_ctrl); 4330b57cec5SDimitry Andric let InsDPP16 = !con(InsDPP, (ins FI:$fi)); 434bdd1243dSDimitry Andric let InsVOP3Base = getInsVOP3Base<Src0VOP3DPP, Src1VOP3DPP, RegisterOperand<VGPR_32>, 3, 43581ad6265SDimitry Andric 0, HasModifiers, HasModifiers, HasOMod, 436297eecfbSDimitry Andric Src0ModVOP3DPP, Src1ModVOP3DPP, Src2Mod, HasOpSel>.ret; 437bdd1243dSDimitry Andric // We need a dummy src2 tied to dst to track the use of that register for s_delay_alu 438bdd1243dSDimitry Andric let InsVOPDX = (ins Src0RC32:$src0X, Src1RC32:$vsrc1X, VGPRSrc_32:$src2X); 439bdd1243dSDimitry Andric let InsVOPDXDeferred = 440bdd1243dSDimitry Andric (ins !if(!eq(Src0VT.Size, 32), VSrc_f32_Deferred, VSrc_f16_Deferred):$src0X, 441bdd1243dSDimitry Andric VGPR_32:$vsrc1X, VGPRSrc_32:$src2X); 442bdd1243dSDimitry Andric let InsVOPDY = (ins Src0RC32:$src0Y, Src1RC32:$vsrc1Y, VGPRSrc_32:$src2Y); 443bdd1243dSDimitry Andric let InsVOPDYDeferred = 444bdd1243dSDimitry Andric (ins !if(!eq(Src1VT.Size, 32), VSrc_f32_Deferred, VSrc_f16_Deferred):$src0Y, 445bdd1243dSDimitry Andric VGPR_32:$vsrc1Y, VGPRSrc_32:$src2Y); 44681ad6265SDimitry Andric 4470b57cec5SDimitry Andric let InsDPP8 = (ins Src0ModDPP:$src0_modifiers, Src0DPP:$src0, 4480b57cec5SDimitry Andric Src1ModDPP:$src1_modifiers, Src1DPP:$src1, 449fe6060f1SDimitry Andric getVregSrcForVT<Src2VT>.ret:$src2, // stub argument 4500b57cec5SDimitry Andric dpp8:$dpp8, FI:$fi); 4510b57cec5SDimitry Andric let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0, 4520b57cec5SDimitry Andric Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1, 453fe6060f1SDimitry Andric getVregSrcForVT<Src2VT>.ret:$src2, // stub argument 4540b57cec5SDimitry Andric clampmod:$clamp, omod:$omod, 4550b57cec5SDimitry Andric dst_sel:$dst_sel, dst_unused:$dst_unused, 4560b57cec5SDimitry Andric src0_sel:$src0_sel, src1_sel:$src1_sel); 4570b57cec5SDimitry Andric let Asm32 = getAsm32<1, 2, vt0>.ret; 4580b57cec5SDimitry Andric let AsmDPP = getAsmDPP<1, 2, HasModifiers, vt0>.ret; 4590b57cec5SDimitry Andric let AsmDPP16 = getAsmDPP16<1, 2, HasModifiers, vt0>.ret; 4600b57cec5SDimitry Andric let AsmDPP8 = getAsmDPP8<1, 2, 0, vt0>.ret; 4610b57cec5SDimitry Andric let AsmSDWA = getAsmSDWA<1, 2, vt0>.ret; 4620b57cec5SDimitry Andric let AsmSDWA9 = getAsmSDWA9<1, 1, 2, vt0>.ret; 463bdd1243dSDimitry Andric let AsmVOP3Base = 464bdd1243dSDimitry Andric getAsmVOP3Base<2 /*NumSrcArgs*/, HasDst, HasClamp, 465bdd1243dSDimitry Andric HasOpSel, HasOMod, IsVOP3P, HasModifiers, 466bdd1243dSDimitry Andric HasModifiers, HasModifiers, 467bdd1243dSDimitry Andric 0 /*Src2HasMods*/, DstVT>.ret; 4680b57cec5SDimitry Andric let HasSrc2 = 0; 4690b57cec5SDimitry Andric let HasSrc2Mods = 0; 4700b57cec5SDimitry Andric 4710b57cec5SDimitry Andric let HasExt = 1; 4720b57cec5SDimitry Andric let HasExtDPP = 1; 47381ad6265SDimitry Andric let HasExt32BitDPP = 1; 4740b57cec5SDimitry Andric let HasExtSDWA = 1; 4750b57cec5SDimitry Andric let HasExtSDWA9 = 0; 4760b57cec5SDimitry Andric let TieRegDPP = "$src2"; 4770b57cec5SDimitry Andric} 4780b57cec5SDimitry Andric 4790b57cec5SDimitry Andricdef VOP_MAC_F16 : VOP_MAC <f16>; 480bdd1243dSDimitry Andricdef VOP_MAC_F16_t16 : VOP_MAC <f16> { 481bdd1243dSDimitry Andric let IsTrue16 = 1; 482bdd1243dSDimitry Andric let HasOpSel = 1; 483bdd1243dSDimitry Andric let AsmVOP3OpSel = getAsmVOP3OpSel<2/*NumSrcArgs*/, HasClamp, HasOMod, 484bdd1243dSDimitry Andric HasSrc0FloatMods, HasSrc1FloatMods, HasSrc2FloatMods>.ret; 485bdd1243dSDimitry Andric let DstRC = VOPDstOperand<VGPR_32_Lo128>; 486bdd1243dSDimitry Andric let DstRC64 = VOPDstOperand<VGPR_32>; 487bdd1243dSDimitry Andric let Src1RC32 = VGPRSrc_32_Lo128; 4887a6dacacSDimitry Andric let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, getVregSrcForVT<Src2VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret:$src2); 4897a6dacacSDimitry Andric let Src0DPP = getVregSrcForVT<Src0VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret; 4907a6dacacSDimitry Andric let Src1DPP = getVregSrcForVT<Src1VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret; 4917a6dacacSDimitry Andric let Src2DPP = getVregSrcForVT<Src2VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret; 492bdd1243dSDimitry Andric let Src0ModDPP = getSrcModDPP_t16<Src0VT>.ret; 493bdd1243dSDimitry Andric let Src1ModDPP = getSrcModDPP_t16<Src1VT>.ret; 494bdd1243dSDimitry Andric let Src2ModDPP = getSrcModDPP_t16<Src2VT>.ret; 495bdd1243dSDimitry Andric let InsDPP = (ins Src0ModDPP:$src0_modifiers, Src0DPP:$src0, 496bdd1243dSDimitry Andric Src1ModDPP:$src1_modifiers, Src1DPP:$src1, 4977a6dacacSDimitry Andric getVregSrcForVT<Src2VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret:$src2, // stub argument 498bdd1243dSDimitry Andric dpp_ctrl:$dpp_ctrl, row_mask:$row_mask, 499bdd1243dSDimitry Andric bank_mask:$bank_mask, bound_ctrl:$bound_ctrl); 500bdd1243dSDimitry Andric let InsDPP8 = (ins Src0ModDPP:$src0_modifiers, Src0DPP:$src0, 501bdd1243dSDimitry Andric Src1ModDPP:$src1_modifiers, Src1DPP:$src1, 5027a6dacacSDimitry Andric getVregSrcForVT<Src2VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret:$src2, // stub argument 503bdd1243dSDimitry Andric dpp8:$dpp8, FI:$fi); 504bdd1243dSDimitry Andric let Src2Mod = FP32InputMods; // dummy unused modifiers 505bdd1243dSDimitry Andric let Src2RC64 = VGPRSrc_32; // stub argument 506bdd1243dSDimitry Andric} 5070b57cec5SDimitry Andricdef VOP_MAC_F32 : VOP_MAC <f32>; 50881ad6265SDimitry Andriclet HasExtDPP = 0, HasExt32BitDPP = 0 in 509e8d8bef9SDimitry Andricdef VOP_MAC_LEGACY_F32 : VOP_MAC <f32>; 51081ad6265SDimitry Andriclet HasExtSDWA = 0, HasExt32BitDPP = 0, HasExt64BitDPP = 1 in 511fe6060f1SDimitry Andricdef VOP_MAC_F64 : VOP_MAC <f64>; 5120b57cec5SDimitry Andric 5130b57cec5SDimitry Andricclass VOP_DOT_ACC<ValueType vt0, ValueType vt1> : VOP_MAC<vt0, vt1> { 5140b57cec5SDimitry Andric let HasClamp = 0; 5150b57cec5SDimitry Andric let HasExtSDWA = 0; 5160b57cec5SDimitry Andric let HasOpSel = 0; 5170b57cec5SDimitry Andric let IsPacked = 0; 5180b57cec5SDimitry Andric} 5190b57cec5SDimitry Andric 5200b57cec5SDimitry Andricdef VOP_DOT_ACC_F32_V2F16 : VOP_DOT_ACC<f32, v2f16> { 5210b57cec5SDimitry Andric let Src0ModDPP = FPVRegInputMods; 5220b57cec5SDimitry Andric let Src1ModDPP = FPVRegInputMods; 523bdd1243dSDimitry Andric let HasClamp = 1; 5240b57cec5SDimitry Andric} 525e8d8bef9SDimitry Andric 526e8d8bef9SDimitry Andricdef VOP_DOT_ACC_I32_I32 : VOP_DOT_ACC<i32, i32> { 52781ad6265SDimitry Andric let HasExtVOP3DPP = 0; 528e8d8bef9SDimitry Andric let HasSrc0Mods = 1; 529e8d8bef9SDimitry Andric let HasSrc1Mods = 1; 530bdd1243dSDimitry Andric let HasClamp = 1; 531bdd1243dSDimitry Andric 532bdd1243dSDimitry Andric let Src0Mod = Int32InputMods; 533bdd1243dSDimitry Andric let Src1Mod = Int32InputMods; 5347a6dacacSDimitry Andric let Ins64 = getIns64<Src0RC64, Src1RC64, getVregSrcForVT<Src2VT>.ret, 535bdd1243dSDimitry Andric 3 /*NumSrcArgs*/, HasClamp, 1 /*HasModifiers*/, 536bdd1243dSDimitry Andric 1 /*HasSrc2Mods*/, HasOMod, 537bdd1243dSDimitry Andric Src0Mod, Src1Mod, Src2Mod>.ret; 538bdd1243dSDimitry Andric let Asm64 = "$vdst, $src0, $src1$clamp"; 539e8d8bef9SDimitry Andric} 5400b57cec5SDimitry Andric 5410b57cec5SDimitry Andric// Write out to vcc or arbitrary SGPR. 542bdd1243dSDimitry Andricdef VOP2b_I32_I1_I32_I32 : VOPProfile<[i32, i32, i32, untyped], /*EnableClamp=*/1> { 5430b57cec5SDimitry Andric let Asm32 = "$vdst, vcc, $src0, $src1"; 544bdd1243dSDimitry Andric let AsmVOP3Base = "$vdst, $sdst, $src0, $src1$clamp"; 5450b57cec5SDimitry Andric let AsmSDWA = "$vdst, vcc, $src0_modifiers, $src1_modifiers$clamp $dst_sel $dst_unused $src0_sel $src1_sel"; 5460b57cec5SDimitry Andric let AsmSDWA9 = "$vdst, vcc, $src0_modifiers, $src1_modifiers$clamp $dst_sel $dst_unused $src0_sel $src1_sel"; 5470b57cec5SDimitry Andric let AsmDPP = "$vdst, vcc, $src0, $src1 $dpp_ctrl$row_mask$bank_mask$bound_ctrl"; 5480b57cec5SDimitry Andric let AsmDPP8 = "$vdst, vcc, $src0, $src1 $dpp8$fi"; 5490b57cec5SDimitry Andric let AsmDPP16 = AsmDPP#"$fi"; 55081ad6265SDimitry Andric let InsDPP = (ins DstRCDPP:$old, 55181ad6265SDimitry Andric Src0DPP:$src0, 55281ad6265SDimitry Andric Src1DPP:$src1, 55381ad6265SDimitry Andric dpp_ctrl:$dpp_ctrl, row_mask:$row_mask, 55481ad6265SDimitry Andric bank_mask:$bank_mask, bound_ctrl:$bound_ctrl); 55581ad6265SDimitry Andric let InsDPP16 = !con(InsDPP, (ins FI:$fi)); 55681ad6265SDimitry Andric let InsDPP8 = (ins DstRCDPP:$old, 55781ad6265SDimitry Andric Src0DPP:$src0, 55881ad6265SDimitry Andric Src1DPP:$src1, 55981ad6265SDimitry Andric dpp8:$dpp8, FI:$fi); 5600b57cec5SDimitry Andric let Outs32 = (outs DstRC:$vdst); 5610b57cec5SDimitry Andric let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst); 56281ad6265SDimitry Andric let OutsVOP3DPP = Outs64; 56381ad6265SDimitry Andric let OutsVOP3DPP8 = Outs64; 5640b57cec5SDimitry Andric} 5650b57cec5SDimitry Andric 5660b57cec5SDimitry Andric// Write out to vcc or arbitrary SGPR and read in from vcc or 5670b57cec5SDimitry Andric// arbitrary SGPR. 568bdd1243dSDimitry Andricdef VOP2b_I32_I1_I32_I32_I1 : VOPProfile<[i32, i32, i32, i1], /*EnableClamp=*/1> { 56981ad6265SDimitry Andric let HasSrc2Mods = 0; 5700b57cec5SDimitry Andric let Asm32 = "$vdst, vcc, $src0, $src1, vcc"; 5710b57cec5SDimitry Andric let AsmSDWA = "$vdst, vcc, $src0_modifiers, $src1_modifiers, vcc$clamp $dst_sel $dst_unused $src0_sel $src1_sel"; 5720b57cec5SDimitry Andric let AsmSDWA9 = "$vdst, vcc, $src0_modifiers, $src1_modifiers, vcc$clamp $dst_sel $dst_unused $src0_sel $src1_sel"; 5730b57cec5SDimitry Andric let AsmDPP = "$vdst, vcc, $src0, $src1, vcc $dpp_ctrl$row_mask$bank_mask$bound_ctrl"; 5740b57cec5SDimitry Andric let AsmDPP8 = "$vdst, vcc, $src0, $src1, vcc $dpp8$fi"; 5750b57cec5SDimitry Andric let AsmDPP16 = AsmDPP#"$fi"; 5760b57cec5SDimitry Andric let Outs32 = (outs DstRC:$vdst); 5770b57cec5SDimitry Andric let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst); 578bdd1243dSDimitry Andric let AsmVOP3Base = "$vdst, $sdst, $src0, $src1, $src2$clamp"; 57981ad6265SDimitry Andric let OutsVOP3DPP = Outs64; 58081ad6265SDimitry Andric let OutsVOP3DPP8 = Outs64; 5810b57cec5SDimitry Andric 5820b57cec5SDimitry Andric // Suppress src2 implied by type since the 32-bit encoding uses an 5830b57cec5SDimitry Andric // implicit VCC use. 5840b57cec5SDimitry Andric let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1); 5850b57cec5SDimitry Andric 5860b57cec5SDimitry Andric let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0, 5870b57cec5SDimitry Andric Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1, 5880b57cec5SDimitry Andric clampmod:$clamp, 5890b57cec5SDimitry Andric dst_sel:$dst_sel, dst_unused:$dst_unused, 5900b57cec5SDimitry Andric src0_sel:$src0_sel, src1_sel:$src1_sel); 5910b57cec5SDimitry Andric 5920b57cec5SDimitry Andric let InsDPP = (ins DstRCDPP:$old, 5930b57cec5SDimitry Andric Src0DPP:$src0, 5940b57cec5SDimitry Andric Src1DPP:$src1, 5950b57cec5SDimitry Andric dpp_ctrl:$dpp_ctrl, row_mask:$row_mask, 5960b57cec5SDimitry Andric bank_mask:$bank_mask, bound_ctrl:$bound_ctrl); 5970b57cec5SDimitry Andric let InsDPP16 = !con(InsDPP, (ins FI:$fi)); 59881ad6265SDimitry Andric let InsDPP8 = (ins DstRCDPP:$old, 59981ad6265SDimitry Andric Src0DPP:$src0, 60081ad6265SDimitry Andric Src1DPP:$src1, 60181ad6265SDimitry Andric dpp8:$dpp8, FI:$fi); 6020b57cec5SDimitry Andric 6030b57cec5SDimitry Andric let HasExt = 1; 6040b57cec5SDimitry Andric let HasExtDPP = 1; 60581ad6265SDimitry Andric let HasExt32BitDPP = 1; 6060b57cec5SDimitry Andric let HasExtSDWA = 1; 6070b57cec5SDimitry Andric let HasExtSDWA9 = 1; 6080b57cec5SDimitry Andric} 6090b57cec5SDimitry Andric 6100b57cec5SDimitry Andric// Read in from vcc or arbitrary SGPR. 611bdd1243dSDimitry Andricclass VOP2e_SGPR<list<ValueType> ArgVT> : VOPProfile<ArgVT> { 6120b57cec5SDimitry Andric let Asm32 = "$vdst, $src0, $src1"; 6130b57cec5SDimitry Andric let AsmSDWA = "$vdst, $src0_modifiers, $src1_modifiers, vcc$clamp $dst_sel $dst_unused $src0_sel $src1_sel"; 6140b57cec5SDimitry Andric let AsmSDWA9 = "$vdst, $src0_modifiers, $src1_modifiers, vcc$clamp $dst_sel $dst_unused $src0_sel $src1_sel"; 615bdd1243dSDimitry Andric let AsmDPP = "$vdst, $src0_modifiers, $src1_modifiers, vcc $dpp_ctrl$row_mask$bank_mask$bound_ctrl"; 6160b57cec5SDimitry Andric let AsmDPP8 = "$vdst, $src0, $src1, vcc $dpp8$fi"; 6170b57cec5SDimitry Andric let AsmDPP16 = AsmDPP#"$fi"; 618bdd1243dSDimitry Andric let AsmVOP3Base = "$vdst, $src0_modifiers, $src1_modifiers, $src2"; 6190b57cec5SDimitry Andric 6200b57cec5SDimitry Andric let Outs32 = (outs DstRC:$vdst); 6210b57cec5SDimitry Andric let Outs64 = (outs DstRC:$vdst); 6220b57cec5SDimitry Andric 6230b57cec5SDimitry Andric // Suppress src2 implied by type since the 32-bit encoding uses an 6240b57cec5SDimitry Andric // implicit VCC use. 625bdd1243dSDimitry Andric let Ins32 = (ins VSrc_f32:$src0, Src1RC32:$src1); 6260b57cec5SDimitry Andric 627bdd1243dSDimitry Andric let HasModifiers = 1; 628bdd1243dSDimitry Andric 629bdd1243dSDimitry Andric // Select FP modifiers for VOP3 630bdd1243dSDimitry Andric let Src0Mod = !if(!eq(Src0VT.Size, 16), FP16InputMods, FP32InputMods); 631bdd1243dSDimitry Andric let Src1Mod = Src0Mod; 632bdd1243dSDimitry Andric 633bdd1243dSDimitry Andric let HasSrc0IntMods = 0; 634bdd1243dSDimitry Andric let HasSrc1IntMods = 0; 635bdd1243dSDimitry Andric let HasSrc0FloatMods = 1; 636bdd1243dSDimitry Andric let HasSrc1FloatMods = 1; 637bdd1243dSDimitry Andric let InsSDWA = (ins FP32SDWAInputMods:$src0_modifiers, SDWASrc_f32:$src0, 638bdd1243dSDimitry Andric FP32SDWAInputMods:$src1_modifiers, SDWASrc_f32:$src1, 6390b57cec5SDimitry Andric clampmod:$clamp, 6400b57cec5SDimitry Andric dst_sel:$dst_sel, dst_unused:$dst_unused, 6410b57cec5SDimitry Andric src0_sel:$src0_sel, src1_sel:$src1_sel); 6420b57cec5SDimitry Andric 6430b57cec5SDimitry Andric let InsDPP = (ins DstRCDPP:$old, 644bdd1243dSDimitry Andric FPVRegInputMods:$src0_modifiers, Src0DPP:$src0, 645bdd1243dSDimitry Andric FPVRegInputMods:$src1_modifiers, Src1DPP:$src1, 6460b57cec5SDimitry Andric dpp_ctrl:$dpp_ctrl, row_mask:$row_mask, 6470b57cec5SDimitry Andric bank_mask:$bank_mask, bound_ctrl:$bound_ctrl); 6480b57cec5SDimitry Andric let InsDPP16 = !con(InsDPP, (ins FI:$fi)); 64981ad6265SDimitry Andric let InsDPP8 = (ins DstRCDPP:$old, 650bdd1243dSDimitry Andric FPVRegInputMods:$src0_modifiers, Src0DPP:$src0, 651bdd1243dSDimitry Andric FPVRegInputMods:$src1_modifiers, Src1DPP:$src1, 65281ad6265SDimitry Andric dpp8:$dpp8, FI:$fi); 6530b57cec5SDimitry Andric 654bdd1243dSDimitry Andric let Src0ModVOP3DPP = FPVRegInputMods; 655bdd1243dSDimitry Andric let Src1ModVOP3DPP = FPVRegInputMods; 656bdd1243dSDimitry Andric 6570b57cec5SDimitry Andric let HasExt = 1; 6580b57cec5SDimitry Andric let HasExtDPP = 1; 65981ad6265SDimitry Andric let HasExt32BitDPP = 1; 6600b57cec5SDimitry Andric let HasExtSDWA = 1; 6610b57cec5SDimitry Andric let HasExtSDWA9 = 1; 6620b57cec5SDimitry Andric} 6630b57cec5SDimitry Andric 66481ad6265SDimitry Andricdef VOP2e_I32_I32_I32_I1 : VOP2e_SGPR<[i32, i32, i32, i1]>; 66581ad6265SDimitry Andricdef VOP2e_I16_I16_I16_I1 : VOP2e_SGPR<[i16, i16, i16, i1]>; 66681ad6265SDimitry Andric 66781ad6265SDimitry Andricdef VOP_READLANE : VOPProfile<[i32, i32, i32, untyped]> { 6680b57cec5SDimitry Andric let Outs32 = (outs SReg_32:$vdst); 6690b57cec5SDimitry Andric let Outs64 = Outs32; 67006c3fb27SDimitry Andric let Ins32 = (ins VRegOrLdsSrc_32:$src0, SCSrc_b32:$src1); 6710b57cec5SDimitry Andric let Ins64 = Ins32; 6720b57cec5SDimitry Andric let Asm32 = " $vdst, $src0, $src1"; 6730b57cec5SDimitry Andric let Asm64 = Asm32; 6740b57cec5SDimitry Andric 6750b57cec5SDimitry Andric let HasExt = 0; 6760b57cec5SDimitry Andric let HasExtDPP = 0; 67781ad6265SDimitry Andric let HasExt32BitDPP = 0; 678fe6060f1SDimitry Andric let HasExt64BitDPP = 0; 6790b57cec5SDimitry Andric let HasExtSDWA = 0; 6800b57cec5SDimitry Andric let HasExtSDWA9 = 0; 6810b57cec5SDimitry Andric} 6820b57cec5SDimitry Andric 6830b57cec5SDimitry Andricdef VOP_WRITELANE : VOPProfile<[i32, i32, i32, i32]> { 6840b57cec5SDimitry Andric let Outs32 = (outs VGPR_32:$vdst); 6850b57cec5SDimitry Andric let Outs64 = Outs32; 6860b57cec5SDimitry Andric let Ins32 = (ins SCSrc_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in); 6870b57cec5SDimitry Andric let Ins64 = Ins32; 6880b57cec5SDimitry Andric let Asm32 = " $vdst, $src0, $src1"; 6890b57cec5SDimitry Andric let Asm64 = Asm32; 6900b57cec5SDimitry Andric let HasSrc2 = 0; 6910b57cec5SDimitry Andric let HasSrc2Mods = 0; 6920b57cec5SDimitry Andric 6930b57cec5SDimitry Andric let HasExt = 0; 6940b57cec5SDimitry Andric let HasExtDPP = 0; 69581ad6265SDimitry Andric let HasExt32BitDPP = 0; 696fe6060f1SDimitry Andric let HasExt64BitDPP = 0; 6970b57cec5SDimitry Andric let HasExtSDWA = 0; 6980b57cec5SDimitry Andric let HasExtSDWA9 = 0; 6990b57cec5SDimitry Andric} 7000b57cec5SDimitry Andric 7010b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 7020b57cec5SDimitry Andric// VOP2 Instructions 7030b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 7040b57cec5SDimitry Andric 70581ad6265SDimitry Andriclet SubtargetPredicate = isGFX11Plus in 70681ad6265SDimitry Andricdefm V_CNDMASK_B16 : VOP2eInst <"v_cndmask_b16", VOP2e_I16_I16_I16_I1>; 70781ad6265SDimitry Andricdefm V_CNDMASK_B32 : VOP2eInst_VOPD <"v_cndmask_b32", VOP2e_I32_I32_I32_I1, 0x9, "v_cndmask_b32">; 708fe6060f1SDimitry Andriclet SubtargetPredicate = HasMadMacF32Insts, isReMaterializable = 1 in 7090b57cec5SDimitry Andricdef V_MADMK_F32 : VOP2_Pseudo <"v_madmk_f32", VOP_MADMK_F32, []>; 7100b57cec5SDimitry Andric 7110b57cec5SDimitry Andriclet isCommutable = 1 in { 712fe6060f1SDimitry Andriclet isReMaterializable = 1 in { 71381ad6265SDimitry Andricdefm V_ADD_F32 : VOP2Inst_VOPD <"v_add_f32", VOP_F32_F32_F32, 0x4, "v_add_f32", any_fadd>; 71481ad6265SDimitry Andricdefm V_SUB_F32 : VOP2Inst_VOPD <"v_sub_f32", VOP_F32_F32_F32, 0x5, "v_sub_f32", any_fsub>; 71581ad6265SDimitry Andricdefm V_SUBREV_F32 : VOP2Inst_VOPD <"v_subrev_f32", VOP_F32_F32_F32, 0x6, "v_subrev_f32", null_frag, "v_sub_f32">; 71681ad6265SDimitry Andricdefm V_MUL_LEGACY_F32 : VOP2Inst_VOPD <"v_mul_legacy_f32", VOP_F32_F32_F32, 0x7, "v_mul_dx9_zero_f32", AMDGPUfmul_legacy>; 71781ad6265SDimitry Andricdefm V_MUL_F32 : VOP2Inst_VOPD <"v_mul_f32", VOP_F32_F32_F32, 0x3, "v_mul_f32", any_fmul>; 7185ffd83dbSDimitry Andricdefm V_MUL_I32_I24 : VOP2Inst <"v_mul_i32_i24", VOP_I32_I32_I32_ARITH, AMDGPUmul_i24>; 719349cc55cSDimitry Andricdefm V_MUL_HI_I32_I24 : VOP2Inst <"v_mul_hi_i32_i24", VOP_I32_I32_I32, AMDGPUmulhi_i24>; 7205ffd83dbSDimitry Andricdefm V_MUL_U32_U24 : VOP2Inst <"v_mul_u32_u24", VOP_I32_I32_I32_ARITH, AMDGPUmul_u24>; 721349cc55cSDimitry Andricdefm V_MUL_HI_U32_U24 : VOP2Inst <"v_mul_hi_u32_u24", VOP_I32_I32_I32, AMDGPUmulhi_u24>; 72281ad6265SDimitry Andricdefm V_MIN_F32 : VOP2Inst_VOPD <"v_min_f32", VOP_F32_F32_F32, 0xb, "v_min_f32", fminnum_like>; 72381ad6265SDimitry Andricdefm V_MAX_F32 : VOP2Inst_VOPD <"v_max_f32", VOP_F32_F32_F32, 0xa, "v_max_f32", fmaxnum_like>; 7240b57cec5SDimitry Andricdefm V_MIN_I32 : VOP2Inst <"v_min_i32", VOP_PAT_GEN<VOP_I32_I32_I32>, smin>; 7250b57cec5SDimitry Andricdefm V_MAX_I32 : VOP2Inst <"v_max_i32", VOP_PAT_GEN<VOP_I32_I32_I32>, smax>; 7260b57cec5SDimitry Andricdefm V_MIN_U32 : VOP2Inst <"v_min_u32", VOP_PAT_GEN<VOP_I32_I32_I32>, umin>; 7270b57cec5SDimitry Andricdefm V_MAX_U32 : VOP2Inst <"v_max_u32", VOP_PAT_GEN<VOP_I32_I32_I32>, umax>; 728349cc55cSDimitry Andricdefm V_LSHRREV_B32 : VOP2Inst <"v_lshrrev_b32", VOP_I32_I32_I32, clshr_rev_32, "v_lshr_b32">; 729349cc55cSDimitry Andricdefm V_ASHRREV_I32 : VOP2Inst <"v_ashrrev_i32", VOP_I32_I32_I32, cashr_rev_32, "v_ashr_i32">; 73081ad6265SDimitry Andricdefm V_LSHLREV_B32 : VOP2Inst_VOPD <"v_lshlrev_b32", VOP_I32_I32_I32, 0x11, "v_lshlrev_b32", clshl_rev_32, "v_lshl_b32">; 73181ad6265SDimitry Andricdefm V_AND_B32 : VOP2Inst_VOPD <"v_and_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, 0x12, "v_and_b32", and>; 7320b57cec5SDimitry Andricdefm V_OR_B32 : VOP2Inst <"v_or_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, or>; 7330b57cec5SDimitry Andricdefm V_XOR_B32 : VOP2Inst <"v_xor_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, xor>; 734fe6060f1SDimitry Andric} // End isReMaterializable = 1 7350b57cec5SDimitry Andric 7365ffd83dbSDimitry Andriclet mayRaiseFPException = 0 in { 737e8d8bef9SDimitry Andriclet OtherPredicates = [HasMadMacF32Insts] in { 7380b57cec5SDimitry Andriclet Constraints = "$vdst = $src2", DisableEncoding="$src2", 7390b57cec5SDimitry Andric isConvertibleToThreeAddress = 1 in { 7400b57cec5SDimitry Andricdefm V_MAC_F32 : VOP2Inst <"v_mac_f32", VOP_MAC_F32>; 741e8d8bef9SDimitry Andric 742e8d8bef9SDimitry Andriclet SubtargetPredicate = isGFX6GFX7GFX10 in 743e8d8bef9SDimitry Andricdefm V_MAC_LEGACY_F32 : VOP2Inst <"v_mac_legacy_f32", VOP_MAC_LEGACY_F32>; 744e8d8bef9SDimitry Andric} // End Constraints = "$vdst = $src2", DisableEncoding="$src2", 745e8d8bef9SDimitry Andric // isConvertibleToThreeAddress = 1 7460b57cec5SDimitry Andric 747fe6060f1SDimitry Andriclet isReMaterializable = 1 in 7480b57cec5SDimitry Andricdef V_MADAK_F32 : VOP2_Pseudo <"v_madak_f32", VOP_MADAK_F32, []>; 749e8d8bef9SDimitry Andric} // End OtherPredicates = [HasMadMacF32Insts] 750e8d8bef9SDimitry Andric} // End mayRaiseFPException = 0 7510b57cec5SDimitry Andric 7520b57cec5SDimitry Andric// No patterns so that the scalar instructions are always selected. 7530b57cec5SDimitry Andric// The scalar versions will be replaced with vector when needed later. 754e8d8bef9SDimitry Andricdefm V_ADD_CO_U32 : VOP2bInst <"v_add_co_u32", VOP2b_I32_I1_I32_I32, null_frag, "v_add_co_u32", 1>; 755e8d8bef9SDimitry Andricdefm V_SUB_CO_U32 : VOP2bInst <"v_sub_co_u32", VOP2b_I32_I1_I32_I32, null_frag, "v_sub_co_u32", 1>; 756e8d8bef9SDimitry Andricdefm V_SUBREV_CO_U32 : VOP2bInst <"v_subrev_co_u32", VOP2b_I32_I1_I32_I32, null_frag, "v_sub_co_u32", 1>; 7570b57cec5SDimitry Andricdefm V_ADDC_U32 : VOP2bInst <"v_addc_u32", VOP2b_I32_I1_I32_I32_I1, null_frag, "v_addc_u32", 1>; 7580b57cec5SDimitry Andricdefm V_SUBB_U32 : VOP2bInst <"v_subb_u32", VOP2b_I32_I1_I32_I32_I1, null_frag, "v_subb_u32", 1>; 7590b57cec5SDimitry Andricdefm V_SUBBREV_U32 : VOP2bInst <"v_subbrev_u32", VOP2b_I32_I1_I32_I32_I1, null_frag, "v_subb_u32", 1>; 7600b57cec5SDimitry Andric 7610b57cec5SDimitry Andric 762fe6060f1SDimitry Andriclet SubtargetPredicate = HasAddNoCarryInsts, isReMaterializable = 1 in { 76381ad6265SDimitry Andricdefm V_ADD_U32 : VOP2Inst_VOPD <"v_add_u32", VOP_I32_I32_I32_ARITH, 0x10, "v_add_nc_u32", null_frag, "v_add_u32", 1>; 7640b57cec5SDimitry Andricdefm V_SUB_U32 : VOP2Inst <"v_sub_u32", VOP_I32_I32_I32_ARITH, null_frag, "v_sub_u32", 1>; 7650b57cec5SDimitry Andricdefm V_SUBREV_U32 : VOP2Inst <"v_subrev_u32", VOP_I32_I32_I32_ARITH, null_frag, "v_sub_u32", 1>; 7660b57cec5SDimitry Andric} 7670b57cec5SDimitry Andric 7680b57cec5SDimitry Andric} // End isCommutable = 1 7690b57cec5SDimitry Andric 7700b57cec5SDimitry Andric// These are special and do not read the exec mask. 7710b57cec5SDimitry Andriclet isConvergent = 1, Uses = []<Register> in { 7720b57cec5SDimitry Andricdef V_READLANE_B32 : VOP2_Pseudo<"v_readlane_b32", VOP_READLANE, 7730b57cec5SDimitry Andric [(set i32:$vdst, (int_amdgcn_readlane i32:$src0, i32:$src1))]>; 77406c3fb27SDimitry Andriclet IsNeverUniform = 1, Constraints = "$vdst = $vdst_in", DisableEncoding="$vdst_in" in { 7750b57cec5SDimitry Andricdef V_WRITELANE_B32 : VOP2_Pseudo<"v_writelane_b32", VOP_WRITELANE, 7760b57cec5SDimitry Andric [(set i32:$vdst, (int_amdgcn_writelane i32:$src0, i32:$src1, i32:$vdst_in))]>; 77706c3fb27SDimitry Andric} // End IsNeverUniform, $vdst = $vdst_in, DisableEncoding $vdst_in 7780b57cec5SDimitry Andric} // End isConvergent = 1 7790b57cec5SDimitry Andric 780fe6060f1SDimitry Andriclet isReMaterializable = 1 in { 78181ad6265SDimitry Andricdefm V_BFM_B32 : VOP2Inst <"v_bfm_b32", VOP_I32_I32_I32>; 78281ad6265SDimitry Andricdefm V_BCNT_U32_B32 : VOP2Inst <"v_bcnt_u32_b32", VOP_I32_I32_I32, add_ctpop>; 78306c3fb27SDimitry Andriclet IsNeverUniform = 1 in { 78481ad6265SDimitry Andricdefm V_MBCNT_LO_U32_B32 : VOP2Inst <"v_mbcnt_lo_u32_b32", VOP_I32_I32_I32, int_amdgcn_mbcnt_lo>; 78581ad6265SDimitry Andricdefm V_MBCNT_HI_U32_B32 : VOP2Inst <"v_mbcnt_hi_u32_b32", VOP_I32_I32_I32, int_amdgcn_mbcnt_hi>; 78606c3fb27SDimitry Andric} // End IsNeverUniform = 1 78706c3fb27SDimitry Andricdefm V_LDEXP_F32 : VOP2Inst <"v_ldexp_f32", VOP_F32_F32_I32, any_fldexp>; 7885ffd83dbSDimitry Andric 7895ffd83dbSDimitry Andriclet ReadsModeReg = 0, mayRaiseFPException = 0 in { 79081ad6265SDimitry Andricdefm V_CVT_PKNORM_I16_F32 : VOP2Inst <"v_cvt_pknorm_i16_f32", VOP_V2I16_F32_F32, AMDGPUpknorm_i16_f32>; 79181ad6265SDimitry Andricdefm V_CVT_PKNORM_U16_F32 : VOP2Inst <"v_cvt_pknorm_u16_f32", VOP_V2I16_F32_F32, AMDGPUpknorm_u16_f32>; 7925ffd83dbSDimitry Andric} 7935ffd83dbSDimitry Andric 79481ad6265SDimitry Andricdefm V_CVT_PKRTZ_F16_F32 : VOP2Inst <"v_cvt_pkrtz_f16_f32", VOP_V2F16_F32_F32, AMDGPUpkrtz_f16_f32>; 79581ad6265SDimitry Andricdefm V_CVT_PK_U16_U32 : VOP2Inst <"v_cvt_pk_u16_u32", VOP_V2I16_I32_I32, AMDGPUpk_u16_u32>; 79681ad6265SDimitry Andricdefm V_CVT_PK_I16_I32 : VOP2Inst <"v_cvt_pk_i16_i32", VOP_V2I16_I32_I32, AMDGPUpk_i16_i32>; 7970b57cec5SDimitry Andric 7980b57cec5SDimitry Andric 7990b57cec5SDimitry Andriclet SubtargetPredicate = isGFX6GFX7 in { 8000b57cec5SDimitry Andricdefm V_MIN_LEGACY_F32 : VOP2Inst <"v_min_legacy_f32", VOP_F32_F32_F32, AMDGPUfmin_legacy>; 8010b57cec5SDimitry Andricdefm V_MAX_LEGACY_F32 : VOP2Inst <"v_max_legacy_f32", VOP_F32_F32_F32, AMDGPUfmax_legacy>; 8020b57cec5SDimitry Andric} // End SubtargetPredicate = isGFX6GFX7 8030b57cec5SDimitry Andric 8040b57cec5SDimitry Andriclet isCommutable = 1 in { 8055ffd83dbSDimitry Andriclet SubtargetPredicate = isGFX6GFX7 in { 806349cc55cSDimitry Andricdefm V_LSHR_B32 : VOP2Inst <"v_lshr_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, csrl_32>; 807349cc55cSDimitry Andricdefm V_ASHR_I32 : VOP2Inst <"v_ashr_i32", VOP_PAT_GEN<VOP_I32_I32_I32>, csra_32>; 808349cc55cSDimitry Andricdefm V_LSHL_B32 : VOP2Inst <"v_lshl_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, cshl_32>; 8095ffd83dbSDimitry Andric} // End SubtargetPredicate = isGFX6GFX7 8105ffd83dbSDimitry Andric} // End isCommutable = 1 811fe6060f1SDimitry Andric} // End isReMaterializable = 1 8125ffd83dbSDimitry Andric 813fe6060f1SDimitry Andricdefm V_CVT_PKACCUM_U8_F32 : VOP2Inst <"v_cvt_pkaccum_u8_f32", VOP_NO_EXT<VOP_I32_F32_I32>>; // TODO: set "Uses = dst" 8140b57cec5SDimitry Andric 8150b57cec5SDimitry Andricclass DivergentBinOp<SDPatternOperator Op, VOP_Pseudo Inst> : 8160b57cec5SDimitry Andric GCNPat< 817bdd1243dSDimitry Andric (DivergentBinFrag<Op> Inst.Pfl.Src0VT:$src0, Inst.Pfl.Src1VT:$src1), 8180b57cec5SDimitry Andric !if(!cast<Commutable_REV>(Inst).IsOrig, 8190b57cec5SDimitry Andric (Inst $src0, $src1), 8200b57cec5SDimitry Andric (Inst $src1, $src0) 8210b57cec5SDimitry Andric ) 8220b57cec5SDimitry Andric >; 8230b57cec5SDimitry Andric 8240b57cec5SDimitry Andricclass DivergentClampingBinOp<SDPatternOperator Op, VOP_Pseudo Inst> : 8250b57cec5SDimitry Andric GCNPat< 826bdd1243dSDimitry Andric (DivergentBinFrag<Op> Inst.Pfl.Src0VT:$src0, Inst.Pfl.Src1VT:$src1), 8270b57cec5SDimitry Andric !if(!cast<Commutable_REV>(Inst).IsOrig, 8280b57cec5SDimitry Andric (Inst $src0, $src1, 0), 8290b57cec5SDimitry Andric (Inst $src1, $src0, 0) 8300b57cec5SDimitry Andric ) 8310b57cec5SDimitry Andric >; 8320b57cec5SDimitry Andric 833349cc55cSDimitry Andricdef : DivergentBinOp<csrl_32, V_LSHRREV_B32_e64>; 834349cc55cSDimitry Andricdef : DivergentBinOp<csra_32, V_ASHRREV_I32_e64>; 835349cc55cSDimitry Andricdef : DivergentBinOp<cshl_32, V_LSHLREV_B32_e64>; 8360b57cec5SDimitry Andric 8370b57cec5SDimitry Andriclet SubtargetPredicate = HasAddNoCarryInsts in { 8380b57cec5SDimitry Andric def : DivergentClampingBinOp<add, V_ADD_U32_e64>; 8390b57cec5SDimitry Andric def : DivergentClampingBinOp<sub, V_SUB_U32_e64>; 8400b57cec5SDimitry Andric} 8410b57cec5SDimitry Andric 8420b57cec5SDimitry Andriclet SubtargetPredicate = isGFX6GFX7GFX8GFX9, Predicates = [isGFX6GFX7GFX8GFX9] in { 843e8d8bef9SDimitry Andricdef : DivergentClampingBinOp<add, V_ADD_CO_U32_e64>; 844e8d8bef9SDimitry Andricdef : DivergentClampingBinOp<sub, V_SUB_CO_U32_e64>; 8450b57cec5SDimitry Andric} 8460b57cec5SDimitry Andric 8470b57cec5SDimitry Andricdef : DivergentBinOp<adde, V_ADDC_U32_e32>; 8480b57cec5SDimitry Andricdef : DivergentBinOp<sube, V_SUBB_U32_e32>; 8490b57cec5SDimitry Andric 8500b57cec5SDimitry Andricclass divergent_i64_BinOp <SDPatternOperator Op, Instruction Inst> : 8510b57cec5SDimitry Andric GCNPat< 852bdd1243dSDimitry Andric (DivergentBinFrag<Op> i64:$src0, i64:$src1), 8530b57cec5SDimitry Andric (REG_SEQUENCE VReg_64, 8540b57cec5SDimitry Andric (Inst 8550b57cec5SDimitry Andric (i32 (EXTRACT_SUBREG $src0, sub0)), 8560b57cec5SDimitry Andric (i32 (EXTRACT_SUBREG $src1, sub0)) 8570b57cec5SDimitry Andric ), sub0, 8580b57cec5SDimitry Andric (Inst 8590b57cec5SDimitry Andric (i32 (EXTRACT_SUBREG $src0, sub1)), 8600b57cec5SDimitry Andric (i32 (EXTRACT_SUBREG $src1, sub1)) 8610b57cec5SDimitry Andric ), sub1 8620b57cec5SDimitry Andric ) 8630b57cec5SDimitry Andric >; 8640b57cec5SDimitry Andric 86504eeddc0SDimitry Andricdef : divergent_i64_BinOp <and, V_AND_B32_e64>; 86604eeddc0SDimitry Andricdef : divergent_i64_BinOp <or, V_OR_B32_e64>; 86704eeddc0SDimitry Andricdef : divergent_i64_BinOp <xor, V_XOR_B32_e64>; 8680b57cec5SDimitry Andric 8695f757f3fSDimitry Andric// mul24 w/ 64 bit output. 8705f757f3fSDimitry Andricclass mul24_64_Pat<SDPatternOperator Op, Instruction InstLo, Instruction InstHi> : GCNPat< 8715f757f3fSDimitry Andric (i64 (Op i32:$src0, i32:$src1)), 8725f757f3fSDimitry Andric (REG_SEQUENCE VReg_64, 8735f757f3fSDimitry Andric (InstLo $src0, $src1), sub0, 8745f757f3fSDimitry Andric (InstHi $src0, $src1), sub1) 8755f757f3fSDimitry Andric>; 8765f757f3fSDimitry Andric 8775f757f3fSDimitry Andricdef : mul24_64_Pat<AMDGPUmul_i24, V_MUL_I32_I24_e64, V_MUL_HI_I32_I24_e64>; 8785f757f3fSDimitry Andricdef : mul24_64_Pat<AMDGPUmul_u24, V_MUL_U32_U24_e64, V_MUL_HI_U32_U24_e64>; 8795f757f3fSDimitry Andric 880bdd1243dSDimitry Andric//===----------------------------------------------------------------------===// 881bdd1243dSDimitry Andric// 16-Bit Operand Instructions 882bdd1243dSDimitry Andric//===----------------------------------------------------------------------===// 883bdd1243dSDimitry Andric 88406c3fb27SDimitry Andric// The ldexp.f16 intrinsic expects a integer src1 operand, though the hardware 885bdd1243dSDimitry Andric// encoding treats src1 as an f16 88606c3fb27SDimitry Andricdef LDEXP_F16_VOPProfile : VOPProfile <[f16, f16, f16, untyped]> { 88706c3fb27SDimitry Andric let Src1Mod = Int32InputMods; 88806c3fb27SDimitry Andric let Src1ModDPP = IntVRegInputMods; 88906c3fb27SDimitry Andric let Src1ModVOP3DPP = IntVRegInputMods; 89006c3fb27SDimitry Andric // SDWA sext is the only modifier allowed. 89106c3fb27SDimitry Andric let HasSrc1IntMods = 1; 89206c3fb27SDimitry Andric let HasSrc1FloatMods = 0; 89306c3fb27SDimitry Andric let Src1ModSDWA = Int16SDWAInputMods; 89406c3fb27SDimitry Andric} 8955f757f3fSDimitry Andricdef LDEXP_F16_VOPProfile_True16 : VOPProfile_Fake16<VOP_F16_F16_F16> { 896bdd1243dSDimitry Andric let Src1RC32 = RegisterOperand<VGPR_32_Lo128>; 8977a6dacacSDimitry Andric let Src1DPP = RegisterOperand<VGPR_32_Lo128>; 8987a6dacacSDimitry Andric let Src1ModDPP = IntT16VRegInputMods</* IsFake16= */ 1>; 899bdd1243dSDimitry Andric} 900bdd1243dSDimitry Andric 901bdd1243dSDimitry Andriclet isReMaterializable = 1 in { 902bdd1243dSDimitry Andriclet FPDPRounding = 1 in { 903bdd1243dSDimitry Andric let SubtargetPredicate = NotHasTrue16BitInsts, OtherPredicates = [Has16BitInsts] in 90406c3fb27SDimitry Andric defm V_LDEXP_F16 : VOP2Inst <"v_ldexp_f16", LDEXP_F16_VOPProfile>; 905bdd1243dSDimitry Andric let SubtargetPredicate = HasTrue16BitInsts in 90606c3fb27SDimitry Andric defm V_LDEXP_F16_t16 : VOP2Inst <"v_ldexp_f16_t16", LDEXP_F16_VOPProfile_True16>; 907bdd1243dSDimitry Andric} // End FPDPRounding = 1 908bdd1243dSDimitry Andric// FIXME VOP3 Only instructions. NFC using VOPProfile_True16 for these until a planned change to use a new register class for VOP3 encoded True16 instuctions 909bdd1243dSDimitry Andricdefm V_LSHLREV_B16 : VOP2Inst_e64_t16 <"v_lshlrev_b16", VOP_I16_I16_I16, clshl_rev_16>; 910bdd1243dSDimitry Andricdefm V_LSHRREV_B16 : VOP2Inst_e64_t16 <"v_lshrrev_b16", VOP_I16_I16_I16, clshr_rev_16>; 911bdd1243dSDimitry Andricdefm V_ASHRREV_I16 : VOP2Inst_e64_t16 <"v_ashrrev_i16", VOP_I16_I16_I16, cashr_rev_16>; 912bdd1243dSDimitry Andriclet isCommutable = 1 in { 913bdd1243dSDimitry Andriclet FPDPRounding = 1 in { 914bdd1243dSDimitry Andricdefm V_ADD_F16 : VOP2Inst_t16 <"v_add_f16", VOP_F16_F16_F16, any_fadd>; 915bdd1243dSDimitry Andricdefm V_SUB_F16 : VOP2Inst_t16 <"v_sub_f16", VOP_F16_F16_F16, any_fsub>; 916bdd1243dSDimitry Andricdefm V_SUBREV_F16 : VOP2Inst_t16 <"v_subrev_f16", VOP_F16_F16_F16, null_frag, "v_sub_f16">; 917bdd1243dSDimitry Andricdefm V_MUL_F16 : VOP2Inst_t16 <"v_mul_f16", VOP_F16_F16_F16, any_fmul>; 918bdd1243dSDimitry Andric} // End FPDPRounding = 1 919bdd1243dSDimitry Andricdefm V_MUL_LO_U16 : VOP2Inst_e64_t16 <"v_mul_lo_u16", VOP_I16_I16_I16, mul>; 920bdd1243dSDimitry Andricdefm V_MAX_F16 : VOP2Inst_t16 <"v_max_f16", VOP_F16_F16_F16, fmaxnum_like>; 921bdd1243dSDimitry Andricdefm V_MIN_F16 : VOP2Inst_t16 <"v_min_f16", VOP_F16_F16_F16, fminnum_like>; 922bdd1243dSDimitry Andricdefm V_MAX_U16 : VOP2Inst_e64_t16 <"v_max_u16", VOP_I16_I16_I16, umax>; 923bdd1243dSDimitry Andricdefm V_MAX_I16 : VOP2Inst_e64_t16 <"v_max_i16", VOP_I16_I16_I16, smax>; 924bdd1243dSDimitry Andricdefm V_MIN_U16 : VOP2Inst_e64_t16 <"v_min_u16", VOP_I16_I16_I16, umin>; 925bdd1243dSDimitry Andricdefm V_MIN_I16 : VOP2Inst_e64_t16 <"v_min_i16", VOP_I16_I16_I16, smin>; 926bdd1243dSDimitry Andric} // End isCommutable = 1 927bdd1243dSDimitry Andric} // End isReMaterializable = 1 928bdd1243dSDimitry Andric 92906c3fb27SDimitry Andricclass LDEXP_F16_Pat <SDPatternOperator op, VOP_Pseudo inst, VOPProfile P = inst.Pfl> : GCNPat < 93006c3fb27SDimitry Andric (P.DstVT (op (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)), 93106c3fb27SDimitry Andric (i16 (VOP3Mods0 P.Src1VT:$src1, i32:$src1_modifiers)))), 93206c3fb27SDimitry Andric (inst $src0_modifiers, $src0, 93306c3fb27SDimitry Andric $src1_modifiers, $src1, 93406c3fb27SDimitry Andric $clamp, /* clamp */ 93506c3fb27SDimitry Andric $omod /* omod */) 93606c3fb27SDimitry Andric>; 93706c3fb27SDimitry Andric 93806c3fb27SDimitry Andriclet OtherPredicates = [NotHasTrue16BitInsts] in 93906c3fb27SDimitry Andricdef : LDEXP_F16_Pat<any_fldexp, V_LDEXP_F16_e64>; 94006c3fb27SDimitry Andric 94106c3fb27SDimitry Andriclet OtherPredicates = [HasTrue16BitInsts] in 94206c3fb27SDimitry Andricdef : LDEXP_F16_Pat<any_fldexp, V_LDEXP_F16_t16_e64>; 94306c3fb27SDimitry Andric 944bdd1243dSDimitry Andriclet SubtargetPredicate = isGFX11Plus in { 945bdd1243dSDimitry Andric let isCommutable = 1 in { 9465f757f3fSDimitry Andric defm V_AND_B16_t16 : VOP2Inst_e64 <"v_and_b16_t16", VOPProfile_Fake16<VOP_I16_I16_I16>, and>; 9475f757f3fSDimitry Andric defm V_OR_B16_t16 : VOP2Inst_e64 <"v_or_b16_t16", VOPProfile_Fake16<VOP_I16_I16_I16>, or>; 9485f757f3fSDimitry Andric defm V_XOR_B16_t16 : VOP2Inst_e64 <"v_xor_b16_t16", VOPProfile_Fake16<VOP_I16_I16_I16>, xor>; 949bdd1243dSDimitry Andric } // End isCommutable = 1 950bdd1243dSDimitry Andric} // End SubtargetPredicate = isGFX11Plus 951bdd1243dSDimitry Andric 9525f757f3fSDimitry Andriclet FPDPRounding = 1, isReMaterializable = 1, FixedSize = 1 in { 953bdd1243dSDimitry Andriclet SubtargetPredicate = isGFX10Plus, OtherPredicates = [NotHasTrue16BitInsts] in { 954bdd1243dSDimitry Andricdef V_FMAMK_F16 : VOP2_Pseudo <"v_fmamk_f16", VOP_MADMK_F16, [], "">; 955bdd1243dSDimitry Andric} 956bdd1243dSDimitry Andriclet SubtargetPredicate = HasTrue16BitInsts in { 957bdd1243dSDimitry Andricdef V_FMAMK_F16_t16 : VOP2_Pseudo <"v_fmamk_f16_t16", VOP_MADMK_F16_t16, [], "">; 958bdd1243dSDimitry Andric} 959bdd1243dSDimitry Andric 960bdd1243dSDimitry Andriclet isCommutable = 1 in { 961bdd1243dSDimitry Andriclet SubtargetPredicate = isGFX10Plus, OtherPredicates = [NotHasTrue16BitInsts] in { 962bdd1243dSDimitry Andricdef V_FMAAK_F16 : VOP2_Pseudo <"v_fmaak_f16", VOP_MADAK_F16, [], "">; 963bdd1243dSDimitry Andric} 964bdd1243dSDimitry Andriclet SubtargetPredicate = HasTrue16BitInsts in { 965bdd1243dSDimitry Andricdef V_FMAAK_F16_t16 : VOP2_Pseudo <"v_fmaak_f16_t16", VOP_MADAK_F16_t16, [], "">; 966bdd1243dSDimitry Andric} 967bdd1243dSDimitry Andric} // End isCommutable = 1 9685f757f3fSDimitry Andric} // End FPDPRounding = 1, isReMaterializable = 1, FixedSize = 1 969bdd1243dSDimitry Andric 970bdd1243dSDimitry Andriclet Constraints = "$vdst = $src2", 971bdd1243dSDimitry Andric DisableEncoding="$src2", 972bdd1243dSDimitry Andric isConvertibleToThreeAddress = 1, 973bdd1243dSDimitry Andric isCommutable = 1 in { 974bdd1243dSDimitry Andriclet SubtargetPredicate = isGFX10Plus, OtherPredicates = [NotHasTrue16BitInsts] in { 975bdd1243dSDimitry Andricdefm V_FMAC_F16 : VOP2Inst <"v_fmac_f16", VOP_MAC_F16>; 976bdd1243dSDimitry Andric} 977bdd1243dSDimitry Andriclet SubtargetPredicate = HasTrue16BitInsts in { 978bdd1243dSDimitry Andricdefm V_FMAC_F16_t16 : VOP2Inst <"v_fmac_f16_t16", VOP_MAC_F16_t16>; 979bdd1243dSDimitry Andric} 980bdd1243dSDimitry Andric} // End FMAC Constraints 9810b57cec5SDimitry Andric 98281ad6265SDimitry Andriclet SubtargetPredicate = Has16BitInsts in { 98381ad6265SDimitry Andriclet isReMaterializable = 1 in { 9840b57cec5SDimitry Andriclet FPDPRounding = 1 in { 9850b57cec5SDimitry Andricdef V_MADMK_F16 : VOP2_Pseudo <"v_madmk_f16", VOP_MADMK_F16, [], "">; 9860b57cec5SDimitry Andric} // End FPDPRounding = 1 9870b57cec5SDimitry Andriclet isCommutable = 1 in { 9885ffd83dbSDimitry Andriclet mayRaiseFPException = 0 in { 9890b57cec5SDimitry Andricdef V_MADAK_F16 : VOP2_Pseudo <"v_madak_f16", VOP_MADAK_F16, [], "">; 9905ffd83dbSDimitry Andric} 99181ad6265SDimitry Andriclet SubtargetPredicate = isGFX8GFX9 in { 99281ad6265SDimitry Andric defm V_ADD_U16 : VOP2Inst <"v_add_u16", VOP_I16_I16_I16_ARITH, add>; 99381ad6265SDimitry Andric defm V_SUB_U16 : VOP2Inst <"v_sub_u16" , VOP_I16_I16_I16_ARITH, sub>; 99481ad6265SDimitry Andric defm V_SUBREV_U16 : VOP2Inst <"v_subrev_u16", VOP_I16_I16_I16_ARITH, null_frag, "v_sub_u16">; 9950b57cec5SDimitry Andric} 9960b57cec5SDimitry Andric} // End isCommutable = 1 99781ad6265SDimitry Andric} // End isReMaterializable = 1 9980b57cec5SDimitry Andric 99981ad6265SDimitry Andric// FIXME: Missing FPDPRounding 100081ad6265SDimitry Andriclet Constraints = "$vdst = $src2", DisableEncoding="$src2", 100181ad6265SDimitry Andric isConvertibleToThreeAddress = 1, isCommutable = 1 in { 100281ad6265SDimitry Andricdefm V_MAC_F16 : VOP2Inst <"v_mac_f16", VOP_MAC_F16>; 100381ad6265SDimitry Andric} 10040b57cec5SDimitry Andric} // End SubtargetPredicate = Has16BitInsts 10050b57cec5SDimitry Andric 1006bdd1243dSDimitry Andric 10070b57cec5SDimitry Andriclet SubtargetPredicate = HasDLInsts in { 10080b57cec5SDimitry Andric 1009fe6060f1SDimitry Andriclet isReMaterializable = 1 in 1010fe6060f1SDimitry Andricdefm V_XNOR_B32 : VOP2Inst <"v_xnor_b32", VOP_I32_I32_I32, xnor>; 10110b57cec5SDimitry Andric 101204eeddc0SDimitry Andricdef : GCNPat< 101304eeddc0SDimitry Andric (i32 (DivergentUnaryFrag<not> (xor_oneuse i32:$src0, i32:$src1))), 101404eeddc0SDimitry Andric (i32 (V_XNOR_B32_e64 $src0, $src1)) 101504eeddc0SDimitry Andric>; 101604eeddc0SDimitry Andric 101704eeddc0SDimitry Andricdef : GCNPat< 101804eeddc0SDimitry Andric (i32 (DivergentBinFrag<xor_oneuse> (not i32:$src0), i32:$src1)), 101904eeddc0SDimitry Andric (i32 (V_XNOR_B32_e64 $src0, $src1)) 102004eeddc0SDimitry Andric>; 102104eeddc0SDimitry Andric 102204eeddc0SDimitry Andricdef : GCNPat< 102304eeddc0SDimitry Andric (i64 (DivergentUnaryFrag<not> (xor_oneuse i64:$src0, i64:$src1))), 102404eeddc0SDimitry Andric (REG_SEQUENCE VReg_64, (i32 (V_XNOR_B32_e64 102504eeddc0SDimitry Andric (i32 (EXTRACT_SUBREG $src0, sub0)), 102604eeddc0SDimitry Andric (i32 (EXTRACT_SUBREG $src1, sub0)))), sub0, 102704eeddc0SDimitry Andric (i32 (V_XNOR_B32_e64 102804eeddc0SDimitry Andric (i32 (EXTRACT_SUBREG $src0, sub1)), 102904eeddc0SDimitry Andric (i32 (EXTRACT_SUBREG $src1, sub1)))), sub1) 103004eeddc0SDimitry Andric>; 103104eeddc0SDimitry Andric 103204eeddc0SDimitry Andricdef : GCNPat< 103304eeddc0SDimitry Andric (i64 (DivergentBinFrag<xor_oneuse> (not i64:$src0), i64:$src1)), 103404eeddc0SDimitry Andric (REG_SEQUENCE VReg_64, (i32 (V_XNOR_B32_e64 103504eeddc0SDimitry Andric (i32 (EXTRACT_SUBREG $src0, sub0)), 103604eeddc0SDimitry Andric (i32 (EXTRACT_SUBREG $src1, sub0)))), sub0, 103704eeddc0SDimitry Andric (i32 (V_XNOR_B32_e64 103804eeddc0SDimitry Andric (i32 (EXTRACT_SUBREG $src0, sub1)), 103904eeddc0SDimitry Andric (i32 (EXTRACT_SUBREG $src1, sub1)))), sub1) 104004eeddc0SDimitry Andric>; 104104eeddc0SDimitry Andric 10420b57cec5SDimitry Andriclet Constraints = "$vdst = $src2", 10430b57cec5SDimitry Andric DisableEncoding = "$src2", 10440b57cec5SDimitry Andric isConvertibleToThreeAddress = 1, 1045e8d8bef9SDimitry Andric isCommutable = 1 in 104681ad6265SDimitry Andricdefm V_FMAC_F32 : VOP2Inst_VOPD <"v_fmac_f32", VOP_MAC_F32, 0x0, "v_fmac_f32">; 10470b57cec5SDimitry Andric} // End SubtargetPredicate = HasDLInsts 10480b57cec5SDimitry Andric 1049e8d8bef9SDimitry Andriclet SubtargetPredicate = HasFmaLegacy32 in { 1050e8d8bef9SDimitry Andric 1051e8d8bef9SDimitry Andriclet Constraints = "$vdst = $src2", 1052e8d8bef9SDimitry Andric DisableEncoding = "$src2", 1053e8d8bef9SDimitry Andric isConvertibleToThreeAddress = 1, 1054e8d8bef9SDimitry Andric isCommutable = 1 in 1055e8d8bef9SDimitry Andricdefm V_FMAC_LEGACY_F32 : VOP2Inst <"v_fmac_legacy_f32", VOP_MAC_LEGACY_F32>; 1056e8d8bef9SDimitry Andric 1057e8d8bef9SDimitry Andric} // End SubtargetPredicate = HasFmaLegacy32 1058e8d8bef9SDimitry Andric 1059bdd1243dSDimitry Andriclet SubtargetPredicate = HasFmacF64Inst, 1060fe6060f1SDimitry Andric Constraints = "$vdst = $src2", 1061fe6060f1SDimitry Andric DisableEncoding="$src2", 1062fe6060f1SDimitry Andric isConvertibleToThreeAddress = 1, 1063fe6060f1SDimitry Andric isCommutable = 1, 1064fe6060f1SDimitry Andric SchedRW = [WriteDoubleAdd] in 1065fe6060f1SDimitry Andricdefm V_FMAC_F64 : VOP2Inst <"v_fmac_f64", VOP_MAC_F64>; 1066fe6060f1SDimitry Andric 10670b57cec5SDimitry Andriclet Constraints = "$vdst = $src2", 10680b57cec5SDimitry Andric DisableEncoding="$src2", 10690b57cec5SDimitry Andric isConvertibleToThreeAddress = 1, 10708bcb0991SDimitry Andric isCommutable = 1, 10718bcb0991SDimitry Andric IsDOT = 1 in { 10720b57cec5SDimitry Andric let SubtargetPredicate = HasDot5Insts in 107381ad6265SDimitry Andric defm V_DOT2C_F32_F16 : VOP2Inst_VOPD<"v_dot2c_f32_f16", VOP_DOT_ACC_F32_V2F16, 0xc, "v_dot2acc_f32_f16">; 10740b57cec5SDimitry Andric let SubtargetPredicate = HasDot6Insts in 10758bcb0991SDimitry Andric defm V_DOT4C_I32_I8 : VOP2Inst<"v_dot4c_i32_i8", VOP_DOT_ACC_I32_I32>; 10760b57cec5SDimitry Andric 10770b57cec5SDimitry Andric let SubtargetPredicate = HasDot4Insts in 10788bcb0991SDimitry Andric defm V_DOT2C_I32_I16 : VOP2Inst<"v_dot2c_i32_i16", VOP_DOT_ACC_I32_I32>; 10790b57cec5SDimitry Andric let SubtargetPredicate = HasDot3Insts in 10808bcb0991SDimitry Andric defm V_DOT8C_I32_I4 : VOP2Inst<"v_dot8c_i32_i4", VOP_DOT_ACC_I32_I32>; 10810b57cec5SDimitry Andric} 10820b57cec5SDimitry Andric 10830b57cec5SDimitry Andriclet AddedComplexity = 30 in { 10840b57cec5SDimitry Andric def : GCNPat< 10850b57cec5SDimitry Andric (f32 (AMDGPUfdot2 v2f16:$src0, v2f16:$src1, f32:$src2, (i1 DSTCLAMP.NONE))), 10860b57cec5SDimitry Andric (f32 (V_DOT2C_F32_F16_e32 $src0, $src1, $src2)) 10870b57cec5SDimitry Andric > { 10880b57cec5SDimitry Andric let SubtargetPredicate = HasDot5Insts; 10890b57cec5SDimitry Andric } 10900b57cec5SDimitry Andric def : GCNPat< 10910b57cec5SDimitry Andric (i32 (int_amdgcn_sdot4 i32:$src0, i32:$src1, i32:$src2, (i1 DSTCLAMP.NONE))), 10920b57cec5SDimitry Andric (i32 (V_DOT4C_I32_I8_e32 $src0, $src1, $src2)) 10930b57cec5SDimitry Andric > { 10940b57cec5SDimitry Andric let SubtargetPredicate = HasDot6Insts; 10950b57cec5SDimitry Andric } 10960b57cec5SDimitry Andric def : GCNPat< 10970b57cec5SDimitry Andric (i32 (int_amdgcn_sdot2 v2i16:$src0, v2i16:$src1, i32:$src2, (i1 DSTCLAMP.NONE))), 10980b57cec5SDimitry Andric (i32 (V_DOT2C_I32_I16_e32 $src0, $src1, $src2)) 10990b57cec5SDimitry Andric > { 11000b57cec5SDimitry Andric let SubtargetPredicate = HasDot4Insts; 11010b57cec5SDimitry Andric } 11020b57cec5SDimitry Andric def : GCNPat< 11030b57cec5SDimitry Andric (i32 (int_amdgcn_sdot8 i32:$src0, i32:$src1, i32:$src2, (i1 DSTCLAMP.NONE))), 11040b57cec5SDimitry Andric (i32 (V_DOT8C_I32_I4_e32 $src0, $src1, $src2)) 11050b57cec5SDimitry Andric > { 11060b57cec5SDimitry Andric let SubtargetPredicate = HasDot3Insts; 11070b57cec5SDimitry Andric } 11080b57cec5SDimitry Andric} // End AddedComplexity = 30 11090b57cec5SDimitry Andric 11105f757f3fSDimitry Andriclet SubtargetPredicate = HasFmaakFmamkF32Insts, isReMaterializable = 1, FixedSize = 1 in { 111181ad6265SDimitry Andricdef V_FMAMK_F32 : VOP2_Pseudo<"v_fmamk_f32", VOP_MADMK_F32, [], "">, VOPD_Component<0x2, "v_fmamk_f32">; 1112fe6060f1SDimitry Andric 1113fe6060f1SDimitry Andriclet isCommutable = 1 in 111481ad6265SDimitry Andricdef V_FMAAK_F32 : VOP2_Pseudo<"v_fmaak_f32", VOP_MADAK_F32, [], "">, VOPD_Component<0x1, "v_fmaak_f32">; 11155f757f3fSDimitry Andric} // End SubtargetPredicate = HasFmaakFmamkF32Insts, isReMaterializable = 1, FixedSize = 1 1116fe6060f1SDimitry Andric 11170b57cec5SDimitry Andriclet SubtargetPredicate = HasPkFmacF16Inst in { 11180b57cec5SDimitry Andricdefm V_PK_FMAC_F16 : VOP2Inst<"v_pk_fmac_f16", VOP_V2F16_V2F16_V2F16>; 11190b57cec5SDimitry Andric} // End SubtargetPredicate = HasPkFmacF16Inst 11200b57cec5SDimitry Andric 11210b57cec5SDimitry Andric// Note: 16-bit instructions produce a 0 result in the high 16-bits 11220b57cec5SDimitry Andric// on GFX8 and GFX9 and preserve high 16 bits on GFX10+ 11238bcb0991SDimitry Andricmulticlass Arithmetic_i16_0Hi_Pats <SDPatternOperator op, Instruction inst> { 11240b57cec5SDimitry Andric 11250b57cec5SDimitry Andricdef : GCNPat< 11260b57cec5SDimitry Andric (i32 (zext (op i16:$src0, i16:$src1))), 1127480093f4SDimitry Andric (inst VSrc_b16:$src0, VSrc_b16:$src1) 11280b57cec5SDimitry Andric>; 11290b57cec5SDimitry Andric 11300b57cec5SDimitry Andricdef : GCNPat< 11310b57cec5SDimitry Andric (i64 (zext (op i16:$src0, i16:$src1))), 11320b57cec5SDimitry Andric (REG_SEQUENCE VReg_64, 11338bcb0991SDimitry Andric (inst $src0, $src1), sub0, 11340b57cec5SDimitry Andric (V_MOV_B32_e32 (i32 0)), sub1) 11350b57cec5SDimitry Andric>; 11360b57cec5SDimitry Andric} 11370b57cec5SDimitry Andric 11380b57cec5SDimitry Andricclass ZExt_i16_i1_Pat <SDNode ext> : GCNPat < 11390b57cec5SDimitry Andric (i16 (ext i1:$src)), 11400b57cec5SDimitry Andric (V_CNDMASK_B32_e64 (i32 0/*src0mod*/), (i32 0/*src0*/), 11410b57cec5SDimitry Andric (i32 0/*src1mod*/), (i32 1/*src1*/), 11420b57cec5SDimitry Andric $src) 11430b57cec5SDimitry Andric>; 11440b57cec5SDimitry Andric 11458bcb0991SDimitry Andricforeach vt = [i16, v2i16] in { 11468bcb0991SDimitry Andricdef : GCNPat < 11478bcb0991SDimitry Andric (and vt:$src0, vt:$src1), 11488bcb0991SDimitry Andric (V_AND_B32_e64 VSrc_b32:$src0, VSrc_b32:$src1) 11498bcb0991SDimitry Andric>; 11508bcb0991SDimitry Andric 11518bcb0991SDimitry Andricdef : GCNPat < 11528bcb0991SDimitry Andric (or vt:$src0, vt:$src1), 11538bcb0991SDimitry Andric (V_OR_B32_e64 VSrc_b32:$src0, VSrc_b32:$src1) 11548bcb0991SDimitry Andric>; 11558bcb0991SDimitry Andric 11568bcb0991SDimitry Andricdef : GCNPat < 11578bcb0991SDimitry Andric (xor vt:$src0, vt:$src1), 11588bcb0991SDimitry Andric (V_XOR_B32_e64 VSrc_b32:$src0, VSrc_b32:$src1) 11598bcb0991SDimitry Andric>; 11608bcb0991SDimitry Andric} 11618bcb0991SDimitry Andric 116281ad6265SDimitry Andriclet Predicates = [Has16BitInsts, isGFX8GFX9] in { 11630b57cec5SDimitry Andric 1164480093f4SDimitry Andric// Undo sub x, c -> add x, -c canonicalization since c is more likely 1165480093f4SDimitry Andric// an inline immediate than -c. 1166480093f4SDimitry Andric// TODO: Also do for 64-bit. 1167480093f4SDimitry Andricdef : GCNPat< 11685ffd83dbSDimitry Andric (add i16:$src0, (i16 NegSubInlineIntConst16:$src1)), 11695ffd83dbSDimitry Andric (V_SUB_U16_e64 VSrc_b16:$src0, NegSubInlineIntConst16:$src1) 1170480093f4SDimitry Andric>; 1171480093f4SDimitry Andric 1172480093f4SDimitry Andricdef : GCNPat< 11735ffd83dbSDimitry Andric (i32 (zext (add i16:$src0, (i16 NegSubInlineIntConst16:$src1)))), 11745ffd83dbSDimitry Andric (V_SUB_U16_e64 VSrc_b16:$src0, NegSubInlineIntConst16:$src1) 1175480093f4SDimitry Andric>; 1176480093f4SDimitry Andric 11778bcb0991SDimitry Andricdefm : Arithmetic_i16_0Hi_Pats<add, V_ADD_U16_e64>; 11788bcb0991SDimitry Andricdefm : Arithmetic_i16_0Hi_Pats<mul, V_MUL_LO_U16_e64>; 11798bcb0991SDimitry Andricdefm : Arithmetic_i16_0Hi_Pats<sub, V_SUB_U16_e64>; 11808bcb0991SDimitry Andricdefm : Arithmetic_i16_0Hi_Pats<smin, V_MIN_I16_e64>; 11818bcb0991SDimitry Andricdefm : Arithmetic_i16_0Hi_Pats<smax, V_MAX_I16_e64>; 11828bcb0991SDimitry Andricdefm : Arithmetic_i16_0Hi_Pats<umin, V_MIN_U16_e64>; 11838bcb0991SDimitry Andricdefm : Arithmetic_i16_0Hi_Pats<umax, V_MAX_U16_e64>; 1184349cc55cSDimitry Andricdefm : Arithmetic_i16_0Hi_Pats<clshl_rev_16, V_LSHLREV_B16_e64>; 1185349cc55cSDimitry Andricdefm : Arithmetic_i16_0Hi_Pats<clshr_rev_16, V_LSHRREV_B16_e64>; 1186349cc55cSDimitry Andricdefm : Arithmetic_i16_0Hi_Pats<cashr_rev_16, V_ASHRREV_I16_e64>; 118781ad6265SDimitry Andric 118881ad6265SDimitry Andric} // End Predicates = [Has16BitInsts, isGFX8GFX9] 118981ad6265SDimitry Andric 119081ad6265SDimitry Andriclet Predicates = [Has16BitInsts] in { 11910b57cec5SDimitry Andric 11920b57cec5SDimitry Andricdef : ZExt_i16_i1_Pat<zext>; 11930b57cec5SDimitry Andricdef : ZExt_i16_i1_Pat<anyext>; 11940b57cec5SDimitry Andric 11950b57cec5SDimitry Andricdef : GCNPat < 11960b57cec5SDimitry Andric (i16 (sext i1:$src)), 11970b57cec5SDimitry Andric (V_CNDMASK_B32_e64 /*src0mod*/(i32 0), /*src0*/(i32 0), 11980b57cec5SDimitry Andric /*src1mod*/(i32 0), /*src1*/(i32 -1), $src) 11990b57cec5SDimitry Andric>; 12000b57cec5SDimitry Andric 1201480093f4SDimitry Andric} // End Predicates = [Has16BitInsts] 12020b57cec5SDimitry Andric 12030b57cec5SDimitry Andric 1204e8d8bef9SDimitry Andriclet SubtargetPredicate = HasIntClamp in { 1205e8d8bef9SDimitry Andric// Set clamp bit for saturation. 1206e8d8bef9SDimitry Andricdef : VOPBinOpClampPat<uaddsat, V_ADD_CO_U32_e64, i32>; 1207e8d8bef9SDimitry Andricdef : VOPBinOpClampPat<usubsat, V_SUB_CO_U32_e64, i32>; 1208e8d8bef9SDimitry Andric} 1209e8d8bef9SDimitry Andric 1210e8d8bef9SDimitry Andriclet SubtargetPredicate = HasAddNoCarryInsts, OtherPredicates = [HasIntClamp] in { 1211e8d8bef9SDimitry Andriclet AddedComplexity = 1 in { // Prefer over form with carry-out. 1212e8d8bef9SDimitry Andricdef : VOPBinOpClampPat<uaddsat, V_ADD_U32_e64, i32>; 1213e8d8bef9SDimitry Andricdef : VOPBinOpClampPat<usubsat, V_SUB_U32_e64, i32>; 1214e8d8bef9SDimitry Andric} 1215e8d8bef9SDimitry Andric} 1216e8d8bef9SDimitry Andric 1217e8d8bef9SDimitry Andriclet SubtargetPredicate = Has16BitInsts, OtherPredicates = [HasIntClamp] in { 1218e8d8bef9SDimitry Andricdef : VOPBinOpClampPat<uaddsat, V_ADD_U16_e64, i16>; 1219e8d8bef9SDimitry Andricdef : VOPBinOpClampPat<usubsat, V_SUB_U16_e64, i16>; 1220e8d8bef9SDimitry Andric} 1221e8d8bef9SDimitry Andric 12225f757f3fSDimitry Andriclet SubtargetPredicate = isGFX12Plus, isReMaterializable = 1 in { 12235f757f3fSDimitry Andric let SchedRW = [WriteDoubleAdd], isCommutable = 1 in { 12245f757f3fSDimitry Andric let FPDPRounding = 1 in { 12255f757f3fSDimitry Andric defm V_ADD_F64_pseudo : VOP2Inst <"v_add_f64_pseudo", VOP_F64_F64_F64, any_fadd>; 12265f757f3fSDimitry Andric defm V_MUL_F64_pseudo : VOP2Inst <"v_mul_f64_pseudo", VOP_F64_F64_F64, fmul>; 12275f757f3fSDimitry Andric } // End FPDPRounding = 1 12285f757f3fSDimitry Andric defm V_MIN_NUM_F64 : VOP2Inst <"v_min_num_f64", VOP_F64_F64_F64, fminnum_like>; 12295f757f3fSDimitry Andric defm V_MAX_NUM_F64 : VOP2Inst <"v_max_num_f64", VOP_F64_F64_F64, fmaxnum_like>; 12305f757f3fSDimitry Andric } // End SchedRW = [WriteDoubleAdd], isCommutable = 1 12315f757f3fSDimitry Andric let SchedRW = [Write64Bit] in { 12325f757f3fSDimitry Andric defm V_LSHLREV_B64_pseudo : VOP2Inst <"v_lshlrev_b64_pseudo", VOP_I64_I32_I64, clshl_rev_64>; 12335f757f3fSDimitry Andric } // End SchedRW = [Write64Bit] 12345f757f3fSDimitry Andric} // End SubtargetPredicate = isGFX12Plus, isReMaterializable = 1 12355f757f3fSDimitry Andric 12360b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 123781ad6265SDimitry Andric// DPP Encodings 12380b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 12390b57cec5SDimitry Andric 12408bcb0991SDimitry Andricclass VOP2_DPP<bits<6> op, VOP2_DPP_Pseudo ps, 12410b57cec5SDimitry Andric string opName = ps.OpName, VOPProfile p = ps.Pfl, 12420b57cec5SDimitry Andric bit IsDPP16 = 0> : 12430b57cec5SDimitry Andric VOP_DPP<opName, p, IsDPP16> { 12440b57cec5SDimitry Andric let hasSideEffects = ps.hasSideEffects; 12450b57cec5SDimitry Andric let Defs = ps.Defs; 12460b57cec5SDimitry Andric let SchedRW = ps.SchedRW; 12470b57cec5SDimitry Andric let Uses = ps.Uses; 12480b57cec5SDimitry Andric 12490b57cec5SDimitry Andric bits<8> vdst; 12500b57cec5SDimitry Andric bits<8> src1; 12510b57cec5SDimitry Andric let Inst{8-0} = 0xfa; 12520b57cec5SDimitry Andric let Inst{16-9} = !if(p.HasSrc1, src1{7-0}, 0); 12530b57cec5SDimitry Andric let Inst{24-17} = !if(p.EmitDst, vdst{7-0}, 0); 12540b57cec5SDimitry Andric let Inst{30-25} = op; 12550b57cec5SDimitry Andric let Inst{31} = 0x0; 12560b57cec5SDimitry Andric} 12570b57cec5SDimitry Andric 12588bcb0991SDimitry Andricclass Base_VOP2_DPP16<bits<6> op, VOP2_DPP_Pseudo ps, 12590b57cec5SDimitry Andric string opName = ps.OpName, VOPProfile p = ps.Pfl> : 12600b57cec5SDimitry Andric VOP2_DPP<op, ps, opName, p, 1> { 12615ffd83dbSDimitry Andric let AssemblerPredicate = HasDPP16; 12620b57cec5SDimitry Andric let SubtargetPredicate = HasDPP16; 1263e8d8bef9SDimitry Andric let OtherPredicates = ps.OtherPredicates; 12640b57cec5SDimitry Andric} 12650b57cec5SDimitry Andric 126681ad6265SDimitry Andricclass VOP2_DPP16<bits<6> op, VOP2_DPP_Pseudo ps, int subtarget, 12678bcb0991SDimitry Andric string opName = ps.OpName, VOPProfile p = ps.Pfl> : 12688bcb0991SDimitry Andric Base_VOP2_DPP16<op, ps, opName, p>, 126981ad6265SDimitry Andric SIMCInstr <ps.PseudoInstr, subtarget>; 12708bcb0991SDimitry Andric 12715f757f3fSDimitry Andricclass VOP2_DPP16_Gen<bits<6> op, VOP2_DPP_Pseudo ps, GFXGen Gen, 12725f757f3fSDimitry Andric string opName = ps.OpName, VOPProfile p = ps.Pfl> : 12735f757f3fSDimitry Andric VOP2_DPP16<op, ps, Gen.Subtarget, opName, p> { 1274297eecfbSDimitry Andric let AssemblerPredicate = Gen.AssemblerPredicate; 1275297eecfbSDimitry Andric let OtherPredicates = !if(ps.Pfl.IsRealTrue16, [UseRealTrue16Insts], []); 12765f757f3fSDimitry Andric let DecoderNamespace = "DPP"#Gen.DecoderNamespace# 12775f757f3fSDimitry Andric !if(ps.Pfl.IsRealTrue16, "", "_FAKE16"); 12785f757f3fSDimitry Andric} 12795f757f3fSDimitry Andric 12800b57cec5SDimitry Andricclass VOP2_DPP8<bits<6> op, VOP2_Pseudo ps, 1281349cc55cSDimitry Andric VOPProfile p = ps.Pfl> : 12820b57cec5SDimitry Andric VOP_DPP8<ps.OpName, p> { 12830b57cec5SDimitry Andric let hasSideEffects = ps.hasSideEffects; 12840b57cec5SDimitry Andric let Defs = ps.Defs; 12850b57cec5SDimitry Andric let SchedRW = ps.SchedRW; 12860b57cec5SDimitry Andric let Uses = ps.Uses; 12870b57cec5SDimitry Andric 12880b57cec5SDimitry Andric bits<8> vdst; 12890b57cec5SDimitry Andric bits<8> src1; 12900b57cec5SDimitry Andric 12910b57cec5SDimitry Andric let Inst{8-0} = fi; 12920b57cec5SDimitry Andric let Inst{16-9} = !if(p.HasSrc1, src1{7-0}, 0); 12930b57cec5SDimitry Andric let Inst{24-17} = !if(p.EmitDst, vdst{7-0}, 0); 12940b57cec5SDimitry Andric let Inst{30-25} = op; 12950b57cec5SDimitry Andric let Inst{31} = 0x0; 12960b57cec5SDimitry Andric 1297e8d8bef9SDimitry Andric let OtherPredicates = ps.OtherPredicates; 12980b57cec5SDimitry Andric} 12990b57cec5SDimitry Andric 13005f757f3fSDimitry Andricclass VOP2_DPP8_Gen<bits<6> op, VOP2_Pseudo ps, GFXGen Gen, 13015f757f3fSDimitry Andric VOPProfile p = ps.Pfl> : 13025f757f3fSDimitry Andric VOP2_DPP8<op, ps, p> { 1303297eecfbSDimitry Andric let AssemblerPredicate = Gen.AssemblerPredicate; 1304297eecfbSDimitry Andric let OtherPredicates = !if(ps.Pfl.IsRealTrue16, [UseRealTrue16Insts], []); 13055f757f3fSDimitry Andric let DecoderNamespace = "DPP8"#Gen.DecoderNamespace# 13065f757f3fSDimitry Andric !if(ps.Pfl.IsRealTrue16, "", "_FAKE16"); 13075f757f3fSDimitry Andric} 13085f757f3fSDimitry Andric 13090b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 13105f757f3fSDimitry Andric// GFX11, GFX12 131181ad6265SDimitry Andric//===----------------------------------------------------------------------===// 131281ad6265SDimitry Andric 131381ad6265SDimitry Andric//===------------------------------- VOP2 -------------------------------===// 13145f757f3fSDimitry Andricmulticlass VOP2Only_Real_MADK<GFXGen Gen, bits<6> op> { 13155f757f3fSDimitry Andric def Gen.Suffix : 13165f757f3fSDimitry Andric VOP2_Real_Gen<!cast<VOP2_Pseudo>(NAME), Gen>, 131781ad6265SDimitry Andric VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>; 131881ad6265SDimitry Andric} 13195f757f3fSDimitry Andric 13205f757f3fSDimitry Andricmulticlass VOP2Only_Real_MADK_with_name<GFXGen Gen, bits<6> op, string asmName, 1321bdd1243dSDimitry Andric string opName = NAME> { 13225f757f3fSDimitry Andric def Gen.Suffix : 13235f757f3fSDimitry Andric VOP2_Real_Gen<!cast<VOP2_Pseudo>(opName), Gen>, 1324bdd1243dSDimitry Andric VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(opName).Pfl> { 1325bdd1243dSDimitry Andric VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName); 1326bdd1243dSDimitry Andric let AsmString = asmName # ps.AsmOperands; 1327bdd1243dSDimitry Andric } 1328bdd1243dSDimitry Andric} 13295f757f3fSDimitry Andric 13305f757f3fSDimitry Andricmulticlass VOP2_Real_e32<GFXGen Gen, bits<6> op> { 13315f757f3fSDimitry Andric def _e32#Gen.Suffix : 13325f757f3fSDimitry Andric VOP2_Real_Gen<!cast<VOP2_Pseudo>(NAME#"_e32"), Gen>, 133381ad6265SDimitry Andric VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>; 133481ad6265SDimitry Andric} 13355f757f3fSDimitry Andric 13365f757f3fSDimitry Andricmulticlass VOP2Only_Real_e32<GFXGen Gen, bits<6> op> { 133781ad6265SDimitry Andric let IsSingle = 1 in 13385f757f3fSDimitry Andric defm NAME: VOP2_Real_e32<Gen, op>; 133981ad6265SDimitry Andric} 13405f757f3fSDimitry Andric 13415f757f3fSDimitry Andricmulticlass VOP2_Real_e64<GFXGen Gen, bits<6> op> { 13425f757f3fSDimitry Andric def _e64#Gen.Suffix : 13435f757f3fSDimitry Andric VOP3_Real_Gen<!cast<VOP3_Pseudo>(NAME#"_e64"), Gen>, 13445f757f3fSDimitry Andric VOP3e_gfx11_gfx12<{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 134581ad6265SDimitry Andric} 13465f757f3fSDimitry Andric 13475f757f3fSDimitry Andricmulticlass VOP2_Real_dpp<GFXGen Gen, bits<6> op> { 134806c3fb27SDimitry Andric if !cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP then 13495f757f3fSDimitry Andric def _dpp#Gen.Suffix : VOP2_DPP16_Gen<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp"), Gen>; 135081ad6265SDimitry Andric} 13515f757f3fSDimitry Andric 13525f757f3fSDimitry Andricmulticlass VOP2_Real_dpp8<GFXGen Gen, bits<6> op> { 135306c3fb27SDimitry Andric if !cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP then 13545f757f3fSDimitry Andric def _dpp8#Gen.Suffix : VOP2_DPP8_Gen<op, !cast<VOP2_Pseudo>(NAME#"_e32"), Gen>; 135581ad6265SDimitry Andric} 135681ad6265SDimitry Andric 135781ad6265SDimitry Andric//===------------------------- VOP2 (with name) -------------------------===// 13585f757f3fSDimitry Andricmulticlass VOP2_Real_e32_with_name<GFXGen Gen, bits<6> op, string opName, 135981ad6265SDimitry Andric string asmName, bit single = 0> { 136081ad6265SDimitry Andric defvar ps = !cast<VOP2_Pseudo>(opName#"_e32"); 13615f757f3fSDimitry Andric def _e32#Gen.Suffix : 13625f757f3fSDimitry Andric VOP2_Real_Gen<ps, Gen, asmName>, 1363bdd1243dSDimitry Andric VOP2e<op{5-0}, ps.Pfl> { 136481ad6265SDimitry Andric let AsmString = asmName # ps.AsmOperands; 136581ad6265SDimitry Andric let IsSingle = single; 136681ad6265SDimitry Andric } 136781ad6265SDimitry Andric} 13685f757f3fSDimitry Andricmulticlass VOP2_Real_e64_with_name<GFXGen Gen, bits<6> op, string opName, 136981ad6265SDimitry Andric string asmName> { 137081ad6265SDimitry Andric defvar ps = !cast<VOP3_Pseudo>(opName#"_e64"); 13715f757f3fSDimitry Andric def _e64#Gen.Suffix : 13725f757f3fSDimitry Andric VOP3_Real_Gen<ps, Gen>, 13735f757f3fSDimitry Andric VOP3e_gfx11_gfx12<{0, 1, 0, 0, op{5-0}}, ps.Pfl> { 137481ad6265SDimitry Andric let AsmString = asmName # ps.AsmOperands; 137581ad6265SDimitry Andric } 137681ad6265SDimitry Andric} 137781ad6265SDimitry Andric 13785f757f3fSDimitry Andricmulticlass VOP2_Real_dpp_with_name<GFXGen Gen, bits<6> op, string opName, 137981ad6265SDimitry Andric string asmName> { 138081ad6265SDimitry Andric defvar ps = !cast<VOP2_Pseudo>(opName#"_e32"); 138106c3fb27SDimitry Andric if ps.Pfl.HasExtDPP then 13825f757f3fSDimitry Andric def _dpp#Gen.Suffix : VOP2_DPP16_Gen<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), Gen> { 138381ad6265SDimitry Andric let AsmString = asmName # ps.Pfl.AsmDPP16; 138481ad6265SDimitry Andric } 138581ad6265SDimitry Andric} 13865f757f3fSDimitry Andricmulticlass VOP2_Real_dpp8_with_name<GFXGen Gen, bits<6> op, string opName, 138781ad6265SDimitry Andric string asmName> { 138881ad6265SDimitry Andric defvar ps = !cast<VOP2_Pseudo>(opName#"_e32"); 138906c3fb27SDimitry Andric if ps.Pfl.HasExtDPP then 13905f757f3fSDimitry Andric def _dpp8#Gen.Suffix : VOP2_DPP8_Gen<op, ps, Gen> { 139181ad6265SDimitry Andric let AsmString = asmName # ps.Pfl.AsmDPP8; 139281ad6265SDimitry Andric } 139381ad6265SDimitry Andric} 139481ad6265SDimitry Andric 139581ad6265SDimitry Andric//===------------------------------ VOP2be ------------------------------===// 13965f757f3fSDimitry Andricmulticlass VOP2be_Real_e32<GFXGen Gen, bits<6> op, string opName, string asmName> { 139781ad6265SDimitry Andric defvar ps = !cast<VOP2_Pseudo>(opName#"_e32"); 13985f757f3fSDimitry Andric def _e32#Gen.Suffix : 13995f757f3fSDimitry Andric VOP2_Real_Gen<ps, Gen>, 140081ad6265SDimitry Andric VOP2e<op{5-0}, ps.Pfl> { 140181ad6265SDimitry Andric let AsmString = asmName # !subst(", vcc", "", ps.AsmOperands); 140281ad6265SDimitry Andric } 140381ad6265SDimitry Andric} 14045f757f3fSDimitry Andricmulticlass VOP2be_Real_dpp<GFXGen Gen, bits<6> op, string opName, string asmName> { 140506c3fb27SDimitry Andric if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP then 14065f757f3fSDimitry Andric def _dpp#Gen.Suffix : 14075f757f3fSDimitry Andric VOP2_DPP16_Gen<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), Gen, asmName> { 140881ad6265SDimitry Andric string AsmDPP = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP16; 140981ad6265SDimitry Andric let AsmString = asmName # !subst(", vcc", "", AsmDPP); 141081ad6265SDimitry Andric } 141106c3fb27SDimitry Andric if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP then 14125f757f3fSDimitry Andric def _dpp_w32#Gen.Suffix : 141381ad6265SDimitry Andric Base_VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), asmName> { 141481ad6265SDimitry Andric string AsmDPP = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP16; 141581ad6265SDimitry Andric let AsmString = asmName # !subst("vcc", "vcc_lo", AsmDPP); 141681ad6265SDimitry Andric let isAsmParserOnly = 1; 141781ad6265SDimitry Andric let WaveSizePredicate = isWave32; 14185f757f3fSDimitry Andric let AssemblerPredicate = Gen.AssemblerPredicate; 14195f757f3fSDimitry Andric let DecoderNamespace = Gen.DecoderNamespace; 142081ad6265SDimitry Andric } 142106c3fb27SDimitry Andric if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP then 14225f757f3fSDimitry Andric def _dpp_w64#Gen.Suffix : 142381ad6265SDimitry Andric Base_VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), asmName> { 142481ad6265SDimitry Andric string AsmDPP = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP16; 142581ad6265SDimitry Andric let AsmString = asmName # AsmDPP; 142681ad6265SDimitry Andric let isAsmParserOnly = 1; 142781ad6265SDimitry Andric let WaveSizePredicate = isWave64; 14285f757f3fSDimitry Andric let AssemblerPredicate = Gen.AssemblerPredicate; 14295f757f3fSDimitry Andric let DecoderNamespace = Gen.DecoderNamespace; 143081ad6265SDimitry Andric } 143181ad6265SDimitry Andric} 14325f757f3fSDimitry Andricmulticlass VOP2be_Real_dpp8<GFXGen Gen, bits<6> op, string opName, string asmName> { 143306c3fb27SDimitry Andric if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP then 14345f757f3fSDimitry Andric def _dpp8#Gen.Suffix : 14355f757f3fSDimitry Andric VOP2_DPP8_Gen<op, !cast<VOP2_Pseudo>(opName#"_e32"), Gen> { 143681ad6265SDimitry Andric string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8; 143781ad6265SDimitry Andric let AsmString = asmName # !subst(", vcc", "", AsmDPP8); 143881ad6265SDimitry Andric } 143906c3fb27SDimitry Andric if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP then 14405f757f3fSDimitry Andric def _dpp8_w32#Gen.Suffix : 144181ad6265SDimitry Andric VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32")> { 144281ad6265SDimitry Andric string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8; 144381ad6265SDimitry Andric let AsmString = asmName # !subst("vcc", "vcc_lo", AsmDPP8); 144481ad6265SDimitry Andric let isAsmParserOnly = 1; 144581ad6265SDimitry Andric let WaveSizePredicate = isWave32; 14465f757f3fSDimitry Andric let AssemblerPredicate = Gen.AssemblerPredicate; 14475f757f3fSDimitry Andric let DecoderNamespace = Gen.DecoderNamespace; 144881ad6265SDimitry Andric } 144906c3fb27SDimitry Andric if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP then 14505f757f3fSDimitry Andric def _dpp8_w64#Gen.Suffix : 145181ad6265SDimitry Andric VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32")> { 145281ad6265SDimitry Andric string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8; 145381ad6265SDimitry Andric let AsmString = asmName # AsmDPP8; 145481ad6265SDimitry Andric let isAsmParserOnly = 1; 145581ad6265SDimitry Andric let WaveSizePredicate = isWave64; 14565f757f3fSDimitry Andric let AssemblerPredicate = Gen.AssemblerPredicate; 14575f757f3fSDimitry Andric let DecoderNamespace = Gen.DecoderNamespace; 145881ad6265SDimitry Andric } 145981ad6265SDimitry Andric} 146081ad6265SDimitry Andric 146181ad6265SDimitry Andric// We don't want to override separate decoderNamespaces within these 14625f757f3fSDimitry Andricmulticlass VOP2_Realtriple_e64<GFXGen Gen, bits<6> op> { 14635f757f3fSDimitry Andric defm NAME : VOP3_Realtriple<Gen, {0, 1, 0, 0, op{5-0}}, /*isSingle=*/ 0, NAME> ; 146481ad6265SDimitry Andric} 146581ad6265SDimitry Andric 14665f757f3fSDimitry Andricmulticlass VOP2_Realtriple_e64_with_name<GFXGen Gen, bits<6> op, string opName, 14675f757f3fSDimitry Andric string asmName> { 14685f757f3fSDimitry Andric defm NAME : VOP3_Realtriple_with_name<Gen, {0, 1, 0, 0, op{5-0}}, opName, asmName> ; 14695f757f3fSDimitry Andric} 14705f757f3fSDimitry Andric 14715f757f3fSDimitry Andricmulticlass VOP2be_Real<GFXGen Gen, bits<6> op, string opName, string asmName> : 14725f757f3fSDimitry Andric VOP2be_Real_e32<Gen, op, opName, asmName>, 14735f757f3fSDimitry Andric VOP3be_Realtriple<Gen, {0, 1, 0, 0, op{5-0}}, /*isSingle=*/ 0, opName, asmName>, 14745f757f3fSDimitry Andric VOP2be_Real_dpp<Gen, op, opName, asmName>, 14755f757f3fSDimitry Andric VOP2be_Real_dpp8<Gen, op, opName, asmName>; 14765f757f3fSDimitry Andric 14775f757f3fSDimitry Andric// Only for CNDMASK 14785f757f3fSDimitry Andricmulticlass VOP2e_Real<GFXGen Gen, bits<6> op, string opName, string asmName> : 14795f757f3fSDimitry Andric VOP2_Real_e32<Gen, op>, 14805f757f3fSDimitry Andric VOP2_Realtriple_e64<Gen, op>, 14815f757f3fSDimitry Andric VOP2be_Real_dpp<Gen, op, opName, asmName>, 14825f757f3fSDimitry Andric VOP2be_Real_dpp8<Gen, op, opName, asmName>; 14835f757f3fSDimitry Andric 14845f757f3fSDimitry Andricmulticlass VOP2Only_Real<GFXGen Gen, bits<6> op> : 14855f757f3fSDimitry Andric VOP2Only_Real_e32<Gen, op>, 14865f757f3fSDimitry Andric VOP2_Real_dpp<Gen, op>, 14875f757f3fSDimitry Andric VOP2_Real_dpp8<Gen, op>; 14885f757f3fSDimitry Andric 14895f757f3fSDimitry Andricmulticlass VOP2_Real_FULL<GFXGen Gen, bits<6> op> : 14905f757f3fSDimitry Andric VOP2_Realtriple_e64<Gen, op>, 14915f757f3fSDimitry Andric VOP2_Real_e32<Gen, op>, 14925f757f3fSDimitry Andric VOP2_Real_dpp<Gen, op>, 14935f757f3fSDimitry Andric VOP2_Real_dpp8<Gen, op>; 14945f757f3fSDimitry Andric 14955f757f3fSDimitry Andricmulticlass VOP2_Real_NO_VOP3_with_name<GFXGen Gen, bits<6> op, string opName, 14965f757f3fSDimitry Andric string asmName, bit isSingle = 0> { 14975f757f3fSDimitry Andric defm NAME : VOP2_Real_e32_with_name<Gen, op, opName, asmName, isSingle>, 14985f757f3fSDimitry Andric VOP2_Real_dpp_with_name<Gen, op, opName, asmName>, 14995f757f3fSDimitry Andric VOP2_Real_dpp8_with_name<Gen, op, opName, asmName>; 15005f757f3fSDimitry Andric defvar ps = !cast<VOP2_Pseudo>(opName#"_e32"); 15015f757f3fSDimitry Andric def Gen.Suffix#"_alias" : MnemonicAlias<ps.Mnemonic, asmName>, Requires<[Gen.AssemblerPredicate]>; 15025f757f3fSDimitry Andric} 15035f757f3fSDimitry Andric 15045f757f3fSDimitry Andricmulticlass VOP2_Real_FULL_with_name<GFXGen Gen, bits<6> op, string opName, 15055f757f3fSDimitry Andric string asmName> : 15065f757f3fSDimitry Andric VOP2_Realtriple_e64_with_name<Gen, op, opName, asmName>, 15075f757f3fSDimitry Andric VOP2_Real_NO_VOP3_with_name<Gen, op, opName, asmName>; 15085f757f3fSDimitry Andric 15095f757f3fSDimitry Andricmulticlass VOP2_Real_NO_DPP_with_name<GFXGen Gen, bits<6> op, string opName, 15105f757f3fSDimitry Andric string asmName> { 15115f757f3fSDimitry Andric defm NAME : VOP2_Real_e32_with_name<Gen, op, opName, asmName>, 15125f757f3fSDimitry Andric VOP2_Real_e64_with_name<Gen, op, opName, asmName>; 15135f757f3fSDimitry Andric defvar ps = !cast<VOP2_Pseudo>(opName#"_e32"); 15145f757f3fSDimitry Andric def Gen.Suffix#"_alias" : MnemonicAlias<ps.Mnemonic, asmName>, Requires<[Gen.AssemblerPredicate]>; 15155f757f3fSDimitry Andric} 15165f757f3fSDimitry Andric 15175f757f3fSDimitry Andricmulticlass VOP2_Real_NO_DPP_with_alias<GFXGen Gen, bits<6> op, string alias> { 15185f757f3fSDimitry Andric defm NAME : VOP2_Real_e32<Gen, op>, 15195f757f3fSDimitry Andric VOP2_Real_e64<Gen, op>; 15205f757f3fSDimitry Andric def Gen.Suffix#"_alias" : MnemonicAlias<alias, NAME>, Requires<[Gen.AssemblerPredicate]>; 15215f757f3fSDimitry Andric} 15225f757f3fSDimitry Andric 15235f757f3fSDimitry Andric//===----------------------------------------------------------------------===// 15245f757f3fSDimitry Andric// GFX12. 15255f757f3fSDimitry Andric//===----------------------------------------------------------------------===// 15265f757f3fSDimitry Andric 15275f757f3fSDimitry Andricmulticlass VOP2be_Real_gfx12<bits<6> op, string opName, string asmName> : 15285f757f3fSDimitry Andric VOP2be_Real<GFX12Gen, op, opName, asmName>; 15295f757f3fSDimitry Andric 15305f757f3fSDimitry Andric// Only for CNDMASK 15315f757f3fSDimitry Andricmulticlass VOP2e_Real_gfx12<bits<6> op, string opName, string asmName> : 15325f757f3fSDimitry Andric VOP2e_Real<GFX12Gen, op, opName, asmName>; 15335f757f3fSDimitry Andric 15345f757f3fSDimitry Andricmulticlass VOP2_Real_FULL_with_name_gfx12<bits<6> op, string opName, 15355f757f3fSDimitry Andric string asmName> : 15365f757f3fSDimitry Andric VOP2_Real_FULL_with_name<GFX12Gen, op, opName, asmName>; 15375f757f3fSDimitry Andric 15385f757f3fSDimitry Andricmulticlass VOP2_Real_FULL_t16_with_name_gfx12<bits<6> op, string opName, 15395f757f3fSDimitry Andric string asmName, string alias> { 15405f757f3fSDimitry Andric defm NAME : VOP2_Real_FULL_with_name<GFX12Gen, op, opName, asmName>; 15415f757f3fSDimitry Andric def _gfx12_2nd_alias : MnemonicAlias<alias, asmName>, Requires<[isGFX12Only]>; 15425f757f3fSDimitry Andric} 15435f757f3fSDimitry Andric 15445f757f3fSDimitry Andricmulticlass VOP2_Real_NO_DPP_with_name_gfx12<bits<6> op, string opName, 15455f757f3fSDimitry Andric string asmName> : 15465f757f3fSDimitry Andric VOP2_Real_NO_DPP_with_name<GFX12Gen, op, opName, asmName>; 15475f757f3fSDimitry Andric 15485f757f3fSDimitry Andricmulticlass VOP2_Real_NO_DPP_with_alias_gfx12<bits<6> op, string alias> : 15495f757f3fSDimitry Andric VOP2_Real_NO_DPP_with_alias<GFX12Gen, op, alias>; 15505f757f3fSDimitry Andric 15515f757f3fSDimitry Andricdefm V_ADD_F64 : VOP2_Real_NO_DPP_with_name_gfx12<0x002, "V_ADD_F64_pseudo", "v_add_f64">; 15525f757f3fSDimitry Andricdefm V_MUL_F64 : VOP2_Real_NO_DPP_with_name_gfx12<0x006, "V_MUL_F64_pseudo", "v_mul_f64">; 15535f757f3fSDimitry Andricdefm V_LSHLREV_B64 : VOP2_Real_NO_DPP_with_name_gfx12<0x01f, "V_LSHLREV_B64_pseudo", "v_lshlrev_b64">; 15545f757f3fSDimitry Andricdefm V_MIN_NUM_F64 : VOP2_Real_NO_DPP_with_alias_gfx12<0x00d, "v_min_f64">; 15555f757f3fSDimitry Andricdefm V_MAX_NUM_F64 : VOP2_Real_NO_DPP_with_alias_gfx12<0x00e, "v_max_f64">; 15565f757f3fSDimitry Andric 15575f757f3fSDimitry Andricdefm V_CNDMASK_B32 : VOP2e_Real_gfx12<0x001, "V_CNDMASK_B32", "v_cndmask_b32">; 15585f757f3fSDimitry Andricdefm V_ADD_CO_CI_U32 : 15595f757f3fSDimitry Andric VOP2be_Real_gfx12<0x020, "V_ADDC_U32", "v_add_co_ci_u32">; 15605f757f3fSDimitry Andricdefm V_SUB_CO_CI_U32 : 15615f757f3fSDimitry Andric VOP2be_Real_gfx12<0x021, "V_SUBB_U32", "v_sub_co_ci_u32">; 15625f757f3fSDimitry Andricdefm V_SUBREV_CO_CI_U32 : 15635f757f3fSDimitry Andric VOP2be_Real_gfx12<0x022, "V_SUBBREV_U32", "v_subrev_co_ci_u32">; 15645f757f3fSDimitry Andric 15655f757f3fSDimitry Andricdefm V_MIN_NUM_F32 : VOP2_Real_FULL_with_name_gfx12<0x015, "V_MIN_F32", "v_min_num_f32">; 15665f757f3fSDimitry Andricdefm V_MAX_NUM_F32 : VOP2_Real_FULL_with_name_gfx12<0x016, "V_MAX_F32", "v_max_num_f32">; 15675f757f3fSDimitry Andricdefm V_MIN_NUM_F16 : VOP2_Real_FULL_t16_with_name_gfx12<0x030, "V_MIN_F16_t16", "v_min_num_f16", "v_min_f16">; 15685f757f3fSDimitry Andricdefm V_MIN_NUM_F16_fake16 : VOP2_Real_FULL_t16_with_name_gfx12<0x030, "V_MIN_F16_fake16", "v_min_num_f16", "v_min_f16">; 15695f757f3fSDimitry Andricdefm V_MAX_NUM_F16 : VOP2_Real_FULL_t16_with_name_gfx12<0x031, "V_MAX_F16_t16", "v_max_num_f16", "v_max_f16">; 15705f757f3fSDimitry Andricdefm V_MAX_NUM_F16_fake16 : VOP2_Real_FULL_t16_with_name_gfx12<0x031, "V_MAX_F16_fake16", "v_max_num_f16", "v_max_f16">; 15715f757f3fSDimitry Andric 15725f757f3fSDimitry Andriclet SubtargetPredicate = isGFX12Plus in { 15735f757f3fSDimitry Andric defm : VOP2eInstAliases<V_CNDMASK_B32_e32, V_CNDMASK_B32_e32_gfx12>; 15745f757f3fSDimitry Andric 15755f757f3fSDimitry Andric defm : VOP2bInstAliases< 15765f757f3fSDimitry Andric V_ADDC_U32_e32, V_ADD_CO_CI_U32_e32_gfx12, "v_add_co_ci_u32">; 15775f757f3fSDimitry Andric defm : VOP2bInstAliases< 15785f757f3fSDimitry Andric V_SUBB_U32_e32, V_SUB_CO_CI_U32_e32_gfx12, "v_sub_co_ci_u32">; 15795f757f3fSDimitry Andric defm : VOP2bInstAliases< 15805f757f3fSDimitry Andric V_SUBBREV_U32_e32, V_SUBREV_CO_CI_U32_e32_gfx12, "v_subrev_co_ci_u32">; 15815f757f3fSDimitry Andric} // End SubtargetPredicate = isGFX12Plus 15825f757f3fSDimitry Andric 15835f757f3fSDimitry Andric//===----------------------------------------------------------------------===// 15845f757f3fSDimitry Andric// GFX11. 15855f757f3fSDimitry Andric//===----------------------------------------------------------------------===// 15865f757f3fSDimitry Andric 158781ad6265SDimitry Andricmulticlass VOP2be_Real_gfx11<bits<6> op, string opName, string asmName> : 15885f757f3fSDimitry Andric VOP2be_Real<GFX11Gen, op, opName, asmName>; 158981ad6265SDimitry Andric 159081ad6265SDimitry Andric// Only for CNDMASK 159181ad6265SDimitry Andricmulticlass VOP2e_Real_gfx11<bits<6> op, string opName, string asmName> : 15925f757f3fSDimitry Andric VOP2e_Real<GFX11Gen, op, opName, asmName>; 159381ad6265SDimitry Andric 159481ad6265SDimitry Andricmulticlass VOP2_Real_NO_VOP3_with_name_gfx11<bits<6> op, string opName, 1595bdd1243dSDimitry Andric string asmName, bit isSingle = 0> { 15965f757f3fSDimitry Andric defm NAME : VOP2_Real_e32_with_name<GFX11Gen, op, opName, asmName, isSingle>, 15975f757f3fSDimitry Andric VOP2_Real_dpp_with_name<GFX11Gen, op, opName, asmName>, 15985f757f3fSDimitry Andric VOP2_Real_dpp8_with_name<GFX11Gen, op, opName, asmName>; 1599bdd1243dSDimitry Andric defvar ps = !cast<VOP2_Pseudo>(opName#"_e32"); 16005f757f3fSDimitry Andric def _gfx11_alias : MnemonicAlias<ps.Mnemonic, asmName>, Requires<[isGFX11Only]>; 1601bdd1243dSDimitry Andric} 160281ad6265SDimitry Andric 160381ad6265SDimitry Andricmulticlass VOP2_Real_NO_DPP_with_name_gfx11<bits<6> op, string opName, 16045f757f3fSDimitry Andric string asmName> : 16055f757f3fSDimitry Andric VOP2_Real_NO_DPP_with_name<GFX11Gen, op, opName, asmName>; 16065f757f3fSDimitry Andric 16075f757f3fSDimitry Andricmulticlass VOP2_Real_FULL_gfx11_gfx12<bits<6> op> : 16085f757f3fSDimitry Andric VOP2_Real_FULL<GFX11Gen, op>, VOP2_Real_FULL<GFX12Gen, op>; 16095f757f3fSDimitry Andric 16105f757f3fSDimitry Andricmulticlass VOP2_Real_FULL_with_name_gfx11_gfx12<bits<6> op, string opName, 16115f757f3fSDimitry Andric string asmName> : 16125f757f3fSDimitry Andric VOP2_Real_FULL_with_name<GFX11Gen, op, opName, asmName>, 16135f757f3fSDimitry Andric VOP2_Real_FULL_with_name<GFX12Gen, op, opName, asmName>; 16145f757f3fSDimitry Andric 16155f757f3fSDimitry Andricmulticlass VOP2_Real_e32_gfx11_gfx12<bits<6> op> : 16165f757f3fSDimitry Andric VOP2Only_Real<GFX11Gen, op>, VOP2Only_Real<GFX12Gen, op>; 16175f757f3fSDimitry Andric 16185f757f3fSDimitry Andricmulticlass VOP3Only_Realtriple_gfx11_gfx12<bits<10> op> : 16195f757f3fSDimitry Andric VOP3Only_Realtriple<GFX11Gen, op>, VOP3Only_Realtriple<GFX12Gen, op>; 16205f757f3fSDimitry Andric 16215f757f3fSDimitry Andricmulticlass VOP3Only_Realtriple_t16_gfx11_gfx12<bits<10> op, string asmName> : 16225f757f3fSDimitry Andric VOP3Only_Realtriple_t16<GFX11Gen, op, asmName>, 16235f757f3fSDimitry Andric VOP3Only_Realtriple_t16<GFX12Gen, op, asmName>; 16245f757f3fSDimitry Andric 16255f757f3fSDimitry Andricmulticlass VOP3beOnly_Realtriple_gfx11_gfx12<bits<10> op> : 16265f757f3fSDimitry Andric VOP3beOnly_Realtriple<GFX11Gen, op>, VOP3beOnly_Realtriple<GFX12Gen, op>; 16275f757f3fSDimitry Andric 16285f757f3fSDimitry Andricmulticlass VOP2Only_Real_MADK_with_name_gfx11_gfx12<bits<6> op, string asmName, 16295f757f3fSDimitry Andric string opName = NAME> : 16305f757f3fSDimitry Andric VOP2Only_Real_MADK_with_name<GFX11Gen, op, asmName, opName>, 16315f757f3fSDimitry Andric VOP2Only_Real_MADK_with_name<GFX12Gen, op, asmName, opName>; 16325f757f3fSDimitry Andric 16335f757f3fSDimitry Andricmulticlass VOP2_Real_FULL_t16_gfx11<bits<6> op, string asmName, 16345f757f3fSDimitry Andric string opName = NAME> : 16355f757f3fSDimitry Andric VOP2_Real_FULL_with_name<GFX11Gen, op, opName, asmName>; 16365f757f3fSDimitry Andric 16375f757f3fSDimitry Andricmulticlass VOP2_Real_FULL_t16_gfx11_gfx12<bits<6> op, string asmName, 16385f757f3fSDimitry Andric string opName = NAME> : 16395f757f3fSDimitry Andric VOP2_Real_FULL_with_name_gfx11_gfx12<op, opName, asmName>; 16405f757f3fSDimitry Andric 16415f757f3fSDimitry Andricmulticlass VOP2_Real_FULL_gfx11<bits<6> op> : 16425f757f3fSDimitry Andric VOP2_Real_FULL<GFX11Gen, op>; 164381ad6265SDimitry Andric 164481ad6265SDimitry Andricdefm V_CNDMASK_B32 : VOP2e_Real_gfx11<0x001, "V_CNDMASK_B32", 164581ad6265SDimitry Andric "v_cndmask_b32">; 164681ad6265SDimitry Andricdefm V_DOT2ACC_F32_F16 : VOP2_Real_NO_VOP3_with_name_gfx11<0x002, 164781ad6265SDimitry Andric "V_DOT2C_F32_F16", "v_dot2acc_f32_f16", 1>; 164881ad6265SDimitry Andricdefm V_FMAC_DX9_ZERO_F32 : VOP2_Real_NO_DPP_with_name_gfx11<0x006, 164981ad6265SDimitry Andric "V_FMAC_LEGACY_F32", "v_fmac_dx9_zero_f32">; 16505f757f3fSDimitry Andricdefm V_MUL_DX9_ZERO_F32 : VOP2_Real_FULL_with_name_gfx11_gfx12<0x007, 165181ad6265SDimitry Andric "V_MUL_LEGACY_F32", "v_mul_dx9_zero_f32">; 16525f757f3fSDimitry Andricdefm V_LSHLREV_B32 : VOP2_Real_FULL_gfx11_gfx12<0x018>; 16535f757f3fSDimitry Andricdefm V_LSHRREV_B32 : VOP2_Real_FULL_gfx11_gfx12<0x019>; 16545f757f3fSDimitry Andricdefm V_ASHRREV_I32 : VOP2_Real_FULL_gfx11_gfx12<0x01a>; 165581ad6265SDimitry Andricdefm V_ADD_CO_CI_U32 : 165681ad6265SDimitry Andric VOP2be_Real_gfx11<0x020, "V_ADDC_U32", "v_add_co_ci_u32">; 165781ad6265SDimitry Andricdefm V_SUB_CO_CI_U32 : 165881ad6265SDimitry Andric VOP2be_Real_gfx11<0x021, "V_SUBB_U32", "v_sub_co_ci_u32">; 165981ad6265SDimitry Andricdefm V_SUBREV_CO_CI_U32 : 166081ad6265SDimitry Andric VOP2be_Real_gfx11<0x022, "V_SUBBREV_U32", "v_subrev_co_ci_u32">; 166181ad6265SDimitry Andric 16625f757f3fSDimitry Andricdefm V_CVT_PK_RTZ_F16_F32 : VOP2_Real_FULL_with_name_gfx11_gfx12<0x02f, 166381ad6265SDimitry Andric "V_CVT_PKRTZ_F16_F32", "v_cvt_pk_rtz_f16_f32">; 16645f757f3fSDimitry Andricdefm V_PK_FMAC_F16 : VOP2_Real_e32_gfx11_gfx12<0x03c>; 166581ad6265SDimitry Andric 16665f757f3fSDimitry Andricdefm V_ADD_F16_t16 : VOP2_Real_FULL_t16_gfx11_gfx12<0x032, "v_add_f16">; 16675f757f3fSDimitry Andricdefm V_ADD_F16_fake16 : VOP2_Real_FULL_t16_gfx11_gfx12<0x032, "v_add_f16">; 16685f757f3fSDimitry Andricdefm V_SUB_F16_t16 : VOP2_Real_FULL_t16_gfx11_gfx12<0x033, "v_sub_f16">; 16695f757f3fSDimitry Andricdefm V_SUB_F16_fake16 : VOP2_Real_FULL_t16_gfx11_gfx12<0x033, "v_sub_f16">; 16705f757f3fSDimitry Andricdefm V_SUBREV_F16_t16 : VOP2_Real_FULL_t16_gfx11_gfx12<0x034, "v_subrev_f16">; 16715f757f3fSDimitry Andricdefm V_SUBREV_F16_fake16 : VOP2_Real_FULL_t16_gfx11_gfx12<0x034, "v_subrev_f16">; 16725f757f3fSDimitry Andricdefm V_MUL_F16_t16 : VOP2_Real_FULL_t16_gfx11_gfx12<0x035, "v_mul_f16">; 16735f757f3fSDimitry Andricdefm V_MUL_F16_fake16 : VOP2_Real_FULL_t16_gfx11_gfx12<0x035, "v_mul_f16">; 16745f757f3fSDimitry Andricdefm V_FMAC_F16_t16 : VOP2_Real_FULL_t16_gfx11_gfx12<0x036, "v_fmac_f16">; 16755f757f3fSDimitry Andricdefm V_LDEXP_F16_t16 : VOP2_Real_FULL_t16_gfx11_gfx12<0x03b, "v_ldexp_f16">; 1676bdd1243dSDimitry Andricdefm V_MAX_F16_t16 : VOP2_Real_FULL_t16_gfx11<0x039, "v_max_f16">; 16775f757f3fSDimitry Andricdefm V_MAX_F16_fake16 : VOP2_Real_FULL_t16_gfx11<0x039, "v_max_f16">; 1678bdd1243dSDimitry Andricdefm V_MIN_F16_t16 : VOP2_Real_FULL_t16_gfx11<0x03a, "v_min_f16">; 16795f757f3fSDimitry Andricdefm V_MIN_F16_fake16 : VOP2_Real_FULL_t16_gfx11<0x03a, "v_min_f16">; 16805f757f3fSDimitry Andricdefm V_FMAMK_F16_t16 : VOP2Only_Real_MADK_with_name_gfx11_gfx12<0x037, "v_fmamk_f16">; 16815f757f3fSDimitry Andricdefm V_FMAAK_F16_t16 : VOP2Only_Real_MADK_with_name_gfx11_gfx12<0x038, "v_fmaak_f16">; 1682bdd1243dSDimitry Andric 168381ad6265SDimitry Andric// VOP3 only. 16845f757f3fSDimitry Andricdefm V_CNDMASK_B16 : VOP3Only_Realtriple_gfx11_gfx12<0x25d>; 16855f757f3fSDimitry Andricdefm V_LDEXP_F32 : VOP3Only_Realtriple_gfx11_gfx12<0x31c>; 16865f757f3fSDimitry Andricdefm V_BFM_B32 : VOP3Only_Realtriple_gfx11_gfx12<0x31d>; 16875f757f3fSDimitry Andricdefm V_BCNT_U32_B32 : VOP3Only_Realtriple_gfx11_gfx12<0x31e>; 16885f757f3fSDimitry Andricdefm V_MBCNT_LO_U32_B32 : VOP3Only_Realtriple_gfx11_gfx12<0x31f>; 16895f757f3fSDimitry Andricdefm V_MBCNT_HI_U32_B32 : VOP3Only_Realtriple_gfx11_gfx12<0x320>; 16905f757f3fSDimitry Andricdefm V_CVT_PK_NORM_I16_F32 : VOP3Only_Realtriple_with_name_gfx11_gfx12<0x321, "V_CVT_PKNORM_I16_F32", "v_cvt_pk_norm_i16_f32">; 16915f757f3fSDimitry Andricdefm V_CVT_PK_NORM_U16_F32 : VOP3Only_Realtriple_with_name_gfx11_gfx12<0x322, "V_CVT_PKNORM_U16_F32", "v_cvt_pk_norm_u16_f32">; 16925f757f3fSDimitry Andricdefm V_CVT_PK_U16_U32 : VOP3Only_Realtriple_gfx11_gfx12<0x323>; 16935f757f3fSDimitry Andricdefm V_CVT_PK_I16_I32 : VOP3Only_Realtriple_gfx11_gfx12<0x324>; 16945f757f3fSDimitry Andricdefm V_ADD_CO_U32 : VOP3beOnly_Realtriple_gfx11_gfx12<0x300>; 16955f757f3fSDimitry Andricdefm V_SUB_CO_U32 : VOP3beOnly_Realtriple_gfx11_gfx12<0x301>; 16965f757f3fSDimitry Andricdefm V_SUBREV_CO_U32 : VOP3beOnly_Realtriple_gfx11_gfx12<0x302>; 169781ad6265SDimitry Andric 16985f757f3fSDimitry Andriclet SubtargetPredicate = isGFX11Only in { 169981ad6265SDimitry Andric defm : VOP2eInstAliases<V_CNDMASK_B32_e32, V_CNDMASK_B32_e32_gfx11>; 170081ad6265SDimitry Andric 170181ad6265SDimitry Andric defm : VOP2bInstAliases< 170281ad6265SDimitry Andric V_ADDC_U32_e32, V_ADD_CO_CI_U32_e32_gfx11, "v_add_co_ci_u32">; 170381ad6265SDimitry Andric defm : VOP2bInstAliases< 170481ad6265SDimitry Andric V_SUBB_U32_e32, V_SUB_CO_CI_U32_e32_gfx11, "v_sub_co_ci_u32">; 170581ad6265SDimitry Andric defm : VOP2bInstAliases< 170681ad6265SDimitry Andric V_SUBBREV_U32_e32, V_SUBREV_CO_CI_U32_e32_gfx11, "v_subrev_co_ci_u32">; 17075f757f3fSDimitry Andric} // End SubtargetPredicate = isGFX11Only 170881ad6265SDimitry Andric 170981ad6265SDimitry Andric//===----------------------------------------------------------------------===// 17100b57cec5SDimitry Andric// GFX10. 17110b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 17120b57cec5SDimitry Andric 171381ad6265SDimitry Andriclet AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10" in { 17140b57cec5SDimitry Andric //===------------------------------- VOP2 -------------------------------===// 17150b57cec5SDimitry Andric multiclass VOP2Only_Real_MADK_gfx10<bits<6> op> { 17160b57cec5SDimitry Andric def _gfx10 : 17170b57cec5SDimitry Andric VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.GFX10>, 17180b57cec5SDimitry Andric VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>; 17190b57cec5SDimitry Andric } 17200b57cec5SDimitry Andric multiclass VOP2Only_Real_MADK_gfx10_with_name<bits<6> op, string opName, 17210b57cec5SDimitry Andric string asmName> { 17220b57cec5SDimitry Andric def _gfx10 : 17230b57cec5SDimitry Andric VOP2_Real<!cast<VOP2_Pseudo>(opName), SIEncodingFamily.GFX10>, 17240b57cec5SDimitry Andric VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(opName).Pfl> { 17250b57cec5SDimitry Andric VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName); 17260b57cec5SDimitry Andric let AsmString = asmName # ps.AsmOperands; 17270b57cec5SDimitry Andric } 17280b57cec5SDimitry Andric } 17290b57cec5SDimitry Andric multiclass VOP2_Real_e32_gfx10<bits<6> op> { 17300b57cec5SDimitry Andric def _e32_gfx10 : 17310b57cec5SDimitry Andric VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.GFX10>, 17320b57cec5SDimitry Andric VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>; 17330b57cec5SDimitry Andric } 17340b57cec5SDimitry Andric multiclass VOP2_Real_e64_gfx10<bits<6> op> { 17350b57cec5SDimitry Andric def _e64_gfx10 : 17360b57cec5SDimitry Andric VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>, 17370b57cec5SDimitry Andric VOP3e_gfx10<{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 17380b57cec5SDimitry Andric } 17390b57cec5SDimitry Andric multiclass VOP2_Real_sdwa_gfx10<bits<6> op> { 174006c3fb27SDimitry Andric if !cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9 then 17410b57cec5SDimitry Andric def _sdwa_gfx10 : 17420b57cec5SDimitry Andric VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>, 17430b57cec5SDimitry Andric VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl> { 17440b57cec5SDimitry Andric let DecoderNamespace = "SDWA10"; 17450b57cec5SDimitry Andric } 17460b57cec5SDimitry Andric } 17470b57cec5SDimitry Andric multiclass VOP2_Real_dpp_gfx10<bits<6> op> { 174806c3fb27SDimitry Andric if !cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExt32BitDPP then 174981ad6265SDimitry Andric def _dpp_gfx10 : VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.GFX10> { 17500b57cec5SDimitry Andric let DecoderNamespace = "SDWA10"; 17510b57cec5SDimitry Andric } 17520b57cec5SDimitry Andric } 17530b57cec5SDimitry Andric multiclass VOP2_Real_dpp8_gfx10<bits<6> op> { 175406c3fb27SDimitry Andric if !cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExt32BitDPP then 17550b57cec5SDimitry Andric def _dpp8_gfx10 : VOP2_DPP8<op, !cast<VOP2_Pseudo>(NAME#"_e32")> { 17560b57cec5SDimitry Andric let DecoderNamespace = "DPP8"; 17570b57cec5SDimitry Andric } 17580b57cec5SDimitry Andric } 17590b57cec5SDimitry Andric 17600b57cec5SDimitry Andric //===------------------------- VOP2 (with name) -------------------------===// 17610b57cec5SDimitry Andric multiclass VOP2_Real_e32_gfx10_with_name<bits<6> op, string opName, 17620b57cec5SDimitry Andric string asmName> { 17630b57cec5SDimitry Andric def _e32_gfx10 : 17640b57cec5SDimitry Andric VOP2_Real<!cast<VOP2_Pseudo>(opName#"_e32"), SIEncodingFamily.GFX10>, 17650b57cec5SDimitry Andric VOP2e<op{5-0}, !cast<VOP2_Pseudo>(opName#"_e32").Pfl> { 17660b57cec5SDimitry Andric VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName#"_e32"); 17670b57cec5SDimitry Andric let AsmString = asmName # ps.AsmOperands; 17680b57cec5SDimitry Andric } 17690b57cec5SDimitry Andric } 17700b57cec5SDimitry Andric multiclass VOP2_Real_e64_gfx10_with_name<bits<6> op, string opName, 17710b57cec5SDimitry Andric string asmName> { 17720b57cec5SDimitry Andric def _e64_gfx10 : 17730b57cec5SDimitry Andric VOP3_Real<!cast<VOP3_Pseudo>(opName#"_e64"), SIEncodingFamily.GFX10>, 17740b57cec5SDimitry Andric VOP3e_gfx10<{0, 1, 0, 0, op{5-0}}, 17750b57cec5SDimitry Andric !cast<VOP3_Pseudo>(opName#"_e64").Pfl> { 17760b57cec5SDimitry Andric VOP3_Pseudo ps = !cast<VOP3_Pseudo>(opName#"_e64"); 17770b57cec5SDimitry Andric let AsmString = asmName # ps.AsmOperands; 17780b57cec5SDimitry Andric } 17790b57cec5SDimitry Andric } 17800b57cec5SDimitry Andric let DecoderNamespace = "SDWA10" in { 17810b57cec5SDimitry Andric multiclass VOP2_Real_sdwa_gfx10_with_name<bits<6> op, string opName, 17820b57cec5SDimitry Andric string asmName> { 178306c3fb27SDimitry Andric if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtSDWA9 then 17840b57cec5SDimitry Andric def _sdwa_gfx10 : 17850b57cec5SDimitry Andric VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>, 17860b57cec5SDimitry Andric VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> { 17870b57cec5SDimitry Andric VOP2_SDWA_Pseudo ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa"); 17880b57cec5SDimitry Andric let AsmString = asmName # ps.AsmOperands; 17890b57cec5SDimitry Andric } 17900b57cec5SDimitry Andric } 17910b57cec5SDimitry Andric multiclass VOP2_Real_dpp_gfx10_with_name<bits<6> op, string opName, 17920b57cec5SDimitry Andric string asmName> { 179306c3fb27SDimitry Andric if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExt32BitDPP then 179481ad6265SDimitry Andric def _dpp_gfx10 : VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), SIEncodingFamily.GFX10> { 17950b57cec5SDimitry Andric VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName#"_e32"); 17960b57cec5SDimitry Andric let AsmString = asmName # ps.Pfl.AsmDPP16; 17970b57cec5SDimitry Andric } 17980b57cec5SDimitry Andric } 17990b57cec5SDimitry Andric multiclass VOP2_Real_dpp8_gfx10_with_name<bits<6> op, string opName, 18000b57cec5SDimitry Andric string asmName> { 180106c3fb27SDimitry Andric if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExt32BitDPP then 18020b57cec5SDimitry Andric def _dpp8_gfx10 : VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32")> { 18030b57cec5SDimitry Andric VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName#"_e32"); 18040b57cec5SDimitry Andric let AsmString = asmName # ps.Pfl.AsmDPP8; 18050b57cec5SDimitry Andric let DecoderNamespace = "DPP8"; 18060b57cec5SDimitry Andric } 18070b57cec5SDimitry Andric } 18080b57cec5SDimitry Andric } // End DecoderNamespace = "SDWA10" 18090b57cec5SDimitry Andric 18100b57cec5SDimitry Andric //===------------------------------ VOP2be ------------------------------===// 18118bcb0991SDimitry Andric multiclass VOP2be_Real_e32_gfx10<bits<6> op, string opName, string asmName> { 18120b57cec5SDimitry Andric def _e32_gfx10 : 18130b57cec5SDimitry Andric VOP2_Real<!cast<VOP2_Pseudo>(opName#"_e32"), SIEncodingFamily.GFX10>, 18140b57cec5SDimitry Andric VOP2e<op{5-0}, !cast<VOP2_Pseudo>(opName#"_e32").Pfl> { 18150b57cec5SDimitry Andric VOP2_Pseudo Ps = !cast<VOP2_Pseudo>(opName#"_e32"); 18160b57cec5SDimitry Andric let AsmString = asmName # !subst(", vcc", "", Ps.AsmOperands); 18170b57cec5SDimitry Andric } 18188bcb0991SDimitry Andric } 18198bcb0991SDimitry Andric multiclass VOP2be_Real_e64_gfx10<bits<6> op, string opName, string asmName> { 18200b57cec5SDimitry Andric def _e64_gfx10 : 18210b57cec5SDimitry Andric VOP3_Real<!cast<VOP3_Pseudo>(opName#"_e64"), SIEncodingFamily.GFX10>, 18220b57cec5SDimitry Andric VOP3be_gfx10<{0, 1, 0, 0, op{5-0}}, 18230b57cec5SDimitry Andric !cast<VOP3_Pseudo>(opName#"_e64").Pfl> { 18240b57cec5SDimitry Andric VOP3_Pseudo Ps = !cast<VOP3_Pseudo>(opName#"_e64"); 18250b57cec5SDimitry Andric let AsmString = asmName # Ps.AsmOperands; 18260b57cec5SDimitry Andric } 18278bcb0991SDimitry Andric } 18288bcb0991SDimitry Andric multiclass VOP2be_Real_sdwa_gfx10<bits<6> op, string opName, string asmName> { 182906c3fb27SDimitry Andric if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtSDWA9 then 18300b57cec5SDimitry Andric def _sdwa_gfx10 : 18310b57cec5SDimitry Andric VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>, 18320b57cec5SDimitry Andric VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> { 18330b57cec5SDimitry Andric VOP2_SDWA_Pseudo Ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa"); 18340b57cec5SDimitry Andric let AsmString = asmName # !subst(", vcc", "", Ps.AsmOperands); 18350b57cec5SDimitry Andric let DecoderNamespace = "SDWA10"; 18360b57cec5SDimitry Andric } 183706c3fb27SDimitry Andric if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtSDWA9 then 18380b57cec5SDimitry Andric def _sdwa_w32_gfx10 : 18390b57cec5SDimitry Andric Base_VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>, 18400b57cec5SDimitry Andric VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> { 18410b57cec5SDimitry Andric VOP2_SDWA_Pseudo Ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa"); 18420b57cec5SDimitry Andric let AsmString = asmName # !subst("vcc", "vcc_lo", Ps.AsmOperands); 18430b57cec5SDimitry Andric let isAsmParserOnly = 1; 18440b57cec5SDimitry Andric let DecoderNamespace = "SDWA10"; 18458bcb0991SDimitry Andric let WaveSizePredicate = isWave32; 18460b57cec5SDimitry Andric } 184706c3fb27SDimitry Andric if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtSDWA9 then 18480b57cec5SDimitry Andric def _sdwa_w64_gfx10 : 18490b57cec5SDimitry Andric Base_VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>, 18500b57cec5SDimitry Andric VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> { 18510b57cec5SDimitry Andric VOP2_SDWA_Pseudo Ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa"); 18520b57cec5SDimitry Andric let AsmString = asmName # Ps.AsmOperands; 18530b57cec5SDimitry Andric let isAsmParserOnly = 1; 18540b57cec5SDimitry Andric let DecoderNamespace = "SDWA10"; 18558bcb0991SDimitry Andric let WaveSizePredicate = isWave64; 18560b57cec5SDimitry Andric } 18578bcb0991SDimitry Andric } 18588bcb0991SDimitry Andric multiclass VOP2be_Real_dpp_gfx10<bits<6> op, string opName, string asmName> { 185906c3fb27SDimitry Andric if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExt32BitDPP then 18608bcb0991SDimitry Andric def _dpp_gfx10 : 186181ad6265SDimitry Andric VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), SIEncodingFamily.GFX10, asmName> { 18628bcb0991SDimitry Andric string AsmDPP = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP16; 18638bcb0991SDimitry Andric let AsmString = asmName # !subst(", vcc", "", AsmDPP); 18648bcb0991SDimitry Andric let DecoderNamespace = "SDWA10"; 18658bcb0991SDimitry Andric } 186606c3fb27SDimitry Andric if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExt32BitDPP then 18678bcb0991SDimitry Andric def _dpp_w32_gfx10 : 18688bcb0991SDimitry Andric Base_VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), asmName> { 18698bcb0991SDimitry Andric string AsmDPP = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP16; 18708bcb0991SDimitry Andric let AsmString = asmName # !subst("vcc", "vcc_lo", AsmDPP); 18718bcb0991SDimitry Andric let isAsmParserOnly = 1; 18728bcb0991SDimitry Andric let WaveSizePredicate = isWave32; 18738bcb0991SDimitry Andric } 187406c3fb27SDimitry Andric if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExt32BitDPP then 18750b57cec5SDimitry Andric def _dpp_w64_gfx10 : 18768bcb0991SDimitry Andric Base_VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), asmName> { 18770b57cec5SDimitry Andric string AsmDPP = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP16; 18780b57cec5SDimitry Andric let AsmString = asmName # AsmDPP; 18790b57cec5SDimitry Andric let isAsmParserOnly = 1; 18808bcb0991SDimitry Andric let WaveSizePredicate = isWave64; 18810b57cec5SDimitry Andric } 18828bcb0991SDimitry Andric } 18838bcb0991SDimitry Andric multiclass VOP2be_Real_dpp8_gfx10<bits<6> op, string opName, string asmName> { 188406c3fb27SDimitry Andric if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExt32BitDPP then 18858bcb0991SDimitry Andric def _dpp8_gfx10 : 1886349cc55cSDimitry Andric VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32")> { 18878bcb0991SDimitry Andric string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8; 18888bcb0991SDimitry Andric let AsmString = asmName # !subst(", vcc", "", AsmDPP8); 18898bcb0991SDimitry Andric let DecoderNamespace = "DPP8"; 18908bcb0991SDimitry Andric } 189106c3fb27SDimitry Andric if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExt32BitDPP then 18928bcb0991SDimitry Andric def _dpp8_w32_gfx10 : 1893349cc55cSDimitry Andric VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32")> { 18948bcb0991SDimitry Andric string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8; 18958bcb0991SDimitry Andric let AsmString = asmName # !subst("vcc", "vcc_lo", AsmDPP8); 18968bcb0991SDimitry Andric let isAsmParserOnly = 1; 18978bcb0991SDimitry Andric let WaveSizePredicate = isWave32; 18988bcb0991SDimitry Andric } 189906c3fb27SDimitry Andric if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExt32BitDPP then 19000b57cec5SDimitry Andric def _dpp8_w64_gfx10 : 1901349cc55cSDimitry Andric VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32")> { 19020b57cec5SDimitry Andric string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8; 19030b57cec5SDimitry Andric let AsmString = asmName # AsmDPP8; 19040b57cec5SDimitry Andric let isAsmParserOnly = 1; 19058bcb0991SDimitry Andric let WaveSizePredicate = isWave64; 19060b57cec5SDimitry Andric } 19070b57cec5SDimitry Andric } 19080b57cec5SDimitry Andric 19090b57cec5SDimitry Andric //===----------------------------- VOP3Only -----------------------------===// 19100b57cec5SDimitry Andric multiclass VOP3Only_Real_gfx10<bits<10> op> { 19110b57cec5SDimitry Andric def _e64_gfx10 : 19120b57cec5SDimitry Andric VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>, 1913fe6060f1SDimitry Andric VOP3e_gfx10<op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> { 1914fe6060f1SDimitry Andric let IsSingle = 1; 1915fe6060f1SDimitry Andric } 19160b57cec5SDimitry Andric } 19170b57cec5SDimitry Andric 19180b57cec5SDimitry Andric //===---------------------------- VOP3beOnly ----------------------------===// 1919e8d8bef9SDimitry Andric multiclass VOP3beOnly_Real_gfx10<bits<10> op> { 19200b57cec5SDimitry Andric def _e64_gfx10 : 1921e8d8bef9SDimitry Andric VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>, 1922fe6060f1SDimitry Andric VOP3be_gfx10<op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> { 1923fe6060f1SDimitry Andric let IsSingle = 1; 1924fe6060f1SDimitry Andric } 19250b57cec5SDimitry Andric } 192681ad6265SDimitry Andric} // End AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10" 192781ad6265SDimitry Andric 192881ad6265SDimitry Andricmulticlass VOP2Only_Real_MADK_gfx10_gfx11<bits<6> op> : 19295f757f3fSDimitry Andric VOP2Only_Real_MADK_gfx10<op>, VOP2Only_Real_MADK<GFX11Gen, op>; 19305f757f3fSDimitry Andric 19315f757f3fSDimitry Andricmulticlass VOP2Only_Real_MADK_gfx10_gfx11_gfx12<bits<6> op> : 19325f757f3fSDimitry Andric VOP2Only_Real_MADK_gfx10_gfx11<op>, VOP2Only_Real_MADK<GFX12Gen, op>; 19330b57cec5SDimitry Andric 19348bcb0991SDimitry Andricmulticlass VOP2be_Real_gfx10<bits<6> op, string opName, string asmName> : 19358bcb0991SDimitry Andric VOP2be_Real_e32_gfx10<op, opName, asmName>, 19368bcb0991SDimitry Andric VOP2be_Real_e64_gfx10<op, opName, asmName>, 19378bcb0991SDimitry Andric VOP2be_Real_sdwa_gfx10<op, opName, asmName>, 19388bcb0991SDimitry Andric VOP2be_Real_dpp_gfx10<op, opName, asmName>, 19398bcb0991SDimitry Andric VOP2be_Real_dpp8_gfx10<op, opName, asmName>; 19408bcb0991SDimitry Andric 19418bcb0991SDimitry Andricmulticlass VOP2e_Real_gfx10<bits<6> op, string opName, string asmName> : 19428bcb0991SDimitry Andric VOP2_Real_e32_gfx10<op>, 19438bcb0991SDimitry Andric VOP2_Real_e64_gfx10<op>, 19448bcb0991SDimitry Andric VOP2be_Real_sdwa_gfx10<op, opName, asmName>, 19458bcb0991SDimitry Andric VOP2be_Real_dpp_gfx10<op, opName, asmName>, 19468bcb0991SDimitry Andric VOP2be_Real_dpp8_gfx10<op, opName, asmName>; 19470b57cec5SDimitry Andric 19480b57cec5SDimitry Andricmulticlass VOP2_Real_gfx10<bits<6> op> : 19490b57cec5SDimitry Andric VOP2_Real_e32_gfx10<op>, VOP2_Real_e64_gfx10<op>, 19500b57cec5SDimitry Andric VOP2_Real_sdwa_gfx10<op>, VOP2_Real_dpp_gfx10<op>, VOP2_Real_dpp8_gfx10<op>; 19510b57cec5SDimitry Andric 195281ad6265SDimitry Andricmulticlass VOP2_Real_gfx10_gfx11<bits<6> op> : 19535f757f3fSDimitry Andric VOP2_Real_gfx10<op>, VOP2_Real_FULL<GFX11Gen, op>; 19545f757f3fSDimitry Andric 19555f757f3fSDimitry Andricmulticlass VOP2_Real_gfx10_gfx11_gfx12<bits<6> op> : 19565f757f3fSDimitry Andric VOP2_Real_gfx10_gfx11<op>, VOP2_Real_FULL<GFX12Gen, op>; 195781ad6265SDimitry Andric 195881ad6265SDimitry Andricmulticlass VOP2_Real_with_name_gfx10<bits<6> op, string opName, 19590b57cec5SDimitry Andric string asmName> : 19600b57cec5SDimitry Andric VOP2_Real_e32_gfx10_with_name<op, opName, asmName>, 19610b57cec5SDimitry Andric VOP2_Real_e64_gfx10_with_name<op, opName, asmName>, 19620b57cec5SDimitry Andric VOP2_Real_sdwa_gfx10_with_name<op, opName, asmName>, 19630b57cec5SDimitry Andric VOP2_Real_dpp_gfx10_with_name<op, opName, asmName>, 19640b57cec5SDimitry Andric VOP2_Real_dpp8_gfx10_with_name<op, opName, asmName>; 19650b57cec5SDimitry Andric 19665f757f3fSDimitry Andricmulticlass VOP2_Real_with_name_gfx10_gfx11_gfx12<bits<6> op, string opName, 196781ad6265SDimitry Andric string asmName> : 196881ad6265SDimitry Andric VOP2_Real_with_name_gfx10<op, opName, asmName>, 19695f757f3fSDimitry Andric VOP2_Real_FULL_with_name<GFX11Gen, op, opName, asmName>, 19705f757f3fSDimitry Andric VOP2_Real_FULL_with_name<GFX12Gen, op, opName, asmName>; 197181ad6265SDimitry Andric 1972e8d8bef9SDimitry Andric// NB: Same opcode as v_mac_legacy_f32 1973e8d8bef9SDimitry Andriclet DecoderNamespace = "GFX10_B" in 1974e8d8bef9SDimitry Andricdefm V_FMAC_LEGACY_F32 : VOP2_Real_gfx10<0x006>; 1975e8d8bef9SDimitry Andric 19765f757f3fSDimitry Andricdefm V_XNOR_B32 : VOP2_Real_gfx10_gfx11_gfx12<0x01e>; 19775f757f3fSDimitry Andricdefm V_FMAC_F32 : VOP2_Real_gfx10_gfx11_gfx12<0x02b>; 19785f757f3fSDimitry Andricdefm V_FMAMK_F32 : VOP2Only_Real_MADK_gfx10_gfx11_gfx12<0x02c>; 19795f757f3fSDimitry Andricdefm V_FMAAK_F32 : VOP2Only_Real_MADK_gfx10_gfx11_gfx12<0x02d>; 1980bdd1243dSDimitry Andricdefm V_ADD_F16 : VOP2_Real_gfx10<0x032>; 1981bdd1243dSDimitry Andricdefm V_SUB_F16 : VOP2_Real_gfx10<0x033>; 1982bdd1243dSDimitry Andricdefm V_SUBREV_F16 : VOP2_Real_gfx10<0x034>; 1983bdd1243dSDimitry Andricdefm V_MUL_F16 : VOP2_Real_gfx10<0x035>; 1984bdd1243dSDimitry Andricdefm V_FMAC_F16 : VOP2_Real_gfx10<0x036>; 1985bdd1243dSDimitry Andricdefm V_FMAMK_F16 : VOP2Only_Real_MADK_gfx10<0x037>; 1986bdd1243dSDimitry Andricdefm V_FMAAK_F16 : VOP2Only_Real_MADK_gfx10<0x038>; 1987bdd1243dSDimitry Andricdefm V_MAX_F16 : VOP2_Real_gfx10<0x039>; 1988bdd1243dSDimitry Andricdefm V_MIN_F16 : VOP2_Real_gfx10<0x03a>; 1989bdd1243dSDimitry Andricdefm V_LDEXP_F16 : VOP2_Real_gfx10<0x03b>; 1990fe6060f1SDimitry Andric 1991fe6060f1SDimitry Andriclet IsSingle = 1 in { 19920b57cec5SDimitry Andric defm V_PK_FMAC_F16 : VOP2_Real_e32_gfx10<0x03c>; 1993fe6060f1SDimitry Andric} 19940b57cec5SDimitry Andric 19950b57cec5SDimitry Andric// VOP2 no carry-in, carry-out. 19960b57cec5SDimitry Andricdefm V_ADD_NC_U32 : 19975f757f3fSDimitry Andric VOP2_Real_with_name_gfx10_gfx11_gfx12<0x025, "V_ADD_U32", "v_add_nc_u32">; 19980b57cec5SDimitry Andricdefm V_SUB_NC_U32 : 19995f757f3fSDimitry Andric VOP2_Real_with_name_gfx10_gfx11_gfx12<0x026, "V_SUB_U32", "v_sub_nc_u32">; 20000b57cec5SDimitry Andricdefm V_SUBREV_NC_U32 : 20015f757f3fSDimitry Andric VOP2_Real_with_name_gfx10_gfx11_gfx12<0x027, "V_SUBREV_U32", "v_subrev_nc_u32">; 20020b57cec5SDimitry Andric 20030b57cec5SDimitry Andric// VOP2 carry-in, carry-out. 20040b57cec5SDimitry Andricdefm V_ADD_CO_CI_U32 : 20050b57cec5SDimitry Andric VOP2be_Real_gfx10<0x028, "V_ADDC_U32", "v_add_co_ci_u32">; 20060b57cec5SDimitry Andricdefm V_SUB_CO_CI_U32 : 20070b57cec5SDimitry Andric VOP2be_Real_gfx10<0x029, "V_SUBB_U32", "v_sub_co_ci_u32">; 20080b57cec5SDimitry Andricdefm V_SUBREV_CO_CI_U32 : 20090b57cec5SDimitry Andric VOP2be_Real_gfx10<0x02a, "V_SUBBREV_U32", "v_subrev_co_ci_u32">; 20100b57cec5SDimitry Andric 20118bcb0991SDimitry Andricdefm V_CNDMASK_B32 : 20128bcb0991SDimitry Andric VOP2e_Real_gfx10<0x001, "V_CNDMASK_B32", "v_cndmask_b32">; 20138bcb0991SDimitry Andric 20140b57cec5SDimitry Andric// VOP3 only. 20150b57cec5SDimitry Andricdefm V_BFM_B32 : VOP3Only_Real_gfx10<0x363>; 20160b57cec5SDimitry Andricdefm V_BCNT_U32_B32 : VOP3Only_Real_gfx10<0x364>; 20170b57cec5SDimitry Andricdefm V_MBCNT_LO_U32_B32 : VOP3Only_Real_gfx10<0x365>; 20180b57cec5SDimitry Andricdefm V_MBCNT_HI_U32_B32 : VOP3Only_Real_gfx10<0x366>; 20190b57cec5SDimitry Andricdefm V_LDEXP_F32 : VOP3Only_Real_gfx10<0x362>; 20200b57cec5SDimitry Andricdefm V_CVT_PKNORM_I16_F32 : VOP3Only_Real_gfx10<0x368>; 20210b57cec5SDimitry Andricdefm V_CVT_PKNORM_U16_F32 : VOP3Only_Real_gfx10<0x369>; 20220b57cec5SDimitry Andricdefm V_CVT_PK_U16_U32 : VOP3Only_Real_gfx10<0x36a>; 20230b57cec5SDimitry Andricdefm V_CVT_PK_I16_I32 : VOP3Only_Real_gfx10<0x36b>; 20240b57cec5SDimitry Andric 2025e8d8bef9SDimitry Andric// VOP3 carry-out. 2026e8d8bef9SDimitry Andricdefm V_ADD_CO_U32 : VOP3beOnly_Real_gfx10<0x30f>; 2027e8d8bef9SDimitry Andricdefm V_SUB_CO_U32 : VOP3beOnly_Real_gfx10<0x310>; 2028e8d8bef9SDimitry Andricdefm V_SUBREV_CO_U32 : VOP3beOnly_Real_gfx10<0x319>; 20290b57cec5SDimitry Andric 203081ad6265SDimitry Andriclet SubtargetPredicate = isGFX10Only in { 20310b57cec5SDimitry Andric defm : VOP2eInstAliases<V_CNDMASK_B32_e32, V_CNDMASK_B32_e32_gfx10>; 20320b57cec5SDimitry Andric 20330b57cec5SDimitry Andric defm : VOP2bInstAliases< 20340b57cec5SDimitry Andric V_ADDC_U32_e32, V_ADD_CO_CI_U32_e32_gfx10, "v_add_co_ci_u32">; 20350b57cec5SDimitry Andric defm : VOP2bInstAliases< 20360b57cec5SDimitry Andric V_SUBB_U32_e32, V_SUB_CO_CI_U32_e32_gfx10, "v_sub_co_ci_u32">; 20370b57cec5SDimitry Andric defm : VOP2bInstAliases< 20380b57cec5SDimitry Andric V_SUBBREV_U32_e32, V_SUBREV_CO_CI_U32_e32_gfx10, "v_subrev_co_ci_u32">; 203981ad6265SDimitry Andric} // End SubtargetPredicate = isGFX10Only 20400b57cec5SDimitry Andric 20410b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 204281ad6265SDimitry Andric// GFX6, GFX7, GFX10, GFX11 20430b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 20440b57cec5SDimitry Andric 20450b57cec5SDimitry Andricclass VOP2_DPPe <bits<6> op, VOP2_DPP_Pseudo ps, VOPProfile P = ps.Pfl> : 20460b57cec5SDimitry Andric VOP_DPPe <P> { 20470b57cec5SDimitry Andric bits<8> vdst; 20480b57cec5SDimitry Andric bits<8> src1; 20490b57cec5SDimitry Andric let Inst{8-0} = 0xfa; //dpp 20500b57cec5SDimitry Andric let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, 0); 20510b57cec5SDimitry Andric let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0); 20520b57cec5SDimitry Andric let Inst{30-25} = op; 20530b57cec5SDimitry Andric let Inst{31} = 0x0; //encoding 20540b57cec5SDimitry Andric} 20550b57cec5SDimitry Andric 20560b57cec5SDimitry Andriclet AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" in { 2057e8d8bef9SDimitry Andric multiclass VOP2_Lane_Real_gfx6_gfx7<bits<6> op> { 20580b57cec5SDimitry Andric def _gfx6_gfx7 : 20590b57cec5SDimitry Andric VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.SI>, 20600b57cec5SDimitry Andric VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>; 20610b57cec5SDimitry Andric } 20620b57cec5SDimitry Andric multiclass VOP2Only_Real_MADK_gfx6_gfx7<bits<6> op> { 20630b57cec5SDimitry Andric def _gfx6_gfx7 : 20640b57cec5SDimitry Andric VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.SI>, 20650b57cec5SDimitry Andric VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>; 20660b57cec5SDimitry Andric } 2067fe6060f1SDimitry Andric multiclass VOP2_Real_e32_gfx6_gfx7<bits<6> op, string opName = NAME> { 20680b57cec5SDimitry Andric def _e32_gfx6_gfx7 : 2069fe6060f1SDimitry Andric VOP2_Real<!cast<VOP2_Pseudo>(opName#"_e32"), SIEncodingFamily.SI>, 2070fe6060f1SDimitry Andric VOP2e<op{5-0}, !cast<VOP2_Pseudo>(opName#"_e32").Pfl>; 20710b57cec5SDimitry Andric } 2072fe6060f1SDimitry Andric multiclass VOP2_Real_e64_gfx6_gfx7<bits<6> op, string opName = NAME> { 20730b57cec5SDimitry Andric def _e64_gfx6_gfx7 : 2074fe6060f1SDimitry Andric VOP3_Real<!cast<VOP3_Pseudo>(opName#"_e64"), SIEncodingFamily.SI>, 2075fe6060f1SDimitry Andric VOP3e_gfx6_gfx7<{1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(opName#"_e64").Pfl>; 20760b57cec5SDimitry Andric } 2077fe6060f1SDimitry Andric multiclass VOP2be_Real_e64_gfx6_gfx7<bits<6> op, string opName = NAME> { 20780b57cec5SDimitry Andric def _e64_gfx6_gfx7 : 2079fe6060f1SDimitry Andric VOP3_Real<!cast<VOP3_Pseudo>(opName#"_e64"), SIEncodingFamily.SI>, 2080fe6060f1SDimitry Andric VOP3be_gfx6_gfx7<{1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(opName#"_e64").Pfl>; 20810b57cec5SDimitry Andric } 20820b57cec5SDimitry Andric} // End AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" 20830b57cec5SDimitry Andric 20840b57cec5SDimitry Andricmulticlass VOP2Only_Real_MADK_gfx6_gfx7_gfx10<bits<6> op> : 20850b57cec5SDimitry Andric VOP2Only_Real_MADK_gfx6_gfx7<op>, VOP2Only_Real_MADK_gfx10<op>; 20860b57cec5SDimitry Andric 20870b57cec5SDimitry Andricmulticlass VOP2_Real_gfx6_gfx7<bits<6> op> : 20880b57cec5SDimitry Andric VOP2_Real_e32_gfx6_gfx7<op>, VOP2_Real_e64_gfx6_gfx7<op>; 20890b57cec5SDimitry Andric 20900b57cec5SDimitry Andricmulticlass VOP2_Real_gfx6_gfx7_gfx10<bits<6> op> : 20910b57cec5SDimitry Andric VOP2_Real_gfx6_gfx7<op>, VOP2_Real_gfx10<op>; 20920b57cec5SDimitry Andric 209381ad6265SDimitry Andricmulticlass VOP2_Real_gfx6_gfx7_gfx10_gfx11<bits<6> op> : 20945f757f3fSDimitry Andric VOP2_Real_gfx6_gfx7_gfx10<op>, VOP2_Real_FULL<GFX11Gen, op>; 20955f757f3fSDimitry Andric 20965f757f3fSDimitry Andricmulticlass VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<bits<6> op> : 20975f757f3fSDimitry Andric VOP2_Real_gfx6_gfx7_gfx10_gfx11<op>, VOP2_Real_FULL<GFX12Gen, op>; 209881ad6265SDimitry Andric 20990b57cec5SDimitry Andricmulticlass VOP2be_Real_gfx6_gfx7<bits<6> op> : 21000b57cec5SDimitry Andric VOP2_Real_e32_gfx6_gfx7<op>, VOP2be_Real_e64_gfx6_gfx7<op>; 21010b57cec5SDimitry Andric 2102e8d8bef9SDimitry Andricmulticlass VOP2be_Real_gfx6_gfx7_with_name<bits<6> op, 2103fe6060f1SDimitry Andric string opName, string asmName> { 2104fe6060f1SDimitry Andric defvar ps32 = !cast<VOP2_Pseudo>(opName#"_e32"); 2105fe6060f1SDimitry Andric defvar ps64 = !cast<VOP3_Pseudo>(opName#"_e64"); 2106e8d8bef9SDimitry Andric 2107e8d8bef9SDimitry Andric let AsmString = asmName # ps32.AsmOperands in { 2108fe6060f1SDimitry Andric defm "" : VOP2_Real_e32_gfx6_gfx7<op, opName>; 2109e8d8bef9SDimitry Andric } 2110e8d8bef9SDimitry Andric 2111e8d8bef9SDimitry Andric let AsmString = asmName # ps64.AsmOperands in { 2112fe6060f1SDimitry Andric defm "" : VOP2be_Real_e64_gfx6_gfx7<op, opName>; 2113e8d8bef9SDimitry Andric } 2114e8d8bef9SDimitry Andric} 2115e8d8bef9SDimitry Andric 21160b57cec5SDimitry Andricdefm V_CNDMASK_B32 : VOP2_Real_gfx6_gfx7<0x000>; 21170b57cec5SDimitry Andricdefm V_MIN_LEGACY_F32 : VOP2_Real_gfx6_gfx7<0x00d>; 21180b57cec5SDimitry Andricdefm V_MAX_LEGACY_F32 : VOP2_Real_gfx6_gfx7<0x00e>; 21190b57cec5SDimitry Andricdefm V_LSHR_B32 : VOP2_Real_gfx6_gfx7<0x015>; 21200b57cec5SDimitry Andricdefm V_ASHR_I32 : VOP2_Real_gfx6_gfx7<0x017>; 21210b57cec5SDimitry Andricdefm V_LSHL_B32 : VOP2_Real_gfx6_gfx7<0x019>; 21220b57cec5SDimitry Andricdefm V_BFM_B32 : VOP2_Real_gfx6_gfx7<0x01e>; 21230b57cec5SDimitry Andricdefm V_BCNT_U32_B32 : VOP2_Real_gfx6_gfx7<0x022>; 21240b57cec5SDimitry Andricdefm V_MBCNT_LO_U32_B32 : VOP2_Real_gfx6_gfx7<0x023>; 21250b57cec5SDimitry Andricdefm V_MBCNT_HI_U32_B32 : VOP2_Real_gfx6_gfx7<0x024>; 21260b57cec5SDimitry Andricdefm V_LDEXP_F32 : VOP2_Real_gfx6_gfx7<0x02b>; 21270b57cec5SDimitry Andricdefm V_CVT_PKACCUM_U8_F32 : VOP2_Real_gfx6_gfx7<0x02c>; 21280b57cec5SDimitry Andricdefm V_CVT_PKNORM_I16_F32 : VOP2_Real_gfx6_gfx7<0x02d>; 21290b57cec5SDimitry Andricdefm V_CVT_PKNORM_U16_F32 : VOP2_Real_gfx6_gfx7<0x02e>; 21300b57cec5SDimitry Andricdefm V_CVT_PK_U16_U32 : VOP2_Real_gfx6_gfx7<0x030>; 21310b57cec5SDimitry Andricdefm V_CVT_PK_I16_I32 : VOP2_Real_gfx6_gfx7<0x031>; 2132e8d8bef9SDimitry Andric 2133e8d8bef9SDimitry Andric// V_ADD_I32, V_SUB_I32, and V_SUBREV_I32 where renamed to *_U32 in 2134e8d8bef9SDimitry Andric// VI, but the VI instructions behave the same as the SI versions. 2135e8d8bef9SDimitry Andricdefm V_ADD_I32 : VOP2be_Real_gfx6_gfx7_with_name<0x025, "V_ADD_CO_U32", "v_add_i32">; 2136e8d8bef9SDimitry Andricdefm V_SUB_I32 : VOP2be_Real_gfx6_gfx7_with_name<0x026, "V_SUB_CO_U32", "v_sub_i32">; 2137e8d8bef9SDimitry Andricdefm V_SUBREV_I32 : VOP2be_Real_gfx6_gfx7_with_name<0x027, "V_SUBREV_CO_U32", "v_subrev_i32">; 21380b57cec5SDimitry Andricdefm V_ADDC_U32 : VOP2be_Real_gfx6_gfx7<0x028>; 21390b57cec5SDimitry Andricdefm V_SUBB_U32 : VOP2be_Real_gfx6_gfx7<0x029>; 21400b57cec5SDimitry Andricdefm V_SUBBREV_U32 : VOP2be_Real_gfx6_gfx7<0x02a>; 21410b57cec5SDimitry Andric 2142e8d8bef9SDimitry Andricdefm V_READLANE_B32 : VOP2_Lane_Real_gfx6_gfx7<0x001>; 21430b57cec5SDimitry Andric 21445ffd83dbSDimitry Andriclet InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in) in { 2145e8d8bef9SDimitry Andric defm V_WRITELANE_B32 : VOP2_Lane_Real_gfx6_gfx7<0x002>; 21465ffd83dbSDimitry Andric} // End InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in) 21470b57cec5SDimitry Andric 21480b57cec5SDimitry Andriclet SubtargetPredicate = isGFX6GFX7 in { 21490b57cec5SDimitry Andric defm : VOP2eInstAliases<V_CNDMASK_B32_e32, V_CNDMASK_B32_e32_gfx6_gfx7>; 2150e8d8bef9SDimitry Andric defm : VOP2eInstAliases<V_ADD_CO_U32_e32, V_ADD_I32_e32_gfx6_gfx7>; 2151e8d8bef9SDimitry Andric defm : VOP2eInstAliases<V_SUB_CO_U32_e32, V_SUB_I32_e32_gfx6_gfx7>; 2152e8d8bef9SDimitry Andric defm : VOP2eInstAliases<V_SUBREV_CO_U32_e32, V_SUBREV_I32_e32_gfx6_gfx7>; 2153e8d8bef9SDimitry Andric 2154e8d8bef9SDimitry Andric def : VOP2e64InstAlias<V_ADD_CO_U32_e64, V_ADD_I32_e64_gfx6_gfx7>; 2155e8d8bef9SDimitry Andric def : VOP2e64InstAlias<V_SUB_CO_U32_e64, V_SUB_I32_e64_gfx6_gfx7>; 2156e8d8bef9SDimitry Andric def : VOP2e64InstAlias<V_SUBREV_CO_U32_e64, V_SUBREV_I32_e64_gfx6_gfx7>; 21570b57cec5SDimitry Andric} // End SubtargetPredicate = isGFX6GFX7 21580b57cec5SDimitry Andric 21595f757f3fSDimitry Andricdefm V_ADD_F32 : VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x003>; 21605f757f3fSDimitry Andricdefm V_SUB_F32 : VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x004>; 21615f757f3fSDimitry Andricdefm V_SUBREV_F32 : VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x005>; 21620b57cec5SDimitry Andricdefm V_MAC_LEGACY_F32 : VOP2_Real_gfx6_gfx7_gfx10<0x006>; 21630b57cec5SDimitry Andricdefm V_MUL_LEGACY_F32 : VOP2_Real_gfx6_gfx7_gfx10<0x007>; 21645f757f3fSDimitry Andricdefm V_MUL_F32 : VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x008>; 21655f757f3fSDimitry Andricdefm V_MUL_I32_I24 : VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x009>; 21665f757f3fSDimitry Andricdefm V_MUL_HI_I32_I24 : VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x00a>; 21675f757f3fSDimitry Andricdefm V_MUL_U32_U24 : VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x00b>; 21685f757f3fSDimitry Andricdefm V_MUL_HI_U32_U24 : VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x00c>; 216981ad6265SDimitry Andricdefm V_MIN_F32 : VOP2_Real_gfx6_gfx7_gfx10_gfx11<0x00f>; 217081ad6265SDimitry Andricdefm V_MAX_F32 : VOP2_Real_gfx6_gfx7_gfx10_gfx11<0x010>; 21715f757f3fSDimitry Andricdefm V_MIN_I32 : VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x011>; 21725f757f3fSDimitry Andricdefm V_MAX_I32 : VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x012>; 21735f757f3fSDimitry Andricdefm V_MIN_U32 : VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x013>; 21745f757f3fSDimitry Andricdefm V_MAX_U32 : VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x014>; 21750b57cec5SDimitry Andricdefm V_LSHRREV_B32 : VOP2_Real_gfx6_gfx7_gfx10<0x016>; 21760b57cec5SDimitry Andricdefm V_ASHRREV_I32 : VOP2_Real_gfx6_gfx7_gfx10<0x018>; 21770b57cec5SDimitry Andricdefm V_LSHLREV_B32 : VOP2_Real_gfx6_gfx7_gfx10<0x01a>; 21785f757f3fSDimitry Andricdefm V_AND_B32 : VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x01b>; 21795f757f3fSDimitry Andricdefm V_OR_B32 : VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x01c>; 21805f757f3fSDimitry Andricdefm V_XOR_B32 : VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x01d>; 21810b57cec5SDimitry Andricdefm V_MAC_F32 : VOP2_Real_gfx6_gfx7_gfx10<0x01f>; 21820b57cec5SDimitry Andricdefm V_CVT_PKRTZ_F16_F32 : VOP2_Real_gfx6_gfx7_gfx10<0x02f>; 21830b57cec5SDimitry Andricdefm V_MADMK_F32 : VOP2Only_Real_MADK_gfx6_gfx7_gfx10<0x020>; 21840b57cec5SDimitry Andricdefm V_MADAK_F32 : VOP2Only_Real_MADK_gfx6_gfx7_gfx10<0x021>; 21850b57cec5SDimitry Andric 21860b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 21870b57cec5SDimitry Andric// GFX8, GFX9 (VI). 21880b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 21890b57cec5SDimitry Andric 2190480093f4SDimitry Andriclet AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8" in { 21910b57cec5SDimitry Andric 21920b57cec5SDimitry Andricmulticlass VOP2_Real_MADK_vi <bits<6> op> { 21930b57cec5SDimitry Andric def _vi : VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.VI>, 21940b57cec5SDimitry Andric VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>; 21950b57cec5SDimitry Andric} 21960b57cec5SDimitry Andric 219781ad6265SDimitry Andricmulticlass VOP2_Real_MADK_gfx940 <bits<6> op> { 219881ad6265SDimitry Andric def _gfx940 : VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.GFX940>, 219981ad6265SDimitry Andric VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl> { 220081ad6265SDimitry Andric let DecoderNamespace = "GFX9"; 220181ad6265SDimitry Andric } 220281ad6265SDimitry Andric} 220381ad6265SDimitry Andric 22040b57cec5SDimitry Andricmulticlass VOP2_Real_e32_vi <bits<6> op> { 22050b57cec5SDimitry Andric def _e32_vi : 22060b57cec5SDimitry Andric VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.VI>, 22070b57cec5SDimitry Andric VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>; 22080b57cec5SDimitry Andric} 22090b57cec5SDimitry Andric 22100b57cec5SDimitry Andricmulticlass VOP2_Real_e64_vi <bits<10> op> { 22110b57cec5SDimitry Andric def _e64_vi : 22120b57cec5SDimitry Andric VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>, 22130b57cec5SDimitry Andric VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 22140b57cec5SDimitry Andric} 22150b57cec5SDimitry Andric 22160b57cec5SDimitry Andricmulticlass VOP2_Real_e64only_vi <bits<10> op> { 22170b57cec5SDimitry Andric def _e64_vi : 22180b57cec5SDimitry Andric VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>, 22190b57cec5SDimitry Andric VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> { 2220fe6060f1SDimitry Andric let IsSingle = 1; 22210b57cec5SDimitry Andric } 22220b57cec5SDimitry Andric} 22230b57cec5SDimitry Andric 22240b57cec5SDimitry Andricmulticlass Base_VOP2_Real_e32e64_vi <bits<6> op> : 22250b57cec5SDimitry Andric VOP2_Real_e32_vi<op>, 22260b57cec5SDimitry Andric VOP2_Real_e64_vi<{0, 1, 0, 0, op{5-0}}>; 22270b57cec5SDimitry Andric 2228480093f4SDimitry Andric} // End AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8" 22290b57cec5SDimitry Andric 22300b57cec5SDimitry Andricmulticlass VOP2_SDWA_Real <bits<6> op> { 223106c3fb27SDimitry Andric if !cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA then 22320b57cec5SDimitry Andric def _sdwa_vi : 22330b57cec5SDimitry Andric VOP_SDWA_Real <!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>, 22340b57cec5SDimitry Andric VOP2_SDWAe <op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl>; 22350b57cec5SDimitry Andric} 22360b57cec5SDimitry Andric 22370b57cec5SDimitry Andricmulticlass VOP2_SDWA9_Real <bits<6> op> { 223806c3fb27SDimitry Andric if !cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9 then 22390b57cec5SDimitry Andric def _sdwa_gfx9 : 22400b57cec5SDimitry Andric VOP_SDWA9_Real <!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>, 22410b57cec5SDimitry Andric VOP2_SDWA9Ae <op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl>; 22420b57cec5SDimitry Andric} 22430b57cec5SDimitry Andric 2244480093f4SDimitry Andriclet AssemblerPredicate = isGFX8Only in { 22450b57cec5SDimitry Andric 22460b57cec5SDimitry Andricmulticlass VOP2be_Real_e32e64_vi_only <bits<6> op, string OpName, string AsmName> { 22470b57cec5SDimitry Andric def _e32_vi : 22480b57cec5SDimitry Andric VOP2_Real<!cast<VOP2_Pseudo>(OpName#"_e32"), SIEncodingFamily.VI>, 22490b57cec5SDimitry Andric VOP2e<op{5-0}, !cast<VOP2_Pseudo>(OpName#"_e32").Pfl> { 22500b57cec5SDimitry Andric VOP2_Pseudo ps = !cast<VOP2_Pseudo>(OpName#"_e32"); 22510b57cec5SDimitry Andric let AsmString = AsmName # ps.AsmOperands; 22520b57cec5SDimitry Andric let DecoderNamespace = "GFX8"; 22530b57cec5SDimitry Andric } 22540b57cec5SDimitry Andric def _e64_vi : 22550b57cec5SDimitry Andric VOP3_Real<!cast<VOP3_Pseudo>(OpName#"_e64"), SIEncodingFamily.VI>, 22560b57cec5SDimitry Andric VOP3be_vi <{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(OpName#"_e64").Pfl> { 22570b57cec5SDimitry Andric VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName#"_e64"); 22580b57cec5SDimitry Andric let AsmString = AsmName # ps.AsmOperands; 22590b57cec5SDimitry Andric let DecoderNamespace = "GFX8"; 22600b57cec5SDimitry Andric } 226106c3fb27SDimitry Andric if !cast<VOP2_Pseudo>(OpName#"_e32").Pfl.HasExtSDWA then 22620b57cec5SDimitry Andric def _sdwa_vi : 22630b57cec5SDimitry Andric VOP_SDWA_Real <!cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa")>, 22640b57cec5SDimitry Andric VOP2_SDWAe <op{5-0}, !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa").Pfl> { 22650b57cec5SDimitry Andric VOP2_SDWA_Pseudo ps = !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa"); 22660b57cec5SDimitry Andric let AsmString = AsmName # ps.AsmOperands; 22670b57cec5SDimitry Andric } 226806c3fb27SDimitry Andric if !cast<VOP2_Pseudo>(OpName#"_e32").Pfl.HasExtDPP then 22690b57cec5SDimitry Andric def _dpp_vi : 22700b57cec5SDimitry Andric VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(OpName#"_dpp"), SIEncodingFamily.VI>, 22710b57cec5SDimitry Andric VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(OpName#"_dpp")> { 22720b57cec5SDimitry Andric VOP2_DPP_Pseudo ps = !cast<VOP2_DPP_Pseudo>(OpName#"_dpp"); 22730b57cec5SDimitry Andric let AsmString = AsmName # ps.AsmOperands; 22740b57cec5SDimitry Andric } 22750b57cec5SDimitry Andric} 22760b57cec5SDimitry Andric} 22770b57cec5SDimitry Andric 2278480093f4SDimitry Andriclet AssemblerPredicate = isGFX9Only in { 22790b57cec5SDimitry Andric 22800b57cec5SDimitry Andricmulticlass VOP2be_Real_e32e64_gfx9 <bits<6> op, string OpName, string AsmName> { 22810b57cec5SDimitry Andric def _e32_gfx9 : 22820b57cec5SDimitry Andric VOP2_Real<!cast<VOP2_Pseudo>(OpName#"_e32"), SIEncodingFamily.GFX9>, 22830b57cec5SDimitry Andric VOP2e<op{5-0}, !cast<VOP2_Pseudo>(OpName#"_e32").Pfl> { 22840b57cec5SDimitry Andric VOP2_Pseudo ps = !cast<VOP2_Pseudo>(OpName#"_e32"); 22850b57cec5SDimitry Andric let AsmString = AsmName # ps.AsmOperands; 22860b57cec5SDimitry Andric let DecoderNamespace = "GFX9"; 22870b57cec5SDimitry Andric } 22880b57cec5SDimitry Andric def _e64_gfx9 : 22890b57cec5SDimitry Andric VOP3_Real<!cast<VOP3_Pseudo>(OpName#"_e64"), SIEncodingFamily.GFX9>, 22900b57cec5SDimitry Andric VOP3be_vi <{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(OpName#"_e64").Pfl> { 22910b57cec5SDimitry Andric VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName#"_e64"); 22920b57cec5SDimitry Andric let AsmString = AsmName # ps.AsmOperands; 22930b57cec5SDimitry Andric let DecoderNamespace = "GFX9"; 22940b57cec5SDimitry Andric } 229506c3fb27SDimitry Andric if !cast<VOP2_Pseudo>(OpName#"_e32").Pfl.HasExtSDWA9 then 22960b57cec5SDimitry Andric def _sdwa_gfx9 : 22970b57cec5SDimitry Andric VOP_SDWA9_Real <!cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa")>, 22980b57cec5SDimitry Andric VOP2_SDWA9Ae <op{5-0}, !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa").Pfl> { 22990b57cec5SDimitry Andric VOP2_SDWA_Pseudo ps = !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa"); 23000b57cec5SDimitry Andric let AsmString = AsmName # ps.AsmOperands; 23010b57cec5SDimitry Andric } 230206c3fb27SDimitry Andric if !cast<VOP2_Pseudo>(OpName#"_e32").Pfl.HasExtDPP then 23030b57cec5SDimitry Andric def _dpp_gfx9 : 23040b57cec5SDimitry Andric VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(OpName#"_dpp"), SIEncodingFamily.GFX9>, 23050b57cec5SDimitry Andric VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(OpName#"_dpp")> { 23060b57cec5SDimitry Andric VOP2_DPP_Pseudo ps = !cast<VOP2_DPP_Pseudo>(OpName#"_dpp"); 23070b57cec5SDimitry Andric let AsmString = AsmName # ps.AsmOperands; 23080b57cec5SDimitry Andric let DecoderNamespace = "SDWA9"; 23090b57cec5SDimitry Andric } 23100b57cec5SDimitry Andric} 23110b57cec5SDimitry Andric 23120b57cec5SDimitry Andricmulticlass VOP2_Real_e32e64_gfx9 <bits<6> op> { 23130b57cec5SDimitry Andric def _e32_gfx9 : 23140b57cec5SDimitry Andric VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.GFX9>, 23150b57cec5SDimitry Andric VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>{ 23160b57cec5SDimitry Andric let DecoderNamespace = "GFX9"; 23170b57cec5SDimitry Andric } 23180b57cec5SDimitry Andric def _e64_gfx9 : 23190b57cec5SDimitry Andric VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX9>, 23200b57cec5SDimitry Andric VOP3e_vi <{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> { 23210b57cec5SDimitry Andric let DecoderNamespace = "GFX9"; 23220b57cec5SDimitry Andric } 232306c3fb27SDimitry Andric if !cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9 then 23240b57cec5SDimitry Andric def _sdwa_gfx9 : 23250b57cec5SDimitry Andric VOP_SDWA9_Real <!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>, 23260b57cec5SDimitry Andric VOP2_SDWA9Ae <op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl> { 23270b57cec5SDimitry Andric } 232806c3fb27SDimitry Andric if !cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP then 23290b57cec5SDimitry Andric def _dpp_gfx9 : 23300b57cec5SDimitry Andric VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.GFX9>, 23310b57cec5SDimitry Andric VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")> { 23320b57cec5SDimitry Andric let DecoderNamespace = "SDWA9"; 23330b57cec5SDimitry Andric } 23340b57cec5SDimitry Andric} 23350b57cec5SDimitry Andric 2336480093f4SDimitry Andric} // AssemblerPredicate = isGFX9Only 23370b57cec5SDimitry Andric 23380b57cec5SDimitry Andricmulticlass VOP2_Real_e32e64_vi <bits<6> op> : 23390b57cec5SDimitry Andric Base_VOP2_Real_e32e64_vi<op>, VOP2_SDWA_Real<op>, VOP2_SDWA9_Real<op> { 23400b57cec5SDimitry Andric 234106c3fb27SDimitry Andric if !cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP then 23420b57cec5SDimitry Andric def _dpp_vi : 23430b57cec5SDimitry Andric VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.VI>, 23440b57cec5SDimitry Andric VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")>; 23450b57cec5SDimitry Andric} 23460b57cec5SDimitry Andric 23470b57cec5SDimitry Andricdefm V_CNDMASK_B32 : VOP2_Real_e32e64_vi <0x0>; 23480b57cec5SDimitry Andricdefm V_ADD_F32 : VOP2_Real_e32e64_vi <0x1>; 23490b57cec5SDimitry Andricdefm V_SUB_F32 : VOP2_Real_e32e64_vi <0x2>; 23500b57cec5SDimitry Andricdefm V_SUBREV_F32 : VOP2_Real_e32e64_vi <0x3>; 2351fe6060f1SDimitry Andriclet AssemblerPredicate = isGCN3ExcludingGFX90A in 23520b57cec5SDimitry Andricdefm V_MUL_LEGACY_F32 : VOP2_Real_e32e64_vi <0x4>; 23530b57cec5SDimitry Andricdefm V_MUL_F32 : VOP2_Real_e32e64_vi <0x5>; 23540b57cec5SDimitry Andricdefm V_MUL_I32_I24 : VOP2_Real_e32e64_vi <0x6>; 23550b57cec5SDimitry Andricdefm V_MUL_HI_I32_I24 : VOP2_Real_e32e64_vi <0x7>; 23560b57cec5SDimitry Andricdefm V_MUL_U32_U24 : VOP2_Real_e32e64_vi <0x8>; 23570b57cec5SDimitry Andricdefm V_MUL_HI_U32_U24 : VOP2_Real_e32e64_vi <0x9>; 23580b57cec5SDimitry Andricdefm V_MIN_F32 : VOP2_Real_e32e64_vi <0xa>; 23590b57cec5SDimitry Andricdefm V_MAX_F32 : VOP2_Real_e32e64_vi <0xb>; 23600b57cec5SDimitry Andricdefm V_MIN_I32 : VOP2_Real_e32e64_vi <0xc>; 23610b57cec5SDimitry Andricdefm V_MAX_I32 : VOP2_Real_e32e64_vi <0xd>; 23620b57cec5SDimitry Andricdefm V_MIN_U32 : VOP2_Real_e32e64_vi <0xe>; 23630b57cec5SDimitry Andricdefm V_MAX_U32 : VOP2_Real_e32e64_vi <0xf>; 23640b57cec5SDimitry Andricdefm V_LSHRREV_B32 : VOP2_Real_e32e64_vi <0x10>; 23650b57cec5SDimitry Andricdefm V_ASHRREV_I32 : VOP2_Real_e32e64_vi <0x11>; 23660b57cec5SDimitry Andricdefm V_LSHLREV_B32 : VOP2_Real_e32e64_vi <0x12>; 23670b57cec5SDimitry Andricdefm V_AND_B32 : VOP2_Real_e32e64_vi <0x13>; 23680b57cec5SDimitry Andricdefm V_OR_B32 : VOP2_Real_e32e64_vi <0x14>; 23690b57cec5SDimitry Andricdefm V_XOR_B32 : VOP2_Real_e32e64_vi <0x15>; 23700b57cec5SDimitry Andricdefm V_MAC_F32 : VOP2_Real_e32e64_vi <0x16>; 23710b57cec5SDimitry Andricdefm V_MADMK_F32 : VOP2_Real_MADK_vi <0x17>; 23720b57cec5SDimitry Andricdefm V_MADAK_F32 : VOP2_Real_MADK_vi <0x18>; 23730b57cec5SDimitry Andric 2374e8d8bef9SDimitry Andricdefm V_ADD_U32 : VOP2be_Real_e32e64_vi_only <0x19, "V_ADD_CO_U32", "v_add_u32">; 2375e8d8bef9SDimitry Andricdefm V_SUB_U32 : VOP2be_Real_e32e64_vi_only <0x1a, "V_SUB_CO_U32", "v_sub_u32">; 2376e8d8bef9SDimitry Andricdefm V_SUBREV_U32 : VOP2be_Real_e32e64_vi_only <0x1b, "V_SUBREV_CO_U32", "v_subrev_u32">; 23770b57cec5SDimitry Andricdefm V_ADDC_U32 : VOP2be_Real_e32e64_vi_only <0x1c, "V_ADDC_U32", "v_addc_u32">; 23780b57cec5SDimitry Andricdefm V_SUBB_U32 : VOP2be_Real_e32e64_vi_only <0x1d, "V_SUBB_U32", "v_subb_u32">; 23790b57cec5SDimitry Andricdefm V_SUBBREV_U32 : VOP2be_Real_e32e64_vi_only <0x1e, "V_SUBBREV_U32", "v_subbrev_u32">; 23800b57cec5SDimitry Andric 2381e8d8bef9SDimitry Andricdefm V_ADD_CO_U32 : VOP2be_Real_e32e64_gfx9 <0x19, "V_ADD_CO_U32", "v_add_co_u32">; 2382e8d8bef9SDimitry Andricdefm V_SUB_CO_U32 : VOP2be_Real_e32e64_gfx9 <0x1a, "V_SUB_CO_U32", "v_sub_co_u32">; 2383e8d8bef9SDimitry Andricdefm V_SUBREV_CO_U32 : VOP2be_Real_e32e64_gfx9 <0x1b, "V_SUBREV_CO_U32", "v_subrev_co_u32">; 23840b57cec5SDimitry Andricdefm V_ADDC_CO_U32 : VOP2be_Real_e32e64_gfx9 <0x1c, "V_ADDC_U32", "v_addc_co_u32">; 23850b57cec5SDimitry Andricdefm V_SUBB_CO_U32 : VOP2be_Real_e32e64_gfx9 <0x1d, "V_SUBB_U32", "v_subb_co_u32">; 23860b57cec5SDimitry Andricdefm V_SUBBREV_CO_U32 : VOP2be_Real_e32e64_gfx9 <0x1e, "V_SUBBREV_U32", "v_subbrev_co_u32">; 23870b57cec5SDimitry Andric 23880b57cec5SDimitry Andricdefm V_ADD_U32 : VOP2_Real_e32e64_gfx9 <0x34>; 23890b57cec5SDimitry Andricdefm V_SUB_U32 : VOP2_Real_e32e64_gfx9 <0x35>; 23900b57cec5SDimitry Andricdefm V_SUBREV_U32 : VOP2_Real_e32e64_gfx9 <0x36>; 23910b57cec5SDimitry Andric 23920b57cec5SDimitry Andricdefm V_BFM_B32 : VOP2_Real_e64only_vi <0x293>; 23930b57cec5SDimitry Andricdefm V_BCNT_U32_B32 : VOP2_Real_e64only_vi <0x28b>; 23940b57cec5SDimitry Andricdefm V_MBCNT_LO_U32_B32 : VOP2_Real_e64only_vi <0x28c>; 23950b57cec5SDimitry Andricdefm V_MBCNT_HI_U32_B32 : VOP2_Real_e64only_vi <0x28d>; 23960b57cec5SDimitry Andricdefm V_LDEXP_F32 : VOP2_Real_e64only_vi <0x288>; 23970b57cec5SDimitry Andricdefm V_CVT_PKACCUM_U8_F32 : VOP2_Real_e64only_vi <0x1f0>; 23980b57cec5SDimitry Andricdefm V_CVT_PKNORM_I16_F32 : VOP2_Real_e64only_vi <0x294>; 23990b57cec5SDimitry Andricdefm V_CVT_PKNORM_U16_F32 : VOP2_Real_e64only_vi <0x295>; 24000b57cec5SDimitry Andricdefm V_CVT_PKRTZ_F16_F32 : VOP2_Real_e64only_vi <0x296>; 24010b57cec5SDimitry Andricdefm V_CVT_PK_U16_U32 : VOP2_Real_e64only_vi <0x297>; 24020b57cec5SDimitry Andricdefm V_CVT_PK_I16_I32 : VOP2_Real_e64only_vi <0x298>; 24030b57cec5SDimitry Andric 24040b57cec5SDimitry Andricdefm V_ADD_F16 : VOP2_Real_e32e64_vi <0x1f>; 24050b57cec5SDimitry Andricdefm V_SUB_F16 : VOP2_Real_e32e64_vi <0x20>; 24060b57cec5SDimitry Andricdefm V_SUBREV_F16 : VOP2_Real_e32e64_vi <0x21>; 24070b57cec5SDimitry Andricdefm V_MUL_F16 : VOP2_Real_e32e64_vi <0x22>; 24080b57cec5SDimitry Andricdefm V_MAC_F16 : VOP2_Real_e32e64_vi <0x23>; 24090b57cec5SDimitry Andricdefm V_MADMK_F16 : VOP2_Real_MADK_vi <0x24>; 24100b57cec5SDimitry Andricdefm V_MADAK_F16 : VOP2_Real_MADK_vi <0x25>; 24110b57cec5SDimitry Andricdefm V_ADD_U16 : VOP2_Real_e32e64_vi <0x26>; 24120b57cec5SDimitry Andricdefm V_SUB_U16 : VOP2_Real_e32e64_vi <0x27>; 24130b57cec5SDimitry Andricdefm V_SUBREV_U16 : VOP2_Real_e32e64_vi <0x28>; 24140b57cec5SDimitry Andricdefm V_MUL_LO_U16 : VOP2_Real_e32e64_vi <0x29>; 24150b57cec5SDimitry Andricdefm V_LSHLREV_B16 : VOP2_Real_e32e64_vi <0x2a>; 24160b57cec5SDimitry Andricdefm V_LSHRREV_B16 : VOP2_Real_e32e64_vi <0x2b>; 24170b57cec5SDimitry Andricdefm V_ASHRREV_I16 : VOP2_Real_e32e64_vi <0x2c>; 24180b57cec5SDimitry Andricdefm V_MAX_F16 : VOP2_Real_e32e64_vi <0x2d>; 24190b57cec5SDimitry Andricdefm V_MIN_F16 : VOP2_Real_e32e64_vi <0x2e>; 24200b57cec5SDimitry Andricdefm V_MAX_U16 : VOP2_Real_e32e64_vi <0x2f>; 24210b57cec5SDimitry Andricdefm V_MAX_I16 : VOP2_Real_e32e64_vi <0x30>; 24220b57cec5SDimitry Andricdefm V_MIN_U16 : VOP2_Real_e32e64_vi <0x31>; 24230b57cec5SDimitry Andricdefm V_MIN_I16 : VOP2_Real_e32e64_vi <0x32>; 24240b57cec5SDimitry Andricdefm V_LDEXP_F16 : VOP2_Real_e32e64_vi <0x33>; 24250b57cec5SDimitry Andric 24260b57cec5SDimitry Andriclet SubtargetPredicate = isGFX8GFX9 in { 24270b57cec5SDimitry Andric 24280b57cec5SDimitry Andric// Aliases to simplify matching of floating-point instructions that 24290b57cec5SDimitry Andric// are VOP2 on SI and VOP3 on VI. 24300b57cec5SDimitry Andricclass SI2_VI3Alias <string name, VOP3_Real inst> : InstAlias < 24310b57cec5SDimitry Andric name#" $dst, $src0, $src1", 24320b57cec5SDimitry Andric !if(inst.Pfl.HasOMod, 24330b57cec5SDimitry Andric (inst VGPR_32:$dst, 0, VCSrc_f32:$src0, 0, VCSrc_f32:$src1, 0, 0), 24340b57cec5SDimitry Andric (inst VGPR_32:$dst, 0, VCSrc_f32:$src0, 0, VCSrc_f32:$src1, 0)) 24350b57cec5SDimitry Andric>, PredicateControl { 24360b57cec5SDimitry Andric let UseInstAsmMatchConverter = 0; 24370b57cec5SDimitry Andric let AsmVariantName = AMDGPUAsmVariants.VOP3; 24380b57cec5SDimitry Andric} 24390b57cec5SDimitry Andric 24400b57cec5SDimitry Andricdef : SI2_VI3Alias <"v_ldexp_f32", V_LDEXP_F32_e64_vi>; 24410b57cec5SDimitry Andricdef : SI2_VI3Alias <"v_cvt_pkaccum_u8_f32", V_CVT_PKACCUM_U8_F32_e64_vi>; 24420b57cec5SDimitry Andricdef : SI2_VI3Alias <"v_cvt_pknorm_i16_f32", V_CVT_PKNORM_I16_F32_e64_vi>; 24430b57cec5SDimitry Andricdef : SI2_VI3Alias <"v_cvt_pknorm_u16_f32", V_CVT_PKNORM_U16_F32_e64_vi>; 24440b57cec5SDimitry Andricdef : SI2_VI3Alias <"v_cvt_pkrtz_f16_f32", V_CVT_PKRTZ_F16_F32_e64_vi>; 24450b57cec5SDimitry Andric 24460b57cec5SDimitry Andricdefm : VOP2eInstAliases<V_CNDMASK_B32_e32, V_CNDMASK_B32_e32_vi>; 24470b57cec5SDimitry Andric 24480b57cec5SDimitry Andric} // End SubtargetPredicate = isGFX8GFX9 24490b57cec5SDimitry Andric 24500b57cec5SDimitry Andriclet SubtargetPredicate = isGFX9Only in { 24510b57cec5SDimitry Andric 2452e8d8bef9SDimitry Andricdefm : VOP2bInstAliases<V_ADD_U32_e32, V_ADD_CO_U32_e32_gfx9, "v_add_co_u32">; 24530b57cec5SDimitry Andricdefm : VOP2bInstAliases<V_ADDC_U32_e32, V_ADDC_CO_U32_e32_gfx9, "v_addc_co_u32">; 2454e8d8bef9SDimitry Andricdefm : VOP2bInstAliases<V_SUB_U32_e32, V_SUB_CO_U32_e32_gfx9, "v_sub_co_u32">; 24550b57cec5SDimitry Andricdefm : VOP2bInstAliases<V_SUBB_U32_e32, V_SUBB_CO_U32_e32_gfx9, "v_subb_co_u32">; 2456e8d8bef9SDimitry Andricdefm : VOP2bInstAliases<V_SUBREV_U32_e32, V_SUBREV_CO_U32_e32_gfx9, "v_subrev_co_u32">; 24570b57cec5SDimitry Andricdefm : VOP2bInstAliases<V_SUBBREV_U32_e32, V_SUBBREV_CO_U32_e32_gfx9, "v_subbrev_co_u32">; 24580b57cec5SDimitry Andric 24590b57cec5SDimitry Andric} // End SubtargetPredicate = isGFX9Only 24600b57cec5SDimitry Andric 24610b57cec5SDimitry Andriclet SubtargetPredicate = HasDLInsts in { 24620b57cec5SDimitry Andric 24630b57cec5SDimitry Andricdefm V_FMAC_F32 : VOP2_Real_e32e64_vi <0x3b>; 24640b57cec5SDimitry Andricdefm V_XNOR_B32 : VOP2_Real_e32e64_vi <0x3d>; 24650b57cec5SDimitry Andric 24660b57cec5SDimitry Andric} // End SubtargetPredicate = HasDLInsts 24670b57cec5SDimitry Andric 2468fe6060f1SDimitry Andriclet AssemblerPredicate = isGFX90APlus, DecoderNamespace = "GFX90A" in { 2469fe6060f1SDimitry Andric multiclass VOP2_Real_e32_gfx90a <bits<6> op> { 2470fe6060f1SDimitry Andric def _e32_gfx90a : 2471fe6060f1SDimitry Andric VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.GFX90A>, 2472fe6060f1SDimitry Andric VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>; 2473fe6060f1SDimitry Andric } 2474fe6060f1SDimitry Andric 2475fe6060f1SDimitry Andric multiclass VOP2_Real_e64_gfx90a <bits<10> op> { 2476fe6060f1SDimitry Andric def _e64_gfx90a : 2477fe6060f1SDimitry Andric VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX90A>, 2478fe6060f1SDimitry Andric VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 2479fe6060f1SDimitry Andric } 2480fe6060f1SDimitry Andric 2481fe6060f1SDimitry Andric multiclass Base_VOP2_Real_e32e64_gfx90a <bits<6> op> : 2482fe6060f1SDimitry Andric VOP2_Real_e32_gfx90a<op>, 2483fe6060f1SDimitry Andric VOP2_Real_e64_gfx90a<{0, 1, 0, 0, op{5-0}}>; 2484fe6060f1SDimitry Andric 2485fe6060f1SDimitry Andric multiclass VOP2_Real_e32e64_gfx90a <bits<6> op> : 2486fe6060f1SDimitry Andric Base_VOP2_Real_e32e64_gfx90a<op> { 2487fe6060f1SDimitry Andric 248806c3fb27SDimitry Andric if !cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP then 2489fe6060f1SDimitry Andric def _dpp_gfx90a : 2490fe6060f1SDimitry Andric VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.GFX90A>, 2491fe6060f1SDimitry Andric VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")> { 2492fe6060f1SDimitry Andric let DecoderNamespace = "SDWA9"; 2493fe6060f1SDimitry Andric } 2494fe6060f1SDimitry Andric } 2495fe6060f1SDimitry Andric} // End AssemblerPredicate = isGFX90APlus, DecoderNamespace = "GFX90A" 2496fe6060f1SDimitry Andric 2497bdd1243dSDimitry Andriclet SubtargetPredicate = HasFmacF64Inst in { 2498fe6060f1SDimitry Andric defm V_FMAC_F64 : VOP2_Real_e32e64_gfx90a <0x4>; 2499bdd1243dSDimitry Andric} // End SubtargetPredicate = HasFmacF64Inst 2500bdd1243dSDimitry Andric 2501bdd1243dSDimitry Andriclet SubtargetPredicate = isGFX90APlus, IsSingle = 1 in { 2502fe6060f1SDimitry Andric defm V_MUL_LEGACY_F32 : VOP2_Real_e64_gfx90a <0x2a1>; 2503fe6060f1SDimitry Andric} 2504fe6060f1SDimitry Andric 250581ad6265SDimitry Andriclet SubtargetPredicate = HasFmaakFmamkF32Insts in { 250681ad6265SDimitry Andricdefm V_FMAMK_F32 : VOP2_Real_MADK_gfx940 <0x17>; 250781ad6265SDimitry Andricdefm V_FMAAK_F32 : VOP2_Real_MADK_gfx940 <0x18>; 250881ad6265SDimitry Andric} 250981ad6265SDimitry Andric 2510bdd1243dSDimitry Andricmulticlass VOP2_Real_DOT_ACC_gfx9<bits<6> op> : Base_VOP2_Real_e32e64_vi<op> { 25117a6dacacSDimitry Andric let SubtargetPredicate = isGFX9Only in 25128bcb0991SDimitry Andric def _dpp_vi : VOP2_DPP<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")>; 25130b57cec5SDimitry Andric} 25140b57cec5SDimitry Andric 25150b57cec5SDimitry Andricmulticlass VOP2_Real_DOT_ACC_gfx10<bits<6> op> : 25160b57cec5SDimitry Andric VOP2_Real_e32_gfx10<op>, 25170b57cec5SDimitry Andric VOP2_Real_dpp_gfx10<op>, 25180b57cec5SDimitry Andric VOP2_Real_dpp8_gfx10<op>; 25190b57cec5SDimitry Andric 25207a6dacacSDimitry Andricmulticlass VOP2Only_Real_DOT_ACC_gfx10<bits<6> op> : VOP2_Real_dpp_gfx10<op>, 25217a6dacacSDimitry Andric VOP2_Real_dpp8_gfx10<op> { 25227a6dacacSDimitry Andric let IsSingle = 1 in 25237a6dacacSDimitry Andric defm NAME : VOP2_Real_e32_gfx10<op>; 25247a6dacacSDimitry Andric} 25257a6dacacSDimitry Andric 25267a6dacacSDimitry Andriclet OtherPredicates = [HasDot5Insts] in { 25270b57cec5SDimitry Andric defm V_DOT2C_F32_F16 : VOP2_Real_DOT_ACC_gfx9<0x37>; 25280b57cec5SDimitry Andric // NB: Opcode conflicts with V_DOT8C_I32_I4 25290b57cec5SDimitry Andric // This opcode exists in gfx 10.1* only 25307a6dacacSDimitry Andric defm V_DOT2C_F32_F16 : VOP2Only_Real_DOT_ACC_gfx10<0x02>; 25310b57cec5SDimitry Andric} 25320b57cec5SDimitry Andric 25337a6dacacSDimitry Andriclet OtherPredicates = [HasDot6Insts] in { 25340b57cec5SDimitry Andric defm V_DOT4C_I32_I8 : VOP2_Real_DOT_ACC_gfx9<0x39>; 25357a6dacacSDimitry Andric defm V_DOT4C_I32_I8 : VOP2Only_Real_DOT_ACC_gfx10<0x0d>; 25360b57cec5SDimitry Andric} 25370b57cec5SDimitry Andric 25387a6dacacSDimitry Andriclet OtherPredicates = [HasDot4Insts] in { 25390b57cec5SDimitry Andric defm V_DOT2C_I32_I16 : VOP2_Real_DOT_ACC_gfx9<0x38>; 25400b57cec5SDimitry Andric} 25417a6dacacSDimitry Andriclet OtherPredicates = [HasDot3Insts] in { 25420b57cec5SDimitry Andric defm V_DOT8C_I32_I4 : VOP2_Real_DOT_ACC_gfx9<0x3a>; 25430b57cec5SDimitry Andric} 25440b57cec5SDimitry Andric 25450b57cec5SDimitry Andriclet SubtargetPredicate = HasPkFmacF16Inst in { 25460b57cec5SDimitry Andricdefm V_PK_FMAC_F16 : VOP2_Real_e32_vi<0x3c>; 25470b57cec5SDimitry Andric} // End SubtargetPredicate = HasPkFmacF16Inst 25485ffd83dbSDimitry Andric 25495ffd83dbSDimitry Andriclet SubtargetPredicate = HasDot3Insts in { 25505ffd83dbSDimitry Andric // NB: Opcode conflicts with V_DOT2C_F32_F16 25515ffd83dbSDimitry Andric let DecoderNamespace = "GFX10_B" in 25525ffd83dbSDimitry Andric defm V_DOT8C_I32_I4 : VOP2_Real_DOT_ACC_gfx10<0x02>; 25535ffd83dbSDimitry Andric} 2554