1//===-- VOP3PInstructions.td - Vector Instruction Definitions -------------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// VOP3P Classes 11//===----------------------------------------------------------------------===// 12 13class VOP3P_Profile<VOPProfile P, VOP3Features Features = VOP3_REGULAR, 14 bit HasDPP = 0> : VOP3_Profile<P, Features> { 15 let IsVOP3P = 1; 16 let HasExtVOP3DPP = HasDPP; 17 // We do not want to print src modifiers for vop3p because the bits are 18 // overloaded in meaning and the logic in printOperandAndFPInputMods is 19 // wrong for vop3p 20 let AsmVOP3DPPBase = AsmVOP3P; 21} 22 23// Used for FMA_MIX* and MAD_MIX* insts 24// Their operands are only sort of f16 operands. Depending on 25// op_sel_hi, these may be interpreted as f32. The inline immediate 26// values are really f16 converted to f32, so we treat these as f16 27// operands. 28class VOP3P_Mix_Profile<VOPProfile P, VOP3Features Features = VOP3_REGULAR, 29 bit useTiedOutput = 0> : VOP3P_Profile<P, Features, 1> { 30 bit UseTiedOutput = useTiedOutput; 31 32 dag srcs = 33 (ins FP16InputMods:$src0_modifiers, VCSrc_f16:$src0, 34 FP16InputMods:$src1_modifiers, VCSrc_f16:$src1, 35 FP16InputMods:$src2_modifiers, VCSrc_f16:$src2); 36 dag dpp_srcs = 37 (ins FPVRegInputMods:$src0_modifiers, VGPRSrc_32:$src0, 38 FP16InputMods:$src1_modifiers, VCSrc_f16:$src1, 39 FP16InputMods:$src2_modifiers, VCSrc_f16:$src2); 40 41 // FIXME: clampmod0 misbehaves with the non-default vdst_in 42 // following it. For now workaround this by requiring clamp 43 // in tied patterns. This should use undef_tied_input, but it 44 // seems underdeveloped and doesn't apply the right register 45 // class constraints. 46 dag mods = !con(!if(UseTiedOutput, (ins clampmod:$clamp, VGPR_32:$vdst_in), 47 (ins clampmod0:$clamp)), 48 (ins op_sel0:$op_sel, op_sel_hi0:$op_sel_hi)); 49 // We use Ins64 because that is the one which populates InOperandList 50 // due to the logic in class VOP3_Pseudo 51 let Ins64 = !con(srcs, mods); 52 let InsVOP3Base = !con(dpp_srcs, mods); 53 let Asm64 = 54 "$vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$op_sel$op_sel_hi$clamp"; 55 let AsmVOP3DPPBase = Asm64; 56} 57 58multiclass VOP3PInst<string OpName, VOPProfile P, 59 SDPatternOperator node = null_frag, bit IsDOT = 0> { 60 def NAME : VOP3P_Pseudo<OpName, P, 61 !if (P.HasModifiers, 62 getVOP3PModPat<P, node, IsDOT, IsDOT>.ret, 63 getVOP3Pat<P, node>.ret)>; 64 let SubtargetPredicate = isGFX11Plus in { 65 if P.HasExtVOP3DPP then 66 def _dpp : VOP3_DPP_Pseudo<OpName, P> { 67 let VOP3P = 1; 68 let PseudoInstr = OpName #"_dpp"; 69 } 70 } // end SubtargetPredicate = isGFX11Plus 71} 72 73// Non-packed instructions that use the VOP3P encoding. 74// VOP3 neg/abs and VOP3P opsel/opsel_hi modifiers are allowed. 75multiclass VOP3_VOP3PInst<string OpName, VOP3P_Mix_Profile P> { 76 def NAME : VOP3P_Pseudo<OpName, P> { 77 let Constraints = !if(P.UseTiedOutput, "$vdst = $vdst_in", ""); 78 let DisableEncoding = !if(P.UseTiedOutput, "$vdst_in", ""); 79 } 80 let SubtargetPredicate = isGFX11Plus in { 81 if P.HasExtVOP3DPP then 82 def _dpp : VOP3_DPP_Pseudo<OpName, P> { 83 let VOP3P = 1; 84 let PseudoInstr = OpName#"_dpp"; 85 let Constraints = !if(P.UseTiedOutput, "$vdst = $vdst_in", ""); 86 let DisableEncoding = !if(P.UseTiedOutput, "$vdst_in", ""); 87 } 88 } // end SubtargetPredicate = isGFX11Plus 89} 90 91let isReMaterializable = 1 in { 92let isCommutable = 1 in { 93defm V_PK_MAD_I16 : VOP3PInst<"v_pk_mad_i16", VOP3P_Profile<VOP_V2I16_V2I16_V2I16_V2I16>>; 94defm V_PK_MAD_U16 : VOP3PInst<"v_pk_mad_u16", VOP3P_Profile<VOP_V2I16_V2I16_V2I16_V2I16>>; 95 96let FPDPRounding = 1 in { 97defm V_PK_FMA_F16 : VOP3PInst<"v_pk_fma_f16", VOP3P_Profile<VOP_V2F16_V2F16_V2F16_V2F16>, any_fma>; 98defm V_PK_ADD_F16 : VOP3PInst<"v_pk_add_f16", VOP3P_Profile<VOP_V2F16_V2F16_V2F16>, any_fadd>; 99defm V_PK_MUL_F16 : VOP3PInst<"v_pk_mul_f16", VOP3P_Profile<VOP_V2F16_V2F16_V2F16>, any_fmul>; 100} // End FPDPRounding = 1 101defm V_PK_MAX_F16 : VOP3PInst<"v_pk_max_f16", VOP3P_Profile<VOP_V2F16_V2F16_V2F16>, fmaxnum_like>; 102defm V_PK_MIN_F16 : VOP3PInst<"v_pk_min_f16", VOP3P_Profile<VOP_V2F16_V2F16_V2F16>, fminnum_like>; 103 104defm V_PK_ADD_U16 : VOP3PInst<"v_pk_add_u16", VOP3P_Profile<VOP_V2I16_V2I16_V2I16>, add>; 105defm V_PK_ADD_I16 : VOP3PInst<"v_pk_add_i16", VOP3P_Profile<VOP_V2I16_V2I16_V2I16>>; 106defm V_PK_MUL_LO_U16 : VOP3PInst<"v_pk_mul_lo_u16", VOP3P_Profile<VOP_V2I16_V2I16_V2I16>, mul>; 107 108defm V_PK_MIN_I16 : VOP3PInst<"v_pk_min_i16", VOP3P_Profile<VOP_V2I16_V2I16_V2I16>, smin>; 109defm V_PK_MIN_U16 : VOP3PInst<"v_pk_min_u16", VOP3P_Profile<VOP_V2I16_V2I16_V2I16>, umin>; 110defm V_PK_MAX_I16 : VOP3PInst<"v_pk_max_i16", VOP3P_Profile<VOP_V2I16_V2I16_V2I16>, smax>; 111defm V_PK_MAX_U16 : VOP3PInst<"v_pk_max_u16", VOP3P_Profile<VOP_V2I16_V2I16_V2I16>, umax>; 112} 113 114defm V_PK_SUB_U16 : VOP3PInst<"v_pk_sub_u16", VOP3P_Profile<VOP_V2I16_V2I16_V2I16>>; 115defm V_PK_SUB_I16 : VOP3PInst<"v_pk_sub_i16", VOP3P_Profile<VOP_V2I16_V2I16_V2I16>, sub>; 116 117defm V_PK_LSHLREV_B16 : VOP3PInst<"v_pk_lshlrev_b16", VOP3P_Profile<VOP_V2I16_V2I16_V2I16>, clshl_rev_16>; 118defm V_PK_ASHRREV_I16 : VOP3PInst<"v_pk_ashrrev_i16", VOP3P_Profile<VOP_V2I16_V2I16_V2I16>, cashr_rev_16>; 119defm V_PK_LSHRREV_B16 : VOP3PInst<"v_pk_lshrrev_b16", VOP3P_Profile<VOP_V2I16_V2I16_V2I16>, clshr_rev_16>; 120} // End isReMaterializable = 1 121 122let SubtargetPredicate = HasVOP3PInsts in { 123 124// Undo sub x, c -> add x, -c canonicalization since c is more likely 125// an inline immediate than -c. 126// The constant will be emitted as a mov, and folded later. 127// TODO: We could directly encode the immediate now 128def : GCNPat< 129 (add (v2i16 (VOP3PMods v2i16:$src0, i32:$src0_modifiers)), NegSubInlineConstV216:$src1), 130 (V_PK_SUB_U16 $src0_modifiers, $src0, SRCMODS.OP_SEL_1, NegSubInlineConstV216:$src1) 131>; 132 133// Integer operations with clamp bit set. 134class VOP3PSatPat<SDPatternOperator pat, Instruction inst> : GCNPat< 135 (pat (v2i16 (VOP3PMods v2i16:$src0, i32:$src0_modifiers)), 136 (v2i16 (VOP3PMods v2i16:$src1, i32:$src1_modifiers))), 137 (inst $src0_modifiers, $src0, $src1_modifiers, $src1, DSTCLAMP.ENABLE) 138>; 139 140def : VOP3PSatPat<uaddsat, V_PK_ADD_U16>; 141def : VOP3PSatPat<saddsat, V_PK_ADD_I16>; 142def : VOP3PSatPat<usubsat, V_PK_SUB_U16>; 143def : VOP3PSatPat<ssubsat, V_PK_SUB_I16>; 144} // End SubtargetPredicate = HasVOP3PInsts 145 146multiclass MadFmaMixPats<SDPatternOperator fma_like, 147 Instruction mixlo_inst, 148 Instruction mixhi_inst> { 149 def : GCNPat < 150 (f16 (fpround (fma_like (f32 (VOP3PMadMixMods f16:$src0, i32:$src0_modifiers)), 151 (f32 (VOP3PMadMixMods f16:$src1, i32:$src1_modifiers)), 152 (f32 (VOP3PMadMixMods f16:$src2, i32:$src2_modifiers))))), 153 (mixlo_inst $src0_modifiers, $src0, 154 $src1_modifiers, $src1, 155 $src2_modifiers, $src2, 156 DSTCLAMP.NONE, 157 (i32 (IMPLICIT_DEF))) 158 >; 159 160 // FIXME: Special case handling for maxhi (especially for clamp) 161 // because dealing with the write to high half of the register is 162 // difficult. 163 def : GCNPat < 164 (build_vector f16:$elt0, (fpround (fma_like (f32 (VOP3PMadMixMods f16:$src0, i32:$src0_modifiers)), 165 (f32 (VOP3PMadMixMods f16:$src1, i32:$src1_modifiers)), 166 (f32 (VOP3PMadMixMods f16:$src2, i32:$src2_modifiers))))), 167 (v2f16 (mixhi_inst $src0_modifiers, $src0, 168 $src1_modifiers, $src1, 169 $src2_modifiers, $src2, 170 DSTCLAMP.NONE, 171 $elt0)) 172 >; 173 174 def : GCNPat < 175 (build_vector 176 f16:$elt0, 177 (AMDGPUclamp (fpround (fma_like (f32 (VOP3PMadMixMods f16:$src0, i32:$src0_modifiers)), 178 (f32 (VOP3PMadMixMods f16:$src1, i32:$src1_modifiers)), 179 (f32 (VOP3PMadMixMods f16:$src2, i32:$src2_modifiers)))))), 180 (v2f16 (mixhi_inst $src0_modifiers, $src0, 181 $src1_modifiers, $src1, 182 $src2_modifiers, $src2, 183 DSTCLAMP.ENABLE, 184 $elt0)) 185 >; 186 187 def : GCNPat < 188 (AMDGPUclamp (build_vector 189 (fpround (fma_like (f32 (VOP3PMadMixMods f16:$lo_src0, i32:$lo_src0_modifiers)), 190 (f32 (VOP3PMadMixMods f16:$lo_src1, i32:$lo_src1_modifiers)), 191 (f32 (VOP3PMadMixMods f16:$lo_src2, i32:$lo_src2_modifiers)))), 192 (fpround (fma_like (f32 (VOP3PMadMixMods f16:$hi_src0, i32:$hi_src0_modifiers)), 193 (f32 (VOP3PMadMixMods f16:$hi_src1, i32:$hi_src1_modifiers)), 194 (f32 (VOP3PMadMixMods f16:$hi_src2, i32:$hi_src2_modifiers)))))), 195 (v2f16 (mixhi_inst $hi_src0_modifiers, $hi_src0, 196 $hi_src1_modifiers, $hi_src1, 197 $hi_src2_modifiers, $hi_src2, 198 DSTCLAMP.ENABLE, 199 (mixlo_inst $lo_src0_modifiers, $lo_src0, 200 $lo_src1_modifiers, $lo_src1, 201 $lo_src2_modifiers, $lo_src2, 202 DSTCLAMP.ENABLE, 203 (i32 (IMPLICIT_DEF))))) 204 >; 205} 206 207let SubtargetPredicate = HasMadMixInsts in { 208 209// These are VOP3a-like opcodes which accept no omod. 210// Size of src arguments (16/32) is controlled by op_sel. 211// For 16-bit src arguments their location (hi/lo) are controlled by op_sel_hi. 212let isCommutable = 1, mayRaiseFPException = 0 in { 213let isReMaterializable = 1 in 214defm V_MAD_MIX_F32 : VOP3_VOP3PInst<"v_mad_mix_f32", VOP3P_Mix_Profile<VOP_F32_F16_F16_F16, VOP3_OPSEL>>; 215 216let FPDPRounding = 1 in { 217// Clamp modifier is applied after conversion to f16. 218defm V_MAD_MIXLO_F16 : VOP3_VOP3PInst<"v_mad_mixlo_f16", VOP3P_Mix_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL, 1>>; 219 220let ClampLo = 0, ClampHi = 1 in { 221defm V_MAD_MIXHI_F16 : VOP3_VOP3PInst<"v_mad_mixhi_f16", VOP3P_Mix_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL, 1>>; 222} 223} // End FPDPRounding = 1 224} 225 226defm : MadFmaMixPats<fmad, V_MAD_MIXLO_F16, V_MAD_MIXHI_F16>; 227} // End SubtargetPredicate = HasMadMixInsts 228 229 230// Essentially the same as the mad_mix versions 231let SubtargetPredicate = HasFmaMixInsts in { 232let isCommutable = 1 in { 233 234let isReMaterializable = 1 in 235defm V_FMA_MIX_F32 : VOP3_VOP3PInst<"v_fma_mix_f32", VOP3P_Mix_Profile<VOP_F32_F16_F16_F16, VOP3_OPSEL>>; 236 237let FPDPRounding = 1 in { 238// Clamp modifier is applied after conversion to f16. 239defm V_FMA_MIXLO_F16 : VOP3_VOP3PInst<"v_fma_mixlo_f16", VOP3P_Mix_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL, 1>>; 240 241let ClampLo = 0, ClampHi = 1 in { 242defm V_FMA_MIXHI_F16 : VOP3_VOP3PInst<"v_fma_mixhi_f16", VOP3P_Mix_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL, 1>>; 243} 244} // End FPDPRounding = 1 245} 246 247defm : MadFmaMixPats<fma, V_FMA_MIXLO_F16, V_FMA_MIXHI_F16>; 248} 249 250// Defines patterns that extract signed 4bit from each Idx[0]. 251foreach Idx = [[0,28],[4,24],[8,20],[12,16],[16,12],[20,8],[24,4]] in 252 def ExtractSigned4bit_#Idx[0] : PatFrag<(ops node:$src), 253 (sra (shl node:$src, (i32 Idx[1])), (i32 28))>; 254 255// Defines code pattern that extracts U(unsigned/signed) 4/8bit from FromBitIndex. 256class Extract<int FromBitIndex, int BitMask, bit U>: PatFrag< 257 (ops node:$src), 258 !if (!or (!and (!eq (BitMask, 255), !eq (FromBitIndex, 24)), !eq (FromBitIndex, 28)), // last element 259 !if (U, (srl node:$src, (i32 FromBitIndex)), (sra node:$src, (i32 FromBitIndex))), 260 !if (!eq (FromBitIndex, 0), // first element 261 !if (U, (and node:$src, (i32 BitMask)), 262 !if (!eq (BitMask, 15), (!cast<PatFrag>("ExtractSigned4bit_"#FromBitIndex) node:$src), 263 (sext_inreg node:$src, i8))), 264 !if (U, (and (srl node:$src, (i32 FromBitIndex)), (i32 BitMask)), 265 !if (!eq (BitMask, 15), (!cast<PatFrag>("ExtractSigned4bit_"#FromBitIndex) node:$src), 266 (sext_inreg (srl node:$src, (i32 FromBitIndex)), i8)))))>; 267 268 269foreach Type = ["I", "U"] in 270 foreach Index = 0-3 in { 271 // Defines patterns that extract each Index'ed 8bit from an unsigned 272 // 32bit scalar value; 273 def Type#Index#"_8bit" : Extract<!shl(Index, 3), 255, !eq (Type, "U")>; 274 275 // Defines multiplication patterns where the multiplication is happening on each 276 // Index'ed 8bit of a 32bit scalar value. 277 278 def Mul#Type#_Elt#Index : PatFrag< 279 (ops node:$src0, node:$src1), 280 (!cast<HasOneUseBinOp>(!if (!eq (Type, "I"), AMDGPUmul_i24_oneuse, AMDGPUmul_u24_oneuse)) 281 (!cast<Extract>(Type#Index#"_8bit") node:$src0), 282 (!cast<Extract>(Type#Index#"_8bit") node:$src1))>; 283 } 284 285// Different variants of dot8 patterns cause a huge increase in the compile time. 286// Define non-associative/commutative add/mul to prevent permutation in the dot8 287// pattern. 288def NonACAdd : SDNode<"ISD::ADD" , SDTIntBinOp>; 289def NonACAdd_oneuse : HasOneUseBinOp<NonACAdd>; 290 291def NonACAMDGPUmul_u24 : SDNode<"AMDGPUISD::MUL_U24" , SDTIntBinOp>; 292def NonACAMDGPUmul_u24_oneuse : HasOneUseBinOp<NonACAMDGPUmul_u24>; 293 294def NonACAMDGPUmul_i24 : SDNode<"AMDGPUISD::MUL_I24" , SDTIntBinOp>; 295def NonACAMDGPUmul_i24_oneuse : HasOneUseBinOp<NonACAMDGPUmul_i24>; 296 297foreach Type = ["I", "U"] in 298 foreach Index = 0-7 in { 299 // Defines patterns that extract each Index'ed 4bit from an unsigned 300 // 32bit scalar value; 301 def Type#Index#"_4bit" : Extract<!shl(Index, 2), 15, !eq (Type, "U")>; 302 303 // Defines multiplication patterns where the multiplication is happening on each 304 // Index'ed 8bit of a 32bit scalar value. 305 def Mul#Type#Index#"_4bit" : PatFrag< 306 (ops node:$src0, node:$src1), 307 (!cast<HasOneUseBinOp>(!if (!eq (Type, "I"), NonACAMDGPUmul_i24_oneuse, NonACAMDGPUmul_u24_oneuse)) 308 (!cast<Extract>(Type#Index#"_4bit") node:$src0), 309 (!cast<Extract>(Type#Index#"_4bit") node:$src1))>; 310 } 311 312class UDot2Pat<Instruction Inst> : GCNPat < 313 (add (add_oneuse (AMDGPUmul_u24_oneuse (srl i32:$src0, (i32 16)), 314 (srl i32:$src1, (i32 16))), i32:$src2), 315 (AMDGPUmul_u24_oneuse (and i32:$src0, (i32 65535)), 316 (and i32:$src1, (i32 65535))) 317 ), 318 (Inst (i32 8), $src0, (i32 8), $src1, (i32 8), $src2, (i1 0))> { 319 let SubtargetPredicate = !cast<VOP_Pseudo>(Inst).SubtargetPredicate; 320} 321 322class SDot2Pat<Instruction Inst> : GCNPat < 323 (add (add_oneuse (AMDGPUmul_i24_oneuse (sra i32:$src0, (i32 16)), 324 (sra i32:$src1, (i32 16))), i32:$src2), 325 (AMDGPUmul_i24_oneuse (sext_inreg i32:$src0, i16), 326 (sext_inreg i32:$src1, i16))), 327 (Inst (i32 8), $src0, (i32 8), $src1, (i32 8), $src2, (i1 0))> { 328 let SubtargetPredicate = !cast<VOP_Pseudo>(Inst).SubtargetPredicate; 329} 330 331let IsDOT = 1 in { 332let SubtargetPredicate = HasDot2Insts in { 333 334defm V_DOT2_I32_I16 : VOP3PInst<"v_dot2_i32_i16", 335 VOP3P_Profile<VOP_I32_V2I16_V2I16_I32>, int_amdgcn_sdot2, 1>; 336defm V_DOT2_U32_U16 : VOP3PInst<"v_dot2_u32_u16", 337 VOP3P_Profile<VOP_I32_V2I16_V2I16_I32>, int_amdgcn_udot2, 1>; 338 339} // End SubtargetPredicate = HasDot2Insts 340 341let SubtargetPredicate = HasDot7Insts in { 342 343defm V_DOT2_F32_F16 : VOP3PInst<"v_dot2_f32_f16", 344 VOP3P_Profile<VOP_F32_V2F16_V2F16_F32, VOP3_REGULAR, /*HasDPP*/ 1>, 345 AMDGPUfdot2, 1/*ExplicitClamp*/>; 346defm V_DOT4_U32_U8 : VOP3PInst<"v_dot4_u32_u8", 347 VOP3P_Profile<VOP_I32_I32_I32_I32, VOP3_PACKED>, int_amdgcn_udot4, 1>; 348defm V_DOT8_U32_U4 : VOP3PInst<"v_dot8_u32_u4", 349 VOP3P_Profile<VOP_I32_I32_I32_I32, VOP3_PACKED>, int_amdgcn_udot8, 1>; 350 351} // End SubtargetPredicate = HasDot7Insts 352 353let SubtargetPredicate = HasDot1Insts in { 354 355defm V_DOT4_I32_I8 : VOP3PInst<"v_dot4_i32_i8", 356 VOP3P_Profile<VOP_I32_I32_I32_I32, VOP3_PACKED>, int_amdgcn_sdot4, 1>; 357defm V_DOT8_I32_I4 : VOP3PInst<"v_dot8_i32_i4", 358 VOP3P_Profile<VOP_I32_I32_I32_I32, VOP3_PACKED>, int_amdgcn_sdot8, 1>; 359 360} // End SubtargetPredicate = HasDot1Insts 361 362let SubtargetPredicate = HasDot8Insts in { 363 364defm V_DOT2_F32_BF16 : VOP3PInst<"v_dot2_f32_bf16", 365 VOP3P_Profile<VOP_F32_V2I16_V2I16_F32, VOP3_REGULAR, /*HasDPP*/ 1>, 366 int_amdgcn_fdot2_f32_bf16, 1>; 367 368} // End SubtargetPredicate = HasDot8Insts 369 370} // End let IsDOT = 1 371 372multiclass VOP3PDOTIUInst <string OpName, SDPatternOperator intrinsic_node> { 373 let IsDOT = 1 in 374 defm NAME : VOP3PInst<OpName, VOP3P_Profile<VOP_I32_I32_I32_I32, VOP3_PACKED>, 375 null_frag, 1>; 376 // Dot-iu instructions consider input as signed if imod neg bits are set. Thus 377 // Dot-iu Intrinsics have extra operands and require separate codegen pattern. 378 def : GCNPat < (intrinsic_node (DotIUVOP3PMods i32:$src0_mods), i32:$src0, 379 (DotIUVOP3PMods i32:$src1_mods), i32:$src1, 380 i32:$src2, (i1 timm:$clamp)), 381 (!cast<Instruction>(NAME) $src0_mods, i32:$src0, 382 $src1_mods, i32:$src1, 383 (i32 8), i32:$src2, i1:$clamp) 384 >; 385} 386 387let SubtargetPredicate = HasDot8Insts in { 388defm V_DOT4_I32_IU8 : VOP3PDOTIUInst<"v_dot4_i32_iu8", int_amdgcn_sudot4>; 389defm V_DOT8_I32_IU4 : VOP3PDOTIUInst<"v_dot8_i32_iu4", int_amdgcn_sudot8>; 390} // End SubtargetPredicate = HasDot8Insts 391 392def : UDot2Pat<V_DOT2_U32_U16>; 393def : SDot2Pat<V_DOT2_I32_I16>; 394 395foreach Type = ["U", "I"] in 396 let SubtargetPredicate = !cast<VOP_Pseudo>("V_DOT4_"#Type#"32_"#Type#8).SubtargetPredicate in 397 def : GCNPat < 398 !cast<dag>(!foldl((i32 i32:$src2), [0, 1, 2, 3], lhs, y, 399 (add_oneuse lhs, (!cast<PatFrag>("Mul"#Type#"_Elt"#y) i32:$src0, i32:$src1)))), 400 (!cast<VOP3P_Pseudo>("V_DOT4_"#Type#"32_"#Type#8) (i32 8), $src0, (i32 8), $src1, (i32 8), $src2, (i1 0))>; 401 402foreach Type = ["U", "I"] in 403 let SubtargetPredicate = !cast<VOP_Pseudo>("V_DOT8_"#Type#"32_"#Type#4).SubtargetPredicate in 404 def : GCNPat < 405 !cast<dag>(!foldl((add_oneuse i32:$src2, (!cast<PatFrag>("Mul"#Type#"0_4bit") i32:$src0, i32:$src1)), 406 [1, 2, 3, 4, 5, 6, 7], lhs, y, 407 (NonACAdd_oneuse lhs, (!cast<PatFrag>("Mul"#Type#y#"_4bit") i32:$src0, i32:$src1)))), 408 (!cast<VOP3P_Pseudo>("V_DOT8_"#Type#"32_"#Type#4) (i32 8), $src0, (i32 8), $src1, (i32 8), $src2, (i1 0))>; 409 410// Different variants of dot8 code-gen dag patterns are not generated through table-gen due to a huge increase 411// in the compile time. Directly handle the pattern generated by the FE here. 412foreach Type = ["U", "I"] in 413 let SubtargetPredicate = !cast<VOP_Pseudo>("V_DOT8_"#Type#"32_"#Type#4).SubtargetPredicate in 414 def : GCNPat < 415 !cast<dag>(!foldl((add_oneuse i32:$src2, (!cast<PatFrag>("Mul"#Type#"0_4bit") i32:$src0, i32:$src1)), 416 [7, 1, 2, 3, 4, 5, 6], lhs, y, 417 (NonACAdd_oneuse lhs, (!cast<PatFrag>("Mul"#Type#y#"_4bit") i32:$src0, i32:$src1)))), 418 (!cast<VOP3P_Pseudo>("V_DOT8_"#Type#"32_"#Type#4) (i32 8), $src0, (i32 8), $src1, (i32 8), $src2, (i1 0))>; 419 420def ADst_32 : VOPDstOperand<AGPR_32>; 421def ADst_64 : VOPDstOperand<AReg_64>; 422def ADst_128 : VOPDstOperand<AReg_128>; 423def ADst_256 : VOPDstOperand<AReg_256>; 424def ADst_512 : VOPDstOperand<AReg_512>; 425def ADst_1024 : VOPDstOperand<AReg_1024>; 426def VDst_64 : VOPDstOperand<VReg_64>; 427def VDst_128 : VOPDstOperand<VReg_128>; 428def VDst_256 : VOPDstOperand<VReg_256>; 429def VDst_512 : VOPDstOperand<VReg_512>; 430def VDst_1024 : VOPDstOperand<VReg_1024>; 431 432def VOPProfileAccRead : VOP3P_Profile<VOP_I32_I32, VOP3_MAI> { 433 let Src0RC64 = ARegSrc_32; 434} 435 436def VOPProfileAccWrite : VOP3P_Profile<VOP_I32_I32, VOP3_MAI> { 437 let DstRC = ADst_32; 438 let Src0RC64 = VCSrc_b32; 439} 440 441class VOPProfileMAI<VOPProfile P, RegisterOperand _SrcRC, RegisterOperand _DstRC, 442 RegisterOperand SrcABRC = AVSrc_32> 443 : VOP3P_Profile<P, VOP3_MAI> { 444 let DstRC = _DstRC; 445 let Src0RC64 = SrcABRC; 446 let Src1RC64 = SrcABRC; 447 let Src2RC64 = _SrcRC; 448 let HasOpSel = 0; 449 let HasClamp = 0; 450 let HasIntClamp = 0; 451 let HasOMod = 0; 452 let HasModifiers = 0; 453 let Asm64 = "$vdst, $src0, $src1, $src2$cbsz$abid$blgp"; 454 let AsmVOP3DPPBase = Asm64; 455 let Ins64 = (ins Src0RC64:$src0, Src1RC64:$src1, Src2RC64:$src2, cbsz:$cbsz, abid:$abid, blgp:$blgp); 456 let InsVOP3Base = Ins64; 457 // Dst and SrcC cannot partially overlap if SrcC/Dst is bigger than 4 VGPRs. 458 // We then create two versions of the instruction: with tied dst and src2 459 // and with the earlyclobber flag on the dst. This is stricter than the 460 // actual HW restriction. In particular earlyclobber also affects src0 and 461 // src1 allocation which is not required. 462 bit NoDstOverlap = !gt(DstVT.Size, 128); 463} 464 465class VOPProfileSMFMAC<VOPProfile P, RegisterOperand _DstRC, 466 RegisterOperand _SrcARC, RegisterOperand _SrcBRC> 467 : VOPProfileMAI<P, _DstRC, _DstRC, _SrcARC> { 468 let Src1RC64 = _SrcBRC; 469 let Src2VT = DstVT; 470 let Asm64 = " $vdst, $src0, $src1, $idx$cbsz$abid"; 471 let Outs64 = (outs DstRC:$vdst); 472 let Ins64 = (ins Src0RC64:$src0, Src1RC64:$src1, VRegSrc_32:$idx, cbsz:$cbsz, abid:$abid, Src2RC64:$src2); 473} 474 475def VOPProfileMAI_F32_F32_X4 : VOPProfileMAI<VOP_V4F32_F32_F32_V4F32, AISrc_128_f32, ADst_128>; 476def VOPProfileMAI_F32_F32_X16 : VOPProfileMAI<VOP_V16F32_F32_F32_V16F32, AISrc_512_f32, ADst_512>; 477def VOPProfileMAI_F32_F32_X32 : VOPProfileMAI<VOP_V32F32_F32_F32_V32F32, AISrc_1024_f32, ADst_1024>; 478def VOPProfileMAI_I32_I32_X4 : VOPProfileMAI<VOP_V4I32_I32_I32_V4I32, AISrc_128_b32, ADst_128>; 479def VOPProfileMAI_I32_I32_X16 : VOPProfileMAI<VOP_V16I32_I32_I32_V16I32, AISrc_512_b32, ADst_512>; 480def VOPProfileMAI_I32_I32_X32 : VOPProfileMAI<VOP_V32I32_I32_I32_V32I32, AISrc_1024_b32, ADst_1024>; 481def VOPProfileMAI_F32_V2I16_X4 : VOPProfileMAI<VOP_V4F32_V2I16_V2I16_V4F32, AISrc_128_b32, ADst_128>; 482def VOPProfileMAI_F32_V2I16_X16 : VOPProfileMAI<VOP_V16F32_V2I16_V2I16_V16F32, AISrc_512_b32, ADst_512>; 483def VOPProfileMAI_F32_V2I16_X32 : VOPProfileMAI<VOP_V32F32_V2I16_V2I16_V32F32, AISrc_1024_b32, ADst_1024>; 484def VOPProfileMAI_F32_V4F16_X4 : VOPProfileMAI<VOP_V4F32_V4F16_V4F16_V4F32, AISrc_128_b32, ADst_128, AVSrc_64>; 485def VOPProfileMAI_F32_V4F16_X16 : VOPProfileMAI<VOP_V16F32_V4F16_V4F16_V16F32, AISrc_512_b32, ADst_512, AVSrc_64>; 486def VOPProfileMAI_F32_V4F16_X32 : VOPProfileMAI<VOP_V32F32_V4F16_V4F16_V32F32, AISrc_1024_b32, ADst_1024, AVSrc_64>; 487def VOPProfileMAI_F32_V4I16_X4 : VOPProfileMAI<VOP_V4F32_V4I16_V4I16_V4F32, AISrc_128_b32, ADst_128, AVSrc_64>; 488def VOPProfileMAI_F32_V4I16_X16 : VOPProfileMAI<VOP_V16F32_V4I16_V4I16_V16F32, AISrc_512_b32, ADst_512, AVSrc_64>; 489def VOPProfileMAI_F32_V4I16_X32 : VOPProfileMAI<VOP_V32F32_V4I16_V4I16_V32F32, AISrc_1024_b32, ADst_1024, AVSrc_64>; 490def VOPProfileMAI_F64_16X16X4F64 : VOPProfileMAI<VOP_V4F64_F64_F64_V4F64, AISrc_256_f64, ADst_256, AVSrc_64>; 491def VOPProfileMAI_F64_4X4X4F64 : VOPProfileMAI<VOP_F64_F64_F64_F64, AISrc_64_f64, ADst_64, AVSrc_64>; 492def VOPProfileMAI_I32_I64_X16 : VOPProfileMAI<VOP_V4I32_I64_I64_V4I32, AISrc_128_b32, ADst_128, AVSrc_64>; 493def VOPProfileMAI_I32_I64_X32 : VOPProfileMAI<VOP_V16I32_I64_I64_V16I32, AISrc_512_b32, ADst_512, AVSrc_64>; 494def VOPProfileMAI_F32_V2F32_X16 : VOPProfileMAI<VOP_V4F32_V2F32_V2F32_V4F32, AISrc_128_b32, ADst_128, AVSrc_64>; 495def VOPProfileMAI_F32_V2F32_X32 : VOPProfileMAI<VOP_V16F32_V2F32_V2F32_V16F32, AISrc_512_b32, ADst_512, AVSrc_64>; 496def VOPProfileMAI_F32_I64_X32 : VOPProfileMAI<VOP_V4F32_I64_I64_V4F32, AISrc_128_b32, ADst_128, AVSrc_64>; 497def VOPProfileMAI_F32_I64_X16 : VOPProfileMAI<VOP_V16F32_I64_I64_V16F32, AISrc_512_b32, ADst_512, AVSrc_64>; 498 499def VOPProfileMAI_F32_F32_X4_VCD : VOPProfileMAI<VOP_V4F32_F32_F32_V4F32, VISrc_128_f32, VDst_128>; 500def VOPProfileMAI_F32_F32_X16_VCD : VOPProfileMAI<VOP_V16F32_F32_F32_V16F32, VISrc_512_f32, VDst_512>; 501def VOPProfileMAI_F32_F32_X32_VCD : VOPProfileMAI<VOP_V32F32_F32_F32_V32F32, VISrc_1024_f32, VDst_1024>; 502def VOPProfileMAI_I32_I32_X4_VCD : VOPProfileMAI<VOP_V4I32_I32_I32_V4I32, VISrc_128_b32, VDst_128>; 503def VOPProfileMAI_I32_I32_X16_VCD : VOPProfileMAI<VOP_V16I32_I32_I32_V16I32, VISrc_512_b32, VDst_512>; 504def VOPProfileMAI_I32_I32_X32_VCD : VOPProfileMAI<VOP_V32I32_I32_I32_V32I32, VISrc_1024_b32, VDst_1024>; 505def VOPProfileMAI_F32_V2I16_X4_VCD : VOPProfileMAI<VOP_V4F32_V2I16_V2I16_V4F32, VISrc_128_b32, VDst_128>; 506def VOPProfileMAI_F32_V2I16_X16_VCD : VOPProfileMAI<VOP_V16F32_V2I16_V2I16_V16F32, VISrc_512_b32, VDst_512>; 507def VOPProfileMAI_F32_V2I16_X32_VCD : VOPProfileMAI<VOP_V32F32_V2I16_V2I16_V32F32, VISrc_1024_b32, VDst_1024>; 508def VOPProfileMAI_F32_V4F16_X4_VCD : VOPProfileMAI<VOP_V4F32_V4F16_V4F16_V4F32, VISrc_128_b32, VDst_128, AVSrc_64>; 509def VOPProfileMAI_F32_V4F16_X16_VCD : VOPProfileMAI<VOP_V16F32_V4F16_V4F16_V16F32, VISrc_512_b32, VDst_512, AVSrc_64>; 510def VOPProfileMAI_F32_V4F16_X32_VCD : VOPProfileMAI<VOP_V32F32_V4F16_V4F16_V32F32, VISrc_1024_b32, VDst_1024, AVSrc_64>; 511def VOPProfileMAI_F32_V4I16_X4_VCD : VOPProfileMAI<VOP_V4F32_V4I16_V4I16_V4F32, VISrc_128_b32, VDst_128, AVSrc_64>; 512def VOPProfileMAI_F32_V4I16_X16_VCD : VOPProfileMAI<VOP_V16F32_V4I16_V4I16_V16F32, VISrc_512_b32, VDst_512, AVSrc_64>; 513def VOPProfileMAI_F32_V4I16_X32_VCD : VOPProfileMAI<VOP_V32F32_V4I16_V4I16_V32F32, VISrc_1024_b32, VDst_1024, AVSrc_64>; 514def VOPProfileMAI_F64_16X16X4F64_VCD : VOPProfileMAI<VOP_V4F64_F64_F64_V4F64, VISrc_256_f64, VDst_256, AVSrc_64>; 515def VOPProfileMAI_F64_4X4X4F64_VCD : VOPProfileMAI<VOP_F64_F64_F64_F64, VISrc_64_f64, VDst_64, AVSrc_64>; 516def VOPProfileMAI_I32_I64_X16_VCD : VOPProfileMAI<VOP_V4I32_I64_I64_V4I32, VISrc_128_b32, VDst_128, AVSrc_64>; 517def VOPProfileMAI_I32_I64_X32_VCD : VOPProfileMAI<VOP_V16I32_I64_I64_V16I32, VISrc_512_b32, VDst_512, AVSrc_64>; 518def VOPProfileMAI_F32_V2F32_X16_VCD : VOPProfileMAI<VOP_V4F32_V2F32_V2F32_V4F32, VISrc_128_b32, VDst_128, AVSrc_64>; 519def VOPProfileMAI_F32_V2F32_X32_VCD : VOPProfileMAI<VOP_V16F32_V2F32_V2F32_V16F32, VISrc_512_b32, VDst_512, AVSrc_64>; 520def VOPProfileMAI_F32_I64_X32_VCD : VOPProfileMAI<VOP_V4F32_I64_I64_V4F32, VISrc_128_b32, VDst_128, AVSrc_64>; 521def VOPProfileMAI_F32_I64_X16_VCD : VOPProfileMAI<VOP_V16F32_I64_I64_V16F32, VISrc_512_b32, VDst_512, AVSrc_64>; 522 523def VOPProfileSMFMAC_F32_16X16X32_F16 : VOPProfileSMFMAC<VOP_V4F32_V4F16_V8F16_I32, AVDst_128, AVSrc_64, AVSrc_128>; 524def VOPProfileSMFMAC_F32_32X32X16_F16 : VOPProfileSMFMAC<VOP_V16F32_V4F16_V8F16_I32, AVDst_512, AVSrc_64, AVSrc_128>; 525def VOPProfileSMFMAC_F32_16X16X32_I16 : VOPProfileSMFMAC<VOP_V4F32_V4I16_V8I16_I32, AVDst_128, AVSrc_64, AVSrc_128>; 526def VOPProfileSMFMAC_F32_32X32X16_I16 : VOPProfileSMFMAC<VOP_V16F32_V4I16_V8I16_I32, AVDst_512, AVSrc_64, AVSrc_128>; 527def VOPProfileSMFMAC_I32_16X16X64_I8 : VOPProfileSMFMAC<VOP_V4I32_V2I32_V4I32_I32, AVDst_128, AVSrc_64, AVSrc_128>; 528def VOPProfileSMFMAC_I32_32X32X32_I8 : VOPProfileSMFMAC<VOP_V16I32_V2I32_V4I32_I32, AVDst_512, AVSrc_64, AVSrc_128>; 529def VOPProfileSMFMAC_F32_16X16X64_F8 : VOPProfileSMFMAC<VOP_V4F32_V2I32_V4I32_I32, AVDst_128, AVSrc_64, AVSrc_128>; 530def VOPProfileSMFMAC_F32_32X32X32_F8 : VOPProfileSMFMAC<VOP_V16F32_V2I32_V4I32_I32, AVDst_512, AVSrc_64, AVSrc_128>; 531 532class MFMATable <bit is_mac, string Name> { 533 bit IsMac = is_mac; 534 string FMAOp = Name; 535} 536 537class MAIFrag<SDPatternOperator Op, code pred> : PatFrag < 538 (ops node:$src0, node:$src1, node:$src2, node:$cbsz, node:$abid, node:$blgp), 539 (Op $src0, $src1, $src2, $cbsz, $abid, $blgp), 540 pred 541>; 542 543let GISelPredicateCode = [{ return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); }] in 544class AgprMAIFrag<SDPatternOperator Op> : 545 MAIFrag<Op, [{ return MF->getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); }]>; 546 547let GISelPredicateCode = [{ return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); }] in 548class VgprMAIFrag<SDPatternOperator Op> : 549 MAIFrag<Op, [{ return !MF->getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); }]>; 550 551let Predicates = [HasMAIInsts] in { 552 553let isAsCheapAsAMove = 1, isReMaterializable = 1 in { 554 defm V_ACCVGPR_READ_B32 : VOP3Inst<"v_accvgpr_read_b32", VOPProfileAccRead>; 555 let isMoveImm = 1 in { 556 defm V_ACCVGPR_WRITE_B32 : VOP3Inst<"v_accvgpr_write_b32", VOPProfileAccWrite>; 557 } // End isMoveImm = 1 558} // End isAsCheapAsAMove = 1, isReMaterializable = 1 559 560class MAIInst<string OpName, VOPProfile P, SDPatternOperator node> 561 : VOP3InstBase<OpName, P, node> { 562 Instruction Opcode = !cast<Instruction>(NAME); 563 bit is_dgemm = 0; 564 bit is_gfx940_xdl = 0; 565} 566 567multiclass MAIInst<string OpName, string P, SDPatternOperator node, 568 bit NoDstOverlap = !cast<VOPProfileMAI>("VOPProfileMAI_" # P).NoDstOverlap> { 569 let isConvergent = 1, mayRaiseFPException = 0, ReadsModeReg = 1 in { 570 // FP32 denorm mode is respected, rounding mode is not. Exceptions are not supported. 571 let Constraints = !if(NoDstOverlap, "@earlyclobber $vdst", "") in { 572 def _e64 : MAIInst<OpName, !cast<VOPProfileMAI>("VOPProfileMAI_" # P), 573 !if(NoDstOverlap, null_frag, AgprMAIFrag<node>)>, 574 MFMATable<0, NAME # "_e64">; 575 576 let SubtargetPredicate = isGFX90APlus, Mnemonic = OpName in 577 def _vgprcd_e64 : MAIInst<OpName # "_vgprcd", !cast<VOPProfileMAI>("VOPProfileMAI_" # P # "_VCD"), 578 !if(NoDstOverlap, null_frag, VgprMAIFrag<node>)>, 579 MFMATable<0, NAME # "_vgprcd_e64">; 580 } 581 582 foreach _ = BoolToList<NoDstOverlap>.ret in { 583 let Constraints = !if(NoDstOverlap, "$vdst = $src2", ""), 584 isConvertibleToThreeAddress = NoDstOverlap, 585 Mnemonic = OpName in { 586 def "_mac_e64" : MAIInst<OpName # "_mac", !cast<VOPProfileMAI>("VOPProfileMAI_" # P), AgprMAIFrag<node>>, 587 MFMATable<1, NAME # "_e64">; 588 589 let SubtargetPredicate = isGFX90APlus in 590 def _mac_vgprcd_e64 : MAIInst<OpName # "_mac_vgprcd", !cast<VOPProfileMAI>("VOPProfileMAI_" # P # "_VCD"), 591 VgprMAIFrag<node>>, 592 MFMATable<1, NAME # "_vgprcd_e64">; 593 } 594 } 595 } // End isConvergent = 1, mayRaiseFPException = 0, ReadsModeReg = 1 596} 597 598defm V_MFMA_F32_4X4X1F32 : MAIInst<"v_mfma_f32_4x4x1f32", "F32_F32_X4", int_amdgcn_mfma_f32_4x4x1f32>; 599defm V_MFMA_F32_16X16X1F32 : MAIInst<"v_mfma_f32_16x16x1f32", "F32_F32_X16", int_amdgcn_mfma_f32_16x16x1f32>; 600defm V_MFMA_F32_16X16X4F32 : MAIInst<"v_mfma_f32_16x16x4f32", "F32_F32_X4", int_amdgcn_mfma_f32_16x16x4f32>; 601defm V_MFMA_F32_32X32X1F32 : MAIInst<"v_mfma_f32_32x32x1f32", "F32_F32_X32", int_amdgcn_mfma_f32_32x32x1f32>; 602defm V_MFMA_F32_32X32X2F32 : MAIInst<"v_mfma_f32_32x32x2f32", "F32_F32_X16", int_amdgcn_mfma_f32_32x32x2f32>; 603 604let is_gfx940_xdl = 1 in { 605defm V_MFMA_F32_4X4X4F16 : MAIInst<"v_mfma_f32_4x4x4f16", "F32_V4F16_X4", int_amdgcn_mfma_f32_4x4x4f16>; 606defm V_MFMA_I32_4X4X4I8 : MAIInst<"v_mfma_i32_4x4x4i8", "I32_I32_X4", int_amdgcn_mfma_i32_4x4x4i8>; 607defm V_MFMA_F32_16X16X4F16 : MAIInst<"v_mfma_f32_16x16x4f16", "F32_V4F16_X16", int_amdgcn_mfma_f32_16x16x4f16>; 608defm V_MFMA_F32_16X16X16F16 : MAIInst<"v_mfma_f32_16x16x16f16", "F32_V4F16_X4", int_amdgcn_mfma_f32_16x16x16f16>; 609defm V_MFMA_I32_16X16X4I8 : MAIInst<"v_mfma_i32_16x16x4i8", "I32_I32_X16", int_amdgcn_mfma_i32_16x16x4i8>; 610defm V_MFMA_F32_32X32X4F16 : MAIInst<"v_mfma_f32_32x32x4f16", "F32_V4F16_X32", int_amdgcn_mfma_f32_32x32x4f16>; 611defm V_MFMA_F32_32X32X8F16 : MAIInst<"v_mfma_f32_32x32x8f16", "F32_V4F16_X16", int_amdgcn_mfma_f32_32x32x8f16>; 612defm V_MFMA_I32_32X32X4I8 : MAIInst<"v_mfma_i32_32x32x4i8", "I32_I32_X32", int_amdgcn_mfma_i32_32x32x4i8>; 613} 614 615let Predicates = [isGFX908orGFX90A] in { 616defm V_MFMA_I32_16X16X16I8 : MAIInst<"v_mfma_i32_16x16x16i8", "I32_I32_X4", int_amdgcn_mfma_i32_16x16x16i8>; 617defm V_MFMA_I32_32X32X8I8 : MAIInst<"v_mfma_i32_32x32x8i8", "I32_I32_X16", int_amdgcn_mfma_i32_32x32x8i8>; 618defm V_MFMA_F32_4X4X2BF16 : MAIInst<"v_mfma_f32_4x4x2bf16", "F32_V2I16_X4", int_amdgcn_mfma_f32_4x4x2bf16>; 619defm V_MFMA_F32_16X16X2BF16 : MAIInst<"v_mfma_f32_16x16x2bf16", "F32_V2I16_X16", int_amdgcn_mfma_f32_16x16x2bf16>; 620defm V_MFMA_F32_16X16X8BF16 : MAIInst<"v_mfma_f32_16x16x8bf16", "F32_V2I16_X4", int_amdgcn_mfma_f32_16x16x8bf16>; 621defm V_MFMA_F32_32X32X2BF16 : MAIInst<"v_mfma_f32_32x32x2bf16", "F32_V2I16_X32", int_amdgcn_mfma_f32_32x32x2bf16>; 622defm V_MFMA_F32_32X32X4BF16 : MAIInst<"v_mfma_f32_32x32x4bf16", "F32_V2I16_X16", int_amdgcn_mfma_f32_32x32x4bf16>; 623} 624 625} // End SubtargetPredicate = HasMAIInsts 626 627let Predicates = [isGFX90APlus] in { 628 let is_gfx940_xdl = 1 in { 629 defm V_MFMA_F32_32X32X4BF16_1K : MAIInst<"v_mfma_f32_32x32x4bf16_1k", "F32_V4I16_X32", int_amdgcn_mfma_f32_32x32x4bf16_1k>; 630 defm V_MFMA_F32_16X16X4BF16_1K : MAIInst<"v_mfma_f32_16x16x4bf16_1k", "F32_V4I16_X16", int_amdgcn_mfma_f32_16x16x4bf16_1k>; 631 defm V_MFMA_F32_4X4X4BF16_1K : MAIInst<"v_mfma_f32_4x4x4bf16_1k", "F32_V4I16_X4", int_amdgcn_mfma_f32_4x4x4bf16_1k>; 632 defm V_MFMA_F32_32X32X8BF16_1K : MAIInst<"v_mfma_f32_32x32x8bf16_1k", "F32_V4I16_X16", int_amdgcn_mfma_f32_32x32x8bf16_1k>; 633 defm V_MFMA_F32_16X16X16BF16_1K : MAIInst<"v_mfma_f32_16x16x16bf16_1k", "F32_V4I16_X4", int_amdgcn_mfma_f32_16x16x16bf16_1k>; 634 } 635 636 let is_dgemm = 1 in { 637 defm V_MFMA_F64_16X16X4F64 : MAIInst<"v_mfma_f64_16x16x4f64", "F64_16X16X4F64", int_amdgcn_mfma_f64_16x16x4f64>; 638 defm V_MFMA_F64_4X4X4F64 : MAIInst<"v_mfma_f64_4x4x4f64", "F64_4X4X4F64", int_amdgcn_mfma_f64_4x4x4f64>; 639 } 640} // End Predicates = [isGFX90APlus] 641 642let Predicates = [isGFX940Plus], is_gfx940_xdl = 1 in { 643 defm V_MFMA_I32_32X32X16I8 : MAIInst<"v_mfma_i32_32x32x16i8", "I32_I64_X32", int_amdgcn_mfma_i32_32x32x16_i8>; 644 defm V_MFMA_I32_16X16X32I8 : MAIInst<"v_mfma_i32_16x16x32i8", "I32_I64_X16", int_amdgcn_mfma_i32_16x16x32_i8>; 645 defm V_MFMA_F32_16X16X8XF32 : MAIInst<"v_mfma_f32_16x16x8xf32", "F32_V2F32_X16", int_amdgcn_mfma_f32_16x16x8_xf32>; 646 defm V_MFMA_F32_32X32X4XF32 : MAIInst<"v_mfma_f32_32x32x4xf32", "F32_V2F32_X32", int_amdgcn_mfma_f32_32x32x4_xf32>; 647 defm V_MFMA_F32_16X16X32_BF8_BF8 : MAIInst<"v_mfma_f32_16x16x32_bf8_bf8", "F32_I64_X32", int_amdgcn_mfma_f32_16x16x32_bf8_bf8>; 648 defm V_MFMA_F32_16X16X32_BF8_FP8 : MAIInst<"v_mfma_f32_16x16x32_bf8_fp8", "F32_I64_X32", int_amdgcn_mfma_f32_16x16x32_bf8_fp8>; 649 defm V_MFMA_F32_16X16X32_FP8_BF8 : MAIInst<"v_mfma_f32_16x16x32_fp8_bf8", "F32_I64_X32", int_amdgcn_mfma_f32_16x16x32_fp8_bf8>; 650 defm V_MFMA_F32_16X16X32_FP8_FP8 : MAIInst<"v_mfma_f32_16x16x32_fp8_fp8", "F32_I64_X32", int_amdgcn_mfma_f32_16x16x32_fp8_fp8>; 651 defm V_MFMA_F32_32X32X16_BF8_BF8 : MAIInst<"v_mfma_f32_32x32x16_bf8_bf8", "F32_I64_X16", int_amdgcn_mfma_f32_32x32x16_bf8_bf8>; 652 defm V_MFMA_F32_32X32X16_BF8_FP8 : MAIInst<"v_mfma_f32_32x32x16_bf8_fp8", "F32_I64_X16", int_amdgcn_mfma_f32_32x32x16_bf8_fp8>; 653 defm V_MFMA_F32_32X32X16_FP8_BF8 : MAIInst<"v_mfma_f32_32x32x16_fp8_bf8", "F32_I64_X16", int_amdgcn_mfma_f32_32x32x16_fp8_bf8>; 654 defm V_MFMA_F32_32X32X16_FP8_FP8 : MAIInst<"v_mfma_f32_32x32x16_fp8_fp8", "F32_I64_X16", int_amdgcn_mfma_f32_32x32x16_fp8_fp8>; 655} // End Predicates = [isGFX940Plus], is_gfx940_xdl = 1 656 657multiclass SMFMACInst<string OpName, string P, SDPatternOperator node> { 658 let Constraints = "$vdst = $src2", DisableEncoding = "$src2", 659 isConvergent = 1, mayRaiseFPException = 0, ReadsModeReg = 1, is_gfx940_xdl = 1 in { 660 def _e64 : MAIInst<OpName, !cast<VOPProfileSMFMAC>("VOPProfileSMFMAC_" # P), node>; 661 } 662} 663 664let SubtargetPredicate = isGFX940Plus in { 665defm V_SMFMAC_F32_16X16X32_F16 : SMFMACInst<"v_smfmac_f32_16x16x32_f16", "F32_16X16X32_F16", int_amdgcn_smfmac_f32_16x16x32_f16>; 666defm V_SMFMAC_F32_32X32X16_F16 : SMFMACInst<"v_smfmac_f32_32x32x16_f16", "F32_32X32X16_F16", int_amdgcn_smfmac_f32_32x32x16_f16>; 667defm V_SMFMAC_F32_16X16X32_BF16 : SMFMACInst<"v_smfmac_f32_16x16x32_bf16", "F32_16X16X32_I16", int_amdgcn_smfmac_f32_16x16x32_bf16>; 668defm V_SMFMAC_F32_32X32X16_BF16 : SMFMACInst<"v_smfmac_f32_32x32x16_bf16", "F32_32X32X16_I16", int_amdgcn_smfmac_f32_32x32x16_bf16>; 669defm V_SMFMAC_I32_16X16X64_I8 : SMFMACInst<"v_smfmac_i32_16x16x64_i8", "I32_16X16X64_I8", int_amdgcn_smfmac_i32_16x16x64_i8>; 670defm V_SMFMAC_I32_32X32X32_I8 : SMFMACInst<"v_smfmac_i32_32x32x32_i8", "I32_32X32X32_I8", int_amdgcn_smfmac_i32_32x32x32_i8>; 671defm V_SMFMAC_F32_16X16X64_BF8_BF8 : SMFMACInst<"v_smfmac_f32_16x16x64_bf8_bf8", "F32_16X16X64_F8", int_amdgcn_smfmac_f32_16x16x64_bf8_bf8>; 672defm V_SMFMAC_F32_16X16X64_BF8_FP8 : SMFMACInst<"v_smfmac_f32_16x16x64_bf8_fp8", "F32_16X16X64_F8", int_amdgcn_smfmac_f32_16x16x64_bf8_fp8>; 673defm V_SMFMAC_F32_16X16X64_FP8_BF8 : SMFMACInst<"v_smfmac_f32_16x16x64_fp8_bf8", "F32_16X16X64_F8", int_amdgcn_smfmac_f32_16x16x64_fp8_bf8>; 674defm V_SMFMAC_F32_16X16X64_FP8_FP8 : SMFMACInst<"v_smfmac_f32_16x16x64_fp8_fp8", "F32_16X16X64_F8", int_amdgcn_smfmac_f32_16x16x64_fp8_fp8>; 675defm V_SMFMAC_F32_32X32X32_BF8_BF8 : SMFMACInst<"v_smfmac_f32_32x32x32_bf8_bf8", "F32_32X32X32_F8", int_amdgcn_smfmac_f32_32x32x32_bf8_bf8>; 676defm V_SMFMAC_F32_32X32X32_BF8_FP8 : SMFMACInst<"v_smfmac_f32_32x32x32_bf8_fp8", "F32_32X32X32_F8", int_amdgcn_smfmac_f32_32x32x32_bf8_fp8>; 677defm V_SMFMAC_F32_32X32X32_FP8_BF8 : SMFMACInst<"v_smfmac_f32_32x32x32_fp8_bf8", "F32_32X32X32_F8", int_amdgcn_smfmac_f32_32x32x32_fp8_bf8>; 678defm V_SMFMAC_F32_32X32X32_FP8_FP8 : SMFMACInst<"v_smfmac_f32_32x32x32_fp8_fp8", "F32_32X32X32_F8", int_amdgcn_smfmac_f32_32x32x32_fp8_fp8>; 679} 680 681def MAIInstInfoTable : GenericTable { 682 let FilterClass = "MAIInst"; 683 let CppTypeName = "MAIInstInfo"; 684 let Fields = [ 685 "Opcode", "is_dgemm", "is_gfx940_xdl" 686 ]; 687 688 let PrimaryKey = ["Opcode"]; 689 let PrimaryKeyName = "getMAIInstInfoHelper"; 690} 691 692let SubtargetPredicate = HasPackedFP32Ops, isCommutable = 1, isReMaterializable = 1 in { 693 defm V_PK_FMA_F32 : VOP3PInst<"v_pk_fma_f32", VOP3P_Profile<VOP_V2F32_V2F32_V2F32_V2F32, VOP3_PACKED>, any_fma>; 694 defm V_PK_MUL_F32 : VOP3PInst<"v_pk_mul_f32", VOP3P_Profile<VOP_V2F32_V2F32_V2F32, VOP3_PACKED>, any_fmul>; 695 defm V_PK_ADD_F32 : VOP3PInst<"v_pk_add_f32", VOP3P_Profile<VOP_V2F32_V2F32_V2F32, VOP3_PACKED>, any_fadd>; 696 defm V_PK_MOV_B32 : VOP3PInst<"v_pk_mov_b32", VOP3P_Profile<VOP_V2I32_V2I32_V2I32, VOP3_PACKED>>; 697} // End SubtargetPredicate = HasPackedFP32Ops, isCommutable = 1 698 699def : MnemonicAlias<"v_accvgpr_read", "v_accvgpr_read_b32">; 700def : MnemonicAlias<"v_accvgpr_write", "v_accvgpr_write_b32">; 701 702class VOPProfileWMMA<VOPProfile P, string Suffix, RegisterOperand _Src01RC64, bit _HasClamp, bit _HasOpSel> : VOP3P_Profile<P> { 703 let DstRC = !if(!eq(Suffix, "_w32"), VDst_256, VDst_128); 704 let Src0RC64 = _Src01RC64; 705 let Src1RC64 = _Src01RC64; 706 let Src2RC64 = !if(!eq(Suffix, "_w32"), VISrc_256_f64, VISrc_128_f32); 707 let HasClamp = _HasClamp; 708 let HasOpSel = _HasOpSel; 709 let IsPacked = 1; 710 let IsWMMA = 1; 711} 712 713def VOP_V8F32_V16F16_V16F16_V8F32 : VOPProfile <[v8f32, v16f16, v16f16, v8f32]>; 714def VOP_V8F32_V16I16_V16I16_V8F32 : VOPProfile <[v8f32, v16i16, v16i16, v8f32]>; 715def VOP_V16F16_V16F16_V16F16_V16F16 : VOPProfile <[v16f16, v16f16, v16f16, v16f16]>; 716def VOP_V16I16_V16I16_V16I16_V16I16 : VOPProfile <[v16i16, v16i16, v16i16, v16i16]>; 717def VOP_V8I32_V4I32_V4I32_V8I32 : VOPProfile <[v8i32, v4i32, v4i32, v8i32]>; 718def VOP_V8I32_V2I32_V2I32_V8I32 : VOPProfile <[v8i32, v2i32, v2i32, v8i32]>; 719 720def VOP_V4F32_V16F16_V16F16_V4F32 : VOPProfile <[v4f32, v16f16, v16f16, v4f32]>; 721def VOP_V4F32_V16I16_V16I16_V4F32 : VOPProfile <[v4f32, v16i16, v16i16, v4f32]>; 722def VOP_V8F16_V16F16_V16F16_V8F16 : VOPProfile <[v8f16, v16f16, v16f16, v8f16]>; 723def VOP_V8I16_V16I16_V16I16_V8I16 : VOPProfile <[v8i16, v16i16, v16i16, v8i16]>; 724def VOP_V4I32_V4I32_V4I32_V4I32 : VOPProfile <[v4i32, v4i32, v4i32, v4i32]>; 725def VOP_V4I32_V2I32_V2I32_V4I32 : VOPProfile <[v4i32, v2i32, v2i32, v4i32]>; 726 727 728class WMMAType <bits<2> val> { 729 bit hasClamp = val{0}; 730 bit hasOpsel = val{1}; 731} 732 733def WMMARegular : WMMAType<0b00>; 734def WMMAUIClamp : WMMAType<0b01>; 735def WMMAOpSel : WMMAType<0b10>; 736 737class WMMARegularPat<Instruction Inst, SDPatternOperator node, VOPProfile P> : 738 GCNPat < (P.DstVT (node 739 (P.Src0VT (VOP3PMods P.Src0VT:$src0, i32:$src0_modifiers)), 740 (P.Src1VT (VOP3PMods P.Src1VT:$src1, i32:$src1_modifiers)), 741 (P.Src2VT (VOP3PMods P.Src2VT:$src2, i32:$src2_modifiers)) 742 )), 743 (P.DstVT (Inst i32:$src0_modifiers, P.Src0VT:$src0, i32:$src1_modifiers, P.Src1VT:$src1, $src2_modifiers, P.Src2VT:$src2)) 744>; 745 746class WMMAOpSelPat<Instruction Inst, SDPatternOperator node, VOPProfile P> : 747 GCNPat < (P.DstVT (node 748 (P.Src0VT P.Src0VT:$src0), 749 (P.Src1VT P.Src1VT:$src1), 750 (P.Src2VT P.Src2VT:$src2), (WMMAOpSelVOP3PMods i32:$src2_modifiers) 751 )), 752 (P.DstVT (Inst (i32 8), P.Src0VT:$src0, (i32 8), P.Src1VT:$src1, i32:$src2_modifiers, P.Src2VT:$src2)) 753>; 754 755class WMMAUIClampPat<Instruction Inst, SDPatternOperator node, VOPProfile P> : 756 GCNPat < (P.DstVT (node 757 (DotIUVOP3PMods i32:$src0_modifiers), (P.Src0VT P.Src0VT:$src0), 758 (DotIUVOP3PMods i32:$src1_modifiers), (P.Src1VT P.Src1VT:$src1), 759 (P.Src2VT P.Src2VT:$src2), (i1 timm:$clamp) 760 )), 761 (P.DstVT (Inst i32:$src0_modifiers, P.Src0VT:$src0, i32:$src1_modifiers, P.Src1VT:$src1, (i32 8), P.Src2VT:$src2, i1:$clamp)) 762>; 763 764class WMMAOpcodeMapping<Instruction TwoAddr, Instruction ThreeAddr> { 765 Instruction Opcode2Addr = TwoAddr; 766 Instruction Opcode3Addr = ThreeAddr; 767 Predicate WaveSizePredicate; 768} 769 770def WMMAOpcode : GenericEnum { 771 let FilterClass = "VOP3P_Pseudo"; 772} 773 774class WMMAMappingTable : GenericTable { 775 let FilterClass = "WMMAOpcodeMapping"; 776 let CppTypeName = "WMMAOpcodeMappingInfo"; 777 let Fields = ["Opcode2Addr", "Opcode3Addr"]; 778 string TypeOf_Opcode2Addr = "WMMAOpcode"; 779 string TypeOf_Opcode3Addr = "WMMAOpcode"; 780} 781 782def WMMAOpcode2AddrMappingTable : WMMAMappingTable { 783 let PrimaryKey = ["Opcode2Addr"]; 784 let PrimaryKeyName = "getWMMAMappingInfoFrom2AddrOpcode"; 785} 786 787def WMMAOpcode3AddrMappingTable : WMMAMappingTable { 788 let PrimaryKey = ["Opcode3Addr"]; 789 let PrimaryKeyName = "getWMMAMappingInfoFrom3AddrOpcode"; 790} 791 792// The WMMA instruction has extra constraints: 793// Matrices A and B cannot overlap with D. C cannot partially overlap with D, 794// but it is OK for them to be the same (which is a typical case). 795// 796// We implement it as follows: 797// 1) Map the intrinsic to the pseudo where D is tied to C ($vdst = $src2). 798// 2) The pass twoaddressinstruction checks if src2 is live and if that is the case 799// it converts the default pseudo to the pseudo where src2 is not the same as vdst. 800// 3) @earlyclobber on the destination satisfies the constraint during RA. 801 802multiclass WMMAInst<string Suffix, string Instr, VOPProfile P, SDPatternOperator node = null_frag, RegisterOperand _Src01RC64 = VRegSrc_256, WMMAType Type> { 803 804 defvar WMMAConstraints2Addr = "@earlyclobber $vdst,$vdst = $src2"; 805 defvar WMMAConstraints3Addr = "@earlyclobber $vdst"; 806 807 defvar WMMAProfile = VOPProfileWMMA<P, Suffix, _Src01RC64, Type.hasClamp, Type.hasOpsel>; 808 if !eq(Suffix, "_w32") then { 809 let Mnemonic = Instr, mayRaiseFPException = 0, ReadsModeReg = 0 in { 810 let Constraints = WMMAConstraints2Addr, isConvertibleToThreeAddress = 1 in { 811 def _twoaddr_w32 : VOP3P_Pseudo<Instr # Suffix, WMMAProfile>; 812 } 813 let Constraints = WMMAConstraints3Addr, SchedRW = [Write32Bit, Write32Bit] in { 814 def _threeaddr_w32 : VOP3P_Pseudo<Instr # Suffix, WMMAProfile>; 815 } 816 } 817 def : WMMAOpcodeMapping<!cast<Instruction>(NAME # _twoaddr_w32), 818 !cast<Instruction>(NAME # _threeaddr_w32)>; 819 } else if !eq(Suffix, "_w64") then { 820 let Mnemonic = Instr, mayRaiseFPException = 0, ReadsModeReg = 0 in { 821 let Constraints = WMMAConstraints2Addr, isConvertibleToThreeAddress = 1 in { 822 def _twoaddr_w64 : VOP3P_Pseudo<Instr # Suffix, WMMAProfile>; 823 } 824 let Constraints = WMMAConstraints3Addr, SchedRW = [Write32Bit, Write32Bit] in { 825 def _threeaddr_w64 : VOP3P_Pseudo<Instr # Suffix, WMMAProfile>; 826 } 827 } 828 def : WMMAOpcodeMapping<!cast<Instruction>(NAME # _twoaddr_w64), 829 !cast<Instruction>(NAME # _threeaddr_w64)>; 830 } 831 832 if !eq(Type, WMMAOpSel) then { 833 def : WMMAOpSelPat<!cast<Instruction>(NAME # _twoaddr # Suffix), node, P>; 834 } else if !eq(Type, WMMAUIClamp) then { 835 def : WMMAUIClampPat<!cast<Instruction>(NAME # _twoaddr # Suffix), node, P>; 836 } else { 837 def : WMMARegularPat<!cast<Instruction>(NAME # _twoaddr # Suffix), node, P>; 838 } 839} 840 841 842let WaveSizePredicate = isWave32 in { 843 defm V_WMMA_F32_16X16X16_F16 : WMMAInst<"_w32", "v_wmma_f32_16x16x16_f16", VOP_V8F32_V16F16_V16F16_V8F32, int_amdgcn_wmma_f32_16x16x16_f16, VRegSrc_256, WMMARegular>; 844 defm V_WMMA_F32_16X16X16_BF16 : WMMAInst<"_w32", "v_wmma_f32_16x16x16_bf16", VOP_V8F32_V16I16_V16I16_V8F32, int_amdgcn_wmma_f32_16x16x16_bf16, VRegSrc_256, WMMARegular>; 845 defm V_WMMA_F16_16X16X16_F16 : WMMAInst<"_w32", "v_wmma_f16_16x16x16_f16", VOP_V16F16_V16F16_V16F16_V16F16, int_amdgcn_wmma_f16_16x16x16_f16, VRegSrc_256, WMMAOpSel>; 846 defm V_WMMA_BF16_16X16X16_BF16 : WMMAInst<"_w32", "v_wmma_bf16_16x16x16_bf16", VOP_V16I16_V16I16_V16I16_V16I16, int_amdgcn_wmma_bf16_16x16x16_bf16, VRegSrc_256, WMMAOpSel>; 847 defm V_WMMA_I32_16X16X16_IU8 : WMMAInst<"_w32", "v_wmma_i32_16x16x16_iu8", VOP_V8I32_V4I32_V4I32_V8I32, int_amdgcn_wmma_i32_16x16x16_iu8, VRegSrc_128, WMMAUIClamp>; 848 defm V_WMMA_I32_16X16X16_IU4 : WMMAInst<"_w32", "v_wmma_i32_16x16x16_iu4", VOP_V8I32_V2I32_V2I32_V8I32, int_amdgcn_wmma_i32_16x16x16_iu4, VRegSrc_64, WMMAUIClamp>; 849} 850 851let WaveSizePredicate = isWave64 in { 852 defm V_WMMA_F32_16X16X16_F16 : WMMAInst<"_w64", "v_wmma_f32_16x16x16_f16", VOP_V4F32_V16F16_V16F16_V4F32, int_amdgcn_wmma_f32_16x16x16_f16, VRegSrc_256, WMMARegular>; 853 defm V_WMMA_F32_16X16X16_BF16 : WMMAInst<"_w64", "v_wmma_f32_16x16x16_bf16", VOP_V4F32_V16I16_V16I16_V4F32, int_amdgcn_wmma_f32_16x16x16_bf16, VRegSrc_256, WMMARegular>; 854 defm V_WMMA_F16_16X16X16_F16 : WMMAInst<"_w64", "v_wmma_f16_16x16x16_f16", VOP_V8F16_V16F16_V16F16_V8F16, int_amdgcn_wmma_f16_16x16x16_f16, VRegSrc_256, WMMAOpSel>; 855 defm V_WMMA_BF16_16X16X16_BF16 : WMMAInst<"_w64", "v_wmma_bf16_16x16x16_bf16", VOP_V8I16_V16I16_V16I16_V8I16, int_amdgcn_wmma_bf16_16x16x16_bf16, VRegSrc_256, WMMAOpSel>; 856 defm V_WMMA_I32_16X16X16_IU8 : WMMAInst<"_w64", "v_wmma_i32_16x16x16_iu8", VOP_V4I32_V4I32_V4I32_V4I32, int_amdgcn_wmma_i32_16x16x16_iu8, VRegSrc_128, WMMAUIClamp>; 857 defm V_WMMA_I32_16X16X16_IU4 : WMMAInst<"_w64", "v_wmma_i32_16x16x16_iu4", VOP_V4I32_V2I32_V2I32_V4I32, int_amdgcn_wmma_i32_16x16x16_iu4, VRegSrc_64, WMMAUIClamp>; 858 859} 860 861//===----------------------------------------------------------------------===// 862// Begin Real Encodings 863//===----------------------------------------------------------------------===// 864 865class VOP3P_DPP16<bits<7> op, VOP_DPP_Pseudo ps, int subtarget, 866 string opName = ps.OpName> 867 : VOP3P_DPP<op, opName, ps.Pfl, 1>, SIMCInstr<ps.PseudoInstr, subtarget> { 868 let hasSideEffects = ps.hasSideEffects; 869 let Defs = ps.Defs; 870 let SchedRW = ps.SchedRW; 871 let Uses = ps.Uses; 872 let AssemblerPredicate = HasDPP16; 873 let SubtargetPredicate = HasDPP16; 874 let OtherPredicates = ps.OtherPredicates; 875} 876 877class VOP3P_DPP8_Base<bits<7> op, VOP_Pseudo ps, string opName = ps.OpName> 878 : VOP3P_DPP8<op, opName, ps.Pfl> { 879 let hasSideEffects = ps.hasSideEffects; 880 let Defs = ps.Defs; 881 let SchedRW = ps.SchedRW; 882 let Uses = ps.Uses; 883 let OtherPredicates = ps.OtherPredicates; 884} 885 886//===----------------------------------------------------------------------===// 887// GFX11. 888//===----------------------------------------------------------------------===// 889 890let AssemblerPredicate = isGFX11Plus, 891 DecoderNamespace = "GFX11" in { 892 893 multiclass VOP3P_Real_gfx11<bits<7> op, string backing_ps_name = NAME, 894 string asmName = !cast<VOP3P_Pseudo>(NAME).Mnemonic> { 895 def _gfx11 : VOP3P_Real<!cast<VOP3P_Pseudo>(backing_ps_name), 896 SIEncodingFamily.GFX11, asmName>, 897 VOP3Pe_gfx11<op, !cast<VOP3P_Pseudo>(backing_ps_name).Pfl>; 898 } 899 900 multiclass VOP3P_Real_dpp_gfx11<bits<7> op, string backing_ps_name = NAME, 901 string asmName = !cast<VOP3P_Pseudo>(NAME).Mnemonic> { 902 defvar ps = !cast<VOP3P_Pseudo>(backing_ps_name); 903 def _dpp_gfx11 904 : VOP3P_DPP16<op, !cast<VOP_DPP_Pseudo>(backing_ps_name #"_dpp"), 905 SIEncodingFamily.GFX11> { 906 let AsmString = asmName #ps.Pfl.AsmVOP3DPP16; 907 let DecoderNamespace = "DPPGFX11"; 908 } 909 } 910 911 multiclass VOP3P_Real_dpp8_gfx11<bits<7> op, string backing_ps_name = NAME, 912 string asmName = !cast<VOP3P_Pseudo>(NAME).Mnemonic> { 913 defvar ps = !cast<VOP3P_Pseudo>(backing_ps_name); 914 def _dpp8_gfx11 : VOP3P_DPP8_Base<op, ps> { 915 let AsmString = asmName #ps.Pfl.AsmVOP3DPP8; 916 let DecoderNamespace = "DPP8GFX11"; 917 } 918 } 919 920 multiclass VOP3P_Realtriple_gfx11<bits<7> op, string backing_ps_name = NAME, 921 string asmName = !cast<VOP3P_Pseudo>(NAME).Mnemonic> 922 : VOP3P_Real_gfx11<op, backing_ps_name, asmName>, 923 VOP3P_Real_dpp_gfx11<op, backing_ps_name, asmName>, 924 VOP3P_Real_dpp8_gfx11<op, backing_ps_name, asmName>; 925} // End AssemblerPredicate = isGFX11Plus, DecoderNamespace = "GFX11" 926 927defm V_DOT4_I32_IU8 : VOP3P_Real_gfx11 <0x16>; 928defm V_DOT8_I32_IU4 : VOP3P_Real_gfx11 <0x18>; 929defm V_DOT2_F32_BF16 : VOP3P_Real_gfx11 <0x1a>; 930 931multiclass VOP3P_Real_WMMA <bits<7> op> { 932 let WaveSizePredicate = isWave32, DecoderNamespace = "GFX11" in { 933 defm _twoaddr_w32 : VOP3P_Real_gfx11 <op>; 934 } 935 let WaveSizePredicate = isWave64, DecoderNamespace = "WMMAGFX11" in { 936 defm _twoaddr_w64 : VOP3P_Real_gfx11 <op>; 937 } 938} 939 940defm V_WMMA_F32_16X16X16_F16 : VOP3P_Real_WMMA <0x040>; 941defm V_WMMA_F32_16X16X16_BF16 : VOP3P_Real_WMMA <0x041>; 942defm V_WMMA_F16_16X16X16_F16 : VOP3P_Real_WMMA <0x042>; 943defm V_WMMA_BF16_16X16X16_BF16 : VOP3P_Real_WMMA <0x043>; 944defm V_WMMA_I32_16X16X16_IU8 : VOP3P_Real_WMMA <0x044>; 945defm V_WMMA_I32_16X16X16_IU4 : VOP3P_Real_WMMA <0x045>; 946 947//===----------------------------------------------------------------------===// 948// GFX8 (VI) 949//===----------------------------------------------------------------------===// 950 951multiclass VOP3P_Real_vi<bits<7> op> { 952 def _vi : VOP3P_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>, 953 VOP3Pe <op, !cast<VOP3_Pseudo>(NAME).Pfl> { 954 let AssemblerPredicate = HasVOP3PInsts; 955 let DecoderNamespace = "GFX8"; 956 let VOP3P = 1; 957 } 958} 959 960multiclass VOP3P_Real_MAI<bits<7> op> { 961 def _vi : VOP3P_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>, 962 VOP3Pe_MAI <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl, ?> { 963 let AssemblerPredicate = HasMAIInsts; 964 let DecoderNamespace = "GFX8"; 965 let Inst{14} = ?; // op_sel_hi(2) 966 let Inst{59} = ?; // op_sel_hi(0) 967 let Inst{60} = ?; // op_sel_hi(1) 968 } 969} 970 971let Constraints = "" in { 972multiclass VOP3P_Real_MFMA_gfx90a<bits<7> op> { 973 let SubtargetPredicate = isGFX90AOnly, 974 AssemblerPredicate = isGFX90AOnly, DecoderNamespace = "GFX90A" in { 975 def _gfx90a_acd : VOP3P_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX90A>, 976 VOP3Pe_MAI <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl, 1>; 977 978 def _gfx90a_vcd : VOP3P_Real<!cast<VOP3_Pseudo>(NAME # "_vgprcd" # "_e64"), SIEncodingFamily.GFX90A>, 979 VOP3Pe_MAI <op, !cast<VOP3_Pseudo>(NAME # "_vgprcd" # "_e64").Pfl, 0>; 980 } // End AssemblerPredicate = isGFX90AOnly, DecoderNamespace = "GFX90A" 981} 982} 983 984multiclass VOP3P_Real_MFMA_gfx940_aliases<string NameFrom, string NameTo, string Op, 985 VOP3_Pseudo PS_ACD = !cast<VOP3_Pseudo>(Op # "_e64"), 986 VOP3_Pseudo PS_VCD = !cast<VOP3_Pseudo>(Op # "_vgprcd" # "_e64"), 987 VOPProfile Pfl_ACD = PS_ACD.Pfl, 988 VOPProfile Pfl_VCD = PS_VCD.Pfl> { 989 let Predicates = [isGFX940Plus] in { 990 foreach _ = BoolToList<!ne(NameFrom, NameTo)>.ret in { 991 def : InstAlias <NameTo # " " # PS_ACD.AsmOperands, 992 (!cast<VOP3P_Real>(Op # "_gfx940_acd") Pfl_ACD.DstRC:$vdst, 993 Pfl_ACD.Src0RC64:$src0, Pfl_ACD.Src1RC64:$src1, Pfl_ACD.Src2RC64:$src2, 994 cbsz:$cbsz, abid:$abid, blgp:$blgp)>, PredicateControl; 995 def : InstAlias <NameTo # " " # PS_VCD.AsmOperands, 996 (!cast<VOP3P_Real>(Op # "_gfx940_vcd") Pfl_VCD.DstRC:$vdst, 997 Pfl_VCD.Src0RC64:$src0, Pfl_VCD.Src1RC64:$src1, Pfl_VCD.Src2RC64:$src2, 998 cbsz:$cbsz, abid:$abid, blgp:$blgp)>, PredicateControl; 999 } 1000 } // End Predicates = [isGFX940Plus] 1001} 1002 1003multiclass VOP3P_Real_MFMA_gfx940<bits<7> op, string Name = !cast<VOP3_Pseudo>(NAME#"_e64").Mnemonic, 1004 VOP3_Pseudo PS_ACD = !cast<VOP3_Pseudo>(NAME # "_e64"), 1005 VOP3_Pseudo PS_VCD = !cast<VOP3_Pseudo>(NAME # "_vgprcd" # "_e64")> { 1006 let SubtargetPredicate = isGFX940Plus, 1007 AssemblerPredicate = isGFX940Plus, DecoderNamespace = "GFX9", 1008 AsmString = Name # PS_ACD.AsmOperands, Constraints = "" in { 1009 def _gfx940_acd : VOP3P_Real<PS_ACD, SIEncodingFamily.GFX940>, 1010 VOP3Pe_MAI <op, PS_ACD.Pfl, 1>; 1011 1012 def _gfx940_vcd : VOP3P_Real<PS_VCD, SIEncodingFamily.GFX940>, 1013 VOP3Pe_MAI <op, PS_VCD.Pfl, 0>; 1014 } // End AssemblerPredicate = isGFX940Plus, DecoderNamespace = "GFX9" 1015 1016 defm : VOP3P_Real_MFMA_gfx940_aliases<Name, PS_ACD.Mnemonic, NAME>; 1017 1018 foreach _ = BoolToList<!ne(!subst("_1k", "", PS_ACD.Mnemonic), PS_ACD.Mnemonic)>.ret in 1019 defm : VOP3P_Real_MFMA_gfx940_aliases<Name, !subst("_1k", "", PS_ACD.Mnemonic), NAME>; 1020} 1021 1022multiclass VOP3P_Real_MFMA<bits<7> op, string GFX940Name = !cast<VOP3_Pseudo>(NAME#"_e64").Mnemonic> : 1023 VOP3P_Real_MFMA_gfx90a <op>, 1024 VOP3P_Real_MFMA_gfx940 <op, GFX940Name> { 1025 def _vi : VOP3P_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>, 1026 VOP3Pe_MAI <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl, ?> { 1027 let AssemblerPredicate = HasMAIInsts; 1028 let DecoderNamespace = "GFX8"; 1029 let Constraints = ""; 1030 } 1031} 1032 1033multiclass VOP3P_Real_SMFMAC<bits<7> op, string alias> { 1034 def _gfx940 : VOP3P_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>, 1035 VOP3Pe_SMFMAC <op> { 1036 let AssemblerPredicate = isGFX940Plus; 1037 let DecoderNamespace = "GFX8"; 1038 } 1039 def : MnemonicAlias<alias, !cast<VOP3_Pseudo>(NAME#"_e64").Mnemonic>; 1040} 1041 1042defm V_PK_MAD_I16 : VOP3P_Real_vi <0x00>; 1043defm V_PK_MUL_LO_U16 : VOP3P_Real_vi <0x01>; 1044defm V_PK_ADD_I16 : VOP3P_Real_vi <0x02>; 1045defm V_PK_SUB_I16 : VOP3P_Real_vi <0x03>; 1046defm V_PK_LSHLREV_B16 : VOP3P_Real_vi <0x04>; 1047defm V_PK_LSHRREV_B16 : VOP3P_Real_vi <0x05>; 1048defm V_PK_ASHRREV_I16 : VOP3P_Real_vi <0x06>; 1049defm V_PK_MAX_I16 : VOP3P_Real_vi <0x07>; 1050defm V_PK_MIN_I16 : VOP3P_Real_vi <0x08>; 1051defm V_PK_MAD_U16 : VOP3P_Real_vi <0x09>; 1052 1053defm V_PK_ADD_U16 : VOP3P_Real_vi <0x0a>; 1054defm V_PK_SUB_U16 : VOP3P_Real_vi <0x0b>; 1055defm V_PK_MAX_U16 : VOP3P_Real_vi <0x0c>; 1056defm V_PK_MIN_U16 : VOP3P_Real_vi <0x0d>; 1057defm V_PK_FMA_F16 : VOP3P_Real_vi <0x0e>; 1058defm V_PK_ADD_F16 : VOP3P_Real_vi <0x0f>; 1059defm V_PK_MUL_F16 : VOP3P_Real_vi <0x10>; 1060defm V_PK_MIN_F16 : VOP3P_Real_vi <0x11>; 1061defm V_PK_MAX_F16 : VOP3P_Real_vi <0x12>; 1062 1063 1064let SubtargetPredicate = HasMadMixInsts in { 1065defm V_MAD_MIX_F32 : VOP3P_Real_vi <0x20>; 1066defm V_MAD_MIXLO_F16 : VOP3P_Real_vi <0x21>; 1067defm V_MAD_MIXHI_F16 : VOP3P_Real_vi <0x22>; 1068} 1069 1070let SubtargetPredicate = HasFmaMixInsts in { 1071let DecoderNamespace = "GFX9_DL" in { 1072// The mad_mix instructions were renamed and their behaviors changed, 1073// but the opcode stayed the same so we need to put these in a 1074// different DecoderNamespace to avoid the ambiguity. 1075defm V_FMA_MIX_F32 : VOP3P_Real_vi <0x20>; 1076defm V_FMA_MIXLO_F16 : VOP3P_Real_vi <0x21>; 1077defm V_FMA_MIXHI_F16 : VOP3P_Real_vi <0x22>; 1078} 1079} 1080 1081 1082let SubtargetPredicate = HasDot2Insts in { 1083 1084defm V_DOT2_I32_I16 : VOP3P_Real_vi <0x26>; 1085defm V_DOT2_U32_U16 : VOP3P_Real_vi <0x27>; 1086 1087} // End SubtargetPredicate = HasDot2Insts 1088 1089let SubtargetPredicate = HasDot7Insts in { 1090 1091defm V_DOT2_F32_F16 : VOP3P_Real_vi <0x23>; 1092defm V_DOT4_U32_U8 : VOP3P_Real_vi <0x29>; 1093defm V_DOT8_U32_U4 : VOP3P_Real_vi <0x2b>; 1094 1095} // End SubtargetPredicate = HasDot7Insts 1096 1097let SubtargetPredicate = HasDot1Insts in { 1098 1099defm V_DOT4_I32_I8 : VOP3P_Real_vi <0x28>; 1100defm V_DOT8_I32_I4 : VOP3P_Real_vi <0x2a>; 1101 1102} // End SubtargetPredicate = HasDot1Insts 1103 1104let SubtargetPredicate = HasMAIInsts in { 1105 1106defm V_ACCVGPR_READ_B32 : VOP3P_Real_MAI <0x58>; 1107defm V_ACCVGPR_WRITE_B32 : VOP3P_Real_MAI <0x59>; 1108defm V_MFMA_F32_32X32X1F32 : VOP3P_Real_MFMA <0x40, "v_mfma_f32_32x32x1_2b_f32">; 1109defm V_MFMA_F32_16X16X1F32 : VOP3P_Real_MFMA <0x41, "v_mfma_f32_16x16x1_4b_f32">; 1110defm V_MFMA_F32_4X4X1F32 : VOP3P_Real_MFMA <0x42, "v_mfma_f32_4x4x1_16b_f32">; 1111defm V_MFMA_F32_32X32X2F32 : VOP3P_Real_MFMA <0x44, "v_mfma_f32_32x32x2_f32">; 1112defm V_MFMA_F32_16X16X4F32 : VOP3P_Real_MFMA <0x45, "v_mfma_f32_16x16x4_f32">; 1113defm V_MFMA_F32_32X32X4F16 : VOP3P_Real_MFMA <0x48, "v_mfma_f32_32x32x4_2b_f16">; 1114defm V_MFMA_F32_16X16X4F16 : VOP3P_Real_MFMA <0x49, "v_mfma_f32_16x16x4_4b_f16">; 1115defm V_MFMA_F32_4X4X4F16 : VOP3P_Real_MFMA <0x4a, "v_mfma_f32_4x4x4_16b_f16">; 1116defm V_MFMA_F32_32X32X8F16 : VOP3P_Real_MFMA <0x4c, "v_mfma_f32_32x32x8_f16">; 1117defm V_MFMA_F32_16X16X16F16 : VOP3P_Real_MFMA <0x4d, "v_mfma_f32_16x16x16_f16">; 1118defm V_MFMA_I32_32X32X4I8 : VOP3P_Real_MFMA <0x50, "v_mfma_i32_32x32x4_2b_i8">; 1119defm V_MFMA_I32_16X16X4I8 : VOP3P_Real_MFMA <0x51, "v_mfma_i32_16x16x4_4b_i8">; 1120defm V_MFMA_I32_4X4X4I8 : VOP3P_Real_MFMA <0x52, "v_mfma_i32_4x4x4_16b_i8">; 1121 1122let SubtargetPredicate = isGFX908orGFX90A in { 1123defm V_MFMA_I32_16X16X16I8 : VOP3P_Real_MFMA <0x55>; 1124defm V_MFMA_I32_32X32X8I8 : VOP3P_Real_MFMA <0x54>; 1125defm V_MFMA_F32_32X32X2BF16 : VOP3P_Real_MFMA <0x68>; 1126defm V_MFMA_F32_16X16X2BF16 : VOP3P_Real_MFMA <0x69>; 1127defm V_MFMA_F32_4X4X2BF16 : VOP3P_Real_MFMA <0x6b>; 1128defm V_MFMA_F32_32X32X4BF16 : VOP3P_Real_MFMA <0x6c>; 1129defm V_MFMA_F32_16X16X8BF16 : VOP3P_Real_MFMA <0x6d>; 1130} 1131 1132} // End SubtargetPredicate = HasMAIInsts 1133 1134defm V_MFMA_F32_32X32X4BF16_1K : VOP3P_Real_MFMA_gfx90a <0x63>; 1135defm V_MFMA_F32_16X16X4BF16_1K : VOP3P_Real_MFMA_gfx90a <0x64>; 1136defm V_MFMA_F32_4X4X4BF16_1K : VOP3P_Real_MFMA_gfx90a <0x65>; 1137defm V_MFMA_F32_32X32X8BF16_1K : VOP3P_Real_MFMA_gfx90a <0x66>; 1138defm V_MFMA_F32_16X16X16BF16_1K : VOP3P_Real_MFMA_gfx90a <0x67>; 1139defm V_MFMA_F64_16X16X4F64 : VOP3P_Real_MFMA_gfx90a <0x6e>; 1140defm V_MFMA_F64_4X4X4F64 : VOP3P_Real_MFMA_gfx90a <0x6f>; 1141 1142defm V_MFMA_I32_32X32X16I8 : VOP3P_Real_MFMA_gfx940 <0x56, "v_mfma_i32_32x32x16_i8">; 1143defm V_MFMA_I32_16X16X32I8 : VOP3P_Real_MFMA_gfx940 <0x57, "v_mfma_i32_16x16x32_i8">; 1144defm V_MFMA_F32_16X16X8XF32 : VOP3P_Real_MFMA_gfx940 <0x3e, "v_mfma_f32_16x16x8_xf32">; 1145defm V_MFMA_F32_32X32X4XF32 : VOP3P_Real_MFMA_gfx940 <0x3f, "v_mfma_f32_32x32x4_xf32">; 1146defm V_MFMA_F32_16X16X32_BF8_BF8 : VOP3P_Real_MFMA_gfx940 <0x70>; 1147defm V_MFMA_F32_16X16X32_BF8_FP8 : VOP3P_Real_MFMA_gfx940 <0x71>; 1148defm V_MFMA_F32_16X16X32_FP8_BF8 : VOP3P_Real_MFMA_gfx940 <0x72>; 1149defm V_MFMA_F32_16X16X32_FP8_FP8 : VOP3P_Real_MFMA_gfx940 <0x73>; 1150defm V_MFMA_F32_32X32X16_BF8_BF8 : VOP3P_Real_MFMA_gfx940 <0x74>; 1151defm V_MFMA_F32_32X32X16_BF8_FP8 : VOP3P_Real_MFMA_gfx940 <0x75>; 1152defm V_MFMA_F32_32X32X16_FP8_BF8 : VOP3P_Real_MFMA_gfx940 <0x76>; 1153defm V_MFMA_F32_32X32X16_FP8_FP8 : VOP3P_Real_MFMA_gfx940 <0x77>; 1154 1155defm V_MFMA_F32_32X32X4BF16_1K : VOP3P_Real_MFMA_gfx940 <0x5d, "v_mfma_f32_32x32x4_2b_bf16">; 1156defm V_MFMA_F32_16X16X4BF16_1K : VOP3P_Real_MFMA_gfx940 <0x5e, "v_mfma_f32_16x16x4_4b_bf16">; 1157defm V_MFMA_F32_4X4X4BF16_1K : VOP3P_Real_MFMA_gfx940 <0x5f, "v_mfma_f32_4x4x4_16b_bf16">; 1158defm V_MFMA_F32_32X32X8BF16_1K : VOP3P_Real_MFMA_gfx940 <0x60, "v_mfma_f32_32x32x8_bf16">; 1159defm V_MFMA_F32_16X16X16BF16_1K : VOP3P_Real_MFMA_gfx940 <0x61, "v_mfma_f32_16x16x16_bf16">; 1160 1161defm V_MFMA_F64_16X16X4F64 : VOP3P_Real_MFMA_gfx940 <0x6e, "v_mfma_f64_16x16x4_f64">; 1162defm V_MFMA_F64_4X4X4F64 : VOP3P_Real_MFMA_gfx940 <0x6f, "v_mfma_f64_4x4x4_4b_f64">; 1163 1164defm V_SMFMAC_F32_16X16X32_F16 : VOP3P_Real_SMFMAC <0x62, "v_smfmac_f32_16x16x32f16">; 1165defm V_SMFMAC_F32_32X32X16_F16 : VOP3P_Real_SMFMAC <0x64, "v_smfmac_f32_32x32x16f16">; 1166defm V_SMFMAC_F32_16X16X32_BF16 : VOP3P_Real_SMFMAC <0x66, "v_smfmac_f32_16x16x32bf16">; 1167defm V_SMFMAC_F32_32X32X16_BF16 : VOP3P_Real_SMFMAC <0x68, "v_smfmac_f32_32x32x16bf16">; 1168defm V_SMFMAC_I32_16X16X64_I8 : VOP3P_Real_SMFMAC <0x6a, "v_smfmac_i32_16x16x64i8">; 1169defm V_SMFMAC_I32_32X32X32_I8 : VOP3P_Real_SMFMAC <0x6c, "v_smfmac_i32_32x32x32i8">; 1170defm V_SMFMAC_F32_16X16X64_BF8_BF8 : VOP3P_Real_SMFMAC <0x78, "v_smfmac_f32_16x16x64bf8bf8">; 1171defm V_SMFMAC_F32_16X16X64_BF8_FP8 : VOP3P_Real_SMFMAC <0x79, "v_smfmac_f32_16x16x64bf8fp8">; 1172defm V_SMFMAC_F32_16X16X64_FP8_BF8 : VOP3P_Real_SMFMAC <0x7a, "v_smfmac_f32_16x16x64fp8bf8">; 1173defm V_SMFMAC_F32_16X16X64_FP8_FP8 : VOP3P_Real_SMFMAC <0x7b, "v_smfmac_f32_16x16x64fp8fp8">; 1174defm V_SMFMAC_F32_32X32X32_BF8_BF8 : VOP3P_Real_SMFMAC <0x7c, "v_smfmac_f32_32x32x32bf8bf8">; 1175defm V_SMFMAC_F32_32X32X32_BF8_FP8 : VOP3P_Real_SMFMAC <0x7d, "v_smfmac_f32_32x32x32bf8fp8">; 1176defm V_SMFMAC_F32_32X32X32_FP8_BF8 : VOP3P_Real_SMFMAC <0x7e, "v_smfmac_f32_32x32x32fp8bf8">; 1177defm V_SMFMAC_F32_32X32X32_FP8_FP8 : VOP3P_Real_SMFMAC <0x7f, "v_smfmac_f32_32x32x32fp8fp8">; 1178 1179let SubtargetPredicate = HasPackedFP32Ops in { 1180 defm V_PK_FMA_F32 : VOP3P_Real_vi <0x30>; 1181 defm V_PK_MUL_F32 : VOP3P_Real_vi <0x31>; 1182 defm V_PK_ADD_F32 : VOP3P_Real_vi <0x32>; 1183 defm V_PK_MOV_B32 : VOP3P_Real_vi <0x33>; 1184} // End SubtargetPredicate = HasPackedFP32Ops 1185 1186//===----------------------------------------------------------------------===// 1187// GFX10. 1188//===----------------------------------------------------------------------===// 1189 1190let AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10", VOP3P = 1 in { 1191 multiclass VOP3P_Real_gfx10<bits<7> op> { 1192 def _gfx10 : VOP3P_Real<!cast<VOP3P_Pseudo>(NAME), SIEncodingFamily.GFX10>, 1193 VOP3Pe_gfx10 <op, !cast<VOP3P_Pseudo>(NAME).Pfl>; 1194 } 1195} // End AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10", VOP3P = 1 1196 1197multiclass VOP3P_Real_gfx10_gfx11<bits<7> op> 1198 : VOP3P_Real_gfx10<op>, VOP3P_Real_gfx11<op>; 1199 1200multiclass VOP3P_Real_gfx10_gfx11_Triple<bits<7> op> 1201 : VOP3P_Real_gfx10<op>, VOP3P_Realtriple_gfx11<op>; 1202 1203defm V_PK_MAD_I16 : VOP3P_Real_gfx10_gfx11<0x00>; 1204defm V_PK_MUL_LO_U16 : VOP3P_Real_gfx10_gfx11<0x01>; 1205defm V_PK_ADD_I16 : VOP3P_Real_gfx10_gfx11<0x02>; 1206defm V_PK_SUB_I16 : VOP3P_Real_gfx10_gfx11<0x03>; 1207defm V_PK_LSHLREV_B16 : VOP3P_Real_gfx10_gfx11<0x04>; 1208defm V_PK_LSHRREV_B16 : VOP3P_Real_gfx10_gfx11<0x05>; 1209defm V_PK_ASHRREV_I16 : VOP3P_Real_gfx10_gfx11<0x06>; 1210defm V_PK_MAX_I16 : VOP3P_Real_gfx10_gfx11<0x07>; 1211defm V_PK_MIN_I16 : VOP3P_Real_gfx10_gfx11<0x08>; 1212defm V_PK_MAD_U16 : VOP3P_Real_gfx10_gfx11<0x09>; 1213defm V_PK_ADD_U16 : VOP3P_Real_gfx10_gfx11<0x0a>; 1214defm V_PK_SUB_U16 : VOP3P_Real_gfx10_gfx11<0x0b>; 1215defm V_PK_MAX_U16 : VOP3P_Real_gfx10_gfx11<0x0c>; 1216defm V_PK_MIN_U16 : VOP3P_Real_gfx10_gfx11<0x0d>; 1217defm V_PK_FMA_F16 : VOP3P_Real_gfx10_gfx11<0x0e>; 1218defm V_PK_ADD_F16 : VOP3P_Real_gfx10_gfx11<0x0f>; 1219defm V_PK_MUL_F16 : VOP3P_Real_gfx10_gfx11<0x10>; 1220defm V_PK_MIN_F16 : VOP3P_Real_gfx10_gfx11<0x11>; 1221defm V_PK_MAX_F16 : VOP3P_Real_gfx10_gfx11<0x12>; 1222defm V_FMA_MIX_F32 : VOP3P_Real_gfx10_gfx11_Triple <0x20>; 1223defm V_FMA_MIXLO_F16 : VOP3P_Real_gfx10_gfx11_Triple <0x21>; 1224defm V_FMA_MIXHI_F16 : VOP3P_Real_gfx10_gfx11_Triple <0x22>; 1225 1226let SubtargetPredicate = HasDot2Insts in { 1227 1228defm V_DOT2_I32_I16 : VOP3P_Real_gfx10 <0x14>; 1229defm V_DOT2_U32_U16 : VOP3P_Real_gfx10 <0x15>; 1230 1231} // End SubtargetPredicate = HasDot2Insts 1232 1233let SubtargetPredicate = HasDot7Insts in { 1234 1235defm V_DOT2_F32_F16 : VOP3P_Real_gfx10_gfx11_Triple <0x13>; 1236defm V_DOT4_U32_U8 : VOP3P_Real_gfx10_gfx11 <0x17>; 1237defm V_DOT8_U32_U4 : VOP3P_Real_gfx10_gfx11 <0x19>; 1238 1239} // End SubtargetPredicate = HasDot7Insts 1240 1241let SubtargetPredicate = HasDot1Insts in { 1242 1243defm V_DOT4_I32_I8 : VOP3P_Real_gfx10 <0x16>; 1244defm V_DOT8_I32_I4 : VOP3P_Real_gfx10 <0x18>; 1245 1246} // End SubtargetPredicate = HasDot1Insts 1247