1//===-- VOP3PInstructions.td - Vector Instruction Definitions -------------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// VOP3P Classes 11//===----------------------------------------------------------------------===// 12 13class VOP3P_Profile<VOPProfile P, VOP3Features Features = VOP3_REGULAR, 14 bit HasDPP = 0> : VOP3_Profile<P, Features> { 15 let IsVOP3P = 1; 16 let HasExtVOP3DPP = HasDPP; 17 // We do not want to print src modifiers for vop3p because the bits are 18 // overloaded in meaning and the logic in printOperandAndFPInputMods is 19 // wrong for vop3p 20 let AsmVOP3Base = AsmVOP3P; 21} 22 23// Used for FMA_MIX* and MAD_MIX* insts 24// Their operands are only sort of f16 operands. Depending on 25// op_sel_hi, these may be interpreted as f32. The inline immediate 26// values are really f16 converted to f32, so we treat these as f16 27// operands. 28class VOP3P_Mix_Profile<VOPProfile P, VOP3Features Features = VOP3_REGULAR, 29 bit useTiedOutput = 0> : VOP3P_Profile<P, Features, 1> { 30 bit UseTiedOutput = useTiedOutput; 31 32 dag srcs = 33 (ins FP16InputMods:$src0_modifiers, VCSrc_f16:$src0, 34 FP16InputMods:$src1_modifiers, VCSrc_f16:$src1, 35 FP16InputMods:$src2_modifiers, VCSrc_f16:$src2); 36 dag dpp_srcs = 37 (ins FPVRegInputMods:$src0_modifiers, VGPRSrc_32:$src0, 38 FPVRegInputMods:$src1_modifiers, VRegSrc_32:$src1, 39 FP16InputMods:$src2_modifiers, VCSrc_f16:$src2); 40 41 // FIXME: clampmod0 misbehaves with the non-default vdst_in 42 // following it. For now workaround this by requiring clamp 43 // in tied patterns. This should use undef_tied_input, but it 44 // seems underdeveloped and doesn't apply the right register 45 // class constraints. 46 dag mods = !con(!if(UseTiedOutput, (ins clampmod:$clamp, VGPR_32:$vdst_in), 47 (ins clampmod0:$clamp)), 48 (ins op_sel0:$op_sel, op_sel_hi0:$op_sel_hi)); 49 // We use Ins64 because that is the one which populates InOperandList 50 // due to the logic in class VOP3_Pseudo 51 let Ins64 = !con(srcs, mods); 52 let InsVOP3Base = !con(dpp_srcs, mods); 53 let AsmVOP3Base = 54 "$vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$op_sel$op_sel_hi$clamp"; 55} 56 57multiclass VOP3PInst<string OpName, VOPProfile P, 58 SDPatternOperator node = null_frag, bit IsDOT = 0> { 59 def NAME : VOP3P_Pseudo<OpName, P, 60 !if (P.HasModifiers, 61 getVOP3PModPat<P, node, IsDOT, IsDOT>.ret, 62 getVOP3Pat<P, node>.ret)>; 63 let SubtargetPredicate = isGFX11Plus in { 64 if P.HasExtVOP3DPP then 65 def _dpp : VOP3_DPP_Pseudo<OpName, P> { 66 let VOP3P = 1; 67 let PseudoInstr = OpName #"_dpp"; 68 } 69 } // end SubtargetPredicate = isGFX11Plus 70} 71 72// Non-packed instructions that use the VOP3P encoding. 73// VOP3 neg/abs and VOP3P opsel/opsel_hi modifiers are allowed. 74multiclass VOP3_VOP3PInst<string OpName, VOP3P_Mix_Profile P> { 75 def NAME : VOP3P_Pseudo<OpName, P> { 76 let Constraints = !if(P.UseTiedOutput, "$vdst = $vdst_in", ""); 77 let DisableEncoding = !if(P.UseTiedOutput, "$vdst_in", ""); 78 } 79 let SubtargetPredicate = isGFX11Plus in { 80 if P.HasExtVOP3DPP then 81 def _dpp : VOP3_DPP_Pseudo<OpName, P> { 82 let VOP3P = 1; 83 let PseudoInstr = OpName#"_dpp"; 84 let Constraints = !if(P.UseTiedOutput, "$vdst = $vdst_in", ""); 85 let DisableEncoding = !if(P.UseTiedOutput, "$vdst_in", ""); 86 } 87 } // end SubtargetPredicate = isGFX11Plus 88} 89 90let isReMaterializable = 1 in { 91let isCommutable = 1 in { 92defm V_PK_MAD_I16 : VOP3PInst<"v_pk_mad_i16", VOP3P_Profile<VOP_V2I16_V2I16_V2I16_V2I16>>; 93defm V_PK_MAD_U16 : VOP3PInst<"v_pk_mad_u16", VOP3P_Profile<VOP_V2I16_V2I16_V2I16_V2I16>>; 94 95let FPDPRounding = 1 in { 96defm V_PK_FMA_F16 : VOP3PInst<"v_pk_fma_f16", VOP3P_Profile<VOP_V2F16_V2F16_V2F16_V2F16>, any_fma>; 97defm V_PK_ADD_F16 : VOP3PInst<"v_pk_add_f16", VOP3P_Profile<VOP_V2F16_V2F16_V2F16>, any_fadd>; 98defm V_PK_MUL_F16 : VOP3PInst<"v_pk_mul_f16", VOP3P_Profile<VOP_V2F16_V2F16_V2F16>, any_fmul>; 99} // End FPDPRounding = 1 100defm V_PK_MAX_F16 : VOP3PInst<"v_pk_max_f16", VOP3P_Profile<VOP_V2F16_V2F16_V2F16>, fmaxnum_like>; 101defm V_PK_MIN_F16 : VOP3PInst<"v_pk_min_f16", VOP3P_Profile<VOP_V2F16_V2F16_V2F16>, fminnum_like>; 102 103defm V_PK_ADD_U16 : VOP3PInst<"v_pk_add_u16", VOP3P_Profile<VOP_V2I16_V2I16_V2I16>, add>; 104defm V_PK_ADD_I16 : VOP3PInst<"v_pk_add_i16", VOP3P_Profile<VOP_V2I16_V2I16_V2I16>>; 105defm V_PK_MUL_LO_U16 : VOP3PInst<"v_pk_mul_lo_u16", VOP3P_Profile<VOP_V2I16_V2I16_V2I16>, mul>; 106 107defm V_PK_MIN_I16 : VOP3PInst<"v_pk_min_i16", VOP3P_Profile<VOP_V2I16_V2I16_V2I16>, smin>; 108defm V_PK_MIN_U16 : VOP3PInst<"v_pk_min_u16", VOP3P_Profile<VOP_V2I16_V2I16_V2I16>, umin>; 109defm V_PK_MAX_I16 : VOP3PInst<"v_pk_max_i16", VOP3P_Profile<VOP_V2I16_V2I16_V2I16>, smax>; 110defm V_PK_MAX_U16 : VOP3PInst<"v_pk_max_u16", VOP3P_Profile<VOP_V2I16_V2I16_V2I16>, umax>; 111} 112 113defm V_PK_SUB_U16 : VOP3PInst<"v_pk_sub_u16", VOP3P_Profile<VOP_V2I16_V2I16_V2I16>>; 114defm V_PK_SUB_I16 : VOP3PInst<"v_pk_sub_i16", VOP3P_Profile<VOP_V2I16_V2I16_V2I16>, sub>; 115 116defm V_PK_LSHLREV_B16 : VOP3PInst<"v_pk_lshlrev_b16", VOP3P_Profile<VOP_V2I16_V2I16_V2I16>, clshl_rev_16>; 117defm V_PK_ASHRREV_I16 : VOP3PInst<"v_pk_ashrrev_i16", VOP3P_Profile<VOP_V2I16_V2I16_V2I16>, cashr_rev_16>; 118defm V_PK_LSHRREV_B16 : VOP3PInst<"v_pk_lshrrev_b16", VOP3P_Profile<VOP_V2I16_V2I16_V2I16>, clshr_rev_16>; 119} // End isReMaterializable = 1 120 121let SubtargetPredicate = HasVOP3PInsts in { 122 123// Undo sub x, c -> add x, -c canonicalization since c is more likely 124// an inline immediate than -c. 125// The constant will be emitted as a mov, and folded later. 126// TODO: We could directly encode the immediate now 127def : GCNPat< 128 (add (v2i16 (VOP3PMods v2i16:$src0, i32:$src0_modifiers)), NegSubInlineConstV216:$src1), 129 (V_PK_SUB_U16 $src0_modifiers, $src0, SRCMODS.OP_SEL_1, NegSubInlineConstV216:$src1) 130>; 131 132// Integer operations with clamp bit set. 133class VOP3PSatPat<SDPatternOperator pat, Instruction inst> : GCNPat< 134 (pat (v2i16 (VOP3PMods v2i16:$src0, i32:$src0_modifiers)), 135 (v2i16 (VOP3PMods v2i16:$src1, i32:$src1_modifiers))), 136 (inst $src0_modifiers, $src0, $src1_modifiers, $src1, DSTCLAMP.ENABLE) 137>; 138 139def : VOP3PSatPat<uaddsat, V_PK_ADD_U16>; 140def : VOP3PSatPat<saddsat, V_PK_ADD_I16>; 141def : VOP3PSatPat<usubsat, V_PK_SUB_U16>; 142def : VOP3PSatPat<ssubsat, V_PK_SUB_I16>; 143} // End SubtargetPredicate = HasVOP3PInsts 144 145// TODO: Make sure we're doing the right thing with denormals. Note 146// that FMA and MAD will differ. 147multiclass MadFmaMixPats<SDPatternOperator fma_like, 148 Instruction mix_inst, 149 Instruction mixlo_inst, 150 Instruction mixhi_inst> { 151 // At least one of the operands needs to be an fpextend of an f16 152 // for this to be worthwhile, so we need three patterns here. 153 // TODO: Could we use a predicate to inspect src1/2/3 instead? 154 def : GCNPat < 155 (f32 (fma_like (f32 (VOP3PMadMixModsExt f16:$src0, i32:$src0_mods)), 156 (f32 (VOP3PMadMixMods f16:$src1, i32:$src1_mods)), 157 (f32 (VOP3PMadMixMods f16:$src2, i32:$src2_mods)))), 158 (mix_inst $src0_mods, $src0, $src1_mods, $src1, $src2_mods, $src2, 159 DSTCLAMP.NONE)>; 160 def : GCNPat < 161 (f32 (fma_like (f32 (VOP3PMadMixMods f16:$src0, i32:$src0_mods)), 162 (f32 (VOP3PMadMixModsExt f16:$src1, i32:$src1_mods)), 163 (f32 (VOP3PMadMixMods f32:$src2, i32:$src2_mods)))), 164 (mix_inst $src0_mods, $src0, $src1_mods, $src1, $src2_mods, $src2, 165 DSTCLAMP.NONE)>; 166 def : GCNPat < 167 (f32 (fma_like (f32 (VOP3PMadMixMods f16:$src0, i32:$src0_mods)), 168 (f32 (VOP3PMadMixMods f32:$src1, i32:$src1_mods)), 169 (f32 (VOP3PMadMixModsExt f16:$src2, i32:$src2_mods)))), 170 (mix_inst $src0_mods, $src0, $src1_mods, $src1, $src2_mods, $src2, 171 DSTCLAMP.NONE)>; 172 173 def : GCNPat < 174 (f16 (fpround (fma_like (f32 (VOP3PMadMixMods f16:$src0, i32:$src0_modifiers)), 175 (f32 (VOP3PMadMixMods f16:$src1, i32:$src1_modifiers)), 176 (f32 (VOP3PMadMixMods f16:$src2, i32:$src2_modifiers))))), 177 (mixlo_inst $src0_modifiers, $src0, 178 $src1_modifiers, $src1, 179 $src2_modifiers, $src2, 180 DSTCLAMP.NONE, 181 (i32 (IMPLICIT_DEF))) 182 >; 183 184 // FIXME: Special case handling for maxhi (especially for clamp) 185 // because dealing with the write to high half of the register is 186 // difficult. 187 def : GCNPat < 188 (build_vector f16:$elt0, (fpround (fma_like (f32 (VOP3PMadMixMods f16:$src0, i32:$src0_modifiers)), 189 (f32 (VOP3PMadMixMods f16:$src1, i32:$src1_modifiers)), 190 (f32 (VOP3PMadMixMods f16:$src2, i32:$src2_modifiers))))), 191 (v2f16 (mixhi_inst $src0_modifiers, $src0, 192 $src1_modifiers, $src1, 193 $src2_modifiers, $src2, 194 DSTCLAMP.NONE, 195 VGPR_32:$elt0)) 196 >; 197 198 def : GCNPat < 199 (build_vector 200 f16:$elt0, 201 (AMDGPUclamp (fpround (fma_like (f32 (VOP3PMadMixMods f16:$src0, i32:$src0_modifiers)), 202 (f32 (VOP3PMadMixMods f16:$src1, i32:$src1_modifiers)), 203 (f32 (VOP3PMadMixMods f16:$src2, i32:$src2_modifiers)))))), 204 (v2f16 (mixhi_inst $src0_modifiers, $src0, 205 $src1_modifiers, $src1, 206 $src2_modifiers, $src2, 207 DSTCLAMP.ENABLE, 208 VGPR_32:$elt0)) 209 >; 210 211 def : GCNPat < 212 (AMDGPUclamp (build_vector 213 (fpround (fma_like (f32 (VOP3PMadMixMods f16:$lo_src0, i32:$lo_src0_modifiers)), 214 (f32 (VOP3PMadMixMods f16:$lo_src1, i32:$lo_src1_modifiers)), 215 (f32 (VOP3PMadMixMods f16:$lo_src2, i32:$lo_src2_modifiers)))), 216 (fpround (fma_like (f32 (VOP3PMadMixMods f16:$hi_src0, i32:$hi_src0_modifiers)), 217 (f32 (VOP3PMadMixMods f16:$hi_src1, i32:$hi_src1_modifiers)), 218 (f32 (VOP3PMadMixMods f16:$hi_src2, i32:$hi_src2_modifiers)))))), 219 (v2f16 (mixhi_inst $hi_src0_modifiers, $hi_src0, 220 $hi_src1_modifiers, $hi_src1, 221 $hi_src2_modifiers, $hi_src2, 222 DSTCLAMP.ENABLE, 223 (mixlo_inst $lo_src0_modifiers, $lo_src0, 224 $lo_src1_modifiers, $lo_src1, 225 $lo_src2_modifiers, $lo_src2, 226 DSTCLAMP.ENABLE, 227 (i32 (IMPLICIT_DEF))))) 228 >; 229 230 def : GCNPat < 231 (f16 (fpround (fmul (f32 (VOP3PMadMixMods f32:$src0, i32:$src0_modifiers)), 232 (f32 (VOP3PMadMixMods f32:$src1, i32:$src1_modifiers))))), 233 (mixlo_inst $src0_modifiers, $src0, 234 $src1_modifiers, $src1, 235 (i32 0), (i32 0), 236 DSTCLAMP.NONE, 237 (i32 (IMPLICIT_DEF))) 238 >; 239 240 def : GCNPat < 241 (build_vector f16:$elt0, (fpround (fmul (f32 (VOP3PMadMixMods f32:$src0, i32:$src0_modifiers)), 242 (f32 (VOP3PMadMixMods f32:$src1, i32:$src1_modifiers))))), 243 (v2f16 (mixhi_inst $src0_modifiers, $src0, 244 $src1_modifiers, $src1, 245 (i32 0), (i32 0), 246 DSTCLAMP.NONE, 247 VGPR_32:$elt0)) 248 >; 249} 250 251let SubtargetPredicate = HasMadMixInsts, OtherPredicates = [NoFP32Denormals] in { 252 253// These are VOP3a-like opcodes which accept no omod. 254// Size of src arguments (16/32) is controlled by op_sel. 255// For 16-bit src arguments their location (hi/lo) are controlled by op_sel_hi. 256let isCommutable = 1, mayRaiseFPException = 0 in { 257let isReMaterializable = 1 in 258defm V_MAD_MIX_F32 : VOP3_VOP3PInst<"v_mad_mix_f32", VOP3P_Mix_Profile<VOP_F32_F16_F16_F16, VOP3_OPSEL>>; 259 260let FPDPRounding = 1 in { 261// Clamp modifier is applied after conversion to f16. 262defm V_MAD_MIXLO_F16 : VOP3_VOP3PInst<"v_mad_mixlo_f16", VOP3P_Mix_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL, 1>>; 263 264let ClampLo = 0, ClampHi = 1 in { 265defm V_MAD_MIXHI_F16 : VOP3_VOP3PInst<"v_mad_mixhi_f16", VOP3P_Mix_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL, 1>>; 266} 267} // End FPDPRounding = 1 268} 269 270defm : MadFmaMixPats<fmad, V_MAD_MIX_F32, V_MAD_MIXLO_F16, V_MAD_MIXHI_F16>; 271} // End SubtargetPredicate = HasMadMixInsts, OtherPredicates = [NoFP32Denormals] 272 273 274// Essentially the same as the mad_mix versions 275let SubtargetPredicate = HasFmaMixInsts in { 276let isCommutable = 1 in { 277 278let isReMaterializable = 1 in 279defm V_FMA_MIX_F32 : VOP3_VOP3PInst<"v_fma_mix_f32", VOP3P_Mix_Profile<VOP_F32_F16_F16_F16, VOP3_OPSEL>>; 280 281let FPDPRounding = 1 in { 282// Clamp modifier is applied after conversion to f16. 283defm V_FMA_MIXLO_F16 : VOP3_VOP3PInst<"v_fma_mixlo_f16", VOP3P_Mix_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL, 1>>; 284 285let ClampLo = 0, ClampHi = 1 in { 286defm V_FMA_MIXHI_F16 : VOP3_VOP3PInst<"v_fma_mixhi_f16", VOP3P_Mix_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL, 1>>; 287} 288} // End FPDPRounding = 1 289} 290 291defm : MadFmaMixPats<fma, V_FMA_MIX_F32, V_FMA_MIXLO_F16, V_FMA_MIXHI_F16>; 292} 293 294// Defines patterns that extract signed 4bit from each Idx[0]. 295foreach Idx = [[0,28],[4,24],[8,20],[12,16],[16,12],[20,8],[24,4]] in 296 def ExtractSigned4bit_#Idx[0] : PatFrag<(ops node:$src), 297 (sra (shl node:$src, (i32 Idx[1])), (i32 28))>; 298 299// Defines code pattern that extracts U(unsigned/signed) 4/8bit from FromBitIndex. 300class Extract<int FromBitIndex, int BitMask, bit U>: PatFrag< 301 (ops node:$src), 302 !if (!or (!and (!eq (BitMask, 255), !eq (FromBitIndex, 24)), !eq (FromBitIndex, 28)), // last element 303 !if (U, (srl node:$src, (i32 FromBitIndex)), (sra node:$src, (i32 FromBitIndex))), 304 !if (!eq (FromBitIndex, 0), // first element 305 !if (U, (and node:$src, (i32 BitMask)), 306 !if (!eq (BitMask, 15), (!cast<PatFrag>("ExtractSigned4bit_"#FromBitIndex) node:$src), 307 (sext_inreg node:$src, i8))), 308 !if (U, (and (srl node:$src, (i32 FromBitIndex)), (i32 BitMask)), 309 !if (!eq (BitMask, 15), (!cast<PatFrag>("ExtractSigned4bit_"#FromBitIndex) node:$src), 310 (sext_inreg (srl node:$src, (i32 FromBitIndex)), i8)))))>; 311 312 313foreach Type = ["I", "U"] in 314 foreach Index = 0-3 in { 315 // Defines patterns that extract each Index'ed 8bit from an unsigned 316 // 32bit scalar value; 317 def Type#Index#"_8bit" : Extract<!shl(Index, 3), 255, !eq (Type, "U")>; 318 319 // Defines multiplication patterns where the multiplication is happening on each 320 // Index'ed 8bit of a 32bit scalar value. 321 322 def Mul#Type#_Elt#Index : PatFrag< 323 (ops node:$src0, node:$src1), 324 (!cast<HasOneUseBinOp>(!if (!eq (Type, "I"), AMDGPUmul_i24_oneuse, AMDGPUmul_u24_oneuse)) 325 (!cast<Extract>(Type#Index#"_8bit") node:$src0), 326 (!cast<Extract>(Type#Index#"_8bit") node:$src1))>; 327 } 328 329// Different variants of dot8 patterns cause a huge increase in the compile time. 330// Define non-associative/commutative add/mul to prevent permutation in the dot8 331// pattern. 332def NonACAdd : SDNode<"ISD::ADD" , SDTIntBinOp>; 333def NonACAdd_oneuse : HasOneUseBinOp<NonACAdd>; 334 335def NonACAMDGPUmul_u24 : SDNode<"AMDGPUISD::MUL_U24" , SDTIntBinOp>; 336def NonACAMDGPUmul_u24_oneuse : HasOneUseBinOp<NonACAMDGPUmul_u24>; 337 338def NonACAMDGPUmul_i24 : SDNode<"AMDGPUISD::MUL_I24" , SDTIntBinOp>; 339def NonACAMDGPUmul_i24_oneuse : HasOneUseBinOp<NonACAMDGPUmul_i24>; 340 341foreach Type = ["I", "U"] in 342 foreach Index = 0-7 in { 343 // Defines patterns that extract each Index'ed 4bit from an unsigned 344 // 32bit scalar value; 345 def Type#Index#"_4bit" : Extract<!shl(Index, 2), 15, !eq (Type, "U")>; 346 347 // Defines multiplication patterns where the multiplication is happening on each 348 // Index'ed 8bit of a 32bit scalar value. 349 def Mul#Type#Index#"_4bit" : PatFrag< 350 (ops node:$src0, node:$src1), 351 (!cast<HasOneUseBinOp>(!if (!eq (Type, "I"), NonACAMDGPUmul_i24_oneuse, NonACAMDGPUmul_u24_oneuse)) 352 (!cast<Extract>(Type#Index#"_4bit") node:$src0), 353 (!cast<Extract>(Type#Index#"_4bit") node:$src1))>; 354 } 355 356class UDot2Pat<Instruction Inst> : GCNPat < 357 (add (add_oneuse (AMDGPUmul_u24_oneuse (srl i32:$src0, (i32 16)), 358 (srl i32:$src1, (i32 16))), i32:$src2), 359 (AMDGPUmul_u24_oneuse (and i32:$src0, (i32 65535)), 360 (and i32:$src1, (i32 65535))) 361 ), 362 (Inst (i32 8), $src0, (i32 8), $src1, (i32 8), $src2, (i1 0))> { 363 let SubtargetPredicate = !cast<VOP_Pseudo>(Inst).SubtargetPredicate; 364} 365 366class SDot2Pat<Instruction Inst> : GCNPat < 367 (add (add_oneuse (AMDGPUmul_i24_oneuse (sra i32:$src0, (i32 16)), 368 (sra i32:$src1, (i32 16))), i32:$src2), 369 (AMDGPUmul_i24_oneuse (sext_inreg i32:$src0, i16), 370 (sext_inreg i32:$src1, i16))), 371 (Inst (i32 8), $src0, (i32 8), $src1, (i32 8), $src2, (i1 0))> { 372 let SubtargetPredicate = !cast<VOP_Pseudo>(Inst).SubtargetPredicate; 373} 374 375let IsDOT = 1 in { 376let SubtargetPredicate = HasDot2Insts in { 377 378defm V_DOT2_I32_I16 : VOP3PInst<"v_dot2_i32_i16", 379 VOP3P_Profile<VOP_I32_V2I16_V2I16_I32>, int_amdgcn_sdot2, 1>; 380defm V_DOT2_U32_U16 : VOP3PInst<"v_dot2_u32_u16", 381 VOP3P_Profile<VOP_I32_V2I16_V2I16_I32>, int_amdgcn_udot2, 1>; 382 383} // End SubtargetPredicate = HasDot2Insts 384 385let SubtargetPredicate = HasDot10Insts in 386defm V_DOT2_F32_F16 : VOP3PInst<"v_dot2_f32_f16", 387 VOP3P_Profile<VOP_F32_V2F16_V2F16_F32, VOP3_REGULAR, /*HasDPP*/ 1>, 388 AMDGPUfdot2, 1/*ExplicitClamp*/>; 389 390let SubtargetPredicate = HasDot7Insts in { 391defm V_DOT4_U32_U8 : VOP3PInst<"v_dot4_u32_u8", 392 VOP3P_Profile<VOP_I32_I32_I32_I32, VOP3_PACKED>, int_amdgcn_udot4, 1>; 393defm V_DOT8_U32_U4 : VOP3PInst<"v_dot8_u32_u4", 394 VOP3P_Profile<VOP_I32_I32_I32_I32, VOP3_PACKED>, int_amdgcn_udot8, 1>; 395 396} // End SubtargetPredicate = HasDot7Insts 397 398let SubtargetPredicate = HasDot1Insts in { 399 400defm V_DOT4_I32_I8 : VOP3PInst<"v_dot4_i32_i8", 401 VOP3P_Profile<VOP_I32_I32_I32_I32, VOP3_PACKED>, int_amdgcn_sdot4, 1>; 402defm V_DOT8_I32_I4 : VOP3PInst<"v_dot8_i32_i4", 403 VOP3P_Profile<VOP_I32_I32_I32_I32, VOP3_PACKED>, int_amdgcn_sdot8, 1>; 404 405} // End SubtargetPredicate = HasDot1Insts 406 407def DOT2_BF16_Profile 408 : VOP3P_Profile<VOP_F32_V2I16_V2I16_F32, VOP3_REGULAR, /*HasDPP*/ 1> { 409 let HasSrc1Mods = 1; 410} 411 412let SubtargetPredicate = HasDot9Insts in { 413 414defm V_DOT2_F32_BF16 : VOP3PInst<"v_dot2_f32_bf16", DOT2_BF16_Profile, 415 int_amdgcn_fdot2_f32_bf16, 1>; 416 417} // End SubtargetPredicate = HasDot9Insts 418 419} // End let IsDOT = 1 420 421multiclass VOP3PDOTIUInst <string OpName, SDPatternOperator intrinsic_node> { 422 let IsDOT = 1 in 423 defm NAME : VOP3PInst<OpName, VOP3P_Profile<VOP_I32_I32_I32_I32, VOP3_PACKED>, 424 null_frag, 1>; 425 // Dot-iu instructions consider input as signed if imod neg bits are set. Thus 426 // Dot-iu Intrinsics have extra operands and require separate codegen pattern. 427 def : GCNPat < (intrinsic_node (DotIUVOP3PMods i32:$src0_mods), i32:$src0, 428 (DotIUVOP3PMods i32:$src1_mods), i32:$src1, 429 i32:$src2, (i1 timm:$clamp)), 430 (!cast<Instruction>(NAME) $src0_mods, i32:$src0, 431 $src1_mods, i32:$src1, 432 (i32 8), i32:$src2, i1:$clamp) 433 >; 434} 435 436let SubtargetPredicate = HasDot8Insts in { 437defm V_DOT4_I32_IU8 : VOP3PDOTIUInst<"v_dot4_i32_iu8", int_amdgcn_sudot4>; 438defm V_DOT8_I32_IU4 : VOP3PDOTIUInst<"v_dot8_i32_iu4", int_amdgcn_sudot8>; 439} // End SubtargetPredicate = HasDot8Insts 440 441def : UDot2Pat<V_DOT2_U32_U16>; 442def : SDot2Pat<V_DOT2_I32_I16>; 443 444foreach Type = ["U", "I"] in 445 let SubtargetPredicate = !cast<VOP_Pseudo>("V_DOT4_"#Type#"32_"#Type#8).SubtargetPredicate in 446 def : GCNPat < 447 !cast<dag>(!foldl((i32 i32:$src2), [0, 1, 2, 3], lhs, y, 448 (add_oneuse lhs, (!cast<PatFrag>("Mul"#Type#"_Elt"#y) i32:$src0, i32:$src1)))), 449 (!cast<VOP3P_Pseudo>("V_DOT4_"#Type#"32_"#Type#8) (i32 8), $src0, (i32 8), $src1, (i32 8), $src2, (i1 0))>; 450 451foreach Type = ["U", "I"] in 452 let SubtargetPredicate = !cast<VOP_Pseudo>("V_DOT8_"#Type#"32_"#Type#4).SubtargetPredicate in 453 def : GCNPat < 454 !cast<dag>(!foldl((add_oneuse i32:$src2, (!cast<PatFrag>("Mul"#Type#"0_4bit") i32:$src0, i32:$src1)), 455 [1, 2, 3, 4, 5, 6, 7], lhs, y, 456 (NonACAdd_oneuse lhs, (!cast<PatFrag>("Mul"#Type#y#"_4bit") i32:$src0, i32:$src1)))), 457 (!cast<VOP3P_Pseudo>("V_DOT8_"#Type#"32_"#Type#4) (i32 8), $src0, (i32 8), $src1, (i32 8), $src2, (i1 0))>; 458 459// Different variants of dot8 code-gen dag patterns are not generated through table-gen due to a huge increase 460// in the compile time. Directly handle the pattern generated by the FE here. 461foreach Type = ["U", "I"] in 462 let SubtargetPredicate = !cast<VOP_Pseudo>("V_DOT8_"#Type#"32_"#Type#4).SubtargetPredicate in 463 def : GCNPat < 464 !cast<dag>(!foldl((add_oneuse i32:$src2, (!cast<PatFrag>("Mul"#Type#"0_4bit") i32:$src0, i32:$src1)), 465 [7, 1, 2, 3, 4, 5, 6], lhs, y, 466 (NonACAdd_oneuse lhs, (!cast<PatFrag>("Mul"#Type#y#"_4bit") i32:$src0, i32:$src1)))), 467 (!cast<VOP3P_Pseudo>("V_DOT8_"#Type#"32_"#Type#4) (i32 8), $src0, (i32 8), $src1, (i32 8), $src2, (i1 0))>; 468 469def ADst_32 : VOPDstOperand<AGPR_32>; 470def ADst_64 : VOPDstOperand<AReg_64>; 471def ADst_128 : VOPDstOperand<AReg_128>; 472def ADst_256 : VOPDstOperand<AReg_256>; 473def ADst_512 : VOPDstOperand<AReg_512>; 474def ADst_1024 : VOPDstOperand<AReg_1024>; 475def VDst_64 : VOPDstOperand<VReg_64>; 476def VDst_128 : VOPDstOperand<VReg_128>; 477def VDst_256 : VOPDstOperand<VReg_256>; 478def VDst_512 : VOPDstOperand<VReg_512>; 479def VDst_1024 : VOPDstOperand<VReg_1024>; 480 481def VOPProfileAccRead : VOP3P_Profile<VOP_I32_I32, VOP3_MAI> { 482 let Src0RC64 = ARegSrc_32; 483} 484 485def VOPProfileAccWrite : VOP3P_Profile<VOP_I32_I32, VOP3_MAI> { 486 let DstRC = ADst_32; 487 let Src0RC64 = VCSrc_b32; 488} 489 490class VOPProfileMAI<VOPProfile P, RegisterOperand _SrcRC, RegisterOperand _DstRC, 491 RegisterOperand SrcABRC = AVSrc_32> 492 : VOP3P_Profile<P, VOP3_MAI> { 493 let DstRC = _DstRC; 494 let Src0RC64 = SrcABRC; 495 let Src1RC64 = SrcABRC; 496 let Src2RC64 = _SrcRC; 497 let HasOpSel = 0; 498 let HasClamp = 0; 499 let HasIntClamp = 0; 500 let HasOMod = 0; 501 let HasModifiers = 0; 502 let AsmVOP3Base = "$vdst, $src0, $src1, $src2$cbsz$abid$blgp"; 503 let Ins64 = (ins Src0RC64:$src0, Src1RC64:$src1, Src2RC64:$src2, cbsz:$cbsz, abid:$abid, blgp:$blgp); 504 let InsVOP3Base = Ins64; 505 // Dst and SrcC cannot partially overlap if SrcC/Dst is bigger than 4 VGPRs. 506 // We then create two versions of the instruction: with tied dst and src2 507 // and with the earlyclobber flag on the dst. This is stricter than the 508 // actual HW restriction. In particular earlyclobber also affects src0 and 509 // src1 allocation which is not required. 510 bit NoDstOverlap = !gt(DstVT.Size, 128); 511} 512 513class VOPProfileSMFMAC<VOPProfile P, RegisterOperand _DstRC, 514 RegisterOperand _SrcARC, RegisterOperand _SrcBRC> 515 : VOPProfileMAI<P, _DstRC, _DstRC, _SrcARC> { 516 let Src1RC64 = _SrcBRC; 517 let Src2VT = DstVT; 518 let Asm64 = " $vdst, $src0, $src1, $idx$cbsz$abid"; 519 let Outs64 = (outs DstRC:$vdst); 520 let Ins64 = (ins Src0RC64:$src0, Src1RC64:$src1, VRegSrc_32:$idx, cbsz:$cbsz, abid:$abid, Src2RC64:$src2); 521} 522 523def VOPProfileMAI_F32_F32_X4 : VOPProfileMAI<VOP_V4F32_F32_F32_V4F32, AISrc_128_f32, ADst_128>; 524def VOPProfileMAI_F32_F32_X16 : VOPProfileMAI<VOP_V16F32_F32_F32_V16F32, AISrc_512_f32, ADst_512>; 525def VOPProfileMAI_F32_F32_X32 : VOPProfileMAI<VOP_V32F32_F32_F32_V32F32, AISrc_1024_f32, ADst_1024>; 526def VOPProfileMAI_I32_I32_X4 : VOPProfileMAI<VOP_V4I32_I32_I32_V4I32, AISrc_128_b32, ADst_128>; 527def VOPProfileMAI_I32_I32_X16 : VOPProfileMAI<VOP_V16I32_I32_I32_V16I32, AISrc_512_b32, ADst_512>; 528def VOPProfileMAI_I32_I32_X32 : VOPProfileMAI<VOP_V32I32_I32_I32_V32I32, AISrc_1024_b32, ADst_1024>; 529def VOPProfileMAI_F32_V2I16_X4 : VOPProfileMAI<VOP_V4F32_V2I16_V2I16_V4F32, AISrc_128_b32, ADst_128>; 530def VOPProfileMAI_F32_V2I16_X16 : VOPProfileMAI<VOP_V16F32_V2I16_V2I16_V16F32, AISrc_512_b32, ADst_512>; 531def VOPProfileMAI_F32_V2I16_X32 : VOPProfileMAI<VOP_V32F32_V2I16_V2I16_V32F32, AISrc_1024_b32, ADst_1024>; 532def VOPProfileMAI_F32_V4F16_X4 : VOPProfileMAI<VOP_V4F32_V4F16_V4F16_V4F32, AISrc_128_b32, ADst_128, AVSrc_64>; 533def VOPProfileMAI_F32_V4F16_X16 : VOPProfileMAI<VOP_V16F32_V4F16_V4F16_V16F32, AISrc_512_b32, ADst_512, AVSrc_64>; 534def VOPProfileMAI_F32_V4F16_X32 : VOPProfileMAI<VOP_V32F32_V4F16_V4F16_V32F32, AISrc_1024_b32, ADst_1024, AVSrc_64>; 535def VOPProfileMAI_F32_V4I16_X4 : VOPProfileMAI<VOP_V4F32_V4I16_V4I16_V4F32, AISrc_128_b32, ADst_128, AVSrc_64>; 536def VOPProfileMAI_F32_V4I16_X16 : VOPProfileMAI<VOP_V16F32_V4I16_V4I16_V16F32, AISrc_512_b32, ADst_512, AVSrc_64>; 537def VOPProfileMAI_F32_V4I16_X32 : VOPProfileMAI<VOP_V32F32_V4I16_V4I16_V32F32, AISrc_1024_b32, ADst_1024, AVSrc_64>; 538def VOPProfileMAI_F64_16X16X4F64 : VOPProfileMAI<VOP_V4F64_F64_F64_V4F64, AISrc_256_f64, ADst_256, AVSrc_64>; 539def VOPProfileMAI_F64_4X4X4F64 : VOPProfileMAI<VOP_F64_F64_F64_F64, AISrc_64_f64, ADst_64, AVSrc_64>; 540def VOPProfileMAI_I32_I64_X16 : VOPProfileMAI<VOP_V4I32_I64_I64_V4I32, AISrc_128_b32, ADst_128, AVSrc_64>; 541def VOPProfileMAI_I32_I64_X32 : VOPProfileMAI<VOP_V16I32_I64_I64_V16I32, AISrc_512_b32, ADst_512, AVSrc_64>; 542def VOPProfileMAI_F32_V2F32_X16 : VOPProfileMAI<VOP_V4F32_V2F32_V2F32_V4F32, AISrc_128_b32, ADst_128, AVSrc_64>; 543def VOPProfileMAI_F32_V2F32_X32 : VOPProfileMAI<VOP_V16F32_V2F32_V2F32_V16F32, AISrc_512_b32, ADst_512, AVSrc_64>; 544def VOPProfileMAI_F32_I64_X32 : VOPProfileMAI<VOP_V4F32_I64_I64_V4F32, AISrc_128_b32, ADst_128, AVSrc_64>; 545def VOPProfileMAI_F32_I64_X16 : VOPProfileMAI<VOP_V16F32_I64_I64_V16F32, AISrc_512_b32, ADst_512, AVSrc_64>; 546 547def VOPProfileMAI_F32_F32_X4_VCD : VOPProfileMAI<VOP_V4F32_F32_F32_V4F32, VISrc_128_f32, VDst_128>; 548def VOPProfileMAI_F32_F32_X16_VCD : VOPProfileMAI<VOP_V16F32_F32_F32_V16F32, VISrc_512_f32, VDst_512>; 549def VOPProfileMAI_F32_F32_X32_VCD : VOPProfileMAI<VOP_V32F32_F32_F32_V32F32, VISrc_1024_f32, VDst_1024>; 550def VOPProfileMAI_I32_I32_X4_VCD : VOPProfileMAI<VOP_V4I32_I32_I32_V4I32, VISrc_128_b32, VDst_128>; 551def VOPProfileMAI_I32_I32_X16_VCD : VOPProfileMAI<VOP_V16I32_I32_I32_V16I32, VISrc_512_b32, VDst_512>; 552def VOPProfileMAI_I32_I32_X32_VCD : VOPProfileMAI<VOP_V32I32_I32_I32_V32I32, VISrc_1024_b32, VDst_1024>; 553def VOPProfileMAI_F32_V2I16_X4_VCD : VOPProfileMAI<VOP_V4F32_V2I16_V2I16_V4F32, VISrc_128_b32, VDst_128>; 554def VOPProfileMAI_F32_V2I16_X16_VCD : VOPProfileMAI<VOP_V16F32_V2I16_V2I16_V16F32, VISrc_512_b32, VDst_512>; 555def VOPProfileMAI_F32_V2I16_X32_VCD : VOPProfileMAI<VOP_V32F32_V2I16_V2I16_V32F32, VISrc_1024_b32, VDst_1024>; 556def VOPProfileMAI_F32_V4F16_X4_VCD : VOPProfileMAI<VOP_V4F32_V4F16_V4F16_V4F32, VISrc_128_b32, VDst_128, AVSrc_64>; 557def VOPProfileMAI_F32_V4F16_X16_VCD : VOPProfileMAI<VOP_V16F32_V4F16_V4F16_V16F32, VISrc_512_b32, VDst_512, AVSrc_64>; 558def VOPProfileMAI_F32_V4F16_X32_VCD : VOPProfileMAI<VOP_V32F32_V4F16_V4F16_V32F32, VISrc_1024_b32, VDst_1024, AVSrc_64>; 559def VOPProfileMAI_F32_V4I16_X4_VCD : VOPProfileMAI<VOP_V4F32_V4I16_V4I16_V4F32, VISrc_128_b32, VDst_128, AVSrc_64>; 560def VOPProfileMAI_F32_V4I16_X16_VCD : VOPProfileMAI<VOP_V16F32_V4I16_V4I16_V16F32, VISrc_512_b32, VDst_512, AVSrc_64>; 561def VOPProfileMAI_F32_V4I16_X32_VCD : VOPProfileMAI<VOP_V32F32_V4I16_V4I16_V32F32, VISrc_1024_b32, VDst_1024, AVSrc_64>; 562def VOPProfileMAI_F64_16X16X4F64_VCD : VOPProfileMAI<VOP_V4F64_F64_F64_V4F64, VISrc_256_f64, VDst_256, AVSrc_64>; 563def VOPProfileMAI_F64_4X4X4F64_VCD : VOPProfileMAI<VOP_F64_F64_F64_F64, VISrc_64_f64, VDst_64, AVSrc_64>; 564def VOPProfileMAI_I32_I64_X16_VCD : VOPProfileMAI<VOP_V4I32_I64_I64_V4I32, VISrc_128_b32, VDst_128, AVSrc_64>; 565def VOPProfileMAI_I32_I64_X32_VCD : VOPProfileMAI<VOP_V16I32_I64_I64_V16I32, VISrc_512_b32, VDst_512, AVSrc_64>; 566def VOPProfileMAI_F32_V2F32_X16_VCD : VOPProfileMAI<VOP_V4F32_V2F32_V2F32_V4F32, VISrc_128_b32, VDst_128, AVSrc_64>; 567def VOPProfileMAI_F32_V2F32_X32_VCD : VOPProfileMAI<VOP_V16F32_V2F32_V2F32_V16F32, VISrc_512_b32, VDst_512, AVSrc_64>; 568def VOPProfileMAI_F32_I64_X32_VCD : VOPProfileMAI<VOP_V4F32_I64_I64_V4F32, VISrc_128_b32, VDst_128, AVSrc_64>; 569def VOPProfileMAI_F32_I64_X16_VCD : VOPProfileMAI<VOP_V16F32_I64_I64_V16F32, VISrc_512_b32, VDst_512, AVSrc_64>; 570 571def VOPProfileSMFMAC_F32_16X16X32_F16 : VOPProfileSMFMAC<VOP_V4F32_V4F16_V8F16_I32, AVDst_128, AVSrc_64, AVSrc_128>; 572def VOPProfileSMFMAC_F32_32X32X16_F16 : VOPProfileSMFMAC<VOP_V16F32_V4F16_V8F16_I32, AVDst_512, AVSrc_64, AVSrc_128>; 573def VOPProfileSMFMAC_F32_16X16X32_I16 : VOPProfileSMFMAC<VOP_V4F32_V4I16_V8I16_I32, AVDst_128, AVSrc_64, AVSrc_128>; 574def VOPProfileSMFMAC_F32_32X32X16_I16 : VOPProfileSMFMAC<VOP_V16F32_V4I16_V8I16_I32, AVDst_512, AVSrc_64, AVSrc_128>; 575def VOPProfileSMFMAC_I32_16X16X64_I8 : VOPProfileSMFMAC<VOP_V4I32_V2I32_V4I32_I32, AVDst_128, AVSrc_64, AVSrc_128>; 576def VOPProfileSMFMAC_I32_32X32X32_I8 : VOPProfileSMFMAC<VOP_V16I32_V2I32_V4I32_I32, AVDst_512, AVSrc_64, AVSrc_128>; 577def VOPProfileSMFMAC_F32_16X16X64_F8 : VOPProfileSMFMAC<VOP_V4F32_V2I32_V4I32_I32, AVDst_128, AVSrc_64, AVSrc_128>; 578def VOPProfileSMFMAC_F32_32X32X32_F8 : VOPProfileSMFMAC<VOP_V16F32_V2I32_V4I32_I32, AVDst_512, AVSrc_64, AVSrc_128>; 579 580class MFMATable <bit is_mac, string Name> { 581 bit IsMac = is_mac; 582 string FMAOp = Name; 583} 584 585class MAIFrag<SDPatternOperator Op, code pred> : PatFrag < 586 (ops node:$src0, node:$src1, node:$src2, node:$cbsz, node:$abid, node:$blgp), 587 (Op $src0, $src1, $src2, $cbsz, $abid, $blgp), 588 pred 589>; 590 591let GISelPredicateCode = [{ return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); }] in 592class AgprMAIFrag<SDPatternOperator Op> : 593 MAIFrag<Op, [{ return MF->getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); }]>; 594 595let GISelPredicateCode = [{ return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); }] in 596class VgprMAIFrag<SDPatternOperator Op> : 597 MAIFrag<Op, [{ return !MF->getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); }]>; 598 599let Predicates = [HasMAIInsts] in { 600 601let isAsCheapAsAMove = 1, isReMaterializable = 1 in { 602 defm V_ACCVGPR_READ_B32 : VOP3Inst<"v_accvgpr_read_b32", VOPProfileAccRead>; 603 let isMoveImm = 1 in { 604 defm V_ACCVGPR_WRITE_B32 : VOP3Inst<"v_accvgpr_write_b32", VOPProfileAccWrite>; 605 } // End isMoveImm = 1 606} // End isAsCheapAsAMove = 1, isReMaterializable = 1 607 608class MAIInst<string OpName, VOPProfile P, SDPatternOperator node> 609 : VOP3InstBase<OpName, P, node> { 610 Instruction Opcode = !cast<Instruction>(NAME); 611 bit is_dgemm = 0; 612 bit is_gfx940_xdl = 0; 613} 614 615multiclass MAIInst<string OpName, string P, SDPatternOperator node, 616 bit NoDstOverlap = !cast<VOPProfileMAI>("VOPProfileMAI_" # P).NoDstOverlap> { 617 let isConvergent = 1, mayRaiseFPException = 0, ReadsModeReg = 1 in { 618 // FP32 denorm mode is respected, rounding mode is not. Exceptions are not supported. 619 let Constraints = !if(NoDstOverlap, "@earlyclobber $vdst", "") in { 620 def _e64 : MAIInst<OpName, !cast<VOPProfileMAI>("VOPProfileMAI_" # P), 621 !if(NoDstOverlap, null_frag, AgprMAIFrag<node>)>, 622 MFMATable<0, NAME # "_e64">; 623 624 let SubtargetPredicate = isGFX90APlus, Mnemonic = OpName in 625 def _vgprcd_e64 : MAIInst<OpName # "_vgprcd", !cast<VOPProfileMAI>("VOPProfileMAI_" # P # "_VCD"), 626 !if(NoDstOverlap, null_frag, VgprMAIFrag<node>)>, 627 MFMATable<0, NAME # "_vgprcd_e64">; 628 } 629 630 if NoDstOverlap then { 631 let Constraints = !if(NoDstOverlap, "$vdst = $src2", ""), 632 isConvertibleToThreeAddress = NoDstOverlap, 633 Mnemonic = OpName in { 634 def "_mac_e64" : MAIInst<OpName # "_mac", !cast<VOPProfileMAI>("VOPProfileMAI_" # P), AgprMAIFrag<node>>, 635 MFMATable<1, NAME # "_e64">; 636 637 let SubtargetPredicate = isGFX90APlus in 638 def _mac_vgprcd_e64 : MAIInst<OpName # "_mac_vgprcd", !cast<VOPProfileMAI>("VOPProfileMAI_" # P # "_VCD"), 639 VgprMAIFrag<node>>, 640 MFMATable<1, NAME # "_vgprcd_e64">; 641 } 642 } 643 } // End isConvergent = 1, mayRaiseFPException = 0, ReadsModeReg = 1 644} 645 646defm V_MFMA_F32_4X4X1F32 : MAIInst<"v_mfma_f32_4x4x1f32", "F32_F32_X4", int_amdgcn_mfma_f32_4x4x1f32>; 647defm V_MFMA_F32_16X16X1F32 : MAIInst<"v_mfma_f32_16x16x1f32", "F32_F32_X16", int_amdgcn_mfma_f32_16x16x1f32>; 648defm V_MFMA_F32_16X16X4F32 : MAIInst<"v_mfma_f32_16x16x4f32", "F32_F32_X4", int_amdgcn_mfma_f32_16x16x4f32>; 649defm V_MFMA_F32_32X32X1F32 : MAIInst<"v_mfma_f32_32x32x1f32", "F32_F32_X32", int_amdgcn_mfma_f32_32x32x1f32>; 650defm V_MFMA_F32_32X32X2F32 : MAIInst<"v_mfma_f32_32x32x2f32", "F32_F32_X16", int_amdgcn_mfma_f32_32x32x2f32>; 651 652let is_gfx940_xdl = 1 in { 653defm V_MFMA_F32_4X4X4F16 : MAIInst<"v_mfma_f32_4x4x4f16", "F32_V4F16_X4", int_amdgcn_mfma_f32_4x4x4f16>; 654defm V_MFMA_I32_4X4X4I8 : MAIInst<"v_mfma_i32_4x4x4i8", "I32_I32_X4", int_amdgcn_mfma_i32_4x4x4i8>; 655defm V_MFMA_F32_16X16X4F16 : MAIInst<"v_mfma_f32_16x16x4f16", "F32_V4F16_X16", int_amdgcn_mfma_f32_16x16x4f16>; 656defm V_MFMA_F32_16X16X16F16 : MAIInst<"v_mfma_f32_16x16x16f16", "F32_V4F16_X4", int_amdgcn_mfma_f32_16x16x16f16>; 657defm V_MFMA_I32_16X16X4I8 : MAIInst<"v_mfma_i32_16x16x4i8", "I32_I32_X16", int_amdgcn_mfma_i32_16x16x4i8>; 658defm V_MFMA_F32_32X32X4F16 : MAIInst<"v_mfma_f32_32x32x4f16", "F32_V4F16_X32", int_amdgcn_mfma_f32_32x32x4f16>; 659defm V_MFMA_F32_32X32X8F16 : MAIInst<"v_mfma_f32_32x32x8f16", "F32_V4F16_X16", int_amdgcn_mfma_f32_32x32x8f16>; 660defm V_MFMA_I32_32X32X4I8 : MAIInst<"v_mfma_i32_32x32x4i8", "I32_I32_X32", int_amdgcn_mfma_i32_32x32x4i8>; 661} 662 663let Predicates = [isGFX908orGFX90A] in { 664defm V_MFMA_I32_16X16X16I8 : MAIInst<"v_mfma_i32_16x16x16i8", "I32_I32_X4", int_amdgcn_mfma_i32_16x16x16i8>; 665defm V_MFMA_I32_32X32X8I8 : MAIInst<"v_mfma_i32_32x32x8i8", "I32_I32_X16", int_amdgcn_mfma_i32_32x32x8i8>; 666defm V_MFMA_F32_4X4X2BF16 : MAIInst<"v_mfma_f32_4x4x2bf16", "F32_V2I16_X4", int_amdgcn_mfma_f32_4x4x2bf16>; 667defm V_MFMA_F32_16X16X2BF16 : MAIInst<"v_mfma_f32_16x16x2bf16", "F32_V2I16_X16", int_amdgcn_mfma_f32_16x16x2bf16>; 668defm V_MFMA_F32_16X16X8BF16 : MAIInst<"v_mfma_f32_16x16x8bf16", "F32_V2I16_X4", int_amdgcn_mfma_f32_16x16x8bf16>; 669defm V_MFMA_F32_32X32X2BF16 : MAIInst<"v_mfma_f32_32x32x2bf16", "F32_V2I16_X32", int_amdgcn_mfma_f32_32x32x2bf16>; 670defm V_MFMA_F32_32X32X4BF16 : MAIInst<"v_mfma_f32_32x32x4bf16", "F32_V2I16_X16", int_amdgcn_mfma_f32_32x32x4bf16>; 671} 672 673} // End SubtargetPredicate = HasMAIInsts 674 675let Predicates = [isGFX90APlus] in { 676 let is_gfx940_xdl = 1 in { 677 defm V_MFMA_F32_32X32X4BF16_1K : MAIInst<"v_mfma_f32_32x32x4bf16_1k", "F32_V4I16_X32", int_amdgcn_mfma_f32_32x32x4bf16_1k>; 678 defm V_MFMA_F32_16X16X4BF16_1K : MAIInst<"v_mfma_f32_16x16x4bf16_1k", "F32_V4I16_X16", int_amdgcn_mfma_f32_16x16x4bf16_1k>; 679 defm V_MFMA_F32_4X4X4BF16_1K : MAIInst<"v_mfma_f32_4x4x4bf16_1k", "F32_V4I16_X4", int_amdgcn_mfma_f32_4x4x4bf16_1k>; 680 defm V_MFMA_F32_32X32X8BF16_1K : MAIInst<"v_mfma_f32_32x32x8bf16_1k", "F32_V4I16_X16", int_amdgcn_mfma_f32_32x32x8bf16_1k>; 681 defm V_MFMA_F32_16X16X16BF16_1K : MAIInst<"v_mfma_f32_16x16x16bf16_1k", "F32_V4I16_X4", int_amdgcn_mfma_f32_16x16x16bf16_1k>; 682 } 683 684 let is_dgemm = 1 in { 685 defm V_MFMA_F64_16X16X4F64 : MAIInst<"v_mfma_f64_16x16x4f64", "F64_16X16X4F64", int_amdgcn_mfma_f64_16x16x4f64>; 686 defm V_MFMA_F64_4X4X4F64 : MAIInst<"v_mfma_f64_4x4x4f64", "F64_4X4X4F64", int_amdgcn_mfma_f64_4x4x4f64>; 687 } 688} // End Predicates = [isGFX90APlus] 689 690let Predicates = [isGFX940Plus], is_gfx940_xdl = 1 in { 691 defm V_MFMA_I32_32X32X16I8 : MAIInst<"v_mfma_i32_32x32x16i8", "I32_I64_X32", int_amdgcn_mfma_i32_32x32x16_i8>; 692 defm V_MFMA_I32_16X16X32I8 : MAIInst<"v_mfma_i32_16x16x32i8", "I32_I64_X16", int_amdgcn_mfma_i32_16x16x32_i8>; 693 defm V_MFMA_F32_16X16X8XF32 : MAIInst<"v_mfma_f32_16x16x8xf32", "F32_V2F32_X16", int_amdgcn_mfma_f32_16x16x8_xf32>; 694 defm V_MFMA_F32_32X32X4XF32 : MAIInst<"v_mfma_f32_32x32x4xf32", "F32_V2F32_X32", int_amdgcn_mfma_f32_32x32x4_xf32>; 695 defm V_MFMA_F32_16X16X32_BF8_BF8 : MAIInst<"v_mfma_f32_16x16x32_bf8_bf8", "F32_I64_X32", int_amdgcn_mfma_f32_16x16x32_bf8_bf8>; 696 defm V_MFMA_F32_16X16X32_BF8_FP8 : MAIInst<"v_mfma_f32_16x16x32_bf8_fp8", "F32_I64_X32", int_amdgcn_mfma_f32_16x16x32_bf8_fp8>; 697 defm V_MFMA_F32_16X16X32_FP8_BF8 : MAIInst<"v_mfma_f32_16x16x32_fp8_bf8", "F32_I64_X32", int_amdgcn_mfma_f32_16x16x32_fp8_bf8>; 698 defm V_MFMA_F32_16X16X32_FP8_FP8 : MAIInst<"v_mfma_f32_16x16x32_fp8_fp8", "F32_I64_X32", int_amdgcn_mfma_f32_16x16x32_fp8_fp8>; 699 defm V_MFMA_F32_32X32X16_BF8_BF8 : MAIInst<"v_mfma_f32_32x32x16_bf8_bf8", "F32_I64_X16", int_amdgcn_mfma_f32_32x32x16_bf8_bf8>; 700 defm V_MFMA_F32_32X32X16_BF8_FP8 : MAIInst<"v_mfma_f32_32x32x16_bf8_fp8", "F32_I64_X16", int_amdgcn_mfma_f32_32x32x16_bf8_fp8>; 701 defm V_MFMA_F32_32X32X16_FP8_BF8 : MAIInst<"v_mfma_f32_32x32x16_fp8_bf8", "F32_I64_X16", int_amdgcn_mfma_f32_32x32x16_fp8_bf8>; 702 defm V_MFMA_F32_32X32X16_FP8_FP8 : MAIInst<"v_mfma_f32_32x32x16_fp8_fp8", "F32_I64_X16", int_amdgcn_mfma_f32_32x32x16_fp8_fp8>; 703} // End Predicates = [isGFX940Plus], is_gfx940_xdl = 1 704 705multiclass SMFMACInst<string OpName, string P, SDPatternOperator node> { 706 let Constraints = "$vdst = $src2", DisableEncoding = "$src2", 707 isConvergent = 1, mayRaiseFPException = 0, ReadsModeReg = 1, is_gfx940_xdl = 1 in { 708 def _e64 : MAIInst<OpName, !cast<VOPProfileSMFMAC>("VOPProfileSMFMAC_" # P), node>; 709 } 710} 711 712let SubtargetPredicate = isGFX940Plus in { 713defm V_SMFMAC_F32_16X16X32_F16 : SMFMACInst<"v_smfmac_f32_16x16x32_f16", "F32_16X16X32_F16", int_amdgcn_smfmac_f32_16x16x32_f16>; 714defm V_SMFMAC_F32_32X32X16_F16 : SMFMACInst<"v_smfmac_f32_32x32x16_f16", "F32_32X32X16_F16", int_amdgcn_smfmac_f32_32x32x16_f16>; 715defm V_SMFMAC_F32_16X16X32_BF16 : SMFMACInst<"v_smfmac_f32_16x16x32_bf16", "F32_16X16X32_I16", int_amdgcn_smfmac_f32_16x16x32_bf16>; 716defm V_SMFMAC_F32_32X32X16_BF16 : SMFMACInst<"v_smfmac_f32_32x32x16_bf16", "F32_32X32X16_I16", int_amdgcn_smfmac_f32_32x32x16_bf16>; 717defm V_SMFMAC_I32_16X16X64_I8 : SMFMACInst<"v_smfmac_i32_16x16x64_i8", "I32_16X16X64_I8", int_amdgcn_smfmac_i32_16x16x64_i8>; 718defm V_SMFMAC_I32_32X32X32_I8 : SMFMACInst<"v_smfmac_i32_32x32x32_i8", "I32_32X32X32_I8", int_amdgcn_smfmac_i32_32x32x32_i8>; 719defm V_SMFMAC_F32_16X16X64_BF8_BF8 : SMFMACInst<"v_smfmac_f32_16x16x64_bf8_bf8", "F32_16X16X64_F8", int_amdgcn_smfmac_f32_16x16x64_bf8_bf8>; 720defm V_SMFMAC_F32_16X16X64_BF8_FP8 : SMFMACInst<"v_smfmac_f32_16x16x64_bf8_fp8", "F32_16X16X64_F8", int_amdgcn_smfmac_f32_16x16x64_bf8_fp8>; 721defm V_SMFMAC_F32_16X16X64_FP8_BF8 : SMFMACInst<"v_smfmac_f32_16x16x64_fp8_bf8", "F32_16X16X64_F8", int_amdgcn_smfmac_f32_16x16x64_fp8_bf8>; 722defm V_SMFMAC_F32_16X16X64_FP8_FP8 : SMFMACInst<"v_smfmac_f32_16x16x64_fp8_fp8", "F32_16X16X64_F8", int_amdgcn_smfmac_f32_16x16x64_fp8_fp8>; 723defm V_SMFMAC_F32_32X32X32_BF8_BF8 : SMFMACInst<"v_smfmac_f32_32x32x32_bf8_bf8", "F32_32X32X32_F8", int_amdgcn_smfmac_f32_32x32x32_bf8_bf8>; 724defm V_SMFMAC_F32_32X32X32_BF8_FP8 : SMFMACInst<"v_smfmac_f32_32x32x32_bf8_fp8", "F32_32X32X32_F8", int_amdgcn_smfmac_f32_32x32x32_bf8_fp8>; 725defm V_SMFMAC_F32_32X32X32_FP8_BF8 : SMFMACInst<"v_smfmac_f32_32x32x32_fp8_bf8", "F32_32X32X32_F8", int_amdgcn_smfmac_f32_32x32x32_fp8_bf8>; 726defm V_SMFMAC_F32_32X32X32_FP8_FP8 : SMFMACInst<"v_smfmac_f32_32x32x32_fp8_fp8", "F32_32X32X32_F8", int_amdgcn_smfmac_f32_32x32x32_fp8_fp8>; 727} 728 729def MAIInstInfoTable : GenericTable { 730 let FilterClass = "MAIInst"; 731 let CppTypeName = "MAIInstInfo"; 732 let Fields = [ 733 "Opcode", "is_dgemm", "is_gfx940_xdl" 734 ]; 735 736 let PrimaryKey = ["Opcode"]; 737 let PrimaryKeyName = "getMAIInstInfoHelper"; 738} 739 740let SubtargetPredicate = HasPackedFP32Ops, isCommutable = 1, isReMaterializable = 1 in { 741 defm V_PK_FMA_F32 : VOP3PInst<"v_pk_fma_f32", VOP3P_Profile<VOP_V2F32_V2F32_V2F32_V2F32, VOP3_PACKED>, any_fma>; 742 defm V_PK_MUL_F32 : VOP3PInst<"v_pk_mul_f32", VOP3P_Profile<VOP_V2F32_V2F32_V2F32, VOP3_PACKED>, any_fmul>; 743 defm V_PK_ADD_F32 : VOP3PInst<"v_pk_add_f32", VOP3P_Profile<VOP_V2F32_V2F32_V2F32, VOP3_PACKED>, any_fadd>; 744 defm V_PK_MOV_B32 : VOP3PInst<"v_pk_mov_b32", VOP3P_Profile<VOP_V2I32_V2I32_V2I32, VOP3_PACKED>>; 745} // End SubtargetPredicate = HasPackedFP32Ops, isCommutable = 1 746 747def : MnemonicAlias<"v_accvgpr_read", "v_accvgpr_read_b32">; 748def : MnemonicAlias<"v_accvgpr_write", "v_accvgpr_write_b32">; 749 750class VOPProfileWMMA<VOPProfile P, string Suffix, RegisterOperand _Src01RC64, bit _HasClamp, bit _HasOpSel> : VOP3P_Profile<P> { 751 let DstRC = !if(!eq(Suffix, "_w32"), VDst_256, VDst_128); 752 let Src0RC64 = _Src01RC64; 753 let Src1RC64 = _Src01RC64; 754 let Src2RC64 = !if(!eq(Suffix, "_w32"), VISrc_256_f64, VISrc_128_f32); 755 let HasClamp = _HasClamp; 756 let HasOpSel = _HasOpSel; 757 let IsPacked = 1; 758 let IsWMMA = 1; 759} 760 761def VOP_V8F32_V16F16_V16F16_V8F32 : VOPProfile <[v8f32, v16f16, v16f16, v8f32]>; 762def VOP_V8F32_V16I16_V16I16_V8F32 : VOPProfile <[v8f32, v16i16, v16i16, v8f32]>; 763def VOP_V16F16_V16F16_V16F16_V16F16 : VOPProfile <[v16f16, v16f16, v16f16, v16f16]>; 764def VOP_V16I16_V16I16_V16I16_V16I16 : VOPProfile <[v16i16, v16i16, v16i16, v16i16]>; 765def VOP_V8I32_V4I32_V4I32_V8I32 : VOPProfile <[v8i32, v4i32, v4i32, v8i32]>; 766def VOP_V8I32_V2I32_V2I32_V8I32 : VOPProfile <[v8i32, v2i32, v2i32, v8i32]>; 767 768def VOP_V4F32_V16F16_V16F16_V4F32 : VOPProfile <[v4f32, v16f16, v16f16, v4f32]>; 769def VOP_V4F32_V16I16_V16I16_V4F32 : VOPProfile <[v4f32, v16i16, v16i16, v4f32]>; 770def VOP_V8F16_V16F16_V16F16_V8F16 : VOPProfile <[v8f16, v16f16, v16f16, v8f16]>; 771def VOP_V8I16_V16I16_V16I16_V8I16 : VOPProfile <[v8i16, v16i16, v16i16, v8i16]>; 772def VOP_V4I32_V4I32_V4I32_V4I32 : VOPProfile <[v4i32, v4i32, v4i32, v4i32]>; 773def VOP_V4I32_V2I32_V2I32_V4I32 : VOPProfile <[v4i32, v2i32, v2i32, v4i32]>; 774 775 776class WMMAType <bits<2> val> { 777 bit hasClamp = val{0}; 778 bit hasOpsel = val{1}; 779} 780 781def WMMARegular : WMMAType<0b00>; 782def WMMAUIClamp : WMMAType<0b01>; 783def WMMAOpSel : WMMAType<0b10>; 784 785class WMMARegularPat<Instruction Inst, SDPatternOperator node, VOPProfile P> : 786 GCNPat < (P.DstVT (node 787 (P.Src0VT (VOP3PMods P.Src0VT:$src0, i32:$src0_modifiers)), 788 (P.Src1VT (VOP3PMods P.Src1VT:$src1, i32:$src1_modifiers)), 789 (P.Src2VT (VOP3PMods P.Src2VT:$src2, i32:$src2_modifiers)) 790 )), 791 (P.DstVT (Inst i32:$src0_modifiers, P.Src0VT:$src0, i32:$src1_modifiers, P.Src1VT:$src1, $src2_modifiers, P.Src2VT:$src2)) 792>; 793 794class WMMAOpSelPat<Instruction Inst, SDPatternOperator node, VOPProfile P> : 795 GCNPat < (P.DstVT (node 796 (P.Src0VT P.Src0VT:$src0), 797 (P.Src1VT P.Src1VT:$src1), 798 (P.Src2VT P.Src2VT:$src2), (WMMAOpSelVOP3PMods i32:$src2_modifiers) 799 )), 800 (P.DstVT (Inst (i32 8), P.Src0VT:$src0, (i32 8), P.Src1VT:$src1, i32:$src2_modifiers, P.Src2VT:$src2)) 801>; 802 803class WMMAUIClampPat<Instruction Inst, SDPatternOperator node, VOPProfile P> : 804 GCNPat < (P.DstVT (node 805 (DotIUVOP3PMods i32:$src0_modifiers), (P.Src0VT P.Src0VT:$src0), 806 (DotIUVOP3PMods i32:$src1_modifiers), (P.Src1VT P.Src1VT:$src1), 807 (P.Src2VT P.Src2VT:$src2), (i1 timm:$clamp) 808 )), 809 (P.DstVT (Inst i32:$src0_modifiers, P.Src0VT:$src0, i32:$src1_modifiers, P.Src1VT:$src1, (i32 8), P.Src2VT:$src2, i1:$clamp)) 810>; 811 812class WMMAOpcodeMapping<Instruction TwoAddr, Instruction ThreeAddr> { 813 Instruction Opcode2Addr = TwoAddr; 814 Instruction Opcode3Addr = ThreeAddr; 815 Predicate WaveSizePredicate; 816} 817 818def WMMAOpcode : GenericEnum { 819 let FilterClass = "VOP3P_Pseudo"; 820} 821 822class WMMAMappingTable : GenericTable { 823 let FilterClass = "WMMAOpcodeMapping"; 824 let CppTypeName = "WMMAOpcodeMappingInfo"; 825 let Fields = ["Opcode2Addr", "Opcode3Addr"]; 826 string TypeOf_Opcode2Addr = "WMMAOpcode"; 827 string TypeOf_Opcode3Addr = "WMMAOpcode"; 828} 829 830def WMMAOpcode2AddrMappingTable : WMMAMappingTable { 831 let PrimaryKey = ["Opcode2Addr"]; 832 let PrimaryKeyName = "getWMMAMappingInfoFrom2AddrOpcode"; 833} 834 835def WMMAOpcode3AddrMappingTable : WMMAMappingTable { 836 let PrimaryKey = ["Opcode3Addr"]; 837 let PrimaryKeyName = "getWMMAMappingInfoFrom3AddrOpcode"; 838} 839 840// The WMMA instruction has extra constraints: 841// Matrices A and B cannot overlap with D. C cannot partially overlap with D, 842// but it is OK for them to be the same (which is a typical case). 843// 844// We implement it as follows: 845// 1) Map the intrinsic to the pseudo where D is tied to C ($vdst = $src2). 846// 2) The pass twoaddressinstruction checks if src2 is live and if that is the case 847// it converts the default pseudo to the pseudo where src2 is not the same as vdst. 848// 3) @earlyclobber on the destination satisfies the constraint during RA. 849 850multiclass WMMAInst<string Suffix, string Instr, VOPProfile P, SDPatternOperator node = null_frag, RegisterOperand _Src01RC64 = VRegSrc_256, WMMAType Type> { 851 852 defvar WMMAConstraints2Addr = "@earlyclobber $vdst,$vdst = $src2"; 853 defvar WMMAConstraints3Addr = "@earlyclobber $vdst"; 854 855 defvar WMMAProfile = VOPProfileWMMA<P, Suffix, _Src01RC64, Type.hasClamp, Type.hasOpsel>; 856 if !eq(Suffix, "_w32") then { 857 let Mnemonic = Instr, mayRaiseFPException = 0, ReadsModeReg = 0 in { 858 let Constraints = WMMAConstraints2Addr, isConvertibleToThreeAddress = 1 in { 859 def _twoaddr_w32 : VOP3P_Pseudo<Instr # Suffix, WMMAProfile>; 860 } 861 let Constraints = WMMAConstraints3Addr, SchedRW = [Write32Bit, Write32Bit] in { 862 def _threeaddr_w32 : VOP3P_Pseudo<Instr # Suffix, WMMAProfile>; 863 } 864 } 865 def : WMMAOpcodeMapping<!cast<Instruction>(NAME # _twoaddr_w32), 866 !cast<Instruction>(NAME # _threeaddr_w32)>; 867 } else if !eq(Suffix, "_w64") then { 868 let Mnemonic = Instr, mayRaiseFPException = 0, ReadsModeReg = 0 in { 869 let Constraints = WMMAConstraints2Addr, isConvertibleToThreeAddress = 1 in { 870 def _twoaddr_w64 : VOP3P_Pseudo<Instr # Suffix, WMMAProfile>; 871 } 872 let Constraints = WMMAConstraints3Addr, SchedRW = [Write32Bit, Write32Bit] in { 873 def _threeaddr_w64 : VOP3P_Pseudo<Instr # Suffix, WMMAProfile>; 874 } 875 } 876 def : WMMAOpcodeMapping<!cast<Instruction>(NAME # _twoaddr_w64), 877 !cast<Instruction>(NAME # _threeaddr_w64)>; 878 } 879 880 if !eq(Type, WMMAOpSel) then { 881 def : WMMAOpSelPat<!cast<Instruction>(NAME # _twoaddr # Suffix), node, P>; 882 } else if !eq(Type, WMMAUIClamp) then { 883 def : WMMAUIClampPat<!cast<Instruction>(NAME # _twoaddr # Suffix), node, P>; 884 } else { 885 def : WMMARegularPat<!cast<Instruction>(NAME # _twoaddr # Suffix), node, P>; 886 } 887} 888 889 890let WaveSizePredicate = isWave32 in { 891 defm V_WMMA_F32_16X16X16_F16 : WMMAInst<"_w32", "v_wmma_f32_16x16x16_f16", VOP_V8F32_V16F16_V16F16_V8F32, int_amdgcn_wmma_f32_16x16x16_f16, VRegSrc_256, WMMARegular>; 892 defm V_WMMA_F32_16X16X16_BF16 : WMMAInst<"_w32", "v_wmma_f32_16x16x16_bf16", VOP_V8F32_V16I16_V16I16_V8F32, int_amdgcn_wmma_f32_16x16x16_bf16, VRegSrc_256, WMMARegular>; 893 defm V_WMMA_F16_16X16X16_F16 : WMMAInst<"_w32", "v_wmma_f16_16x16x16_f16", VOP_V16F16_V16F16_V16F16_V16F16, int_amdgcn_wmma_f16_16x16x16_f16, VRegSrc_256, WMMAOpSel>; 894 defm V_WMMA_BF16_16X16X16_BF16 : WMMAInst<"_w32", "v_wmma_bf16_16x16x16_bf16", VOP_V16I16_V16I16_V16I16_V16I16, int_amdgcn_wmma_bf16_16x16x16_bf16, VRegSrc_256, WMMAOpSel>; 895 defm V_WMMA_I32_16X16X16_IU8 : WMMAInst<"_w32", "v_wmma_i32_16x16x16_iu8", VOP_V8I32_V4I32_V4I32_V8I32, int_amdgcn_wmma_i32_16x16x16_iu8, VRegSrc_128, WMMAUIClamp>; 896 defm V_WMMA_I32_16X16X16_IU4 : WMMAInst<"_w32", "v_wmma_i32_16x16x16_iu4", VOP_V8I32_V2I32_V2I32_V8I32, int_amdgcn_wmma_i32_16x16x16_iu4, VRegSrc_64, WMMAUIClamp>; 897} 898 899let WaveSizePredicate = isWave64 in { 900 defm V_WMMA_F32_16X16X16_F16 : WMMAInst<"_w64", "v_wmma_f32_16x16x16_f16", VOP_V4F32_V16F16_V16F16_V4F32, int_amdgcn_wmma_f32_16x16x16_f16, VRegSrc_256, WMMARegular>; 901 defm V_WMMA_F32_16X16X16_BF16 : WMMAInst<"_w64", "v_wmma_f32_16x16x16_bf16", VOP_V4F32_V16I16_V16I16_V4F32, int_amdgcn_wmma_f32_16x16x16_bf16, VRegSrc_256, WMMARegular>; 902 defm V_WMMA_F16_16X16X16_F16 : WMMAInst<"_w64", "v_wmma_f16_16x16x16_f16", VOP_V8F16_V16F16_V16F16_V8F16, int_amdgcn_wmma_f16_16x16x16_f16, VRegSrc_256, WMMAOpSel>; 903 defm V_WMMA_BF16_16X16X16_BF16 : WMMAInst<"_w64", "v_wmma_bf16_16x16x16_bf16", VOP_V8I16_V16I16_V16I16_V8I16, int_amdgcn_wmma_bf16_16x16x16_bf16, VRegSrc_256, WMMAOpSel>; 904 defm V_WMMA_I32_16X16X16_IU8 : WMMAInst<"_w64", "v_wmma_i32_16x16x16_iu8", VOP_V4I32_V4I32_V4I32_V4I32, int_amdgcn_wmma_i32_16x16x16_iu8, VRegSrc_128, WMMAUIClamp>; 905 defm V_WMMA_I32_16X16X16_IU4 : WMMAInst<"_w64", "v_wmma_i32_16x16x16_iu4", VOP_V4I32_V2I32_V2I32_V4I32, int_amdgcn_wmma_i32_16x16x16_iu4, VRegSrc_64, WMMAUIClamp>; 906 907} 908 909//===----------------------------------------------------------------------===// 910// Begin Real Encodings 911//===----------------------------------------------------------------------===// 912 913class VOP3P_DPP16<bits<7> op, VOP_DPP_Pseudo ps, int subtarget, 914 string opName = ps.OpName> 915 : VOP3P_DPP<op, opName, ps.Pfl, 1>, SIMCInstr<ps.PseudoInstr, subtarget> { 916 let hasSideEffects = ps.hasSideEffects; 917 let Defs = ps.Defs; 918 let SchedRW = ps.SchedRW; 919 let Uses = ps.Uses; 920 let AssemblerPredicate = HasDPP16; 921 let SubtargetPredicate = HasDPP16; 922 let OtherPredicates = ps.OtherPredicates; 923} 924 925class VOP3P_DPP8_Base<bits<7> op, VOP_Pseudo ps, string opName = ps.OpName> 926 : VOP3P_DPP8<op, opName, ps.Pfl> { 927 let hasSideEffects = ps.hasSideEffects; 928 let Defs = ps.Defs; 929 let SchedRW = ps.SchedRW; 930 let Uses = ps.Uses; 931 let OtherPredicates = ps.OtherPredicates; 932} 933 934//===----------------------------------------------------------------------===// 935// GFX11. 936//===----------------------------------------------------------------------===// 937 938let AssemblerPredicate = isGFX11Plus, 939 DecoderNamespace = "GFX11" in { 940 941 multiclass VOP3P_Real_gfx11<bits<7> op, string backing_ps_name = NAME, 942 string asmName = !cast<VOP3P_Pseudo>(NAME).Mnemonic> { 943 def _gfx11 : VOP3P_Real<!cast<VOP3P_Pseudo>(backing_ps_name), 944 SIEncodingFamily.GFX11, asmName>, 945 VOP3Pe_gfx11<op, !cast<VOP3P_Pseudo>(backing_ps_name).Pfl>; 946 } 947 948 multiclass VOP3P_Real_dpp_gfx11<bits<7> op, string backing_ps_name = NAME, 949 string asmName = !cast<VOP3P_Pseudo>(NAME).Mnemonic> { 950 defvar ps = !cast<VOP3P_Pseudo>(backing_ps_name); 951 def _dpp_gfx11 952 : VOP3P_DPP16<op, !cast<VOP_DPP_Pseudo>(backing_ps_name #"_dpp"), 953 SIEncodingFamily.GFX11> { 954 let AsmString = asmName #ps.Pfl.AsmVOP3DPP16; 955 let DecoderNamespace = "DPPGFX11"; 956 } 957 } 958 959 multiclass VOP3P_Real_dpp8_gfx11<bits<7> op, string backing_ps_name = NAME, 960 string asmName = !cast<VOP3P_Pseudo>(NAME).Mnemonic> { 961 defvar ps = !cast<VOP3P_Pseudo>(backing_ps_name); 962 def _dpp8_gfx11 : VOP3P_DPP8_Base<op, ps> { 963 let AsmString = asmName #ps.Pfl.AsmVOP3DPP8; 964 let DecoderNamespace = "DPP8GFX11"; 965 } 966 } 967 968 multiclass VOP3P_Realtriple_gfx11<bits<7> op, string backing_ps_name = NAME, 969 string asmName = !cast<VOP3P_Pseudo>(NAME).Mnemonic> 970 : VOP3P_Real_gfx11<op, backing_ps_name, asmName>, 971 VOP3P_Real_dpp_gfx11<op, backing_ps_name, asmName>, 972 VOP3P_Real_dpp8_gfx11<op, backing_ps_name, asmName>; 973} // End AssemblerPredicate = isGFX11Plus, DecoderNamespace = "GFX11" 974 975defm V_DOT4_I32_IU8 : VOP3P_Real_gfx11 <0x16>; 976defm V_DOT8_I32_IU4 : VOP3P_Real_gfx11 <0x18>; 977defm V_DOT2_F32_BF16 : VOP3P_Real_gfx11 <0x1a>; 978 979multiclass VOP3P_Real_WMMA <bits<7> op> { 980 let WaveSizePredicate = isWave32, DecoderNamespace = "GFX11" in { 981 defm _twoaddr_w32 : VOP3P_Real_gfx11 <op>; 982 } 983 let WaveSizePredicate = isWave64, DecoderNamespace = "WMMAGFX11" in { 984 defm _twoaddr_w64 : VOP3P_Real_gfx11 <op>; 985 } 986} 987 988defm V_WMMA_F32_16X16X16_F16 : VOP3P_Real_WMMA <0x040>; 989defm V_WMMA_F32_16X16X16_BF16 : VOP3P_Real_WMMA <0x041>; 990defm V_WMMA_F16_16X16X16_F16 : VOP3P_Real_WMMA <0x042>; 991defm V_WMMA_BF16_16X16X16_BF16 : VOP3P_Real_WMMA <0x043>; 992defm V_WMMA_I32_16X16X16_IU8 : VOP3P_Real_WMMA <0x044>; 993defm V_WMMA_I32_16X16X16_IU4 : VOP3P_Real_WMMA <0x045>; 994 995//===----------------------------------------------------------------------===// 996// GFX8 (VI) 997//===----------------------------------------------------------------------===// 998 999multiclass VOP3P_Real_vi<bits<7> op> { 1000 def _vi : VOP3P_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>, 1001 VOP3Pe <op, !cast<VOP3_Pseudo>(NAME).Pfl> { 1002 let AssemblerPredicate = HasVOP3PInsts; 1003 let DecoderNamespace = "GFX8"; 1004 let VOP3P = 1; 1005 } 1006} 1007 1008multiclass VOP3P_Real_MAI<bits<7> op> { 1009 def _vi : VOP3P_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>, 1010 VOP3Pe_MAI <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl, ?> { 1011 let AssemblerPredicate = HasMAIInsts; 1012 let DecoderNamespace = "GFX8"; 1013 let Inst{14} = ?; // op_sel_hi(2) 1014 let Inst{59} = ?; // op_sel_hi(0) 1015 let Inst{60} = ?; // op_sel_hi(1) 1016 } 1017} 1018 1019let Constraints = "" in { 1020multiclass VOP3P_Real_MFMA_gfx90a<bits<7> op> { 1021 let SubtargetPredicate = isGFX90AOnly, 1022 AssemblerPredicate = isGFX90AOnly, DecoderNamespace = "GFX90A" in { 1023 def _gfx90a_acd : VOP3P_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX90A>, 1024 VOP3Pe_MAI <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl, 1>; 1025 1026 def _gfx90a_vcd : VOP3P_Real<!cast<VOP3_Pseudo>(NAME # "_vgprcd" # "_e64"), SIEncodingFamily.GFX90A>, 1027 VOP3Pe_MAI <op, !cast<VOP3_Pseudo>(NAME # "_vgprcd" # "_e64").Pfl, 0>; 1028 } // End AssemblerPredicate = isGFX90AOnly, DecoderNamespace = "GFX90A" 1029} 1030} 1031 1032multiclass VOP3P_Real_MFMA_gfx940_aliases<string NameFrom, string NameTo, string Op, 1033 VOP3_Pseudo PS_ACD = !cast<VOP3_Pseudo>(Op # "_e64"), 1034 VOP3_Pseudo PS_VCD = !cast<VOP3_Pseudo>(Op # "_vgprcd" # "_e64"), 1035 VOPProfile Pfl_ACD = PS_ACD.Pfl, 1036 VOPProfile Pfl_VCD = PS_VCD.Pfl> { 1037 let Predicates = [isGFX940Plus] in { 1038 if !ne(NameFrom, NameTo) then { 1039 def : InstAlias <NameTo # " " # PS_ACD.AsmOperands, 1040 (!cast<VOP3P_Real>(Op # "_gfx940_acd") Pfl_ACD.DstRC:$vdst, 1041 Pfl_ACD.Src0RC64:$src0, Pfl_ACD.Src1RC64:$src1, Pfl_ACD.Src2RC64:$src2, 1042 cbsz:$cbsz, abid:$abid, blgp:$blgp)>, PredicateControl; 1043 def : InstAlias <NameTo # " " # PS_VCD.AsmOperands, 1044 (!cast<VOP3P_Real>(Op # "_gfx940_vcd") Pfl_VCD.DstRC:$vdst, 1045 Pfl_VCD.Src0RC64:$src0, Pfl_VCD.Src1RC64:$src1, Pfl_VCD.Src2RC64:$src2, 1046 cbsz:$cbsz, abid:$abid, blgp:$blgp)>, PredicateControl; 1047 } 1048 } // End Predicates = [isGFX940Plus] 1049} 1050 1051multiclass VOP3P_Real_MFMA_gfx940<bits<7> op, string Name = !cast<VOP3_Pseudo>(NAME#"_e64").Mnemonic, 1052 VOP3_Pseudo PS_ACD = !cast<VOP3_Pseudo>(NAME # "_e64"), 1053 VOP3_Pseudo PS_VCD = !cast<VOP3_Pseudo>(NAME # "_vgprcd" # "_e64")> { 1054 let SubtargetPredicate = isGFX940Plus, 1055 AssemblerPredicate = isGFX940Plus, DecoderNamespace = "GFX940", 1056 AsmString = Name # PS_ACD.AsmOperands, Constraints = "" in { 1057 def _gfx940_acd : VOP3P_Real<PS_ACD, SIEncodingFamily.GFX940>, 1058 VOP3Pe_MAI <op, PS_ACD.Pfl, 1>; 1059 1060 def _gfx940_vcd : VOP3P_Real<PS_VCD, SIEncodingFamily.GFX940>, 1061 VOP3Pe_MAI <op, PS_VCD.Pfl, 0>; 1062 } // End AssemblerPredicate = isGFX940Plus, DecoderNamespace = "GFX940" 1063 1064 defm : VOP3P_Real_MFMA_gfx940_aliases<Name, PS_ACD.Mnemonic, NAME>; 1065 1066 if !ne(!subst("_1k", "", PS_ACD.Mnemonic), PS_ACD.Mnemonic) then 1067 defm : VOP3P_Real_MFMA_gfx940_aliases<Name, !subst("_1k", "", PS_ACD.Mnemonic), NAME>; 1068} 1069 1070multiclass VOP3P_Real_MFMA<bits<7> op, string GFX940Name = !cast<VOP3_Pseudo>(NAME#"_e64").Mnemonic> : 1071 VOP3P_Real_MFMA_gfx90a <op>, 1072 VOP3P_Real_MFMA_gfx940 <op, GFX940Name> { 1073 def _vi : VOP3P_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>, 1074 VOP3Pe_MAI <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl, ?> { 1075 let AssemblerPredicate = HasMAIInsts; 1076 let DecoderNamespace = "GFX8"; 1077 let Constraints = ""; 1078 } 1079} 1080 1081multiclass VOP3P_Real_SMFMAC<bits<7> op, string alias> { 1082 def _gfx940 : VOP3P_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>, 1083 VOP3Pe_SMFMAC <op> { 1084 let AssemblerPredicate = isGFX940Plus; 1085 let DecoderNamespace = "GFX8"; 1086 } 1087 def : MnemonicAlias<alias, !cast<VOP3_Pseudo>(NAME#"_e64").Mnemonic>; 1088} 1089 1090defm V_PK_MAD_I16 : VOP3P_Real_vi <0x00>; 1091defm V_PK_MUL_LO_U16 : VOP3P_Real_vi <0x01>; 1092defm V_PK_ADD_I16 : VOP3P_Real_vi <0x02>; 1093defm V_PK_SUB_I16 : VOP3P_Real_vi <0x03>; 1094defm V_PK_LSHLREV_B16 : VOP3P_Real_vi <0x04>; 1095defm V_PK_LSHRREV_B16 : VOP3P_Real_vi <0x05>; 1096defm V_PK_ASHRREV_I16 : VOP3P_Real_vi <0x06>; 1097defm V_PK_MAX_I16 : VOP3P_Real_vi <0x07>; 1098defm V_PK_MIN_I16 : VOP3P_Real_vi <0x08>; 1099defm V_PK_MAD_U16 : VOP3P_Real_vi <0x09>; 1100 1101defm V_PK_ADD_U16 : VOP3P_Real_vi <0x0a>; 1102defm V_PK_SUB_U16 : VOP3P_Real_vi <0x0b>; 1103defm V_PK_MAX_U16 : VOP3P_Real_vi <0x0c>; 1104defm V_PK_MIN_U16 : VOP3P_Real_vi <0x0d>; 1105defm V_PK_FMA_F16 : VOP3P_Real_vi <0x0e>; 1106defm V_PK_ADD_F16 : VOP3P_Real_vi <0x0f>; 1107defm V_PK_MUL_F16 : VOP3P_Real_vi <0x10>; 1108defm V_PK_MIN_F16 : VOP3P_Real_vi <0x11>; 1109defm V_PK_MAX_F16 : VOP3P_Real_vi <0x12>; 1110 1111 1112let SubtargetPredicate = HasMadMixInsts in { 1113defm V_MAD_MIX_F32 : VOP3P_Real_vi <0x20>; 1114defm V_MAD_MIXLO_F16 : VOP3P_Real_vi <0x21>; 1115defm V_MAD_MIXHI_F16 : VOP3P_Real_vi <0x22>; 1116} 1117 1118let SubtargetPredicate = HasFmaMixInsts in { 1119let DecoderNamespace = "GFX9_DL" in { 1120// The mad_mix instructions were renamed and their behaviors changed, 1121// but the opcode stayed the same so we need to put these in a 1122// different DecoderNamespace to avoid the ambiguity. 1123defm V_FMA_MIX_F32 : VOP3P_Real_vi <0x20>; 1124defm V_FMA_MIXLO_F16 : VOP3P_Real_vi <0x21>; 1125defm V_FMA_MIXHI_F16 : VOP3P_Real_vi <0x22>; 1126} 1127} 1128 1129 1130defm V_DOT2_I32_I16 : VOP3P_Real_vi <0x26>; 1131defm V_DOT2_U32_U16 : VOP3P_Real_vi <0x27>; 1132 1133defm V_DOT2_F32_F16 : VOP3P_Real_vi <0x23>; 1134defm V_DOT4_U32_U8 : VOP3P_Real_vi <0x29>; 1135defm V_DOT8_U32_U4 : VOP3P_Real_vi <0x2b>; 1136 1137defm V_DOT4_I32_I8 : VOP3P_Real_vi <0x28>; 1138defm V_DOT8_I32_I4 : VOP3P_Real_vi <0x2a>; 1139 1140let SubtargetPredicate = HasMAIInsts in { 1141 1142defm V_ACCVGPR_READ_B32 : VOP3P_Real_MAI <0x58>; 1143defm V_ACCVGPR_WRITE_B32 : VOP3P_Real_MAI <0x59>; 1144defm V_MFMA_F32_32X32X1F32 : VOP3P_Real_MFMA <0x40, "v_mfma_f32_32x32x1_2b_f32">; 1145defm V_MFMA_F32_16X16X1F32 : VOP3P_Real_MFMA <0x41, "v_mfma_f32_16x16x1_4b_f32">; 1146defm V_MFMA_F32_4X4X1F32 : VOP3P_Real_MFMA <0x42, "v_mfma_f32_4x4x1_16b_f32">; 1147defm V_MFMA_F32_32X32X2F32 : VOP3P_Real_MFMA <0x44, "v_mfma_f32_32x32x2_f32">; 1148defm V_MFMA_F32_16X16X4F32 : VOP3P_Real_MFMA <0x45, "v_mfma_f32_16x16x4_f32">; 1149defm V_MFMA_F32_32X32X4F16 : VOP3P_Real_MFMA <0x48, "v_mfma_f32_32x32x4_2b_f16">; 1150defm V_MFMA_F32_16X16X4F16 : VOP3P_Real_MFMA <0x49, "v_mfma_f32_16x16x4_4b_f16">; 1151defm V_MFMA_F32_4X4X4F16 : VOP3P_Real_MFMA <0x4a, "v_mfma_f32_4x4x4_16b_f16">; 1152defm V_MFMA_F32_32X32X8F16 : VOP3P_Real_MFMA <0x4c, "v_mfma_f32_32x32x8_f16">; 1153defm V_MFMA_F32_16X16X16F16 : VOP3P_Real_MFMA <0x4d, "v_mfma_f32_16x16x16_f16">; 1154defm V_MFMA_I32_32X32X4I8 : VOP3P_Real_MFMA <0x50, "v_mfma_i32_32x32x4_2b_i8">; 1155defm V_MFMA_I32_16X16X4I8 : VOP3P_Real_MFMA <0x51, "v_mfma_i32_16x16x4_4b_i8">; 1156defm V_MFMA_I32_4X4X4I8 : VOP3P_Real_MFMA <0x52, "v_mfma_i32_4x4x4_16b_i8">; 1157 1158let SubtargetPredicate = isGFX908orGFX90A in { 1159defm V_MFMA_I32_16X16X16I8 : VOP3P_Real_MFMA <0x55>; 1160defm V_MFMA_I32_32X32X8I8 : VOP3P_Real_MFMA <0x54>; 1161defm V_MFMA_F32_32X32X2BF16 : VOP3P_Real_MFMA <0x68>; 1162defm V_MFMA_F32_16X16X2BF16 : VOP3P_Real_MFMA <0x69>; 1163defm V_MFMA_F32_4X4X2BF16 : VOP3P_Real_MFMA <0x6b>; 1164defm V_MFMA_F32_32X32X4BF16 : VOP3P_Real_MFMA <0x6c>; 1165defm V_MFMA_F32_16X16X8BF16 : VOP3P_Real_MFMA <0x6d>; 1166} 1167 1168} // End SubtargetPredicate = HasMAIInsts 1169 1170defm V_MFMA_F32_32X32X4BF16_1K : VOP3P_Real_MFMA_gfx90a <0x63>; 1171defm V_MFMA_F32_16X16X4BF16_1K : VOP3P_Real_MFMA_gfx90a <0x64>; 1172defm V_MFMA_F32_4X4X4BF16_1K : VOP3P_Real_MFMA_gfx90a <0x65>; 1173defm V_MFMA_F32_32X32X8BF16_1K : VOP3P_Real_MFMA_gfx90a <0x66>; 1174defm V_MFMA_F32_16X16X16BF16_1K : VOP3P_Real_MFMA_gfx90a <0x67>; 1175defm V_MFMA_F64_16X16X4F64 : VOP3P_Real_MFMA_gfx90a <0x6e>; 1176defm V_MFMA_F64_4X4X4F64 : VOP3P_Real_MFMA_gfx90a <0x6f>; 1177 1178defm V_MFMA_I32_32X32X16I8 : VOP3P_Real_MFMA_gfx940 <0x56, "v_mfma_i32_32x32x16_i8">; 1179defm V_MFMA_I32_16X16X32I8 : VOP3P_Real_MFMA_gfx940 <0x57, "v_mfma_i32_16x16x32_i8">; 1180defm V_MFMA_F32_16X16X8XF32 : VOP3P_Real_MFMA_gfx940 <0x3e, "v_mfma_f32_16x16x8_xf32">; 1181defm V_MFMA_F32_32X32X4XF32 : VOP3P_Real_MFMA_gfx940 <0x3f, "v_mfma_f32_32x32x4_xf32">; 1182defm V_MFMA_F32_16X16X32_BF8_BF8 : VOP3P_Real_MFMA_gfx940 <0x70>; 1183defm V_MFMA_F32_16X16X32_BF8_FP8 : VOP3P_Real_MFMA_gfx940 <0x71>; 1184defm V_MFMA_F32_16X16X32_FP8_BF8 : VOP3P_Real_MFMA_gfx940 <0x72>; 1185defm V_MFMA_F32_16X16X32_FP8_FP8 : VOP3P_Real_MFMA_gfx940 <0x73>; 1186defm V_MFMA_F32_32X32X16_BF8_BF8 : VOP3P_Real_MFMA_gfx940 <0x74>; 1187defm V_MFMA_F32_32X32X16_BF8_FP8 : VOP3P_Real_MFMA_gfx940 <0x75>; 1188defm V_MFMA_F32_32X32X16_FP8_BF8 : VOP3P_Real_MFMA_gfx940 <0x76>; 1189defm V_MFMA_F32_32X32X16_FP8_FP8 : VOP3P_Real_MFMA_gfx940 <0x77>; 1190 1191defm V_MFMA_F32_32X32X4BF16_1K : VOP3P_Real_MFMA_gfx940 <0x5d, "v_mfma_f32_32x32x4_2b_bf16">; 1192defm V_MFMA_F32_16X16X4BF16_1K : VOP3P_Real_MFMA_gfx940 <0x5e, "v_mfma_f32_16x16x4_4b_bf16">; 1193defm V_MFMA_F32_4X4X4BF16_1K : VOP3P_Real_MFMA_gfx940 <0x5f, "v_mfma_f32_4x4x4_16b_bf16">; 1194defm V_MFMA_F32_32X32X8BF16_1K : VOP3P_Real_MFMA_gfx940 <0x60, "v_mfma_f32_32x32x8_bf16">; 1195defm V_MFMA_F32_16X16X16BF16_1K : VOP3P_Real_MFMA_gfx940 <0x61, "v_mfma_f32_16x16x16_bf16">; 1196 1197defm V_MFMA_F64_16X16X4F64 : VOP3P_Real_MFMA_gfx940 <0x6e, "v_mfma_f64_16x16x4_f64">; 1198defm V_MFMA_F64_4X4X4F64 : VOP3P_Real_MFMA_gfx940 <0x6f, "v_mfma_f64_4x4x4_4b_f64">; 1199 1200defm V_SMFMAC_F32_16X16X32_F16 : VOP3P_Real_SMFMAC <0x62, "v_smfmac_f32_16x16x32f16">; 1201defm V_SMFMAC_F32_32X32X16_F16 : VOP3P_Real_SMFMAC <0x64, "v_smfmac_f32_32x32x16f16">; 1202defm V_SMFMAC_F32_16X16X32_BF16 : VOP3P_Real_SMFMAC <0x66, "v_smfmac_f32_16x16x32bf16">; 1203defm V_SMFMAC_F32_32X32X16_BF16 : VOP3P_Real_SMFMAC <0x68, "v_smfmac_f32_32x32x16bf16">; 1204defm V_SMFMAC_I32_16X16X64_I8 : VOP3P_Real_SMFMAC <0x6a, "v_smfmac_i32_16x16x64i8">; 1205defm V_SMFMAC_I32_32X32X32_I8 : VOP3P_Real_SMFMAC <0x6c, "v_smfmac_i32_32x32x32i8">; 1206defm V_SMFMAC_F32_16X16X64_BF8_BF8 : VOP3P_Real_SMFMAC <0x78, "v_smfmac_f32_16x16x64bf8bf8">; 1207defm V_SMFMAC_F32_16X16X64_BF8_FP8 : VOP3P_Real_SMFMAC <0x79, "v_smfmac_f32_16x16x64bf8fp8">; 1208defm V_SMFMAC_F32_16X16X64_FP8_BF8 : VOP3P_Real_SMFMAC <0x7a, "v_smfmac_f32_16x16x64fp8bf8">; 1209defm V_SMFMAC_F32_16X16X64_FP8_FP8 : VOP3P_Real_SMFMAC <0x7b, "v_smfmac_f32_16x16x64fp8fp8">; 1210defm V_SMFMAC_F32_32X32X32_BF8_BF8 : VOP3P_Real_SMFMAC <0x7c, "v_smfmac_f32_32x32x32bf8bf8">; 1211defm V_SMFMAC_F32_32X32X32_BF8_FP8 : VOP3P_Real_SMFMAC <0x7d, "v_smfmac_f32_32x32x32bf8fp8">; 1212defm V_SMFMAC_F32_32X32X32_FP8_BF8 : VOP3P_Real_SMFMAC <0x7e, "v_smfmac_f32_32x32x32fp8bf8">; 1213defm V_SMFMAC_F32_32X32X32_FP8_FP8 : VOP3P_Real_SMFMAC <0x7f, "v_smfmac_f32_32x32x32fp8fp8">; 1214 1215let SubtargetPredicate = HasPackedFP32Ops in { 1216 defm V_PK_FMA_F32 : VOP3P_Real_vi <0x30>; 1217 defm V_PK_MUL_F32 : VOP3P_Real_vi <0x31>; 1218 defm V_PK_ADD_F32 : VOP3P_Real_vi <0x32>; 1219 defm V_PK_MOV_B32 : VOP3P_Real_vi <0x33>; 1220} // End SubtargetPredicate = HasPackedFP32Ops 1221 1222//===----------------------------------------------------------------------===// 1223// GFX10. 1224//===----------------------------------------------------------------------===// 1225 1226let AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10", VOP3P = 1 in { 1227 multiclass VOP3P_Real_gfx10<bits<7> op> { 1228 def _gfx10 : VOP3P_Real<!cast<VOP3P_Pseudo>(NAME), SIEncodingFamily.GFX10>, 1229 VOP3Pe_gfx10 <op, !cast<VOP3P_Pseudo>(NAME).Pfl>; 1230 } 1231} // End AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10", VOP3P = 1 1232 1233multiclass VOP3P_Real_gfx10_gfx11<bits<7> op> 1234 : VOP3P_Real_gfx10<op>, VOP3P_Real_gfx11<op>; 1235 1236multiclass VOP3P_Real_gfx10_gfx11_Triple<bits<7> op> 1237 : VOP3P_Real_gfx10<op>, VOP3P_Realtriple_gfx11<op>; 1238 1239defm V_PK_MAD_I16 : VOP3P_Real_gfx10_gfx11<0x00>; 1240defm V_PK_MUL_LO_U16 : VOP3P_Real_gfx10_gfx11<0x01>; 1241defm V_PK_ADD_I16 : VOP3P_Real_gfx10_gfx11<0x02>; 1242defm V_PK_SUB_I16 : VOP3P_Real_gfx10_gfx11<0x03>; 1243defm V_PK_LSHLREV_B16 : VOP3P_Real_gfx10_gfx11<0x04>; 1244defm V_PK_LSHRREV_B16 : VOP3P_Real_gfx10_gfx11<0x05>; 1245defm V_PK_ASHRREV_I16 : VOP3P_Real_gfx10_gfx11<0x06>; 1246defm V_PK_MAX_I16 : VOP3P_Real_gfx10_gfx11<0x07>; 1247defm V_PK_MIN_I16 : VOP3P_Real_gfx10_gfx11<0x08>; 1248defm V_PK_MAD_U16 : VOP3P_Real_gfx10_gfx11<0x09>; 1249defm V_PK_ADD_U16 : VOP3P_Real_gfx10_gfx11<0x0a>; 1250defm V_PK_SUB_U16 : VOP3P_Real_gfx10_gfx11<0x0b>; 1251defm V_PK_MAX_U16 : VOP3P_Real_gfx10_gfx11<0x0c>; 1252defm V_PK_MIN_U16 : VOP3P_Real_gfx10_gfx11<0x0d>; 1253defm V_PK_FMA_F16 : VOP3P_Real_gfx10_gfx11<0x0e>; 1254defm V_PK_ADD_F16 : VOP3P_Real_gfx10_gfx11<0x0f>; 1255defm V_PK_MUL_F16 : VOP3P_Real_gfx10_gfx11<0x10>; 1256defm V_PK_MIN_F16 : VOP3P_Real_gfx10_gfx11<0x11>; 1257defm V_PK_MAX_F16 : VOP3P_Real_gfx10_gfx11<0x12>; 1258defm V_FMA_MIX_F32 : VOP3P_Real_gfx10_gfx11_Triple <0x20>; 1259defm V_FMA_MIXLO_F16 : VOP3P_Real_gfx10_gfx11_Triple <0x21>; 1260defm V_FMA_MIXHI_F16 : VOP3P_Real_gfx10_gfx11_Triple <0x22>; 1261 1262defm V_DOT2_I32_I16 : VOP3P_Real_gfx10 <0x14>; 1263defm V_DOT2_U32_U16 : VOP3P_Real_gfx10 <0x15>; 1264 1265defm V_DOT2_F32_F16 : VOP3P_Real_gfx10_gfx11_Triple <0x13>; 1266defm V_DOT4_U32_U8 : VOP3P_Real_gfx10_gfx11 <0x17>; 1267defm V_DOT8_U32_U4 : VOP3P_Real_gfx10_gfx11 <0x19>; 1268 1269defm V_DOT4_I32_I8 : VOP3P_Real_gfx10 <0x16>; 1270defm V_DOT8_I32_I4 : VOP3P_Real_gfx10 <0x18>; 1271