10b57cec5SDimitry Andric//===- ARC.td - Describe the ARC Target Machine ------------*- tablegen -*-===// 20b57cec5SDimitry Andric// 30b57cec5SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric// 70b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric 90b57cec5SDimitry Andricinclude "llvm/Target/Target.td" 100b57cec5SDimitry Andric 110b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 120b57cec5SDimitry Andric// ARC Subtarget features 130b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 140b57cec5SDimitry Andric 150b57cec5SDimitry Andricdef FeatureNORM 160b57cec5SDimitry Andric : SubtargetFeature<"norm", "Xnorm", "true", 170b57cec5SDimitry Andric "Enable support for norm instruction.">; 180b57cec5SDimitry Andric 190b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 200b57cec5SDimitry Andric// Registers, calling conventions, instruction descriptions 210b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 220b57cec5SDimitry Andric 230b57cec5SDimitry Andricinclude "ARCRegisterInfo.td" 240b57cec5SDimitry Andricinclude "ARCInstrInfo.td" 25include "ARCCallingConv.td" 26 27def ARCInstrInfo : InstrInfo; 28 29class Proc<string Name, list<SubtargetFeature> Features> 30 : Processor<Name, NoItineraries, Features>; 31 32def : Proc<"generic", []>; 33 34def ARC : Target { 35 let InstructionSet = ARCInstrInfo; 36} 37